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authorNick Kossifidis <mickflemm@gmail.com>2010-11-23 14:33:22 -0500
committerJohn W. Linville <linville@tuxdriver.com>2010-11-30 13:53:23 -0500
commitf08fbf6cf4a31c8df52b21440c7a7e6fbe474b28 (patch)
treed409b41e9460c7e0004e7c55531b286157c20e4b /drivers
parenta2677fe4298c61f0e93c063e59815bf21c530c4a (diff)
ath5k: Update PLL programming for turbo/half/quarter
* Set correct PLL settings for each bwmode Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/ath/ath5k/reset.c28
1 files changed, 23 insertions, 5 deletions
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c
index c871d40b1ad7..ec013103a6af 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -500,7 +500,6 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
500 500
501/* 501/*
502 * Bring up MAC + PHY Chips and program PLL 502 * Bring up MAC + PHY Chips and program PLL
503 * TODO: Half/Quarter rate support
504 */ 503 */
505int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial) 504int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
506{ 505{
@@ -588,7 +587,8 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
588 * CCK headers) operation. We need to test 587 * CCK headers) operation. We need to test
589 * this, 5211 might support ofdm-only g after 588 * this, 5211 might support ofdm-only g after
590 * all, there are also initial register values 589 * all, there are also initial register values
591 * in the code for g mode (see initvals.c). */ 590 * in the code for g mode (see initvals.c).
591 */
592 if (ah->ah_version == AR5K_AR5211) 592 if (ah->ah_version == AR5K_AR5211)
593 mode |= AR5K_PHY_MODE_MOD_OFDM; 593 mode |= AR5K_PHY_MODE_MOD_OFDM;
594 else 594 else
@@ -601,6 +601,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
601 } else if (flags & CHANNEL_5GHZ) { 601 } else if (flags & CHANNEL_5GHZ) {
602 mode |= AR5K_PHY_MODE_FREQ_5GHZ; 602 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
603 603
604 /* Different PLL setting for 5413 */
604 if (ah->ah_radio == AR5K_RF5413) 605 if (ah->ah_radio == AR5K_RF5413)
605 clock = AR5K_PHY_PLL_40MHZ_5413; 606 clock = AR5K_PHY_PLL_40MHZ_5413;
606 else 607 else
@@ -618,12 +619,29 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
618 return -EINVAL; 619 return -EINVAL;
619 } 620 }
620 621
621 if (flags & CHANNEL_TURBO) 622 /*XXX: Can bwmode be used with dynamic mode ?
622 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT; 623 * (I don't think it supports 44MHz) */
624 /* On 2425 initvals TURBO_SHORT is not pressent */
625 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
626 turbo = AR5K_PHY_TURBO_MODE |
627 (ah->ah_radio == AR5K_RF2425) ? 0 :
628 AR5K_PHY_TURBO_SHORT;
629 } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
630 if (ah->ah_radio == AR5K_RF5413) {
631 mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
632 AR5K_PHY_MODE_HALF_RATE :
633 AR5K_PHY_MODE_QUARTER_RATE;
634 } else if (ah->ah_version == AR5K_AR5212) {
635 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
636 AR5K_PHY_PLL_HALF_RATE :
637 AR5K_PHY_PLL_QUARTER_RATE;
638 }
639 }
640
623 } else { /* Reset the device */ 641 } else { /* Reset the device */
624 642
625 /* ...enable Atheros turbo mode if requested */ 643 /* ...enable Atheros turbo mode if requested */
626 if (flags & CHANNEL_TURBO) 644 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
627 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE, 645 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
628 AR5K_PHY_TURBO); 646 AR5K_PHY_TURBO);
629 } 647 }