omap_hsmmc: Flush posted write to IRQ

Spurious IRQs seen on MMC after 2.6.29.  Flush posted write in IRQ
handler.

The interrupt line is released by clearing the error status bits
in the MMCHS_STAT register, which must occur before the interrupt
handler returns to avoid unwanted irqs.  Hence the need to flush
the posted write.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Acked-by: Tony Lindgen <tony@atomide.com>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index d183be6f2a5f..a752788fa4e9 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -434,6 +434,8 @@ static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
         if (host->mrq == NULL) {
                 OMAP_HSMMC_WRITE(host->base, STAT,
                         OMAP_HSMMC_READ(host->base, STAT));
+                /* Flush posted write */
+                OMAP_HSMMC_READ(host->base, STAT);
                 return IRQ_HANDLED;
         }
 
@@ -489,6 +491,8 @@ static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
         }
 
         OMAP_HSMMC_WRITE(host->base, STAT, status);
+        /* Flush posted write */
+        OMAP_HSMMC_READ(host->base, STAT);
 
         if (end_cmd || (status & CC))
                 mmc_omap_cmd_done(host, host->cmd);