diff options
author | Alan Cox <alan@linux.intel.com> | 2009-08-27 06:02:25 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2009-09-15 15:02:29 -0400 |
commit | b8c4cc46541d864b37497d0047b81b62a5d4e073 (patch) | |
tree | 7709393cc60976d97baa2e3b1d2c8aac5b01cd95 /drivers | |
parent | 2211b732ba8050bc228e129cdc30b4fdedcbea86 (diff) |
Staging: et131x: put the jagcore routines in with their users
We have two trivial IRQ routines, a single statement and a real function -
relocate them. While we are at it kill the trivial to sort out soft reset
and slv bits in the same areas of code.
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/staging/et131x/Makefile | 1 | ||||
-rw-r--r-- | drivers/staging/et131x/et1310_address_map.h | 56 | ||||
-rw-r--r-- | drivers/staging/et131x/et1310_jagcore.c | 214 | ||||
-rw-r--r-- | drivers/staging/et131x/et131x_initpci.c | 77 | ||||
-rw-r--r-- | drivers/staging/et131x/et131x_isr.c | 43 |
5 files changed, 128 insertions, 263 deletions
diff --git a/drivers/staging/et131x/Makefile b/drivers/staging/et131x/Makefile index 3ddbc64aa5f3..111049405cb3 100644 --- a/drivers/staging/et131x/Makefile +++ b/drivers/staging/et131x/Makefile | |||
@@ -5,7 +5,6 @@ | |||
5 | obj-$(CONFIG_ET131X) += et131x.o | 5 | obj-$(CONFIG_ET131X) += et131x.o |
6 | 6 | ||
7 | et131x-objs := et1310_eeprom.o \ | 7 | et131x-objs := et1310_eeprom.o \ |
8 | et1310_jagcore.o \ | ||
9 | et1310_mac.o \ | 8 | et1310_mac.o \ |
10 | et1310_phy.o \ | 9 | et1310_phy.o \ |
11 | et1310_pm.o \ | 10 | et1310_pm.o \ |
diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index c4b0a4f2b844..6dea0d91110b 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h | |||
@@ -116,52 +116,20 @@ | |||
116 | */ | 116 | */ |
117 | 117 | ||
118 | /* | 118 | /* |
119 | * structure for software reset reg in global address map | 119 | * Software reset reg at address 0x0028 |
120 | * located at address 0x0028 | 120 | * 0: txdma_sw_reset |
121 | * 1: rxdma_sw_reset | ||
122 | * 2: txmac_sw_reset | ||
123 | * 3: rxmac_sw_reset | ||
124 | * 4: mac_sw_reset | ||
125 | * 5: mac_stat_sw_reset | ||
126 | * 6: mmc_sw_reset | ||
127 | *31: selfclr_disable | ||
121 | */ | 128 | */ |
122 | typedef union _SW_RESET_t { | ||
123 | u32 value; | ||
124 | struct { | ||
125 | #ifdef _BIT_FIELDS_HTOL | ||
126 | u32 selfclr_disable:1; /* bit 31 */ | ||
127 | u32 unused:24; /* bits 7-30 */ | ||
128 | u32 mmc_sw_reset:1; /* bit 6 */ | ||
129 | u32 mac_stat_sw_reset:1; /* bit 5 */ | ||
130 | u32 mac_sw_reset:1; /* bit 4 */ | ||
131 | u32 rxmac_sw_reset:1; /* bit 3 */ | ||
132 | u32 txmac_sw_reset:1; /* bit 2 */ | ||
133 | u32 rxdma_sw_reset:1; /* bit 1 */ | ||
134 | u32 txdma_sw_reset:1; /* bit 0 */ | ||
135 | #else | ||
136 | u32 txdma_sw_reset:1; /* bit 0 */ | ||
137 | u32 rxdma_sw_reset:1; /* bit 1 */ | ||
138 | u32 txmac_sw_reset:1; /* bit 2 */ | ||
139 | u32 rxmac_sw_reset:1; /* bit 3 */ | ||
140 | u32 mac_sw_reset:1; /* bit 4 */ | ||
141 | u32 mac_stat_sw_reset:1; /* bit 5 */ | ||
142 | u32 mmc_sw_reset:1; /* bit 6 */ | ||
143 | u32 unused:24; /* bits 7-30 */ | ||
144 | u32 selfclr_disable:1; /* bit 31 */ | ||
145 | #endif | ||
146 | } bits; | ||
147 | } SW_RESET_t, *PSW_RESET_t; | ||
148 | 129 | ||
149 | /* | 130 | /* |
150 | * structure for SLV Timer reg in global address map | 131 | * SLV Timer reg at address 0x002C (low 24 bits) |
151 | * located at address 0x002C | ||
152 | */ | 132 | */ |
153 | typedef union _SLV_TIMER_t { | ||
154 | u32 value; | ||
155 | struct { | ||
156 | #ifdef _BIT_FIELDS_HTOL | ||
157 | u32 unused:8; /* bits 24-31 */ | ||
158 | u32 timer_ini:24; /* bits 0-23 */ | ||
159 | #else | ||
160 | u32 timer_ini:24; /* bits 0-23 */ | ||
161 | u32 unused:8; /* bits 24-31 */ | ||
162 | #endif | ||
163 | } bits; | ||
164 | } SLV_TIMER_t, *PSLV_TIMER_t; | ||
165 | 133 | ||
166 | /* | 134 | /* |
167 | * structure for MSI Configuration reg in global address map | 135 | * structure for MSI Configuration reg in global address map |
@@ -218,8 +186,8 @@ typedef struct _GLOBAL_t { /* Location: */ | |||
218 | u32 int_mask; /* 0x001C */ | 186 | u32 int_mask; /* 0x001C */ |
219 | u32 int_alias_clr_en; /* 0x0020 */ | 187 | u32 int_alias_clr_en; /* 0x0020 */ |
220 | u32 int_status_alias; /* 0x0024 */ | 188 | u32 int_status_alias; /* 0x0024 */ |
221 | SW_RESET_t sw_reset; /* 0x0028 */ | 189 | u32 sw_reset; /* 0x0028 */ |
222 | SLV_TIMER_t slv_timer; /* 0x002C */ | 190 | u32 slv_timer; /* 0x002C */ |
223 | MSI_CONFIG_t msi_config; /* 0x0030 */ | 191 | MSI_CONFIG_t msi_config; /* 0x0030 */ |
224 | LOOPBACK_t loopback; /* 0x0034 */ | 192 | LOOPBACK_t loopback; /* 0x0034 */ |
225 | u32 watchdog_timer; /* 0x0038 */ | 193 | u32 watchdog_timer; /* 0x0038 */ |
diff --git a/drivers/staging/et131x/et1310_jagcore.c b/drivers/staging/et131x/et1310_jagcore.c deleted file mode 100644 index ff238ef97283..000000000000 --- a/drivers/staging/et131x/et1310_jagcore.c +++ /dev/null | |||
@@ -1,214 +0,0 @@ | |||
1 | /* | ||
2 | * Agere Systems Inc. | ||
3 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs | ||
4 | * | ||
5 | * Copyright © 2005 Agere Systems Inc. | ||
6 | * All rights reserved. | ||
7 | * http://www.agere.com | ||
8 | * | ||
9 | *------------------------------------------------------------------------------ | ||
10 | * | ||
11 | * et1310_jagcore.c - All code pertaining to the ET1301/ET131x's JAGcore | ||
12 | * | ||
13 | *------------------------------------------------------------------------------ | ||
14 | * | ||
15 | * SOFTWARE LICENSE | ||
16 | * | ||
17 | * This software is provided subject to the following terms and conditions, | ||
18 | * which you should read carefully before using the software. Using this | ||
19 | * software indicates your acceptance of these terms and conditions. If you do | ||
20 | * not agree with these terms and conditions, do not use the software. | ||
21 | * | ||
22 | * Copyright © 2005 Agere Systems Inc. | ||
23 | * All rights reserved. | ||
24 | * | ||
25 | * Redistribution and use in source or binary forms, with or without | ||
26 | * modifications, are permitted provided that the following conditions are met: | ||
27 | * | ||
28 | * . Redistributions of source code must retain the above copyright notice, this | ||
29 | * list of conditions and the following Disclaimer as comments in the code as | ||
30 | * well as in the documentation and/or other materials provided with the | ||
31 | * distribution. | ||
32 | * | ||
33 | * . Redistributions in binary form must reproduce the above copyright notice, | ||
34 | * this list of conditions and the following Disclaimer in the documentation | ||
35 | * and/or other materials provided with the distribution. | ||
36 | * | ||
37 | * . Neither the name of Agere Systems Inc. nor the names of the contributors | ||
38 | * may be used to endorse or promote products derived from this software | ||
39 | * without specific prior written permission. | ||
40 | * | ||
41 | * Disclaimer | ||
42 | * | ||
43 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, | ||
44 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF | ||
45 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY | ||
46 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN | ||
47 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY | ||
48 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | ||
49 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | ||
50 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | ||
51 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT | ||
52 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT | ||
53 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH | ||
54 | * DAMAGE. | ||
55 | * | ||
56 | */ | ||
57 | |||
58 | #include "et131x_version.h" | ||
59 | #include "et131x_debug.h" | ||
60 | #include "et131x_defs.h" | ||
61 | |||
62 | #include <linux/init.h> | ||
63 | #include <linux/module.h> | ||
64 | #include <linux/types.h> | ||
65 | #include <linux/kernel.h> | ||
66 | |||
67 | #include <linux/sched.h> | ||
68 | #include <linux/ptrace.h> | ||
69 | #include <linux/slab.h> | ||
70 | #include <linux/ctype.h> | ||
71 | #include <linux/string.h> | ||
72 | #include <linux/timer.h> | ||
73 | #include <linux/interrupt.h> | ||
74 | #include <linux/in.h> | ||
75 | #include <linux/delay.h> | ||
76 | #include <linux/io.h> | ||
77 | #include <linux/bitops.h> | ||
78 | #include <asm/system.h> | ||
79 | |||
80 | #include <linux/netdevice.h> | ||
81 | #include <linux/etherdevice.h> | ||
82 | #include <linux/skbuff.h> | ||
83 | #include <linux/if_arp.h> | ||
84 | #include <linux/ioport.h> | ||
85 | |||
86 | #include "et1310_phy.h" | ||
87 | #include "et1310_pm.h" | ||
88 | #include "et1310_jagcore.h" | ||
89 | |||
90 | #include "et131x_adapter.h" | ||
91 | #include "et131x_initpci.h" | ||
92 | |||
93 | /* Data for debugging facilities */ | ||
94 | #ifdef CONFIG_ET131X_DEBUG | ||
95 | extern dbg_info_t *et131x_dbginfo; | ||
96 | #endif /* CONFIG_ET131X_DEBUG */ | ||
97 | |||
98 | /** | ||
99 | * ConfigGlobalRegs - Used to configure the global registers on the JAGCore | ||
100 | * @pAdpater: pointer to our adapter structure | ||
101 | */ | ||
102 | void ConfigGlobalRegs(struct et131x_adapter *etdev) | ||
103 | { | ||
104 | struct _GLOBAL_t __iomem *pGbl = &etdev->regs->global; | ||
105 | |||
106 | DBG_ENTER(et131x_dbginfo); | ||
107 | |||
108 | if (etdev->RegistryPhyLoopbk == false) { | ||
109 | if (etdev->RegistryJumboPacket < 2048) { | ||
110 | /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word | ||
111 | * block of RAM that the driver can split between Tx | ||
112 | * and Rx as it desires. Our default is to split it | ||
113 | * 50/50: | ||
114 | */ | ||
115 | writel(0, &pGbl->rxq_start_addr); | ||
116 | writel(PARM_RX_MEM_END_DEF, &pGbl->rxq_end_addr); | ||
117 | writel(PARM_RX_MEM_END_DEF + 1, &pGbl->txq_start_addr); | ||
118 | writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr); | ||
119 | } else if (etdev->RegistryJumboPacket < 8192) { | ||
120 | /* For jumbo packets > 2k but < 8k, split 50-50. */ | ||
121 | writel(0, &pGbl->rxq_start_addr); | ||
122 | writel(INTERNAL_MEM_RX_OFFSET, &pGbl->rxq_end_addr); | ||
123 | writel(INTERNAL_MEM_RX_OFFSET + 1, &pGbl->txq_start_addr); | ||
124 | writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr); | ||
125 | } else { | ||
126 | /* 9216 is the only packet size greater than 8k that | ||
127 | * is available. The Tx buffer has to be big enough | ||
128 | * for one whole packet on the Tx side. We'll make | ||
129 | * the Tx 9408, and give the rest to Rx | ||
130 | */ | ||
131 | writel(0x0000, &pGbl->rxq_start_addr); | ||
132 | writel(0x01b3, &pGbl->rxq_end_addr); | ||
133 | writel(0x01b4, &pGbl->txq_start_addr); | ||
134 | writel(INTERNAL_MEM_SIZE - 1,&pGbl->txq_end_addr); | ||
135 | } | ||
136 | |||
137 | /* Initialize the loopback register. Disable all loopbacks. */ | ||
138 | writel(0, &pGbl->loopback.value); | ||
139 | } else { | ||
140 | /* For PHY Line loopback, the memory is configured as if Tx | ||
141 | * and Rx both have all the memory. This is because the | ||
142 | * RxMAC will write data into the space, and the TxMAC will | ||
143 | * read it out. | ||
144 | */ | ||
145 | writel(0, &pGbl->rxq_start_addr); | ||
146 | writel(INTERNAL_MEM_SIZE - 1, &pGbl->rxq_end_addr); | ||
147 | writel(0, &pGbl->txq_start_addr); | ||
148 | writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr); | ||
149 | |||
150 | /* Initialize the loopback register (MAC loopback). */ | ||
151 | writel(1, &pGbl->loopback); | ||
152 | } | ||
153 | |||
154 | /* MSI Register */ | ||
155 | writel(0, &pGbl->msi_config.value); | ||
156 | |||
157 | /* By default, disable the watchdog timer. It will be enabled when | ||
158 | * a packet is queued. | ||
159 | */ | ||
160 | writel(0, &pGbl->watchdog_timer); | ||
161 | |||
162 | DBG_LEAVE(et131x_dbginfo); | ||
163 | } | ||
164 | |||
165 | /** | ||
166 | * ConfigMMCRegs - Used to configure the main memory registers in the JAGCore | ||
167 | * @etdev: pointer to our adapter structure | ||
168 | */ | ||
169 | void ConfigMMCRegs(struct et131x_adapter *etdev) | ||
170 | { | ||
171 | DBG_ENTER(et131x_dbginfo); | ||
172 | /* All we need to do is initialize the Memory Control Register */ | ||
173 | writel(ET_MMC_ENABLE, &etdev->regs->mmc.mmc_ctrl); | ||
174 | DBG_LEAVE(et131x_dbginfo); | ||
175 | } | ||
176 | |||
177 | /** | ||
178 | * et131x_enable_interrupts - enable interrupt | ||
179 | * @adapter: et131x device | ||
180 | * | ||
181 | * Enable the appropriate interrupts on the ET131x according to our | ||
182 | * configuration | ||
183 | */ | ||
184 | |||
185 | void et131x_enable_interrupts(struct et131x_adapter *adapter) | ||
186 | { | ||
187 | u32 mask; | ||
188 | |||
189 | /* Enable all global interrupts */ | ||
190 | if (adapter->FlowControl == TxOnly || adapter->FlowControl == Both) | ||
191 | mask = INT_MASK_ENABLE; | ||
192 | else | ||
193 | mask = INT_MASK_ENABLE_NO_FLOW; | ||
194 | |||
195 | if (adapter->DriverNoPhyAccess) | ||
196 | mask |= ET_INTR_PHY; | ||
197 | |||
198 | adapter->CachedMaskValue = mask; | ||
199 | writel(mask, &adapter->regs->global.int_mask); | ||
200 | } | ||
201 | |||
202 | /** | ||
203 | * et131x_disable_interrupts - interrupt disable | ||
204 | * @adapter: et131x device | ||
205 | * | ||
206 | * Block all interrupts from the et131x device at the device itself | ||
207 | */ | ||
208 | |||
209 | void et131x_disable_interrupts(struct et131x_adapter *adapter) | ||
210 | { | ||
211 | /* Disable all global interrupts */ | ||
212 | adapter->CachedMaskValue = INT_MASK_DISABLE; | ||
213 | writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask); | ||
214 | } | ||
diff --git a/drivers/staging/et131x/et131x_initpci.c b/drivers/staging/et131x/et131x_initpci.c index 0a3464aa3809..936e5e6c8a88 100644 --- a/drivers/staging/et131x/et131x_initpci.c +++ b/drivers/staging/et131x/et131x_initpci.c | |||
@@ -532,6 +532,76 @@ void et131x_link_detection_handler(unsigned long data) | |||
532 | } | 532 | } |
533 | 533 | ||
534 | /** | 534 | /** |
535 | * et131x_configure_global_regs - configure JAGCore global regs | ||
536 | * @etdev: pointer to our adapter structure | ||
537 | * | ||
538 | * Used to configure the global registers on the JAGCore | ||
539 | */ | ||
540 | void ConfigGlobalRegs(struct et131x_adapter *etdev) | ||
541 | { | ||
542 | struct _GLOBAL_t __iomem *pGbl = &etdev->regs->global; | ||
543 | |||
544 | DBG_ENTER(et131x_dbginfo); | ||
545 | |||
546 | if (etdev->RegistryPhyLoopbk == false) { | ||
547 | if (etdev->RegistryJumboPacket < 2048) { | ||
548 | /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word | ||
549 | * block of RAM that the driver can split between Tx | ||
550 | * and Rx as it desires. Our default is to split it | ||
551 | * 50/50: | ||
552 | */ | ||
553 | writel(0, &pGbl->rxq_start_addr); | ||
554 | writel(PARM_RX_MEM_END_DEF, &pGbl->rxq_end_addr); | ||
555 | writel(PARM_RX_MEM_END_DEF + 1, &pGbl->txq_start_addr); | ||
556 | writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr); | ||
557 | } else if (etdev->RegistryJumboPacket < 8192) { | ||
558 | /* For jumbo packets > 2k but < 8k, split 50-50. */ | ||
559 | writel(0, &pGbl->rxq_start_addr); | ||
560 | writel(INTERNAL_MEM_RX_OFFSET, &pGbl->rxq_end_addr); | ||
561 | writel(INTERNAL_MEM_RX_OFFSET + 1, &pGbl->txq_start_addr); | ||
562 | writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr); | ||
563 | } else { | ||
564 | /* 9216 is the only packet size greater than 8k that | ||
565 | * is available. The Tx buffer has to be big enough | ||
566 | * for one whole packet on the Tx side. We'll make | ||
567 | * the Tx 9408, and give the rest to Rx | ||
568 | */ | ||
569 | writel(0x0000, &pGbl->rxq_start_addr); | ||
570 | writel(0x01b3, &pGbl->rxq_end_addr); | ||
571 | writel(0x01b4, &pGbl->txq_start_addr); | ||
572 | writel(INTERNAL_MEM_SIZE - 1,&pGbl->txq_end_addr); | ||
573 | } | ||
574 | |||
575 | /* Initialize the loopback register. Disable all loopbacks. */ | ||
576 | writel(0, &pGbl->loopback.value); | ||
577 | } else { | ||
578 | /* For PHY Line loopback, the memory is configured as if Tx | ||
579 | * and Rx both have all the memory. This is because the | ||
580 | * RxMAC will write data into the space, and the TxMAC will | ||
581 | * read it out. | ||
582 | */ | ||
583 | writel(0, &pGbl->rxq_start_addr); | ||
584 | writel(INTERNAL_MEM_SIZE - 1, &pGbl->rxq_end_addr); | ||
585 | writel(0, &pGbl->txq_start_addr); | ||
586 | writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr); | ||
587 | |||
588 | /* Initialize the loopback register (MAC loopback). */ | ||
589 | writel(1, &pGbl->loopback); | ||
590 | } | ||
591 | |||
592 | /* MSI Register */ | ||
593 | writel(0, &pGbl->msi_config.value); | ||
594 | |||
595 | /* By default, disable the watchdog timer. It will be enabled when | ||
596 | * a packet is queued. | ||
597 | */ | ||
598 | writel(0, &pGbl->watchdog_timer); | ||
599 | |||
600 | DBG_LEAVE(et131x_dbginfo); | ||
601 | } | ||
602 | |||
603 | |||
604 | /** | ||
535 | * et131x_adapter_setup - Set the adapter up as per cassini+ documentation | 605 | * et131x_adapter_setup - Set the adapter up as per cassini+ documentation |
536 | * @adapter: pointer to our private adapter structure | 606 | * @adapter: pointer to our private adapter structure |
537 | * | 607 | * |
@@ -547,7 +617,10 @@ int et131x_adapter_setup(struct et131x_adapter *etdev) | |||
547 | ConfigGlobalRegs(etdev); | 617 | ConfigGlobalRegs(etdev); |
548 | 618 | ||
549 | ConfigMACRegs1(etdev); | 619 | ConfigMACRegs1(etdev); |
550 | ConfigMMCRegs(etdev); | 620 | |
621 | /* Configure the MMC registers */ | ||
622 | /* All we need to do is initialize the Memory Control Register */ | ||
623 | writel(ET_MMC_ENABLE, &etdev->regs->mmc.mmc_ctrl); | ||
551 | 624 | ||
552 | ConfigRxMacRegs(etdev); | 625 | ConfigRxMacRegs(etdev); |
553 | ConfigTxMacRegs(etdev); | 626 | ConfigTxMacRegs(etdev); |
@@ -645,7 +718,7 @@ void et131x_soft_reset(struct et131x_adapter *adapter) | |||
645 | writel(0xc00f0000, &adapter->regs->mac.cfg1.value); | 718 | writel(0xc00f0000, &adapter->regs->mac.cfg1.value); |
646 | 719 | ||
647 | /* Set everything to a reset value */ | 720 | /* Set everything to a reset value */ |
648 | writel(0x7F, &adapter->regs->global.sw_reset.value); | 721 | writel(0x7F, &adapter->regs->global.sw_reset); |
649 | writel(0x000f0000, &adapter->regs->mac.cfg1.value); | 722 | writel(0x000f0000, &adapter->regs->mac.cfg1.value); |
650 | writel(0x00000000, &adapter->regs->mac.cfg1.value); | 723 | writel(0x00000000, &adapter->regs->mac.cfg1.value); |
651 | 724 | ||
diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c index 656df12acf72..878fd205e415 100644 --- a/drivers/staging/et131x/et131x_isr.c +++ b/drivers/staging/et131x/et131x_isr.c | |||
@@ -97,12 +97,53 @@ extern dbg_info_t *et131x_dbginfo; | |||
97 | #endif /* CONFIG_ET131X_DEBUG */ | 97 | #endif /* CONFIG_ET131X_DEBUG */ |
98 | 98 | ||
99 | /** | 99 | /** |
100 | * et131x_enable_interrupts - enable interrupt | ||
101 | * @adapter: et131x device | ||
102 | * | ||
103 | * Enable the appropriate interrupts on the ET131x according to our | ||
104 | * configuration | ||
105 | */ | ||
106 | |||
107 | void et131x_enable_interrupts(struct et131x_adapter *adapter) | ||
108 | { | ||
109 | u32 mask; | ||
110 | |||
111 | /* Enable all global interrupts */ | ||
112 | if (adapter->FlowControl == TxOnly || adapter->FlowControl == Both) | ||
113 | mask = INT_MASK_ENABLE; | ||
114 | else | ||
115 | mask = INT_MASK_ENABLE_NO_FLOW; | ||
116 | |||
117 | if (adapter->DriverNoPhyAccess) | ||
118 | mask |= ET_INTR_PHY; | ||
119 | |||
120 | adapter->CachedMaskValue = mask; | ||
121 | writel(mask, &adapter->regs->global.int_mask); | ||
122 | } | ||
123 | |||
124 | /** | ||
125 | * et131x_disable_interrupts - interrupt disable | ||
126 | * @adapter: et131x device | ||
127 | * | ||
128 | * Block all interrupts from the et131x device at the device itself | ||
129 | */ | ||
130 | |||
131 | void et131x_disable_interrupts(struct et131x_adapter *adapter) | ||
132 | { | ||
133 | /* Disable all global interrupts */ | ||
134 | adapter->CachedMaskValue = INT_MASK_DISABLE; | ||
135 | writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask); | ||
136 | } | ||
137 | |||
138 | |||
139 | /** | ||
100 | * et131x_isr - The Interrupt Service Routine for the driver. | 140 | * et131x_isr - The Interrupt Service Routine for the driver. |
101 | * @irq: the IRQ on which the interrupt was received. | 141 | * @irq: the IRQ on which the interrupt was received. |
102 | * @dev_id: device-specific info (here a pointer to a net_device struct) | 142 | * @dev_id: device-specific info (here a pointer to a net_device struct) |
103 | * | 143 | * |
104 | * Returns a value indicating if the interrupt was handled. | 144 | * Returns a value indicating if the interrupt was handled. |
105 | */ | 145 | */ |
146 | |||
106 | irqreturn_t et131x_isr(int irq, void *dev_id) | 147 | irqreturn_t et131x_isr(int irq, void *dev_id) |
107 | { | 148 | { |
108 | bool handled = true; | 149 | bool handled = true; |
@@ -197,7 +238,6 @@ irqreturn_t et131x_isr(int irq, void *dev_id) | |||
197 | * execution | 238 | * execution |
198 | */ | 239 | */ |
199 | schedule_work(&adapter->task); | 240 | schedule_work(&adapter->task); |
200 | |||
201 | out: | 241 | out: |
202 | return IRQ_RETVAL(handled); | 242 | return IRQ_RETVAL(handled); |
203 | } | 243 | } |
@@ -476,6 +516,5 @@ void et131x_isr_handler(struct work_struct *work) | |||
476 | DBG_VERBOSE(et131x_dbginfo, "SLV_TIMEOUT interrupt\n"); | 516 | DBG_VERBOSE(et131x_dbginfo, "SLV_TIMEOUT interrupt\n"); |
477 | } | 517 | } |
478 | } | 518 | } |
479 | |||
480 | et131x_enable_interrupts(etdev); | 519 | et131x_enable_interrupts(etdev); |
481 | } | 520 | } |