aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorMatt Carlson <mcarlson@broadcom.com>2007-10-08 02:27:28 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:54:44 -0400
commit9974a356b204833b32173210ca25edfdc24dcdd5 (patch)
tree1b6a4d69ec46c01934fb5ff2cf4d76d57a103752 /drivers
parent8658251dc3fed54b09991a2c5e0a7084755157d7 (diff)
[TG3]: Walk PCI capability lists.
Newer tg3 devices shuffle around the registers in PCI configuration space. This patch changes the way the driver accesses the PCI capabilities registers. Hardcoded register locations are replaced with offsets from pci_find_capability() return values. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/tg3.c48
-rw-r--r--drivers/net/tg3.h28
2 files changed, 37 insertions, 39 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index d4ac6e9ef6db..4f9fbe268ec9 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -4865,9 +4865,15 @@ static void tg3_restore_pci_state(struct tg3 *tp)
4865 pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd); 4865 pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
4866 4866
4867 /* Make sure PCI-X relaxed ordering bit is clear. */ 4867 /* Make sure PCI-X relaxed ordering bit is clear. */
4868 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val); 4868 if (tp->pcix_cap) {
4869 val &= ~PCIX_CAPS_RELAXED_ORDERING; 4869 u16 pcix_cmd;
4870 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val); 4870
4871 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
4872 &pcix_cmd);
4873 pcix_cmd &= ~PCI_X_CMD_ERO;
4874 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
4875 pcix_cmd);
4876 }
4871 4877
4872 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { 4878 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4873 4879
@@ -6574,16 +6580,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6574 tw32_f(WDMAC_MODE, val); 6580 tw32_f(WDMAC_MODE, val);
6575 udelay(40); 6581 udelay(40);
6576 6582
6577 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) { 6583 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6578 val = tr32(TG3PCI_X_CAPS); 6584 u16 pcix_cmd;
6585
6586 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6587 &pcix_cmd);
6579 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { 6588 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6580 val &= ~PCIX_CAPS_BURST_MASK; 6589 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
6581 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT); 6590 pcix_cmd |= PCI_X_CMD_READ_2K;
6582 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { 6591 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6583 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK); 6592 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
6584 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT); 6593 pcix_cmd |= PCI_X_CMD_READ_2K;
6585 } 6594 }
6586 tw32(TG3PCI_X_CAPS, val); 6595 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6596 pcix_cmd);
6587 } 6597 }
6588 6598
6589 tw32_f(RDMAC_MODE, rdmac_mode); 6599 tw32_f(RDMAC_MODE, rdmac_mode);
@@ -10712,10 +10722,20 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10712 cacheline_sz_reg); 10722 cacheline_sz_reg);
10713 } 10723 }
10714 10724
10725 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
10726 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10727 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
10728 if (!tp->pcix_cap) {
10729 printk(KERN_ERR PFX "Cannot find PCI-X "
10730 "capability, aborting.\n");
10731 return -EIO;
10732 }
10733 }
10734
10715 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, 10735 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10716 &pci_state_reg); 10736 &pci_state_reg);
10717 10737
10718 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) { 10738 if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10719 tp->tg3_flags |= TG3_FLAG_PCIX_MODE; 10739 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10720 10740
10721 /* If this is a 5700 BX chipset, and we are in PCI-X 10741 /* If this is a 5700 BX chipset, and we are in PCI-X
@@ -10733,11 +10753,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10733 * space registers clobbered due to this bug. 10753 * space registers clobbered due to this bug.
10734 * So explicitly force the chip into D0 here. 10754 * So explicitly force the chip into D0 here.
10735 */ 10755 */
10736 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT, 10756 pci_read_config_dword(tp->pdev,
10757 tp->pm_cap + PCI_PM_CTRL,
10737 &pm_reg); 10758 &pm_reg);
10738 pm_reg &= ~PCI_PM_CTRL_STATE_MASK; 10759 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10739 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; 10760 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10740 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT, 10761 pci_write_config_dword(tp->pdev,
10762 tp->pm_cap + PCI_PM_CTRL,
10741 pm_reg); 10763 pm_reg);
10742 10764
10743 /* Also, force SERR#/PERR# in PCI command. */ 10765 /* Also, force SERR#/PERR# in PCI command. */
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index a6a23bbcdfee..c4f845dd1e8b 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -57,32 +57,7 @@
57#define TG3PCI_IRQ_PIN 0x0000003d 57#define TG3PCI_IRQ_PIN 0x0000003d
58#define TG3PCI_MIN_GNT 0x0000003e 58#define TG3PCI_MIN_GNT 0x0000003e
59#define TG3PCI_MAX_LAT 0x0000003f 59#define TG3PCI_MAX_LAT 0x0000003f
60#define TG3PCI_X_CAPS 0x00000040 60/* 0x40 --> 0x64 unused */
61#define PCIX_CAPS_RELAXED_ORDERING 0x00020000
62#define PCIX_CAPS_SPLIT_MASK 0x00700000
63#define PCIX_CAPS_SPLIT_SHIFT 20
64#define PCIX_CAPS_BURST_MASK 0x000c0000
65#define PCIX_CAPS_BURST_SHIFT 18
66#define PCIX_CAPS_MAX_BURST_CPIOB 2
67#define TG3PCI_PM_CAP_PTR 0x00000041
68#define TG3PCI_X_COMMAND 0x00000042
69#define TG3PCI_X_STATUS 0x00000044
70#define TG3PCI_PM_CAP_ID 0x00000048
71#define TG3PCI_VPD_CAP_PTR 0x00000049
72#define TG3PCI_PM_CAPS 0x0000004a
73#define TG3PCI_PM_CTRL_STAT 0x0000004c
74#define TG3PCI_BR_SUPP_EXT 0x0000004e
75#define TG3PCI_PM_DATA 0x0000004f
76#define TG3PCI_VPD_CAP_ID 0x00000050
77#define TG3PCI_MSI_CAP_PTR 0x00000051
78#define TG3PCI_VPD_ADDR_FLAG 0x00000052
79#define VPD_ADDR_FLAG_WRITE 0x00008000
80#define TG3PCI_VPD_DATA 0x00000054
81#define TG3PCI_MSI_CAP_ID 0x00000058
82#define TG3PCI_NXT_CAP_PTR 0x00000059
83#define TG3PCI_MSI_CTRL 0x0000005a
84#define TG3PCI_MSI_ADDR_LOW 0x0000005c
85#define TG3PCI_MSI_ADDR_HIGH 0x00000060
86#define TG3PCI_MSI_DATA 0x00000064 61#define TG3PCI_MSI_DATA 0x00000064
87/* 0x66 --> 0x68 unused */ 62/* 0x66 --> 0x68 unused */
88#define TG3PCI_MISC_HOST_CTRL 0x00000068 63#define TG3PCI_MISC_HOST_CTRL 0x00000068
@@ -2318,6 +2293,7 @@ struct tg3 {
2318 2293
2319 int pm_cap; 2294 int pm_cap;
2320 int msi_cap; 2295 int msi_cap;
2296 int pcix_cap;
2321 2297
2322 /* PHY info */ 2298 /* PHY info */
2323 u32 phy_id; 2299 u32 phy_id;