aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorMatt Carlson <mcarlson@broadcom.com>2007-10-10 21:01:09 -0400
committerDavid S. Miller <davem@davemloft.net>2007-10-10 21:01:09 -0400
commit6b91fa02796292c322b20572188c74c1ef5bb02b (patch)
treedee1577ca9507e256302dc6b33dfb057fb267481 /drivers
parent227b60f5102cda4e4ab792b526a59c8cb20cd9f8 (diff)
[TG3]: Add new 5761 NVRAM decode routines
This patch adds a new 5761-specific NVRAM strapping decode routine. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/tg3.c79
-rw-r--r--drivers/net/tg3.h25
2 files changed, 102 insertions, 2 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 1e0c9e0dc394..3200c9c5ff5e 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -9581,6 +9581,81 @@ static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9581 } 9581 }
9582} 9582}
9583 9583
9584static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
9585{
9586 u32 nvcfg1, protect = 0;
9587
9588 nvcfg1 = tr32(NVRAM_CFG1);
9589
9590 /* NVRAM protection for TPM */
9591 if (nvcfg1 & (1 << 27)) {
9592 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9593 protect = 1;
9594 }
9595
9596 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9597 switch (nvcfg1) {
9598 case FLASH_5761VENDOR_ATMEL_ADB021D:
9599 case FLASH_5761VENDOR_ATMEL_ADB041D:
9600 case FLASH_5761VENDOR_ATMEL_ADB081D:
9601 case FLASH_5761VENDOR_ATMEL_ADB161D:
9602 case FLASH_5761VENDOR_ATMEL_MDB021D:
9603 case FLASH_5761VENDOR_ATMEL_MDB041D:
9604 case FLASH_5761VENDOR_ATMEL_MDB081D:
9605 case FLASH_5761VENDOR_ATMEL_MDB161D:
9606 tp->nvram_jedecnum = JEDEC_ATMEL;
9607 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9608 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9609 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
9610 tp->nvram_pagesize = 256;
9611 break;
9612 case FLASH_5761VENDOR_ST_A_M45PE20:
9613 case FLASH_5761VENDOR_ST_A_M45PE40:
9614 case FLASH_5761VENDOR_ST_A_M45PE80:
9615 case FLASH_5761VENDOR_ST_A_M45PE16:
9616 case FLASH_5761VENDOR_ST_M_M45PE20:
9617 case FLASH_5761VENDOR_ST_M_M45PE40:
9618 case FLASH_5761VENDOR_ST_M_M45PE80:
9619 case FLASH_5761VENDOR_ST_M_M45PE16:
9620 tp->nvram_jedecnum = JEDEC_ST;
9621 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9622 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9623 tp->nvram_pagesize = 256;
9624 break;
9625 }
9626
9627 if (protect) {
9628 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
9629 } else {
9630 switch (nvcfg1) {
9631 case FLASH_5761VENDOR_ATMEL_ADB161D:
9632 case FLASH_5761VENDOR_ATMEL_MDB161D:
9633 case FLASH_5761VENDOR_ST_A_M45PE16:
9634 case FLASH_5761VENDOR_ST_M_M45PE16:
9635 tp->nvram_size = 0x100000;
9636 break;
9637 case FLASH_5761VENDOR_ATMEL_ADB081D:
9638 case FLASH_5761VENDOR_ATMEL_MDB081D:
9639 case FLASH_5761VENDOR_ST_A_M45PE80:
9640 case FLASH_5761VENDOR_ST_M_M45PE80:
9641 tp->nvram_size = 0x80000;
9642 break;
9643 case FLASH_5761VENDOR_ATMEL_ADB041D:
9644 case FLASH_5761VENDOR_ATMEL_MDB041D:
9645 case FLASH_5761VENDOR_ST_A_M45PE40:
9646 case FLASH_5761VENDOR_ST_M_M45PE40:
9647 tp->nvram_size = 0x40000;
9648 break;
9649 case FLASH_5761VENDOR_ATMEL_ADB021D:
9650 case FLASH_5761VENDOR_ATMEL_MDB021D:
9651 case FLASH_5761VENDOR_ST_A_M45PE20:
9652 case FLASH_5761VENDOR_ST_M_M45PE20:
9653 tp->nvram_size = 0x20000;
9654 break;
9655 }
9656 }
9657}
9658
9584static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) 9659static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9585{ 9660{
9586 tp->nvram_jedecnum = JEDEC_ATMEL; 9661 tp->nvram_jedecnum = JEDEC_ATMEL;
@@ -9623,6 +9698,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
9623 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 9698 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9624 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) 9699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
9625 tg3_get_5787_nvram_info(tp); 9700 tg3_get_5787_nvram_info(tp);
9701 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9702 tg3_get_5761_nvram_info(tp);
9626 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 9703 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9627 tg3_get_5906_nvram_info(tp); 9704 tg3_get_5906_nvram_info(tp);
9628 else 9705 else
@@ -9700,6 +9777,7 @@ static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9700 if ((tp->tg3_flags & TG3_FLAG_NVRAM) && 9777 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9701 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && 9778 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9702 (tp->tg3_flags2 & TG3_FLG2_FLASH) && 9779 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9780 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
9703 (tp->nvram_jedecnum == JEDEC_ATMEL)) 9781 (tp->nvram_jedecnum == JEDEC_ATMEL))
9704 9782
9705 addr = ((addr / tp->nvram_pagesize) << 9783 addr = ((addr / tp->nvram_pagesize) <<
@@ -9714,6 +9792,7 @@ static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9714 if ((tp->tg3_flags & TG3_FLAG_NVRAM) && 9792 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9715 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && 9793 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9716 (tp->tg3_flags2 & TG3_FLG2_FLASH) && 9794 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9795 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
9717 (tp->nvram_jedecnum == JEDEC_ATMEL)) 9796 (tp->nvram_jedecnum == JEDEC_ATMEL))
9718 9797
9719 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * 9798 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index d8e829f6fcb2..88d08f3ede03 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -124,6 +124,7 @@
124#define ASIC_REV_5906 0x0c 124#define ASIC_REV_5906 0x0c
125#define ASIC_REV_USE_PROD_ID_REG 0x0f 125#define ASIC_REV_USE_PROD_ID_REG 0x0f
126#define ASIC_REV_5784 0x5784 126#define ASIC_REV_5784 0x5784
127#define ASIC_REV_5761 0x5761
127#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) 128#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
128#define CHIPREV_5700_AX 0x70 129#define CHIPREV_5700_AX 0x70
129#define CHIPREV_5700_BX 0x71 130#define CHIPREV_5700_BX 0x71
@@ -1463,6 +1464,22 @@
1463#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002 1464#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1464#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000 1465#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1465#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000 1466#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
1467#define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1468#define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1469#define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1470#define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1471#define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1472#define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1473#define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1474#define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1475#define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1476#define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1477#define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1478#define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1479#define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1480#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1481#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1482#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
1466#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 1483#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1467#define FLASH_5752PAGE_SIZE_256 0x00000000 1484#define FLASH_5752PAGE_SIZE_256 0x00000000
1468#define FLASH_5752PAGE_SIZE_512 0x10000000 1485#define FLASH_5752PAGE_SIZE_512 0x10000000
@@ -1493,9 +1510,11 @@
1493#define ACCESS_ENABLE 0x00000001 1510#define ACCESS_ENABLE 0x00000001
1494#define ACCESS_WR_ENABLE 0x00000002 1511#define ACCESS_WR_ENABLE 0x00000002
1495#define NVRAM_WRITE1 0x00007028 1512#define NVRAM_WRITE1 0x00007028
1496/* 0x702c --> 0x7400 unused */ 1513/* 0x702c unused */
1514
1515#define NVRAM_ADDR_LOCKOUT 0x00007030
1516/* 0x7034 --> 0x7c00 unused */
1497 1517
1498/* 0x7400 --> 0x7c00 unused */
1499#define PCIE_TRANSACTION_CFG 0x00007c04 1518#define PCIE_TRANSACTION_CFG 0x00007c04
1500#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 1519#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
1501#define PCIE_TRANS_CFG_LOM 0x00000020 1520#define PCIE_TRANS_CFG_LOM 0x00000020
@@ -2269,6 +2288,8 @@ struct tg3 {
2269#define TG3_FLG2_PHY_JITTER_BUG 0x20000000 2288#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
2270#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000 2289#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
2271#define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000 2290#define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000
2291 u32 tg3_flags3;
2292#define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001
2272 2293
2273 struct timer_list timer; 2294 struct timer_list timer;
2274 u16 timer_counter; 2295 u16 timer_counter;