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authorManfred Spraul <manfred@colorfullife.com>2005-07-31 12:26:05 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-07-31 12:59:56 -0400
commitdc8216c192795b62f30ca34299fb79e897438372 (patch)
tree383af26fbfd1ae517cbc7ad4626ca3c1ba751da1 /drivers
parentd81c0983de80c956cf37835b0d35adb3ab4bb03a (diff)
[PATCH] forcedeth: Improve ethtool support
This is a multi-part message in MIME format. Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/forcedeth.c171
1 files changed, 90 insertions, 81 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 91f09e583cea..9c49c5ec89bf 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -85,7 +85,8 @@
85 * 0.33: 16 May 2005: Support for MCP51 added. 85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics. 86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added. 87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jul 2005: Add jumbo frame support. 88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
89 * 90 *
90 * Known bugs: 91 * Known bugs:
91 * We suspect that on some hardware no TX done interrupts are generated. 92 * We suspect that on some hardware no TX done interrupts are generated.
@@ -97,7 +98,7 @@
97 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few 98 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
98 * superfluous timer interrupts from the nic. 99 * superfluous timer interrupts from the nic.
99 */ 100 */
100#define FORCEDETH_VERSION "0.36" 101#define FORCEDETH_VERSION "0.37"
101#define DRV_NAME "forcedeth" 102#define DRV_NAME "forcedeth"
102 103
103#include <linux/module.h> 104#include <linux/module.h>
@@ -137,6 +138,7 @@
137#define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */ 138#define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */
138#define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */ 139#define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */
139#define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */ 140#define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */
141#define DEV_HAS_LARGEDESC 0x0020 /* device supports jumbo frames and needs packet format 2 */
140 142
141enum { 143enum {
142 NvRegIrqStatus = 0x000, 144 NvRegIrqStatus = 0x000,
@@ -1846,6 +1848,50 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1846 return 0; 1848 return 0;
1847} 1849}
1848 1850
1851#define FORCEDETH_REGS_VER 1
1852#define FORCEDETH_REGS_SIZE 0x400 /* 256 32-bit registers */
1853
1854static int nv_get_regs_len(struct net_device *dev)
1855{
1856 return FORCEDETH_REGS_SIZE;
1857}
1858
1859static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1860{
1861 struct fe_priv *np = get_nvpriv(dev);
1862 u8 __iomem *base = get_hwbase(dev);
1863 u32 *rbuf = buf;
1864 int i;
1865
1866 regs->version = FORCEDETH_REGS_VER;
1867 spin_lock_irq(&np->lock);
1868 for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
1869 rbuf[i] = readl(base + i*sizeof(u32));
1870 spin_unlock_irq(&np->lock);
1871}
1872
1873static int nv_nway_reset(struct net_device *dev)
1874{
1875 struct fe_priv *np = get_nvpriv(dev);
1876 int ret;
1877
1878 spin_lock_irq(&np->lock);
1879 if (np->autoneg) {
1880 int bmcr;
1881
1882 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1883 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1884 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1885
1886 ret = 0;
1887 } else {
1888 ret = -EINVAL;
1889 }
1890 spin_unlock_irq(&np->lock);
1891
1892 return ret;
1893}
1894
1849static struct ethtool_ops ops = { 1895static struct ethtool_ops ops = {
1850 .get_drvinfo = nv_get_drvinfo, 1896 .get_drvinfo = nv_get_drvinfo,
1851 .get_link = ethtool_op_get_link, 1897 .get_link = ethtool_op_get_link,
@@ -1853,6 +1899,9 @@ static struct ethtool_ops ops = {
1853 .set_wol = nv_set_wol, 1899 .set_wol = nv_set_wol,
1854 .get_settings = nv_get_settings, 1900 .get_settings = nv_get_settings,
1855 .set_settings = nv_set_settings, 1901 .set_settings = nv_set_settings,
1902 .get_regs_len = nv_get_regs_len,
1903 .get_regs = nv_get_regs,
1904 .nway_reset = nv_nway_reset,
1856}; 1905};
1857 1906
1858static int nv_open(struct net_device *dev) 1907static int nv_open(struct net_device *dev)
@@ -2092,18 +2141,13 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
2092 } 2141 }
2093 2142
2094 /* handle different descriptor versions */ 2143 /* handle different descriptor versions */
2095 if (pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 || 2144 np->desc_ver = DESC_VER_1;
2096 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 || 2145 np->pkt_limit = NV_PKTLIMIT_1;
2097 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_3 || 2146 if (id->driver_data & DEV_HAS_LARGEDESC) {
2098 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
2099 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) {
2100 np->desc_ver = DESC_VER_1;
2101 np->pkt_limit = NV_PKTLIMIT_1;
2102 } else {
2103 np->desc_ver = DESC_VER_2; 2147 np->desc_ver = DESC_VER_2;
2104 np->pkt_limit = NV_PKTLIMIT_2; 2148 np->pkt_limit = NV_PKTLIMIT_2;
2105 } 2149 }
2106 2150
2107 err = -ENOMEM; 2151 err = -ENOMEM;
2108 np->base = ioremap(addr, NV_PCI_REGSZ); 2152 np->base = ioremap(addr, NV_PCI_REGSZ);
2109 if (!np->base) 2153 if (!np->base)
@@ -2284,109 +2328,74 @@ static void __devexit nv_remove(struct pci_dev *pci_dev)
2284 2328
2285static struct pci_device_id pci_tbl[] = { 2329static struct pci_device_id pci_tbl[] = {
2286 { /* nForce Ethernet Controller */ 2330 { /* nForce Ethernet Controller */
2287 .vendor = PCI_VENDOR_ID_NVIDIA, 2331 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2288 .device = PCI_DEVICE_ID_NVIDIA_NVENET_1,
2289 .subvendor = PCI_ANY_ID,
2290 .subdevice = PCI_ANY_ID,
2291 .driver_data = DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, 2332 .driver_data = DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2292 }, 2333 },
2293 { /* nForce2 Ethernet Controller */ 2334 { /* nForce2 Ethernet Controller */
2294 .vendor = PCI_VENDOR_ID_NVIDIA, 2335 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2295 .device = PCI_DEVICE_ID_NVIDIA_NVENET_2,
2296 .subvendor = PCI_ANY_ID,
2297 .subdevice = PCI_ANY_ID,
2298 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, 2336 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2299 }, 2337 },
2300 { /* nForce3 Ethernet Controller */ 2338 { /* nForce3 Ethernet Controller */
2301 .vendor = PCI_VENDOR_ID_NVIDIA, 2339 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2302 .device = PCI_DEVICE_ID_NVIDIA_NVENET_3,
2303 .subvendor = PCI_ANY_ID,
2304 .subdevice = PCI_ANY_ID,
2305 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, 2340 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2306 }, 2341 },
2307 { /* nForce3 Ethernet Controller */ 2342 { /* nForce3 Ethernet Controller */
2308 .vendor = PCI_VENDOR_ID_NVIDIA, 2343 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2309 .device = PCI_DEVICE_ID_NVIDIA_NVENET_4, 2344 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
2310 .subvendor = PCI_ANY_ID, 2345 DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2311 .subdevice = PCI_ANY_ID,
2312 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2313 }, 2346 },
2314 { /* nForce3 Ethernet Controller */ 2347 { /* nForce3 Ethernet Controller */
2315 .vendor = PCI_VENDOR_ID_NVIDIA, 2348 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2316 .device = PCI_DEVICE_ID_NVIDIA_NVENET_5, 2349 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
2317 .subvendor = PCI_ANY_ID, 2350 DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2318 .subdevice = PCI_ANY_ID,
2319 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2320 }, 2351 },
2321 { /* nForce3 Ethernet Controller */ 2352 { /* nForce3 Ethernet Controller */
2322 .vendor = PCI_VENDOR_ID_NVIDIA, 2353 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2323 .device = PCI_DEVICE_ID_NVIDIA_NVENET_6, 2354 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
2324 .subvendor = PCI_ANY_ID, 2355 DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2325 .subdevice = PCI_ANY_ID,
2326 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2327 }, 2356 },
2328 { /* nForce3 Ethernet Controller */ 2357 { /* nForce3 Ethernet Controller */
2329 .vendor = PCI_VENDOR_ID_NVIDIA, 2358 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2330 .device = PCI_DEVICE_ID_NVIDIA_NVENET_7, 2359 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
2331 .subvendor = PCI_ANY_ID, 2360 DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2332 .subdevice = PCI_ANY_ID,
2333 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2334 }, 2361 },
2335 { /* CK804 Ethernet Controller */ 2362 { /* CK804 Ethernet Controller */
2336 .vendor = PCI_VENDOR_ID_NVIDIA, 2363 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2337 .device = PCI_DEVICE_ID_NVIDIA_NVENET_8, 2364 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
2338 .subvendor = PCI_ANY_ID, 2365 DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2339 .subdevice = PCI_ANY_ID,
2340 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2341 }, 2366 },
2342 { /* CK804 Ethernet Controller */ 2367 { /* CK804 Ethernet Controller */
2343 .vendor = PCI_VENDOR_ID_NVIDIA, 2368 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2344 .device = PCI_DEVICE_ID_NVIDIA_NVENET_9, 2369 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
2345 .subvendor = PCI_ANY_ID, 2370 DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2346 .subdevice = PCI_ANY_ID,
2347 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2348 }, 2371 },
2349 { /* MCP04 Ethernet Controller */ 2372 { /* MCP04 Ethernet Controller */
2350 .vendor = PCI_VENDOR_ID_NVIDIA, 2373 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2351 .device = PCI_DEVICE_ID_NVIDIA_NVENET_10, 2374 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
2352 .subvendor = PCI_ANY_ID, 2375 DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2353 .subdevice = PCI_ANY_ID,
2354 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2355 }, 2376 },
2356 { /* MCP04 Ethernet Controller */ 2377 { /* MCP04 Ethernet Controller */
2357 .vendor = PCI_VENDOR_ID_NVIDIA, 2378 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2358 .device = PCI_DEVICE_ID_NVIDIA_NVENET_11, 2379 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
2359 .subvendor = PCI_ANY_ID, 2380 DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2360 .subdevice = PCI_ANY_ID,
2361 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2362 }, 2381 },
2363 { /* MCP51 Ethernet Controller */ 2382 { /* MCP51 Ethernet Controller */
2364 .vendor = PCI_VENDOR_ID_NVIDIA, 2383 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2365 .device = PCI_DEVICE_ID_NVIDIA_NVENET_12,
2366 .subvendor = PCI_ANY_ID,
2367 .subdevice = PCI_ANY_ID,
2368 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, 2384 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2369 }, 2385 },
2370 { /* MCP51 Ethernet Controller */ 2386 { /* MCP51 Ethernet Controller */
2371 .vendor = PCI_VENDOR_ID_NVIDIA, 2387 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2372 .device = PCI_DEVICE_ID_NVIDIA_NVENET_13,
2373 .subvendor = PCI_ANY_ID,
2374 .subdevice = PCI_ANY_ID,
2375 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, 2388 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2376 }, 2389 },
2377 { /* MCP55 Ethernet Controller */ 2390 { /* MCP55 Ethernet Controller */
2378 .vendor = PCI_VENDOR_ID_NVIDIA, 2391 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2379 .device = PCI_DEVICE_ID_NVIDIA_NVENET_14, 2392 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
2380 .subvendor = PCI_ANY_ID, 2393 DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2381 .subdevice = PCI_ANY_ID,
2382 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2383 }, 2394 },
2384 { /* MCP55 Ethernet Controller */ 2395 { /* MCP55 Ethernet Controller */
2385 .vendor = PCI_VENDOR_ID_NVIDIA, 2396 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2386 .device = PCI_DEVICE_ID_NVIDIA_NVENET_15, 2397 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
2387 .subvendor = PCI_ANY_ID, 2398 DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2388 .subdevice = PCI_ANY_ID,
2389 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2390 }, 2399 },
2391 {0,}, 2400 {0,},
2392}; 2401};
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