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authorH Hartley Sweeten <hartleys@visionengravers.com>2012-09-24 16:38:39 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-09-26 12:37:32 -0400
commitdc598176bbd7dfbcfcd6177d14b10768c59effae (patch)
tree2b00f6144b029c246659e8d48971d2aa7ac554d7 /drivers
parent7f98961c0d4bdebc4508c59cead7f349e47feb7f (diff)
staging: comedi: s626: remove 'WDInterval' from private data
This variable is never used in the driver. Just remove it. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/comedi/drivers/s626.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/staging/comedi/drivers/s626.c b/drivers/staging/comedi/drivers/s626.c
index 4eb1a6708bdf..0b897375eda6 100644
--- a/drivers/staging/comedi/drivers/s626.c
+++ b/drivers/staging/comedi/drivers/s626.c
@@ -99,7 +99,6 @@ struct s626_private {
99 uint16_t Dacpol; /* Image of DAC polarity register. */ 99 uint16_t Dacpol; /* Image of DAC polarity register. */
100 uint8_t TrimSetpoint[12]; /* Images of TrimDAC setpoints */ 100 uint8_t TrimSetpoint[12]; /* Images of TrimDAC setpoints */
101 /* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */ 101 /* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
102 uint16_t WDInterval; /* Image of MISC2 watchdog interval control bits. */
103 uint32_t I2CAdrs; 102 uint32_t I2CAdrs;
104 /* I2C device address for onboard EEPROM (board rev dependent). */ 103 /* I2C device address for onboard EEPROM (board rev dependent). */
105 /* short I2Cards; */ 104 /* short I2Cards; */
@@ -2666,12 +2665,6 @@ static void s626_initialize(struct comedi_device *dev)
2666 for (chan = 0; chan < S626_DAC_CHANNELS; chan++) 2665 for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
2667 SetDAC(dev, chan, 0); 2666 SetDAC(dev, chan, 0);
2668 2667
2669 /* Init image of watchdog timer interval in WRMISC2. This image
2670 * maintains the value of the control bits of MISC2 are
2671 * continuously reset to zero as long as the WD timer is disabled.
2672 */
2673 devpriv->WDInterval = 0;
2674
2675 /* Init Counter Interrupt enab mask for RDMISC2. This mask is 2668 /* Init Counter Interrupt enab mask for RDMISC2. This mask is
2676 * applied against MISC2 when testing to determine which timer 2669 * applied against MISC2 when testing to determine which timer
2677 * events are requesting interrupt service. 2670 * events are requesting interrupt service.