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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-12 15:05:15 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-12 15:05:15 -0500
commitd027db132b395dabfac208e52a7e510e441bb9d2 (patch)
tree24b055b2385f9848e77e646ce475991d8675c3c4 /drivers
parentd01e4afdbb65e030fd6f1f96c30a558e2eb0f279 (diff)
parent5faf7cbb848da827f6ea1458b5a1c26a44e7510a (diff)
Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC updates from Olof Johansson: "This contains the bulk of new SoC development for this merge window. Two new platforms have been added, the sunxi platforms (Allwinner A1x SoCs) by Maxime Ripard, and a generic Broadcom platform for a new series of ARMv7 platforms from them, where the hope is that we can keep the platform code generic enough to have them all share one mach directory. The new Broadcom platform is contributed by Christian Daudt. Highbank has grown support for Calxeda's next generation of hardware, ECX-2000. clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also taken on maintainership of the platform. Beyond this there has been a bunch of work from a number of people on converting more platforms to IRQ domains, pinctrl conversion, cleanup and general feature enablement across most of the active platforms." Fix up trivial conflicts as per Olof. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits) mfd: vexpress-sysreg: Remove LEDs code irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids irq: versatile: delete dangling variable ARM: sunxi: add missing include for mdelay() ARM: EXYNOS: Avoid early use of of_machine_is_compatible() ARM: dts: add node for PL330 MDMA1 controller for exynos4 ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412 ARM: EXYNOS: add UART3 to DEBUG_LL ports ARM: S3C24XX: Add clkdev entry for camif-upll clock ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers ARM: sunxi: Add missing sun4i.dtsi file pinctrl: samsung: Do not initialise statics to 0 ARM i.MX6: remove gate_mask from pllv3 ARM i.MX6: Fix ethernet PLL clocks ARM i.MX6: rename PLLs according to datasheet ARM i.MX6: Add pwm support ARM i.MX51: Add pwm support ARM i.MX53: Add pwm support ARM: mx5: Replace clk_register_clkdev with clock DT lookup ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/clk-sunxi.c30
-rw-r--r--drivers/clocksource/Kconfig3
-rw-r--r--drivers/clocksource/Makefile1
-rw-r--r--drivers/clocksource/sunxi_timer.c171
-rw-r--r--drivers/cpuidle/Kconfig10
-rw-r--r--drivers/cpuidle/Makefile2
-rw-r--r--drivers/cpuidle/cpuidle-calxeda.c161
-rw-r--r--drivers/irqchip/Kconfig9
-rw-r--r--drivers/irqchip/Makefile2
-rw-r--r--drivers/irqchip/irq-sunxi.c151
-rw-r--r--drivers/irqchip/irq-versatile-fpga.c203
-rw-r--r--drivers/media/platform/soc_camera/mx2_camera.c39
-rw-r--r--drivers/mfd/Kconfig6
-rw-r--r--drivers/mfd/Makefile1
-rw-r--r--drivers/mfd/vexpress-config.c277
-rw-r--r--drivers/mfd/vexpress-sysreg.c475
-rw-r--r--drivers/mtd/maps/Kconfig7
-rw-r--r--drivers/mtd/maps/Makefile1
-rw-r--r--drivers/mtd/maps/cdb89712.c278
-rw-r--r--drivers/mtd/nand/Kconfig13
-rw-r--r--drivers/mtd/nand/Makefile2
-rw-r--r--drivers/mtd/nand/autcpu12.c237
-rw-r--r--drivers/mtd/nand/spia.c176
-rw-r--r--drivers/pinctrl/Kconfig5
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/pinctrl-exynos.c477
-rw-r--r--drivers/pinctrl/pinctrl-exynos.h170
-rw-r--r--drivers/pinctrl/pinctrl-exynos5440.c919
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c207
-rw-r--r--drivers/pinctrl/pinctrl-samsung.h30
-rw-r--r--drivers/sh/clk/cpg.c86
-rw-r--r--drivers/tty/serial/samsung.c3
-rw-r--r--drivers/uio/Kconfig1
-rw-r--r--drivers/uio/uio_pruss.c24
-rw-r--r--drivers/video/clps711xfb.c156
36 files changed, 3064 insertions, 1271 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 2701235d5757..a96bda3d3b84 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -19,6 +19,7 @@ endif
19obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o 19obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
20obj-$(CONFIG_ARCH_U8500) += ux500/ 20obj-$(CONFIG_ARCH_U8500) += ux500/
21obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o 21obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
22obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o
22 23
23# Chip specific 24# Chip specific
24obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o 25obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-sunxi.c b/drivers/clk/clk-sunxi.c
new file mode 100644
index 000000000000..0e831b584ba7
--- /dev/null
+++ b/drivers/clk/clk-sunxi.c
@@ -0,0 +1,30 @@
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/clkdev.h>
19#include <linux/clk/sunxi.h>
20#include <linux/of.h>
21
22static const __initconst struct of_device_id clk_match[] = {
23 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
24 {}
25};
26
27void __init sunxi_init_clocks(void)
28{
29 of_clk_init(clk_match);
30}
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 6a78073c3808..a0985732f1e2 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -22,6 +22,9 @@ config DW_APB_TIMER_OF
22config ARMADA_370_XP_TIMER 22config ARMADA_370_XP_TIMER
23 bool 23 bool
24 24
25config SUNXI_TIMER
26 bool
27
25config CLKSRC_DBX500_PRCMU 28config CLKSRC_DBX500_PRCMU
26 bool "Clocksource PRCMU Timer" 29 bool "Clocksource PRCMU Timer"
27 depends on UX500_SOC_DB8500 30 depends on UX500_SOC_DB8500
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 603be366f762..36f06de4c5ab 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -14,5 +14,6 @@ obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
14obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o 14obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
15obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o 15obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
16obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o 16obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
17obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o
17 18
18obj-$(CONFIG_CLKSRC_ARM_GENERIC) += arm_generic.o 19obj-$(CONFIG_CLKSRC_ARM_GENERIC) += arm_generic.o
diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sunxi_timer.c
new file mode 100644
index 000000000000..3cd1bd3d7aee
--- /dev/null
+++ b/drivers/clocksource/sunxi_timer.c
@@ -0,0 +1,171 @@
1/*
2 * Allwinner A1X SoCs timer handling.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code from
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * Benn Huang <benn@allwinnertech.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqreturn.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25#include <linux/sunxi_timer.h>
26#include <linux/clk/sunxi.h>
27
28#define TIMER_CTL_REG 0x00
29#define TIMER_CTL_ENABLE (1 << 0)
30#define TIMER_IRQ_ST_REG 0x04
31#define TIMER0_CTL_REG 0x10
32#define TIMER0_CTL_ENABLE (1 << 0)
33#define TIMER0_CTL_AUTORELOAD (1 << 1)
34#define TIMER0_CTL_ONESHOT (1 << 7)
35#define TIMER0_INTVAL_REG 0x14
36#define TIMER0_CNTVAL_REG 0x18
37
38#define TIMER_SCAL 16
39
40static void __iomem *timer_base;
41
42static void sunxi_clkevt_mode(enum clock_event_mode mode,
43 struct clock_event_device *clk)
44{
45 u32 u = readl(timer_base + TIMER0_CTL_REG);
46
47 switch (mode) {
48 case CLOCK_EVT_MODE_PERIODIC:
49 u &= ~(TIMER0_CTL_ONESHOT);
50 writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG);
51 break;
52
53 case CLOCK_EVT_MODE_ONESHOT:
54 writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG);
55 break;
56 case CLOCK_EVT_MODE_UNUSED:
57 case CLOCK_EVT_MODE_SHUTDOWN:
58 default:
59 writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG);
60 break;
61 }
62}
63
64static int sunxi_clkevt_next_event(unsigned long evt,
65 struct clock_event_device *unused)
66{
67 u32 u = readl(timer_base + TIMER0_CTL_REG);
68 writel(evt, timer_base + TIMER0_CNTVAL_REG);
69 writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD,
70 timer_base + TIMER0_CTL_REG);
71
72 return 0;
73}
74
75static struct clock_event_device sunxi_clockevent = {
76 .name = "sunxi_tick",
77 .shift = 32,
78 .rating = 300,
79 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
80 .set_mode = sunxi_clkevt_mode,
81 .set_next_event = sunxi_clkevt_next_event,
82};
83
84
85static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
86{
87 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
88
89 writel(0x1, timer_base + TIMER_IRQ_ST_REG);
90 evt->event_handler(evt);
91
92 return IRQ_HANDLED;
93}
94
95static struct irqaction sunxi_timer_irq = {
96 .name = "sunxi_timer0",
97 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
98 .handler = sunxi_timer_interrupt,
99 .dev_id = &sunxi_clockevent,
100};
101
102static struct of_device_id sunxi_timer_dt_ids[] = {
103 { .compatible = "allwinner,sunxi-timer" },
104 { }
105};
106
107static void __init sunxi_timer_init(void)
108{
109 struct device_node *node;
110 unsigned long rate = 0;
111 struct clk *clk;
112 int ret, irq;
113 u32 val;
114
115 node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
116 if (!node)
117 panic("No sunxi timer node");
118
119 timer_base = of_iomap(node, 0);
120 if (!timer_base)
121 panic("Can't map registers");
122
123 irq = irq_of_parse_and_map(node, 0);
124 if (irq <= 0)
125 panic("Can't parse IRQ");
126
127 sunxi_init_clocks();
128
129 clk = of_clk_get(node, 0);
130 if (IS_ERR(clk))
131 panic("Can't get timer clock");
132
133 rate = clk_get_rate(clk);
134
135 writel(rate / (TIMER_SCAL * HZ),
136 timer_base + TIMER0_INTVAL_REG);
137
138 /* set clock source to HOSC, 16 pre-division */
139 val = readl(timer_base + TIMER0_CTL_REG);
140 val &= ~(0x07 << 4);
141 val &= ~(0x03 << 2);
142 val |= (4 << 4) | (1 << 2);
143 writel(val, timer_base + TIMER0_CTL_REG);
144
145 /* set mode to auto reload */
146 val = readl(timer_base + TIMER0_CTL_REG);
147 writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
148
149 ret = setup_irq(irq, &sunxi_timer_irq);
150 if (ret)
151 pr_warn("failed to setup irq %d\n", irq);
152
153 /* Enable timer0 interrupt */
154 val = readl(timer_base + TIMER_CTL_REG);
155 writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
156
157 sunxi_clockevent.mult = div_sc(rate / TIMER_SCAL,
158 NSEC_PER_SEC,
159 sunxi_clockevent.shift);
160 sunxi_clockevent.max_delta_ns = clockevent_delta2ns(0xff,
161 &sunxi_clockevent);
162 sunxi_clockevent.min_delta_ns = clockevent_delta2ns(0x1,
163 &sunxi_clockevent);
164 sunxi_clockevent.cpumask = cpumask_of(0);
165
166 clockevents_register_device(&sunxi_clockevent);
167}
168
169struct sys_timer sunxi_timer = {
170 .init = sunxi_timer_init,
171};
diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
index 234ae651b38f..c4cc27e5c8a5 100644
--- a/drivers/cpuidle/Kconfig
+++ b/drivers/cpuidle/Kconfig
@@ -30,3 +30,13 @@ config CPU_IDLE_GOV_MENU
30 30
31config ARCH_NEEDS_CPU_IDLE_COUPLED 31config ARCH_NEEDS_CPU_IDLE_COUPLED
32 def_bool n 32 def_bool n
33
34if CPU_IDLE
35
36config CPU_IDLE_CALXEDA
37 bool "CPU Idle Driver for Calxeda processors"
38 depends on ARCH_HIGHBANK
39 help
40 Select this to enable cpuidle on Calxeda processors.
41
42endif
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index 38c8f69f30cf..03ee87482c71 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -4,3 +4,5 @@
4 4
5obj-y += cpuidle.o driver.o governor.o sysfs.o governors/ 5obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
6obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o 6obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
7
8obj-$(CONFIG_CPU_IDLE_CALXEDA) += cpuidle-calxeda.o
diff --git a/drivers/cpuidle/cpuidle-calxeda.c b/drivers/cpuidle/cpuidle-calxeda.c
new file mode 100644
index 000000000000..e1aab38c5a8d
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-calxeda.c
@@ -0,0 +1,161 @@
1/*
2 * Copyright 2012 Calxeda, Inc.
3 *
4 * Based on arch/arm/plat-mxc/cpuidle.c:
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Copyright 2012 Linaro Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/cpuidle.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/time.h>
26#include <linux/delay.h>
27#include <linux/suspend.h>
28#include <asm/cpuidle.h>
29#include <asm/proc-fns.h>
30#include <asm/smp_scu.h>
31#include <asm/suspend.h>
32#include <asm/cacheflush.h>
33#include <asm/cp15.h>
34
35extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
36extern void *scu_base_addr;
37
38static struct cpuidle_device __percpu *calxeda_idle_cpuidle_devices;
39
40static inline unsigned int get_auxcr(void)
41{
42 unsigned int val;
43 asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val) : : "cc");
44 return val;
45}
46
47static inline void set_auxcr(unsigned int val)
48{
49 asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
50 : : "r" (val) : "cc");
51 isb();
52}
53
54static noinline void calxeda_idle_restore(void)
55{
56 set_cr(get_cr() | CR_C);
57 set_auxcr(get_auxcr() | 0x40);
58 scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
59}
60
61static int calxeda_idle_finish(unsigned long val)
62{
63 /* Already flushed cache, but do it again as the outer cache functions
64 * dirty the cache with spinlocks */
65 flush_cache_all();
66
67 set_auxcr(get_auxcr() & ~0x40);
68 set_cr(get_cr() & ~CR_C);
69
70 scu_power_mode(scu_base_addr, SCU_PM_DORMANT);
71
72 cpu_do_idle();
73
74 /* Restore things if we didn't enter power-gating */
75 calxeda_idle_restore();
76 return 1;
77}
78
79static int calxeda_pwrdown_idle(struct cpuidle_device *dev,
80 struct cpuidle_driver *drv,
81 int index)
82{
83 highbank_set_cpu_jump(smp_processor_id(), cpu_resume);
84 cpu_suspend(0, calxeda_idle_finish);
85 return index;
86}
87
88static void calxeda_idle_cpuidle_devices_uninit(void)
89{
90 int i;
91 struct cpuidle_device *dev;
92
93 for_each_possible_cpu(i) {
94 dev = per_cpu_ptr(calxeda_idle_cpuidle_devices, i);
95 cpuidle_unregister_device(dev);
96 }
97
98 free_percpu(calxeda_idle_cpuidle_devices);
99}
100
101static struct cpuidle_driver calxeda_idle_driver = {
102 .name = "calxeda_idle",
103 .en_core_tk_irqen = 1,
104 .states = {
105 ARM_CPUIDLE_WFI_STATE,
106 {
107 .name = "PG",
108 .desc = "Power Gate",
109 .flags = CPUIDLE_FLAG_TIME_VALID,
110 .exit_latency = 30,
111 .power_usage = 50,
112 .target_residency = 200,
113 .enter = calxeda_pwrdown_idle,
114 },
115 },
116 .state_count = 2,
117};
118
119static int __init calxeda_cpuidle_init(void)
120{
121 int cpu_id;
122 int ret;
123 struct cpuidle_device *dev;
124 struct cpuidle_driver *drv = &calxeda_idle_driver;
125
126 if (!of_machine_is_compatible("calxeda,highbank"))
127 return -ENODEV;
128
129 ret = cpuidle_register_driver(drv);
130 if (ret)
131 return ret;
132
133 calxeda_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
134 if (calxeda_idle_cpuidle_devices == NULL) {
135 ret = -ENOMEM;
136 goto unregister_drv;
137 }
138
139 /* initialize state data for each cpuidle_device */
140 for_each_possible_cpu(cpu_id) {
141 dev = per_cpu_ptr(calxeda_idle_cpuidle_devices, cpu_id);
142 dev->cpu = cpu_id;
143 dev->state_count = drv->state_count;
144
145 ret = cpuidle_register_device(dev);
146 if (ret) {
147 pr_err("Failed to register cpu %u, error: %d\n",
148 cpu_id, ret);
149 goto uninit;
150 }
151 }
152
153 return 0;
154
155uninit:
156 calxeda_idle_cpuidle_devices_uninit();
157unregister_drv:
158 cpuidle_unregister_driver(drv);
159 return ret;
160}
161module_init(calxeda_cpuidle_init);
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 1bb8bf6d7fd4..62ca575701d3 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -1 +1,8 @@
1# empty 1config VERSATILE_FPGA_IRQ
2 bool
3 select IRQ_DOMAIN
4
5config VERSATILE_FPGA_IRQ_NR
6 int
7 default 4
8 depends on VERSATILE_FPGA_IRQ
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 054321db4350..02bd37a6187f 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1 +1,3 @@
1obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o 1obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
2obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
3obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
diff --git a/drivers/irqchip/irq-sunxi.c b/drivers/irqchip/irq-sunxi.c
new file mode 100644
index 000000000000..10974fa42653
--- /dev/null
+++ b/drivers/irqchip/irq-sunxi.c
@@ -0,0 +1,151 @@
1/*
2 * Allwinner A1X SoCs IRQ chip driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code from
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * Benn Huang <benn@allwinnertech.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22
23#include <linux/irqchip/sunxi.h>
24
25#define SUNXI_IRQ_VECTOR_REG 0x00
26#define SUNXI_IRQ_PROTECTION_REG 0x08
27#define SUNXI_IRQ_NMI_CTRL_REG 0x0c
28#define SUNXI_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
29#define SUNXI_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
30#define SUNXI_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
31#define SUNXI_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
32
33static void __iomem *sunxi_irq_base;
34static struct irq_domain *sunxi_irq_domain;
35
36void sunxi_irq_ack(struct irq_data *irqd)
37{
38 unsigned int irq = irqd_to_hwirq(irqd);
39 unsigned int irq_off = irq % 32;
40 int reg = irq / 32;
41 u32 val;
42
43 val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
44 writel(val | (1 << irq_off),
45 sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
46}
47
48static void sunxi_irq_mask(struct irq_data *irqd)
49{
50 unsigned int irq = irqd_to_hwirq(irqd);
51 unsigned int irq_off = irq % 32;
52 int reg = irq / 32;
53 u32 val;
54
55 val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
56 writel(val & ~(1 << irq_off),
57 sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
58}
59
60static void sunxi_irq_unmask(struct irq_data *irqd)
61{
62 unsigned int irq = irqd_to_hwirq(irqd);
63 unsigned int irq_off = irq % 32;
64 int reg = irq / 32;
65 u32 val;
66
67 val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
68 writel(val | (1 << irq_off),
69 sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
70}
71
72static struct irq_chip sunxi_irq_chip = {
73 .name = "sunxi_irq",
74 .irq_ack = sunxi_irq_ack,
75 .irq_mask = sunxi_irq_mask,
76 .irq_unmask = sunxi_irq_unmask,
77};
78
79static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
80 irq_hw_number_t hw)
81{
82 irq_set_chip_and_handler(virq, &sunxi_irq_chip,
83 handle_level_irq);
84 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
85
86 return 0;
87}
88
89static struct irq_domain_ops sunxi_irq_ops = {
90 .map = sunxi_irq_map,
91 .xlate = irq_domain_xlate_onecell,
92};
93
94static int __init sunxi_of_init(struct device_node *node,
95 struct device_node *parent)
96{
97 sunxi_irq_base = of_iomap(node, 0);
98 if (!sunxi_irq_base)
99 panic("%s: unable to map IC registers\n",
100 node->full_name);
101
102 /* Disable all interrupts */
103 writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
104 writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
105 writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
106
107 /* Mask all the interrupts */
108 writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
109 writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
110 writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));
111
112 /* Clear all the pending interrupts */
113 writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
114 writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
115 writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
116
117 /* Enable protection mode */
118 writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
119
120 /* Configure the external interrupt source type */
121 writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
122
123 sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
124 &sunxi_irq_ops, NULL);
125 if (!sunxi_irq_domain)
126 panic("%s: unable to create IRQ domain\n", node->full_name);
127
128 return 0;
129}
130
131static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
132 { .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init },
133 { }
134};
135
136void __init sunxi_init_irq(void)
137{
138 of_irq_init(sunxi_irq_dt_ids);
139}
140
141asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
142{
143 u32 irq, hwirq;
144
145 hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
146 while (hwirq != 0) {
147 irq = irq_find_mapping(sunxi_irq_domain, hwirq);
148 handle_IRQ(irq, regs);
149 hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
150 }
151}
diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c
new file mode 100644
index 000000000000..9dbd82b716d3
--- /dev/null
+++ b/drivers/irqchip/irq-versatile-fpga.c
@@ -0,0 +1,203 @@
1/*
2 * Support for Versatile FPGA-based IRQ controllers
3 */
4#include <linux/bitops.h>
5#include <linux/irq.h>
6#include <linux/io.h>
7#include <linux/irqchip/versatile-fpga.h>
8#include <linux/irqdomain.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/of_address.h>
12
13#include <asm/exception.h>
14#include <asm/mach/irq.h>
15
16#define IRQ_STATUS 0x00
17#define IRQ_RAW_STATUS 0x04
18#define IRQ_ENABLE_SET 0x08
19#define IRQ_ENABLE_CLEAR 0x0c
20#define INT_SOFT_SET 0x10
21#define INT_SOFT_CLEAR 0x14
22#define FIQ_STATUS 0x20
23#define FIQ_RAW_STATUS 0x24
24#define FIQ_ENABLE 0x28
25#define FIQ_ENABLE_SET 0x28
26#define FIQ_ENABLE_CLEAR 0x2C
27
28/**
29 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
30 * @base: memory offset in virtual memory
31 * @chip: chip container for this instance
32 * @domain: IRQ domain for this instance
33 * @valid: mask for valid IRQs on this controller
34 * @used_irqs: number of active IRQs on this controller
35 */
36struct fpga_irq_data {
37 void __iomem *base;
38 struct irq_chip chip;
39 u32 valid;
40 struct irq_domain *domain;
41 u8 used_irqs;
42};
43
44/* we cannot allocate memory when the controllers are initially registered */
45static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
46static int fpga_irq_id;
47
48static void fpga_irq_mask(struct irq_data *d)
49{
50 struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
51 u32 mask = 1 << d->hwirq;
52
53 writel(mask, f->base + IRQ_ENABLE_CLEAR);
54}
55
56static void fpga_irq_unmask(struct irq_data *d)
57{
58 struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
59 u32 mask = 1 << d->hwirq;
60
61 writel(mask, f->base + IRQ_ENABLE_SET);
62}
63
64static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
65{
66 struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
67 u32 status = readl(f->base + IRQ_STATUS);
68
69 if (status == 0) {
70 do_bad_IRQ(irq, desc);
71 return;
72 }
73
74 do {
75 irq = ffs(status) - 1;
76 status &= ~(1 << irq);
77 generic_handle_irq(irq_find_mapping(f->domain, irq));
78 } while (status);
79}
80
81/*
82 * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero
83 * if we've handled at least one interrupt. This does a single read of the
84 * status register and handles all interrupts in order from LSB first.
85 */
86static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
87{
88 int handled = 0;
89 int irq;
90 u32 status;
91
92 while ((status = readl(f->base + IRQ_STATUS))) {
93 irq = ffs(status) - 1;
94 handle_IRQ(irq_find_mapping(f->domain, irq), regs);
95 handled = 1;
96 }
97
98 return handled;
99}
100
101/*
102 * Keep iterating over all registered FPGA IRQ controllers until there are
103 * no pending interrupts.
104 */
105asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
106{
107 int i, handled;
108
109 do {
110 for (i = 0, handled = 0; i < fpga_irq_id; ++i)
111 handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
112 } while (handled);
113}
114
115static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
116 irq_hw_number_t hwirq)
117{
118 struct fpga_irq_data *f = d->host_data;
119
120 /* Skip invalid IRQs, only register handlers for the real ones */
121 if (!(f->valid & BIT(hwirq)))
122 return -ENOTSUPP;
123 irq_set_chip_data(irq, f);
124 irq_set_chip_and_handler(irq, &f->chip,
125 handle_level_irq);
126 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
127 return 0;
128}
129
130static struct irq_domain_ops fpga_irqdomain_ops = {
131 .map = fpga_irqdomain_map,
132 .xlate = irq_domain_xlate_onetwocell,
133};
134
135void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
136 int parent_irq, u32 valid, struct device_node *node)
137{
138 struct fpga_irq_data *f;
139 int i;
140
141 if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
142 pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
143 return;
144 }
145 f = &fpga_irq_devices[fpga_irq_id];
146 f->base = base;
147 f->chip.name = name;
148 f->chip.irq_ack = fpga_irq_mask;
149 f->chip.irq_mask = fpga_irq_mask;
150 f->chip.irq_unmask = fpga_irq_unmask;
151 f->valid = valid;
152
153 if (parent_irq != -1) {
154 irq_set_handler_data(parent_irq, f);
155 irq_set_chained_handler(parent_irq, fpga_irq_handle);
156 }
157
158 /* This will also allocate irq descriptors */
159 f->domain = irq_domain_add_simple(node, fls(valid), irq_start,
160 &fpga_irqdomain_ops, f);
161
162 /* This will allocate all valid descriptors in the linear case */
163 for (i = 0; i < fls(valid); i++)
164 if (valid & BIT(i)) {
165 if (!irq_start)
166 irq_create_mapping(f->domain, i);
167 f->used_irqs++;
168 }
169
170 pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
171 fpga_irq_id, name, base, f->used_irqs);
172
173 fpga_irq_id++;
174}
175
176#ifdef CONFIG_OF
177int __init fpga_irq_of_init(struct device_node *node,
178 struct device_node *parent)
179{
180 void __iomem *base;
181 u32 clear_mask;
182 u32 valid_mask;
183
184 if (WARN_ON(!node))
185 return -ENODEV;
186
187 base = of_iomap(node, 0);
188 WARN(!base, "unable to map fpga irq registers\n");
189
190 if (of_property_read_u32(node, "clear-mask", &clear_mask))
191 clear_mask = 0;
192
193 if (of_property_read_u32(node, "valid-mask", &valid_mask))
194 valid_mask = 0;
195
196 fpga_irq_init(base, node->name, 0, -1, valid_mask, node);
197
198 writel(clear_mask, base + IRQ_ENABLE_CLEAR);
199 writel(clear_mask, base + FIQ_ENABLE_CLEAR);
200
201 return 0;
202}
203#endif
diff --git a/drivers/media/platform/soc_camera/mx2_camera.c b/drivers/media/platform/soc_camera/mx2_camera.c
index 8ac9b72b5ec7..791cd1d54a76 100644
--- a/drivers/media/platform/soc_camera/mx2_camera.c
+++ b/drivers/media/platform/soc_camera/mx2_camera.c
@@ -278,7 +278,8 @@ struct mx2_camera_dev {
278 struct device *dev; 278 struct device *dev;
279 struct soc_camera_host soc_host; 279 struct soc_camera_host soc_host;
280 struct soc_camera_device *icd; 280 struct soc_camera_device *icd;
281 struct clk *clk_csi, *clk_emma_ahb, *clk_emma_ipg; 281 struct clk *clk_emma_ahb, *clk_emma_ipg;
282 struct clk *clk_csi_ahb, *clk_csi_per;
282 283
283 void __iomem *base_csi, *base_emma; 284 void __iomem *base_csi, *base_emma;
284 285
@@ -464,7 +465,8 @@ static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
464{ 465{
465 unsigned long flags; 466 unsigned long flags;
466 467
467 clk_disable_unprepare(pcdev->clk_csi); 468 clk_disable_unprepare(pcdev->clk_csi_ahb);
469 clk_disable_unprepare(pcdev->clk_csi_per);
468 writel(0, pcdev->base_csi + CSICR1); 470 writel(0, pcdev->base_csi + CSICR1);
469 if (is_imx27_camera(pcdev)) { 471 if (is_imx27_camera(pcdev)) {
470 writel(0, pcdev->base_emma + PRP_CNTL); 472 writel(0, pcdev->base_emma + PRP_CNTL);
@@ -492,10 +494,14 @@ static int mx2_camera_add_device(struct soc_camera_device *icd)
492 if (pcdev->icd) 494 if (pcdev->icd)
493 return -EBUSY; 495 return -EBUSY;
494 496
495 ret = clk_prepare_enable(pcdev->clk_csi); 497 ret = clk_prepare_enable(pcdev->clk_csi_ahb);
496 if (ret < 0) 498 if (ret < 0)
497 return ret; 499 return ret;
498 500
501 ret = clk_prepare_enable(pcdev->clk_csi_per);
502 if (ret < 0)
503 goto exit_csi_ahb;
504
499 csicr1 = CSICR1_MCLKEN; 505 csicr1 = CSICR1_MCLKEN;
500 506
501 if (is_imx27_camera(pcdev)) 507 if (is_imx27_camera(pcdev))
@@ -512,6 +518,11 @@ static int mx2_camera_add_device(struct soc_camera_device *icd)
512 icd->devnum); 518 icd->devnum);
513 519
514 return 0; 520 return 0;
521
522exit_csi_ahb:
523 clk_disable_unprepare(pcdev->clk_csi_ahb);
524
525 return ret;
515} 526}
516 527
517static void mx2_camera_remove_device(struct soc_camera_device *icd) 528static void mx2_camera_remove_device(struct soc_camera_device *icd)
@@ -1777,10 +1788,17 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
1777 break; 1788 break;
1778 } 1789 }
1779 1790
1780 pcdev->clk_csi = devm_clk_get(&pdev->dev, "ahb"); 1791 pcdev->clk_csi_ahb = devm_clk_get(&pdev->dev, "ahb");
1781 if (IS_ERR(pcdev->clk_csi)) { 1792 if (IS_ERR(pcdev->clk_csi_ahb)) {
1782 dev_err(&pdev->dev, "Could not get csi clock\n"); 1793 dev_err(&pdev->dev, "Could not get csi ahb clock\n");
1783 err = PTR_ERR(pcdev->clk_csi); 1794 err = PTR_ERR(pcdev->clk_csi_ahb);
1795 goto exit;
1796 }
1797
1798 pcdev->clk_csi_per = devm_clk_get(&pdev->dev, "per");
1799 if (IS_ERR(pcdev->clk_csi_per)) {
1800 dev_err(&pdev->dev, "Could not get csi per clock\n");
1801 err = PTR_ERR(pcdev->clk_csi_per);
1784 goto exit; 1802 goto exit;
1785 } 1803 }
1786 1804
@@ -1790,12 +1808,13 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
1790 1808
1791 pcdev->platform_flags = pcdev->pdata->flags; 1809 pcdev->platform_flags = pcdev->pdata->flags;
1792 1810
1793 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2); 1811 rate = clk_round_rate(pcdev->clk_csi_per,
1812 pcdev->pdata->clk * 2);
1794 if (rate <= 0) { 1813 if (rate <= 0) {
1795 err = -ENODEV; 1814 err = -ENODEV;
1796 goto exit; 1815 goto exit;
1797 } 1816 }
1798 err = clk_set_rate(pcdev->clk_csi, rate); 1817 err = clk_set_rate(pcdev->clk_csi_per, rate);
1799 if (err < 0) 1818 if (err < 0)
1800 goto exit; 1819 goto exit;
1801 } 1820 }
@@ -1853,7 +1872,7 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
1853 goto exit_free_emma; 1872 goto exit_free_emma;
1854 1873
1855 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n", 1874 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1856 clk_get_rate(pcdev->clk_csi)); 1875 clk_get_rate(pcdev->clk_csi_per));
1857 1876
1858 return 0; 1877 return 0;
1859 1878
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 2c10938b3567..94bdf83b4bc8 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1080,3 +1080,9 @@ config MCP_UCB1200_TS
1080 depends on MCP_UCB1200 && INPUT 1080 depends on MCP_UCB1200 && INPUT
1081 1081
1082endmenu 1082endmenu
1083
1084config VEXPRESS_CONFIG
1085 bool
1086 help
1087 Platform configuration infrastructure for the ARM Ltd.
1088 Versatile Express.
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b53db06d1b46..69f260ae0225 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -141,3 +141,4 @@ obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o
141obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o 141obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o
142obj-$(CONFIG_MFD_SYSCON) += syscon.o 142obj-$(CONFIG_MFD_SYSCON) += syscon.o
143obj-$(CONFIG_MFD_LM3533) += lm3533-core.o lm3533-ctrlbank.o 143obj-$(CONFIG_MFD_LM3533) += lm3533-core.o lm3533-ctrlbank.o
144obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o vexpress-sysreg.o
diff --git a/drivers/mfd/vexpress-config.c b/drivers/mfd/vexpress-config.c
new file mode 100644
index 000000000000..fae15d880758
--- /dev/null
+++ b/drivers/mfd/vexpress-config.c
@@ -0,0 +1,277 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2012 ARM Limited
12 */
13
14#define pr_fmt(fmt) "vexpress-config: " fmt
15
16#include <linux/bitops.h>
17#include <linux/completion.h>
18#include <linux/export.h>
19#include <linux/init.h>
20#include <linux/list.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/slab.h>
24#include <linux/string.h>
25#include <linux/vexpress.h>
26
27
28#define VEXPRESS_CONFIG_MAX_BRIDGES 2
29
30struct vexpress_config_bridge {
31 struct device_node *node;
32 struct vexpress_config_bridge_info *info;
33 struct list_head transactions;
34 spinlock_t transactions_lock;
35} vexpress_config_bridges[VEXPRESS_CONFIG_MAX_BRIDGES];
36
37static DECLARE_BITMAP(vexpress_config_bridges_map,
38 ARRAY_SIZE(vexpress_config_bridges));
39static DEFINE_MUTEX(vexpress_config_bridges_mutex);
40
41struct vexpress_config_bridge *vexpress_config_bridge_register(
42 struct device_node *node,
43 struct vexpress_config_bridge_info *info)
44{
45 struct vexpress_config_bridge *bridge;
46 int i;
47
48 pr_debug("Registering bridge '%s'\n", info->name);
49
50 mutex_lock(&vexpress_config_bridges_mutex);
51 i = find_first_zero_bit(vexpress_config_bridges_map,
52 ARRAY_SIZE(vexpress_config_bridges));
53 if (i >= ARRAY_SIZE(vexpress_config_bridges)) {
54 pr_err("Can't register more bridges!\n");
55 mutex_unlock(&vexpress_config_bridges_mutex);
56 return NULL;
57 }
58 __set_bit(i, vexpress_config_bridges_map);
59 bridge = &vexpress_config_bridges[i];
60
61 bridge->node = node;
62 bridge->info = info;
63 INIT_LIST_HEAD(&bridge->transactions);
64 spin_lock_init(&bridge->transactions_lock);
65
66 mutex_unlock(&vexpress_config_bridges_mutex);
67
68 return bridge;
69}
70
71void vexpress_config_bridge_unregister(struct vexpress_config_bridge *bridge)
72{
73 struct vexpress_config_bridge __bridge = *bridge;
74 int i;
75
76 mutex_lock(&vexpress_config_bridges_mutex);
77 for (i = 0; i < ARRAY_SIZE(vexpress_config_bridges); i++)
78 if (&vexpress_config_bridges[i] == bridge)
79 __clear_bit(i, vexpress_config_bridges_map);
80 mutex_unlock(&vexpress_config_bridges_mutex);
81
82 WARN_ON(!list_empty(&__bridge.transactions));
83 while (!list_empty(&__bridge.transactions))
84 cpu_relax();
85}
86
87
88struct vexpress_config_func {
89 struct vexpress_config_bridge *bridge;
90 void *func;
91};
92
93struct vexpress_config_func *__vexpress_config_func_get(struct device *dev,
94 struct device_node *node)
95{
96 struct device_node *bridge_node;
97 struct vexpress_config_func *func;
98 int i;
99
100 if (WARN_ON(dev && node && dev->of_node != node))
101 return NULL;
102 if (dev && !node)
103 node = dev->of_node;
104
105 func = kzalloc(sizeof(*func), GFP_KERNEL);
106 if (!func)
107 return NULL;
108
109 bridge_node = of_node_get(node);
110 while (bridge_node) {
111 const __be32 *prop = of_get_property(bridge_node,
112 "arm,vexpress,config-bridge", NULL);
113
114 if (prop) {
115 bridge_node = of_find_node_by_phandle(
116 be32_to_cpup(prop));
117 break;
118 }
119
120 bridge_node = of_get_next_parent(bridge_node);
121 }
122
123 mutex_lock(&vexpress_config_bridges_mutex);
124 for (i = 0; i < ARRAY_SIZE(vexpress_config_bridges); i++) {
125 struct vexpress_config_bridge *bridge =
126 &vexpress_config_bridges[i];
127
128 if (test_bit(i, vexpress_config_bridges_map) &&
129 bridge->node == bridge_node) {
130 func->bridge = bridge;
131 func->func = bridge->info->func_get(dev, node);
132 break;
133 }
134 }
135 mutex_unlock(&vexpress_config_bridges_mutex);
136
137 if (!func->func) {
138 of_node_put(node);
139 kfree(func);
140 return NULL;
141 }
142
143 return func;
144}
145
146void vexpress_config_func_put(struct vexpress_config_func *func)
147{
148 func->bridge->info->func_put(func->func);
149 of_node_put(func->bridge->node);
150 kfree(func);
151}
152
153
154struct vexpress_config_trans {
155 struct vexpress_config_func *func;
156 int offset;
157 bool write;
158 u32 *data;
159 int status;
160 struct completion completion;
161 struct list_head list;
162};
163
164static void vexpress_config_dump_trans(const char *what,
165 struct vexpress_config_trans *trans)
166{
167 pr_debug("%s %s trans %p func 0x%p offset %d data 0x%x status %d\n",
168 what, trans->write ? "write" : "read", trans,
169 trans->func->func, trans->offset,
170 trans->data ? *trans->data : 0, trans->status);
171}
172
173static int vexpress_config_schedule(struct vexpress_config_trans *trans)
174{
175 int status;
176 struct vexpress_config_bridge *bridge = trans->func->bridge;
177 unsigned long flags;
178
179 init_completion(&trans->completion);
180 trans->status = -EFAULT;
181
182 spin_lock_irqsave(&bridge->transactions_lock, flags);
183
184 vexpress_config_dump_trans("Executing", trans);
185
186 if (list_empty(&bridge->transactions))
187 status = bridge->info->func_exec(trans->func->func,
188 trans->offset, trans->write, trans->data);
189 else
190 status = VEXPRESS_CONFIG_STATUS_WAIT;
191
192 switch (status) {
193 case VEXPRESS_CONFIG_STATUS_DONE:
194 vexpress_config_dump_trans("Finished", trans);
195 trans->status = status;
196 break;
197 case VEXPRESS_CONFIG_STATUS_WAIT:
198 list_add_tail(&trans->list, &bridge->transactions);
199 break;
200 }
201
202 spin_unlock_irqrestore(&bridge->transactions_lock, flags);
203
204 return status;
205}
206
207void vexpress_config_complete(struct vexpress_config_bridge *bridge,
208 int status)
209{
210 struct vexpress_config_trans *trans;
211 unsigned long flags;
212
213 spin_lock_irqsave(&bridge->transactions_lock, flags);
214
215 trans = list_first_entry(&bridge->transactions,
216 struct vexpress_config_trans, list);
217 vexpress_config_dump_trans("Completed", trans);
218
219 trans->status = status;
220 list_del(&trans->list);
221
222 if (!list_empty(&bridge->transactions)) {
223 vexpress_config_dump_trans("Pending", trans);
224
225 bridge->info->func_exec(trans->func->func, trans->offset,
226 trans->write, trans->data);
227 }
228 spin_unlock_irqrestore(&bridge->transactions_lock, flags);
229
230 complete(&trans->completion);
231}
232
233int vexpress_config_wait(struct vexpress_config_trans *trans)
234{
235 wait_for_completion(&trans->completion);
236
237 return trans->status;
238}
239
240
241int vexpress_config_read(struct vexpress_config_func *func, int offset,
242 u32 *data)
243{
244 struct vexpress_config_trans trans = {
245 .func = func,
246 .offset = offset,
247 .write = false,
248 .data = data,
249 .status = 0,
250 };
251 int status = vexpress_config_schedule(&trans);
252
253 if (status == VEXPRESS_CONFIG_STATUS_WAIT)
254 status = vexpress_config_wait(&trans);
255
256 return status;
257}
258EXPORT_SYMBOL(vexpress_config_read);
259
260int vexpress_config_write(struct vexpress_config_func *func, int offset,
261 u32 data)
262{
263 struct vexpress_config_trans trans = {
264 .func = func,
265 .offset = offset,
266 .write = true,
267 .data = &data,
268 .status = 0,
269 };
270 int status = vexpress_config_schedule(&trans);
271
272 if (status == VEXPRESS_CONFIG_STATUS_WAIT)
273 status = vexpress_config_wait(&trans);
274
275 return status;
276}
277EXPORT_SYMBOL(vexpress_config_write);
diff --git a/drivers/mfd/vexpress-sysreg.c b/drivers/mfd/vexpress-sysreg.c
new file mode 100644
index 000000000000..733c06bd2d17
--- /dev/null
+++ b/drivers/mfd/vexpress-sysreg.c
@@ -0,0 +1,475 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2012 ARM Limited
12 */
13
14#include <linux/err.h>
15#include <linux/gpio.h>
16#include <linux/io.h>
17#include <linux/leds.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
20#include <linux/regulator/driver.h>
21#include <linux/slab.h>
22#include <linux/stat.h>
23#include <linux/timer.h>
24#include <linux/vexpress.h>
25
26#define SYS_ID 0x000
27#define SYS_SW 0x004
28#define SYS_LED 0x008
29#define SYS_100HZ 0x024
30#define SYS_FLAGS 0x030
31#define SYS_FLAGSSET 0x030
32#define SYS_FLAGSCLR 0x034
33#define SYS_NVFLAGS 0x038
34#define SYS_NVFLAGSSET 0x038
35#define SYS_NVFLAGSCLR 0x03c
36#define SYS_MCI 0x048
37#define SYS_FLASH 0x04c
38#define SYS_CFGSW 0x058
39#define SYS_24MHZ 0x05c
40#define SYS_MISC 0x060
41#define SYS_DMA 0x064
42#define SYS_PROCID0 0x084
43#define SYS_PROCID1 0x088
44#define SYS_CFGDATA 0x0a0
45#define SYS_CFGCTRL 0x0a4
46#define SYS_CFGSTAT 0x0a8
47
48#define SYS_HBI_MASK 0xfff
49#define SYS_ID_HBI_SHIFT 16
50#define SYS_PROCIDx_HBI_SHIFT 0
51
52#define SYS_MCI_CARDIN (1 << 0)
53#define SYS_MCI_WPROT (1 << 1)
54
55#define SYS_FLASH_WPn (1 << 0)
56
57#define SYS_MISC_MASTERSITE (1 << 14)
58
59#define SYS_CFGCTRL_START (1 << 31)
60#define SYS_CFGCTRL_WRITE (1 << 30)
61#define SYS_CFGCTRL_DCC(n) (((n) & 0xf) << 26)
62#define SYS_CFGCTRL_FUNC(n) (((n) & 0x3f) << 20)
63#define SYS_CFGCTRL_SITE(n) (((n) & 0x3) << 16)
64#define SYS_CFGCTRL_POSITION(n) (((n) & 0xf) << 12)
65#define SYS_CFGCTRL_DEVICE(n) (((n) & 0xfff) << 0)
66
67#define SYS_CFGSTAT_ERR (1 << 1)
68#define SYS_CFGSTAT_COMPLETE (1 << 0)
69
70
71static void __iomem *vexpress_sysreg_base;
72static struct device *vexpress_sysreg_dev;
73static int vexpress_master_site;
74
75
76void vexpress_flags_set(u32 data)
77{
78 writel(~0, vexpress_sysreg_base + SYS_FLAGSCLR);
79 writel(data, vexpress_sysreg_base + SYS_FLAGSSET);
80}
81
82u32 vexpress_get_procid(int site)
83{
84 if (site == VEXPRESS_SITE_MASTER)
85 site = vexpress_master_site;
86
87 return readl(vexpress_sysreg_base + (site == VEXPRESS_SITE_DB1 ?
88 SYS_PROCID0 : SYS_PROCID1));
89}
90
91u32 vexpress_get_hbi(int site)
92{
93 u32 id;
94
95 switch (site) {
96 case VEXPRESS_SITE_MB:
97 id = readl(vexpress_sysreg_base + SYS_ID);
98 return (id >> SYS_ID_HBI_SHIFT) & SYS_HBI_MASK;
99 case VEXPRESS_SITE_MASTER:
100 case VEXPRESS_SITE_DB1:
101 case VEXPRESS_SITE_DB2:
102 id = vexpress_get_procid(site);
103 return (id >> SYS_PROCIDx_HBI_SHIFT) & SYS_HBI_MASK;
104 }
105
106 return ~0;
107}
108
109void __iomem *vexpress_get_24mhz_clock_base(void)
110{
111 return vexpress_sysreg_base + SYS_24MHZ;
112}
113
114
115static void vexpress_sysreg_find_prop(struct device_node *node,
116 const char *name, u32 *val)
117{
118 of_node_get(node);
119 while (node) {
120 if (of_property_read_u32(node, name, val) == 0) {
121 of_node_put(node);
122 return;
123 }
124 node = of_get_next_parent(node);
125 }
126}
127
128unsigned __vexpress_get_site(struct device *dev, struct device_node *node)
129{
130 u32 site = 0;
131
132 WARN_ON(dev && node && dev->of_node != node);
133 if (dev && !node)
134 node = dev->of_node;
135
136 if (node) {
137 vexpress_sysreg_find_prop(node, "arm,vexpress,site", &site);
138 } else if (dev && dev->bus == &platform_bus_type) {
139 struct platform_device *pdev = to_platform_device(dev);
140
141 if (pdev->num_resources == 1 &&
142 pdev->resource[0].flags == IORESOURCE_BUS)
143 site = pdev->resource[0].start;
144 } else if (dev && strncmp(dev_name(dev), "ct:", 3) == 0) {
145 site = VEXPRESS_SITE_MASTER;
146 }
147
148 if (site == VEXPRESS_SITE_MASTER)
149 site = vexpress_master_site;
150
151 return site;
152}
153
154
155struct vexpress_sysreg_config_func {
156 u32 template;
157 u32 device;
158};
159
160static struct vexpress_config_bridge *vexpress_sysreg_config_bridge;
161static struct timer_list vexpress_sysreg_config_timer;
162static u32 *vexpress_sysreg_config_data;
163static int vexpress_sysreg_config_tries;
164
165static void *vexpress_sysreg_config_func_get(struct device *dev,
166 struct device_node *node)
167{
168 struct vexpress_sysreg_config_func *config_func;
169 u32 site;
170 u32 position = 0;
171 u32 dcc = 0;
172 u32 func_device[2];
173 int err = -EFAULT;
174
175 if (node) {
176 of_node_get(node);
177 vexpress_sysreg_find_prop(node, "arm,vexpress,site", &site);
178 vexpress_sysreg_find_prop(node, "arm,vexpress,position",
179 &position);
180 vexpress_sysreg_find_prop(node, "arm,vexpress,dcc", &dcc);
181 err = of_property_read_u32_array(node,
182 "arm,vexpress-sysreg,func", func_device,
183 ARRAY_SIZE(func_device));
184 of_node_put(node);
185 } else if (dev && dev->bus == &platform_bus_type) {
186 struct platform_device *pdev = to_platform_device(dev);
187
188 if (pdev->num_resources == 1 &&
189 pdev->resource[0].flags == IORESOURCE_BUS) {
190 site = pdev->resource[0].start;
191 func_device[0] = pdev->resource[0].end;
192 func_device[1] = pdev->id;
193 err = 0;
194 }
195 }
196 if (err)
197 return NULL;
198
199 config_func = kzalloc(sizeof(*config_func), GFP_KERNEL);
200 if (!config_func)
201 return NULL;
202
203 config_func->template = SYS_CFGCTRL_DCC(dcc);
204 config_func->template |= SYS_CFGCTRL_FUNC(func_device[0]);
205 config_func->template |= SYS_CFGCTRL_SITE(site == VEXPRESS_SITE_MASTER ?
206 vexpress_master_site : site);
207 config_func->template |= SYS_CFGCTRL_POSITION(position);
208 config_func->device |= func_device[1];
209
210 dev_dbg(vexpress_sysreg_dev, "func 0x%p = 0x%x, %d\n", config_func,
211 config_func->template, config_func->device);
212
213 return config_func;
214}
215
216static void vexpress_sysreg_config_func_put(void *func)
217{
218 kfree(func);
219}
220
221static int vexpress_sysreg_config_func_exec(void *func, int offset,
222 bool write, u32 *data)
223{
224 int status;
225 struct vexpress_sysreg_config_func *config_func = func;
226 u32 command;
227
228 if (WARN_ON(!vexpress_sysreg_base))
229 return -ENOENT;
230
231 command = readl(vexpress_sysreg_base + SYS_CFGCTRL);
232 if (WARN_ON(command & SYS_CFGCTRL_START))
233 return -EBUSY;
234
235 command = SYS_CFGCTRL_START;
236 command |= write ? SYS_CFGCTRL_WRITE : 0;
237 command |= config_func->template;
238 command |= SYS_CFGCTRL_DEVICE(config_func->device + offset);
239
240 /* Use a canary for reads */
241 if (!write)
242 *data = 0xdeadbeef;
243
244 dev_dbg(vexpress_sysreg_dev, "command %x, data %x\n",
245 command, *data);
246 writel(*data, vexpress_sysreg_base + SYS_CFGDATA);
247 writel(0, vexpress_sysreg_base + SYS_CFGSTAT);
248 writel(command, vexpress_sysreg_base + SYS_CFGCTRL);
249 mb();
250
251 if (vexpress_sysreg_dev) {
252 /* Schedule completion check */
253 if (!write)
254 vexpress_sysreg_config_data = data;
255 vexpress_sysreg_config_tries = 100;
256 mod_timer(&vexpress_sysreg_config_timer,
257 jiffies + usecs_to_jiffies(100));
258 status = VEXPRESS_CONFIG_STATUS_WAIT;
259 } else {
260 /* Early execution, no timer available, have to spin */
261 u32 cfgstat;
262
263 do {
264 cpu_relax();
265 cfgstat = readl(vexpress_sysreg_base + SYS_CFGSTAT);
266 } while (!cfgstat);
267
268 if (!write && (cfgstat & SYS_CFGSTAT_COMPLETE))
269 *data = readl(vexpress_sysreg_base + SYS_CFGDATA);
270 status = VEXPRESS_CONFIG_STATUS_DONE;
271
272 if (cfgstat & SYS_CFGSTAT_ERR)
273 status = -EINVAL;
274 }
275
276 return status;
277}
278
279struct vexpress_config_bridge_info vexpress_sysreg_config_bridge_info = {
280 .name = "vexpress-sysreg",
281 .func_get = vexpress_sysreg_config_func_get,
282 .func_put = vexpress_sysreg_config_func_put,
283 .func_exec = vexpress_sysreg_config_func_exec,
284};
285
286static void vexpress_sysreg_config_complete(unsigned long data)
287{
288 int status = VEXPRESS_CONFIG_STATUS_DONE;
289 u32 cfgstat = readl(vexpress_sysreg_base + SYS_CFGSTAT);
290
291 if (cfgstat & SYS_CFGSTAT_ERR)
292 status = -EINVAL;
293 if (!vexpress_sysreg_config_tries--)
294 status = -ETIMEDOUT;
295
296 if (status < 0) {
297 dev_err(vexpress_sysreg_dev, "error %d\n", status);
298 } else if (!(cfgstat & SYS_CFGSTAT_COMPLETE)) {
299 mod_timer(&vexpress_sysreg_config_timer,
300 jiffies + usecs_to_jiffies(50));
301 return;
302 }
303
304 if (vexpress_sysreg_config_data) {
305 *vexpress_sysreg_config_data = readl(vexpress_sysreg_base +
306 SYS_CFGDATA);
307 dev_dbg(vexpress_sysreg_dev, "read data %x\n",
308 *vexpress_sysreg_config_data);
309 vexpress_sysreg_config_data = NULL;
310 }
311
312 vexpress_config_complete(vexpress_sysreg_config_bridge, status);
313}
314
315
316void __init vexpress_sysreg_early_init(void __iomem *base)
317{
318 struct device_node *node = of_find_compatible_node(NULL, NULL,
319 "arm,vexpress-sysreg");
320
321 if (node)
322 base = of_iomap(node, 0);
323
324 if (WARN_ON(!base))
325 return;
326
327 vexpress_sysreg_base = base;
328
329 if (readl(vexpress_sysreg_base + SYS_MISC) & SYS_MISC_MASTERSITE)
330 vexpress_master_site = VEXPRESS_SITE_DB2;
331 else
332 vexpress_master_site = VEXPRESS_SITE_DB1;
333
334 vexpress_sysreg_config_bridge = vexpress_config_bridge_register(
335 node, &vexpress_sysreg_config_bridge_info);
336 WARN_ON(!vexpress_sysreg_config_bridge);
337}
338
339void __init vexpress_sysreg_of_early_init(void)
340{
341 vexpress_sysreg_early_init(NULL);
342}
343
344
345static struct vexpress_sysreg_gpio {
346 unsigned long reg;
347 u32 value;
348} vexpress_sysreg_gpios[] = {
349 [VEXPRESS_GPIO_MMC_CARDIN] = {
350 .reg = SYS_MCI,
351 .value = SYS_MCI_CARDIN,
352 },
353 [VEXPRESS_GPIO_MMC_WPROT] = {
354 .reg = SYS_MCI,
355 .value = SYS_MCI_WPROT,
356 },
357 [VEXPRESS_GPIO_FLASH_WPn] = {
358 .reg = SYS_FLASH,
359 .value = SYS_FLASH_WPn,
360 },
361};
362
363static int vexpress_sysreg_gpio_direction_input(struct gpio_chip *chip,
364 unsigned offset)
365{
366 return 0;
367}
368
369static int vexpress_sysreg_gpio_direction_output(struct gpio_chip *chip,
370 unsigned offset, int value)
371{
372 return 0;
373}
374
375static int vexpress_sysreg_gpio_get(struct gpio_chip *chip,
376 unsigned offset)
377{
378 struct vexpress_sysreg_gpio *gpio = &vexpress_sysreg_gpios[offset];
379 u32 reg_value = readl(vexpress_sysreg_base + gpio->reg);
380
381 return !!(reg_value & gpio->value);
382}
383
384static void vexpress_sysreg_gpio_set(struct gpio_chip *chip,
385 unsigned offset, int value)
386{
387 struct vexpress_sysreg_gpio *gpio = &vexpress_sysreg_gpios[offset];
388 u32 reg_value = readl(vexpress_sysreg_base + gpio->reg);
389
390 if (value)
391 reg_value |= gpio->value;
392 else
393 reg_value &= ~gpio->value;
394
395 writel(reg_value, vexpress_sysreg_base + gpio->reg);
396}
397
398static struct gpio_chip vexpress_sysreg_gpio_chip = {
399 .label = "vexpress-sysreg",
400 .direction_input = vexpress_sysreg_gpio_direction_input,
401 .direction_output = vexpress_sysreg_gpio_direction_output,
402 .get = vexpress_sysreg_gpio_get,
403 .set = vexpress_sysreg_gpio_set,
404 .ngpio = ARRAY_SIZE(vexpress_sysreg_gpios),
405 .base = 0,
406};
407
408
409static ssize_t vexpress_sysreg_sys_id_show(struct device *dev,
410 struct device_attribute *attr, char *buf)
411{
412 return sprintf(buf, "0x%08x\n", readl(vexpress_sysreg_base + SYS_ID));
413}
414
415DEVICE_ATTR(sys_id, S_IRUGO, vexpress_sysreg_sys_id_show, NULL);
416
417static int __devinit vexpress_sysreg_probe(struct platform_device *pdev)
418{
419 int err;
420 struct resource *res = platform_get_resource(pdev,
421 IORESOURCE_MEM, 0);
422
423 if (!devm_request_mem_region(&pdev->dev, res->start,
424 resource_size(res), pdev->name)) {
425 dev_err(&pdev->dev, "Failed to request memory region!\n");
426 return -EBUSY;
427 }
428
429 if (!vexpress_sysreg_base)
430 vexpress_sysreg_base = devm_ioremap(&pdev->dev, res->start,
431 resource_size(res));
432
433 if (!vexpress_sysreg_base) {
434 dev_err(&pdev->dev, "Failed to obtain base address!\n");
435 return -EFAULT;
436 }
437
438 setup_timer(&vexpress_sysreg_config_timer,
439 vexpress_sysreg_config_complete, 0);
440
441 vexpress_sysreg_gpio_chip.dev = &pdev->dev;
442 err = gpiochip_add(&vexpress_sysreg_gpio_chip);
443 if (err) {
444 vexpress_config_bridge_unregister(
445 vexpress_sysreg_config_bridge);
446 dev_err(&pdev->dev, "Failed to register GPIO chip! (%d)\n",
447 err);
448 return err;
449 }
450
451 vexpress_sysreg_dev = &pdev->dev;
452
453 device_create_file(vexpress_sysreg_dev, &dev_attr_sys_id);
454
455 return 0;
456}
457
458static const struct of_device_id vexpress_sysreg_match[] = {
459 { .compatible = "arm,vexpress-sysreg", },
460 {},
461};
462
463static struct platform_driver vexpress_sysreg_driver = {
464 .driver = {
465 .name = "vexpress-sysreg",
466 .of_match_table = vexpress_sysreg_match,
467 },
468 .probe = vexpress_sysreg_probe,
469};
470
471static int __init vexpress_sysreg_init(void)
472{
473 return platform_driver_register(&vexpress_sysreg_driver);
474}
475core_initcall(vexpress_sysreg_init);
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 2e47c2ed0a2d..df304868bebb 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -324,13 +324,6 @@ config MTD_SOLUTIONENGINE
324 This enables access to the flash chips on the Hitachi SolutionEngine and 324 This enables access to the flash chips on the Hitachi SolutionEngine and
325 similar boards. Say 'Y' if you are building a kernel for such a board. 325 similar boards. Say 'Y' if you are building a kernel for such a board.
326 326
327config MTD_CDB89712
328 tristate "Cirrus CDB89712 evaluation board mappings"
329 depends on MTD_CFI && ARCH_CDB89712
330 help
331 This enables access to the flash or ROM chips on the CDB89712 board.
332 If you have such a board, say 'Y'.
333
334config MTD_SA1100 327config MTD_SA1100
335 tristate "CFI Flash device mapped on StrongARM SA11x0" 328 tristate "CFI Flash device mapped on StrongARM SA11x0"
336 depends on MTD_CFI && ARCH_SA1100 329 depends on MTD_CFI && ARCH_SA1100
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index deb43e9a1e7f..a0240edd1961 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_MTD) += map_funcs.o
7endif 7endif
8 8
9# Chip mappings 9# Chip mappings
10obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
11obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o 10obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
12obj-$(CONFIG_MTD_DC21285) += dc21285.o 11obj-$(CONFIG_MTD_DC21285) += dc21285.o
13obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o 12obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o
diff --git a/drivers/mtd/maps/cdb89712.c b/drivers/mtd/maps/cdb89712.c
deleted file mode 100644
index c29cbf87ea0c..000000000000
--- a/drivers/mtd/maps/cdb89712.c
+++ /dev/null
@@ -1,278 +0,0 @@
1/*
2 * Flash on Cirrus CDB89712
3 *
4 */
5
6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/kernel.h>
9#include <linux/ioport.h>
10#include <linux/init.h>
11#include <asm/io.h>
12#include <mach/hardware.h>
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/map.h>
15#include <linux/mtd/partitions.h>
16
17/* dynamic ioremap() areas */
18#define FLASH_START 0x00000000
19#define FLASH_SIZE 0x800000
20#define FLASH_WIDTH 4
21
22#define SRAM_START 0x60000000
23#define SRAM_SIZE 0xc000
24#define SRAM_WIDTH 4
25
26#define BOOTROM_START 0x70000000
27#define BOOTROM_SIZE 0x80
28#define BOOTROM_WIDTH 4
29
30
31static struct mtd_info *flash_mtd;
32
33struct map_info cdb89712_flash_map = {
34 .name = "flash",
35 .size = FLASH_SIZE,
36 .bankwidth = FLASH_WIDTH,
37 .phys = FLASH_START,
38};
39
40struct resource cdb89712_flash_resource = {
41 .name = "Flash",
42 .start = FLASH_START,
43 .end = FLASH_START + FLASH_SIZE - 1,
44 .flags = IORESOURCE_IO | IORESOURCE_BUSY,
45};
46
47static int __init init_cdb89712_flash (void)
48{
49 int err;
50
51 if (request_resource (&ioport_resource, &cdb89712_flash_resource)) {
52 printk(KERN_NOTICE "Failed to reserve Cdb89712 FLASH space\n");
53 err = -EBUSY;
54 goto out;
55 }
56
57 cdb89712_flash_map.virt = ioremap(FLASH_START, FLASH_SIZE);
58 if (!cdb89712_flash_map.virt) {
59 printk(KERN_NOTICE "Failed to ioremap Cdb89712 FLASH space\n");
60 err = -EIO;
61 goto out_resource;
62 }
63 simple_map_init(&cdb89712_flash_map);
64 flash_mtd = do_map_probe("cfi_probe", &cdb89712_flash_map);
65 if (!flash_mtd) {
66 flash_mtd = do_map_probe("map_rom", &cdb89712_flash_map);
67 if (flash_mtd)
68 flash_mtd->erasesize = 0x10000;
69 }
70 if (!flash_mtd) {
71 printk("FLASH probe failed\n");
72 err = -ENXIO;
73 goto out_ioremap;
74 }
75
76 flash_mtd->owner = THIS_MODULE;
77
78 if (mtd_device_register(flash_mtd, NULL, 0)) {
79 printk("FLASH device addition failed\n");
80 err = -ENOMEM;
81 goto out_probe;
82 }
83
84 return 0;
85
86out_probe:
87 map_destroy(flash_mtd);
88 flash_mtd = 0;
89out_ioremap:
90 iounmap((void *)cdb89712_flash_map.virt);
91out_resource:
92 release_resource (&cdb89712_flash_resource);
93out:
94 return err;
95}
96
97
98
99
100
101static struct mtd_info *sram_mtd;
102
103struct map_info cdb89712_sram_map = {
104 .name = "SRAM",
105 .size = SRAM_SIZE,
106 .bankwidth = SRAM_WIDTH,
107 .phys = SRAM_START,
108};
109
110struct resource cdb89712_sram_resource = {
111 .name = "SRAM",
112 .start = SRAM_START,
113 .end = SRAM_START + SRAM_SIZE - 1,
114 .flags = IORESOURCE_IO | IORESOURCE_BUSY,
115};
116
117static int __init init_cdb89712_sram (void)
118{
119 int err;
120
121 if (request_resource (&ioport_resource, &cdb89712_sram_resource)) {
122 printk(KERN_NOTICE "Failed to reserve Cdb89712 SRAM space\n");
123 err = -EBUSY;
124 goto out;
125 }
126
127 cdb89712_sram_map.virt = ioremap(SRAM_START, SRAM_SIZE);
128 if (!cdb89712_sram_map.virt) {
129 printk(KERN_NOTICE "Failed to ioremap Cdb89712 SRAM space\n");
130 err = -EIO;
131 goto out_resource;
132 }
133 simple_map_init(&cdb89712_sram_map);
134 sram_mtd = do_map_probe("map_ram", &cdb89712_sram_map);
135 if (!sram_mtd) {
136 printk("SRAM probe failed\n");
137 err = -ENXIO;
138 goto out_ioremap;
139 }
140
141 sram_mtd->owner = THIS_MODULE;
142 sram_mtd->erasesize = 16;
143
144 if (mtd_device_register(sram_mtd, NULL, 0)) {
145 printk("SRAM device addition failed\n");
146 err = -ENOMEM;
147 goto out_probe;
148 }
149
150 return 0;
151
152out_probe:
153 map_destroy(sram_mtd);
154 sram_mtd = 0;
155out_ioremap:
156 iounmap((void *)cdb89712_sram_map.virt);
157out_resource:
158 release_resource (&cdb89712_sram_resource);
159out:
160 return err;
161}
162
163
164
165
166
167
168
169static struct mtd_info *bootrom_mtd;
170
171struct map_info cdb89712_bootrom_map = {
172 .name = "BootROM",
173 .size = BOOTROM_SIZE,
174 .bankwidth = BOOTROM_WIDTH,
175 .phys = BOOTROM_START,
176};
177
178struct resource cdb89712_bootrom_resource = {
179 .name = "BootROM",
180 .start = BOOTROM_START,
181 .end = BOOTROM_START + BOOTROM_SIZE - 1,
182 .flags = IORESOURCE_IO | IORESOURCE_BUSY,
183};
184
185static int __init init_cdb89712_bootrom (void)
186{
187 int err;
188
189 if (request_resource (&ioport_resource, &cdb89712_bootrom_resource)) {
190 printk(KERN_NOTICE "Failed to reserve Cdb89712 BOOTROM space\n");
191 err = -EBUSY;
192 goto out;
193 }
194
195 cdb89712_bootrom_map.virt = ioremap(BOOTROM_START, BOOTROM_SIZE);
196 if (!cdb89712_bootrom_map.virt) {
197 printk(KERN_NOTICE "Failed to ioremap Cdb89712 BootROM space\n");
198 err = -EIO;
199 goto out_resource;
200 }
201 simple_map_init(&cdb89712_bootrom_map);
202 bootrom_mtd = do_map_probe("map_rom", &cdb89712_bootrom_map);
203 if (!bootrom_mtd) {
204 printk("BootROM probe failed\n");
205 err = -ENXIO;
206 goto out_ioremap;
207 }
208
209 bootrom_mtd->owner = THIS_MODULE;
210 bootrom_mtd->erasesize = 0x10000;
211
212 if (mtd_device_register(bootrom_mtd, NULL, 0)) {
213 printk("BootROM device addition failed\n");
214 err = -ENOMEM;
215 goto out_probe;
216 }
217
218 return 0;
219
220out_probe:
221 map_destroy(bootrom_mtd);
222 bootrom_mtd = 0;
223out_ioremap:
224 iounmap((void *)cdb89712_bootrom_map.virt);
225out_resource:
226 release_resource (&cdb89712_bootrom_resource);
227out:
228 return err;
229}
230
231
232
233
234
235static int __init init_cdb89712_maps(void)
236{
237
238 printk(KERN_INFO "Cirrus CDB89712 MTD mappings:\n Flash 0x%x at 0x%x\n SRAM 0x%x at 0x%x\n BootROM 0x%x at 0x%x\n",
239 FLASH_SIZE, FLASH_START, SRAM_SIZE, SRAM_START, BOOTROM_SIZE, BOOTROM_START);
240
241 init_cdb89712_flash();
242 init_cdb89712_sram();
243 init_cdb89712_bootrom();
244
245 return 0;
246}
247
248
249static void __exit cleanup_cdb89712_maps(void)
250{
251 if (sram_mtd) {
252 mtd_device_unregister(sram_mtd);
253 map_destroy(sram_mtd);
254 iounmap((void *)cdb89712_sram_map.virt);
255 release_resource (&cdb89712_sram_resource);
256 }
257
258 if (flash_mtd) {
259 mtd_device_unregister(flash_mtd);
260 map_destroy(flash_mtd);
261 iounmap((void *)cdb89712_flash_map.virt);
262 release_resource (&cdb89712_flash_resource);
263 }
264
265 if (bootrom_mtd) {
266 mtd_device_unregister(bootrom_mtd);
267 map_destroy(bootrom_mtd);
268 iounmap((void *)cdb89712_bootrom_map.virt);
269 release_resource (&cdb89712_bootrom_resource);
270 }
271}
272
273module_init(init_cdb89712_maps);
274module_exit(cleanup_cdb89712_maps);
275
276MODULE_AUTHOR("Ray L");
277MODULE_DESCRIPTION("ARM CDB89712 map driver");
278MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 4883139460be..531807dec6b3 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -49,13 +49,6 @@ config MTD_NAND_MUSEUM_IDS
49 NAND chips (page size 256 byte, erase size 4-8KiB). The IDs 49 NAND chips (page size 256 byte, erase size 4-8KiB). The IDs
50 of these chips were reused by later, larger chips. 50 of these chips were reused by later, larger chips.
51 51
52config MTD_NAND_AUTCPU12
53 tristate "SmartMediaCard on autronix autcpu12 board"
54 depends on ARCH_AUTCPU12
55 help
56 This enables the driver for the autronix autcpu12 board to
57 access the SmartMediaCard.
58
59config MTD_NAND_DENALI 52config MTD_NAND_DENALI
60 depends on PCI 53 depends on PCI
61 tristate "Support Denali NAND controller on Intel Moorestown" 54 tristate "Support Denali NAND controller on Intel Moorestown"
@@ -86,12 +79,6 @@ config MTD_NAND_GPIO
86 help 79 help
87 This enables a GPIO based NAND flash driver. 80 This enables a GPIO based NAND flash driver.
88 81
89config MTD_NAND_SPIA
90 tristate "NAND Flash device on SPIA board"
91 depends on ARCH_P720T
92 help
93 If you had to ask, you don't have one. Say 'N'.
94
95config MTD_NAND_AMS_DELTA 82config MTD_NAND_AMS_DELTA
96 tristate "NAND Flash device on Amstrad E3" 83 tristate "NAND Flash device on Amstrad E3"
97 depends on MACH_AMS_DELTA 84 depends on MACH_AMS_DELTA
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 2cbd0916b733..6c7f2b3ca8ae 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -9,9 +9,7 @@ obj-$(CONFIG_MTD_NAND_IDS) += nand_ids.o
9obj-$(CONFIG_MTD_SM_COMMON) += sm_common.o 9obj-$(CONFIG_MTD_SM_COMMON) += sm_common.o
10 10
11obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o 11obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o
12obj-$(CONFIG_MTD_NAND_SPIA) += spia.o
13obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o 12obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o
14obj-$(CONFIG_MTD_NAND_AUTCPU12) += autcpu12.o
15obj-$(CONFIG_MTD_NAND_DENALI) += denali.o 13obj-$(CONFIG_MTD_NAND_DENALI) += denali.o
16obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o 14obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
17obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o 15obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o
diff --git a/drivers/mtd/nand/autcpu12.c b/drivers/mtd/nand/autcpu12.c
deleted file mode 100644
index 04769a49a7cb..000000000000
--- a/drivers/mtd/nand/autcpu12.c
+++ /dev/null
@@ -1,237 +0,0 @@
1/*
2 * drivers/mtd/autcpu12.c
3 *
4 * Copyright (c) 2002 Thomas Gleixner <tgxl@linutronix.de>
5 *
6 * Derived from drivers/mtd/spia.c
7 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Overview:
14 * This is a device driver for the NAND flash device found on the
15 * autronix autcpu12 board, which is a SmartMediaCard. It supports
16 * 16MiB, 32MiB and 64MiB cards.
17 *
18 *
19 * 02-12-2002 TG Cleanup of module params
20 *
21 * 02-20-2002 TG adjusted for different rd/wr address support
22 * added support for read device ready/busy line
23 * added page_cache
24 *
25 * 10-06-2002 TG 128K card support added
26 */
27
28#include <linux/slab.h>
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/mtd/mtd.h>
32#include <linux/mtd/nand.h>
33#include <linux/mtd/partitions.h>
34#include <asm/io.h>
35#include <mach/hardware.h>
36#include <asm/sizes.h>
37#include <mach/autcpu12.h>
38
39/*
40 * MTD structure for AUTCPU12 board
41 */
42static struct mtd_info *autcpu12_mtd = NULL;
43static void __iomem *autcpu12_fio_base;
44
45/*
46 * Define partitions for flash devices
47 */
48static struct mtd_partition partition_info16k[] = {
49 { .name = "AUTCPU12 flash partition 1",
50 .offset = 0,
51 .size = 8 * SZ_1M },
52 { .name = "AUTCPU12 flash partition 2",
53 .offset = 8 * SZ_1M,
54 .size = 8 * SZ_1M },
55};
56
57static struct mtd_partition partition_info32k[] = {
58 { .name = "AUTCPU12 flash partition 1",
59 .offset = 0,
60 .size = 8 * SZ_1M },
61 { .name = "AUTCPU12 flash partition 2",
62 .offset = 8 * SZ_1M,
63 .size = 24 * SZ_1M },
64};
65
66static struct mtd_partition partition_info64k[] = {
67 { .name = "AUTCPU12 flash partition 1",
68 .offset = 0,
69 .size = 16 * SZ_1M },
70 { .name = "AUTCPU12 flash partition 2",
71 .offset = 16 * SZ_1M,
72 .size = 48 * SZ_1M },
73};
74
75static struct mtd_partition partition_info128k[] = {
76 { .name = "AUTCPU12 flash partition 1",
77 .offset = 0,
78 .size = 16 * SZ_1M },
79 { .name = "AUTCPU12 flash partition 2",
80 .offset = 16 * SZ_1M,
81 .size = 112 * SZ_1M },
82};
83
84#define NUM_PARTITIONS16K 2
85#define NUM_PARTITIONS32K 2
86#define NUM_PARTITIONS64K 2
87#define NUM_PARTITIONS128K 2
88/*
89 * hardware specific access to control-lines
90 *
91 * ALE bit 4 autcpu12_pedr
92 * CLE bit 5 autcpu12_pedr
93 * NCE bit 0 fio_ctrl
94 *
95 */
96static void autcpu12_hwcontrol(struct mtd_info *mtd, int cmd,
97 unsigned int ctrl)
98{
99 struct nand_chip *chip = mtd->priv;
100
101 if (ctrl & NAND_CTRL_CHANGE) {
102 void __iomem *addr;
103 unsigned char bits;
104
105 bits = clps_readb(AUTCPU12_SMC_PORT_OFFSET) & ~0x30;
106 bits |= (ctrl & NAND_CLE) << 4;
107 bits |= (ctrl & NAND_ALE) << 2;
108 clps_writeb(bits, AUTCPU12_SMC_PORT_OFFSET);
109
110 addr = autcpu12_fio_base + AUTCPU12_SMC_SELECT_OFFSET;
111 writeb((readb(addr) & ~0x1) | (ctrl & NAND_NCE), addr);
112 }
113
114 if (cmd != NAND_CMD_NONE)
115 writeb(cmd, chip->IO_ADDR_W);
116}
117
118/*
119 * read device ready pin
120 */
121int autcpu12_device_ready(struct mtd_info *mtd)
122{
123 return clps_readb(AUTCPU12_SMC_PORT_OFFSET) & AUTCPU12_SMC_RDY;
124}
125
126/*
127 * Main initialization routine
128 */
129static int __init autcpu12_init(void)
130{
131 struct nand_chip *this;
132 int err = 0;
133
134 /* Allocate memory for MTD device structure and private data */
135 autcpu12_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
136 GFP_KERNEL);
137 if (!autcpu12_mtd) {
138 printk("Unable to allocate AUTCPU12 NAND MTD device structure.\n");
139 err = -ENOMEM;
140 goto out;
141 }
142
143 /* map physical address */
144 autcpu12_fio_base = ioremap(AUTCPU12_PHYS_SMC, SZ_1K);
145 if (!autcpu12_fio_base) {
146 printk("Ioremap autcpu12 SmartMedia Card failed\n");
147 err = -EIO;
148 goto out_mtd;
149 }
150
151 /* Get pointer to private data */
152 this = (struct nand_chip *)(&autcpu12_mtd[1]);
153
154 /* Initialize structures */
155 memset(autcpu12_mtd, 0, sizeof(struct mtd_info));
156 memset(this, 0, sizeof(struct nand_chip));
157
158 /* Link the private data with the MTD structure */
159 autcpu12_mtd->priv = this;
160 autcpu12_mtd->owner = THIS_MODULE;
161
162 /* Set address of NAND IO lines */
163 this->IO_ADDR_R = autcpu12_fio_base;
164 this->IO_ADDR_W = autcpu12_fio_base;
165 this->cmd_ctrl = autcpu12_hwcontrol;
166 this->dev_ready = autcpu12_device_ready;
167 /* 20 us command delay time */
168 this->chip_delay = 20;
169 this->ecc.mode = NAND_ECC_SOFT;
170
171 /* Enable the following for a flash based bad block table */
172 /*
173 this->bbt_options = NAND_BBT_USE_FLASH;
174 */
175 this->bbt_options = NAND_BBT_USE_FLASH;
176
177 /* Scan to find existence of the device */
178 if (nand_scan(autcpu12_mtd, 1)) {
179 err = -ENXIO;
180 goto out_ior;
181 }
182
183 /* Register the partitions */
184 switch (autcpu12_mtd->size) {
185 case SZ_16M:
186 mtd_device_register(autcpu12_mtd, partition_info16k,
187 NUM_PARTITIONS16K);
188 break;
189 case SZ_32M:
190 mtd_device_register(autcpu12_mtd, partition_info32k,
191 NUM_PARTITIONS32K);
192 break;
193 case SZ_64M:
194 mtd_device_register(autcpu12_mtd, partition_info64k,
195 NUM_PARTITIONS64K);
196 break;
197 case SZ_128M:
198 mtd_device_register(autcpu12_mtd, partition_info128k,
199 NUM_PARTITIONS128K);
200 break;
201 default:
202 printk("Unsupported SmartMedia device\n");
203 err = -ENXIO;
204 goto out_ior;
205 }
206 goto out;
207
208 out_ior:
209 iounmap(autcpu12_fio_base);
210 out_mtd:
211 kfree(autcpu12_mtd);
212 out:
213 return err;
214}
215
216module_init(autcpu12_init);
217
218/*
219 * Clean up routine
220 */
221static void __exit autcpu12_cleanup(void)
222{
223 /* Release resources, unregister device */
224 nand_release(autcpu12_mtd);
225
226 /* unmap physical address */
227 iounmap(autcpu12_fio_base);
228
229 /* Free the MTD device structure */
230 kfree(autcpu12_mtd);
231}
232
233module_exit(autcpu12_cleanup);
234
235MODULE_LICENSE("GPL");
236MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
237MODULE_DESCRIPTION("Glue layer for SmartMediaCard on autronix autcpu12");
diff --git a/drivers/mtd/nand/spia.c b/drivers/mtd/nand/spia.c
deleted file mode 100644
index bef76cd7c24c..000000000000
--- a/drivers/mtd/nand/spia.c
+++ /dev/null
@@ -1,176 +0,0 @@
1/*
2 * drivers/mtd/nand/spia.c
3 *
4 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
5 *
6 *
7 * 10-29-2001 TG change to support hardwarespecific access
8 * to controllines (due to change in nand.c)
9 * page_cache added
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * Overview:
16 * This is a device driver for the NAND flash device found on the
17 * SPIA board which utilizes the Toshiba TC58V64AFT part. This is
18 * a 64Mibit (8MiB x 8 bits) NAND flash device.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/slab.h>
24#include <linux/module.h>
25#include <linux/mtd/mtd.h>
26#include <linux/mtd/nand.h>
27#include <linux/mtd/partitions.h>
28#include <asm/io.h>
29
30/*
31 * MTD structure for SPIA board
32 */
33static struct mtd_info *spia_mtd = NULL;
34
35/*
36 * Values specific to the SPIA board (used with EP7212 processor)
37 */
38#define SPIA_IO_BASE 0xd0000000 /* Start of EP7212 IO address space */
39#define SPIA_FIO_BASE 0xf0000000 /* Address where flash is mapped */
40#define SPIA_PEDR 0x0080 /*
41 * IO offset to Port E data register
42 * where the CLE, ALE and NCE pins
43 * are wired to.
44 */
45#define SPIA_PEDDR 0x00c0 /*
46 * IO offset to Port E data direction
47 * register so we can control the IO
48 * lines.
49 */
50
51/*
52 * Module stuff
53 */
54
55static int spia_io_base = SPIA_IO_BASE;
56static int spia_fio_base = SPIA_FIO_BASE;
57static int spia_pedr = SPIA_PEDR;
58static int spia_peddr = SPIA_PEDDR;
59
60module_param(spia_io_base, int, 0);
61module_param(spia_fio_base, int, 0);
62module_param(spia_pedr, int, 0);
63module_param(spia_peddr, int, 0);
64
65/*
66 * Define partitions for flash device
67 */
68static const struct mtd_partition partition_info[] = {
69 {
70 .name = "SPIA flash partition 1",
71 .offset = 0,
72 .size = 2 * 1024 * 1024},
73 {
74 .name = "SPIA flash partition 2",
75 .offset = 2 * 1024 * 1024,
76 .size = 6 * 1024 * 1024}
77};
78
79#define NUM_PARTITIONS 2
80
81/*
82 * hardware specific access to control-lines
83 *
84 * ctrl:
85 * NAND_CNE: bit 0 -> bit 2
86 * NAND_CLE: bit 1 -> bit 0
87 * NAND_ALE: bit 2 -> bit 1
88 */
89static void spia_hwcontrol(struct mtd_info *mtd, int cmd)
90{
91 struct nand_chip *chip = mtd->priv;
92
93 if (ctrl & NAND_CTRL_CHANGE) {
94 void __iomem *addr = spia_io_base + spia_pedr;
95 unsigned char bits;
96
97 bits = (ctrl & NAND_CNE) << 2;
98 bits |= (ctrl & NAND_CLE | NAND_ALE) >> 1;
99 writeb((readb(addr) & ~0x7) | bits, addr);
100 }
101
102 if (cmd != NAND_CMD_NONE)
103 writeb(cmd, chip->IO_ADDR_W);
104}
105
106/*
107 * Main initialization routine
108 */
109static int __init spia_init(void)
110{
111 struct nand_chip *this;
112
113 /* Allocate memory for MTD device structure and private data */
114 spia_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
115 if (!spia_mtd) {
116 printk("Unable to allocate SPIA NAND MTD device structure.\n");
117 return -ENOMEM;
118 }
119
120 /* Get pointer to private data */
121 this = (struct nand_chip *)(&spia_mtd[1]);
122
123 /* Initialize structures */
124 memset(spia_mtd, 0, sizeof(struct mtd_info));
125 memset(this, 0, sizeof(struct nand_chip));
126
127 /* Link the private data with the MTD structure */
128 spia_mtd->priv = this;
129 spia_mtd->owner = THIS_MODULE;
130
131 /*
132 * Set GPIO Port E control register so that the pins are configured
133 * to be outputs for controlling the NAND flash.
134 */
135 (*(volatile unsigned char *)(spia_io_base + spia_peddr)) = 0x07;
136
137 /* Set address of NAND IO lines */
138 this->IO_ADDR_R = (void __iomem *)spia_fio_base;
139 this->IO_ADDR_W = (void __iomem *)spia_fio_base;
140 /* Set address of hardware control function */
141 this->cmd_ctrl = spia_hwcontrol;
142 /* 15 us command delay time */
143 this->chip_delay = 15;
144
145 /* Scan to find existence of the device */
146 if (nand_scan(spia_mtd, 1)) {
147 kfree(spia_mtd);
148 return -ENXIO;
149 }
150
151 /* Register the partitions */
152 mtd_device_register(spia_mtd, partition_info, NUM_PARTITIONS);
153
154 /* Return happy */
155 return 0;
156}
157
158module_init(spia_init);
159
160/*
161 * Clean up routine
162 */
163static void __exit spia_cleanup(void)
164{
165 /* Release resources, unregister device */
166 nand_release(spia_mtd);
167
168 /* Free the MTD device structure */
169 kfree(spia_mtd);
170}
171
172module_exit(spia_cleanup);
173
174MODULE_LICENSE("GPL");
175MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com");
176MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on SPIA board");
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 390ab69ea569..c31aeb01bb00 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -190,6 +190,11 @@ config PINCTRL_EXYNOS4
190 depends on OF && GPIOLIB 190 depends on OF && GPIOLIB
191 select PINCTRL_SAMSUNG 191 select PINCTRL_SAMSUNG
192 192
193config PINCTRL_EXYNOS5440
194 bool "Samsung EXYNOS5440 SoC pinctrl driver"
195 select PINMUX
196 select PINCONF
197
193source "drivers/pinctrl/mvebu/Kconfig" 198source "drivers/pinctrl/mvebu/Kconfig"
194 199
195source "drivers/pinctrl/spear/Kconfig" 200source "drivers/pinctrl/spear/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f95f5ed923be..fc4606f27dc7 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
37obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o 37obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
38obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o 38obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
39obj-$(CONFIG_PINCTRL_EXYNOS4) += pinctrl-exynos.o 39obj-$(CONFIG_PINCTRL_EXYNOS4) += pinctrl-exynos.o
40obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o
40obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o 41obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
41obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o 42obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
42 43
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 6ff665209a4c..538b9ddaadf7 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -41,46 +41,46 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
41 41
42static void exynos_gpio_irq_unmask(struct irq_data *irqd) 42static void exynos_gpio_irq_unmask(struct irq_data *irqd)
43{ 43{
44 struct samsung_pinctrl_drv_data *d = irqd->domain->host_data; 44 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
45 struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd); 45 struct samsung_pinctrl_drv_data *d = bank->drvdata;
46 unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset; 46 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
47 unsigned long mask; 47 unsigned long mask;
48 48
49 mask = readl(d->virt_base + reg_mask); 49 mask = readl(d->virt_base + reg_mask);
50 mask &= ~(1 << edata->pin); 50 mask &= ~(1 << irqd->hwirq);
51 writel(mask, d->virt_base + reg_mask); 51 writel(mask, d->virt_base + reg_mask);
52} 52}
53 53
54static void exynos_gpio_irq_mask(struct irq_data *irqd) 54static void exynos_gpio_irq_mask(struct irq_data *irqd)
55{ 55{
56 struct samsung_pinctrl_drv_data *d = irqd->domain->host_data; 56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
57 struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd); 57 struct samsung_pinctrl_drv_data *d = bank->drvdata;
58 unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset; 58 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
59 unsigned long mask; 59 unsigned long mask;
60 60
61 mask = readl(d->virt_base + reg_mask); 61 mask = readl(d->virt_base + reg_mask);
62 mask |= 1 << edata->pin; 62 mask |= 1 << irqd->hwirq;
63 writel(mask, d->virt_base + reg_mask); 63 writel(mask, d->virt_base + reg_mask);
64} 64}
65 65
66static void exynos_gpio_irq_ack(struct irq_data *irqd) 66static void exynos_gpio_irq_ack(struct irq_data *irqd)
67{ 67{
68 struct samsung_pinctrl_drv_data *d = irqd->domain->host_data; 68 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
69 struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd); 69 struct samsung_pinctrl_drv_data *d = bank->drvdata;
70 unsigned long reg_pend = d->ctrl->geint_pend + edata->eint_offset; 70 unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset;
71 71
72 writel(1 << edata->pin, d->virt_base + reg_pend); 72 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
73} 73}
74 74
75static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 75static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
76{ 76{
77 struct samsung_pinctrl_drv_data *d = irqd->domain->host_data; 77 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
78 struct samsung_pinctrl_drv_data *d = bank->drvdata;
78 struct samsung_pin_ctrl *ctrl = d->ctrl; 79 struct samsung_pin_ctrl *ctrl = d->ctrl;
79 struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd); 80 unsigned int pin = irqd->hwirq;
80 struct samsung_pin_bank *bank = edata->bank; 81 unsigned int shift = EXYNOS_EINT_CON_LEN * pin;
81 unsigned int shift = EXYNOS_EINT_CON_LEN * edata->pin;
82 unsigned int con, trig_type; 82 unsigned int con, trig_type;
83 unsigned long reg_con = ctrl->geint_con + edata->eint_offset; 83 unsigned long reg_con = ctrl->geint_con + bank->eint_offset;
84 unsigned int mask; 84 unsigned int mask;
85 85
86 switch (type) { 86 switch (type) {
@@ -115,7 +115,7 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
115 writel(con, d->virt_base + reg_con); 115 writel(con, d->virt_base + reg_con);
116 116
117 reg_con = bank->pctl_offset; 117 reg_con = bank->pctl_offset;
118 shift = edata->pin * bank->func_width; 118 shift = pin * bank->func_width;
119 mask = (1 << bank->func_width) - 1; 119 mask = (1 << bank->func_width) - 1;
120 120
121 con = readl(d->virt_base + reg_con); 121 con = readl(d->virt_base + reg_con);
@@ -137,82 +137,23 @@ static struct irq_chip exynos_gpio_irq_chip = {
137 .irq_set_type = exynos_gpio_irq_set_type, 137 .irq_set_type = exynos_gpio_irq_set_type,
138}; 138};
139 139
140/*
141 * given a controller-local external gpio interrupt number, prepare the handler
142 * data for it.
143 */
144static struct exynos_geint_data *exynos_get_eint_data(irq_hw_number_t hw,
145 struct samsung_pinctrl_drv_data *d)
146{
147 struct samsung_pin_bank *bank = d->ctrl->pin_banks;
148 struct exynos_geint_data *eint_data;
149 unsigned int nr_banks = d->ctrl->nr_banks, idx;
150 unsigned int irq_base = 0, eint_offset = 0;
151
152 if (hw >= d->ctrl->nr_gint) {
153 dev_err(d->dev, "unsupported ext-gpio interrupt\n");
154 return NULL;
155 }
156
157 for (idx = 0; idx < nr_banks; idx++, bank++) {
158 if (bank->eint_type != EINT_TYPE_GPIO)
159 continue;
160 if ((hw >= irq_base) && (hw < (irq_base + bank->nr_pins)))
161 break;
162 irq_base += bank->nr_pins;
163 eint_offset += 4;
164 }
165
166 if (idx == nr_banks) {
167 dev_err(d->dev, "pin bank not found for ext-gpio interrupt\n");
168 return NULL;
169 }
170
171 eint_data = devm_kzalloc(d->dev, sizeof(*eint_data), GFP_KERNEL);
172 if (!eint_data) {
173 dev_err(d->dev, "no memory for eint-gpio data\n");
174 return NULL;
175 }
176
177 eint_data->bank = bank;
178 eint_data->pin = hw - irq_base;
179 eint_data->eint_offset = eint_offset;
180 return eint_data;
181}
182
183static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, 140static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
184 irq_hw_number_t hw) 141 irq_hw_number_t hw)
185{ 142{
186 struct samsung_pinctrl_drv_data *d = h->host_data; 143 struct samsung_pin_bank *b = h->host_data;
187 struct exynos_geint_data *eint_data;
188
189 eint_data = exynos_get_eint_data(hw, d);
190 if (!eint_data)
191 return -EINVAL;
192 144
193 irq_set_handler_data(virq, eint_data); 145 irq_set_chip_data(virq, b);
194 irq_set_chip_data(virq, h->host_data);
195 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip, 146 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip,
196 handle_level_irq); 147 handle_level_irq);
197 set_irq_flags(virq, IRQF_VALID); 148 set_irq_flags(virq, IRQF_VALID);
198 return 0; 149 return 0;
199} 150}
200 151
201static void exynos_gpio_irq_unmap(struct irq_domain *h, unsigned int virq)
202{
203 struct samsung_pinctrl_drv_data *d = h->host_data;
204 struct exynos_geint_data *eint_data;
205
206 eint_data = irq_get_handler_data(virq);
207 devm_kfree(d->dev, eint_data);
208}
209
210/* 152/*
211 * irq domain callbacks for external gpio interrupt controller. 153 * irq domain callbacks for external gpio interrupt controller.
212 */ 154 */
213static const struct irq_domain_ops exynos_gpio_irqd_ops = { 155static const struct irq_domain_ops exynos_gpio_irqd_ops = {
214 .map = exynos_gpio_irq_map, 156 .map = exynos_gpio_irq_map,
215 .unmap = exynos_gpio_irq_unmap,
216 .xlate = irq_domain_xlate_twocell, 157 .xlate = irq_domain_xlate_twocell,
217}; 158};
218 159
@@ -231,7 +172,7 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
231 return IRQ_HANDLED; 172 return IRQ_HANDLED;
232 bank += (group - 1); 173 bank += (group - 1);
233 174
234 virq = irq_linear_revmap(d->gpio_irqd, bank->irq_base + pin); 175 virq = irq_linear_revmap(bank->irq_domain, pin);
235 if (!virq) 176 if (!virq)
236 return IRQ_NONE; 177 return IRQ_NONE;
237 generic_handle_irq(virq); 178 generic_handle_irq(virq);
@@ -244,8 +185,10 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
244 */ 185 */
245static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) 186static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
246{ 187{
188 struct samsung_pin_bank *bank;
247 struct device *dev = d->dev; 189 struct device *dev = d->dev;
248 unsigned int ret; 190 unsigned int ret;
191 unsigned int i;
249 192
250 if (!d->irq) { 193 if (!d->irq) {
251 dev_err(dev, "irq number not available\n"); 194 dev_err(dev, "irq number not available\n");
@@ -259,11 +202,16 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
259 return -ENXIO; 202 return -ENXIO;
260 } 203 }
261 204
262 d->gpio_irqd = irq_domain_add_linear(dev->of_node, d->ctrl->nr_gint, 205 bank = d->ctrl->pin_banks;
263 &exynos_gpio_irqd_ops, d); 206 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
264 if (!d->gpio_irqd) { 207 if (bank->eint_type != EINT_TYPE_GPIO)
265 dev_err(dev, "gpio irq domain allocation failed\n"); 208 continue;
266 return -ENXIO; 209 bank->irq_domain = irq_domain_add_linear(bank->of_node,
210 bank->nr_pins, &exynos_gpio_irqd_ops, bank);
211 if (!bank->irq_domain) {
212 dev_err(dev, "gpio irq domain add failed\n");
213 return -ENXIO;
214 }
267 } 215 }
268 216
269 return 0; 217 return 0;
@@ -271,48 +219,46 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
271 219
272static void exynos_wkup_irq_unmask(struct irq_data *irqd) 220static void exynos_wkup_irq_unmask(struct irq_data *irqd)
273{ 221{
274 struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd); 222 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
275 unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK; 223 struct samsung_pinctrl_drv_data *d = b->drvdata;
276 unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1); 224 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
277 unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
278 unsigned long mask; 225 unsigned long mask;
279 226
280 mask = readl(d->virt_base + reg_mask); 227 mask = readl(d->virt_base + reg_mask);
281 mask &= ~(1 << pin); 228 mask &= ~(1 << irqd->hwirq);
282 writel(mask, d->virt_base + reg_mask); 229 writel(mask, d->virt_base + reg_mask);
283} 230}
284 231
285static void exynos_wkup_irq_mask(struct irq_data *irqd) 232static void exynos_wkup_irq_mask(struct irq_data *irqd)
286{ 233{
287 struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd); 234 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
288 unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK; 235 struct samsung_pinctrl_drv_data *d = b->drvdata;
289 unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1); 236 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
290 unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
291 unsigned long mask; 237 unsigned long mask;
292 238
293 mask = readl(d->virt_base + reg_mask); 239 mask = readl(d->virt_base + reg_mask);
294 mask |= 1 << pin; 240 mask |= 1 << irqd->hwirq;
295 writel(mask, d->virt_base + reg_mask); 241 writel(mask, d->virt_base + reg_mask);
296} 242}
297 243
298static void exynos_wkup_irq_ack(struct irq_data *irqd) 244static void exynos_wkup_irq_ack(struct irq_data *irqd)
299{ 245{
300 struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd); 246 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
301 unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK; 247 struct samsung_pinctrl_drv_data *d = b->drvdata;
302 unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1); 248 unsigned long pend = d->ctrl->weint_pend + b->eint_offset;
303 unsigned long pend = d->ctrl->weint_pend + (bank << 2);
304 249
305 writel(1 << pin, d->virt_base + pend); 250 writel(1 << irqd->hwirq, d->virt_base + pend);
306} 251}
307 252
308static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type) 253static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
309{ 254{
310 struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd); 255 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
311 unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK; 256 struct samsung_pinctrl_drv_data *d = bank->drvdata;
312 unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1); 257 unsigned int pin = irqd->hwirq;
313 unsigned long reg_con = d->ctrl->weint_con + (bank << 2); 258 unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset;
314 unsigned long shift = EXYNOS_EINT_CON_LEN * pin; 259 unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
315 unsigned long con, trig_type; 260 unsigned long con, trig_type;
261 unsigned int mask;
316 262
317 switch (type) { 263 switch (type) {
318 case IRQ_TYPE_EDGE_RISING: 264 case IRQ_TYPE_EDGE_RISING:
@@ -344,6 +290,16 @@ static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
344 con &= ~(EXYNOS_EINT_CON_MASK << shift); 290 con &= ~(EXYNOS_EINT_CON_MASK << shift);
345 con |= trig_type << shift; 291 con |= trig_type << shift;
346 writel(con, d->virt_base + reg_con); 292 writel(con, d->virt_base + reg_con);
293
294 reg_con = bank->pctl_offset;
295 shift = pin * bank->func_width;
296 mask = (1 << bank->func_width) - 1;
297
298 con = readl(d->virt_base + reg_con);
299 con &= ~(mask << shift);
300 con |= EXYNOS_EINT_FUNC << shift;
301 writel(con, d->virt_base + reg_con);
302
347 return 0; 303 return 0;
348} 304}
349 305
@@ -362,6 +318,7 @@ static struct irq_chip exynos_wkup_irq_chip = {
362static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) 318static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
363{ 319{
364 struct exynos_weint_data *eintd = irq_get_handler_data(irq); 320 struct exynos_weint_data *eintd = irq_get_handler_data(irq);
321 struct samsung_pin_bank *bank = eintd->bank;
365 struct irq_chip *chip = irq_get_chip(irq); 322 struct irq_chip *chip = irq_get_chip(irq);
366 int eint_irq; 323 int eint_irq;
367 324
@@ -371,20 +328,20 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
371 if (chip->irq_ack) 328 if (chip->irq_ack)
372 chip->irq_ack(&desc->irq_data); 329 chip->irq_ack(&desc->irq_data);
373 330
374 eint_irq = irq_linear_revmap(eintd->domain, eintd->irq); 331 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
375 generic_handle_irq(eint_irq); 332 generic_handle_irq(eint_irq);
376 chip->irq_unmask(&desc->irq_data); 333 chip->irq_unmask(&desc->irq_data);
377 chained_irq_exit(chip, desc); 334 chained_irq_exit(chip, desc);
378} 335}
379 336
380static inline void exynos_irq_demux_eint(int irq_base, unsigned long pend, 337static inline void exynos_irq_demux_eint(unsigned long pend,
381 struct irq_domain *domain) 338 struct irq_domain *domain)
382{ 339{
383 unsigned int irq; 340 unsigned int irq;
384 341
385 while (pend) { 342 while (pend) {
386 irq = fls(pend) - 1; 343 irq = fls(pend) - 1;
387 generic_handle_irq(irq_find_mapping(domain, irq_base + irq)); 344 generic_handle_irq(irq_find_mapping(domain, irq));
388 pend &= ~(1 << irq); 345 pend &= ~(1 << irq);
389 } 346 }
390} 347}
@@ -393,18 +350,22 @@ static inline void exynos_irq_demux_eint(int irq_base, unsigned long pend,
393static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) 350static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
394{ 351{
395 struct irq_chip *chip = irq_get_chip(irq); 352 struct irq_chip *chip = irq_get_chip(irq);
396 struct exynos_weint_data *eintd = irq_get_handler_data(irq); 353 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
397 struct samsung_pinctrl_drv_data *d = eintd->domain->host_data; 354 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
355 struct samsung_pin_ctrl *ctrl = d->ctrl;
398 unsigned long pend; 356 unsigned long pend;
399 unsigned long mask; 357 unsigned long mask;
358 int i;
400 359
401 chained_irq_enter(chip, desc); 360 chained_irq_enter(chip, desc);
402 pend = readl(d->virt_base + d->ctrl->weint_pend + 0x8); 361
403 mask = readl(d->virt_base + d->ctrl->weint_mask + 0x8); 362 for (i = 0; i < eintd->nr_banks; ++i) {
404 exynos_irq_demux_eint(16, pend & ~mask, eintd->domain); 363 struct samsung_pin_bank *b = eintd->banks[i];
405 pend = readl(d->virt_base + d->ctrl->weint_pend + 0xC); 364 pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset);
406 mask = readl(d->virt_base + d->ctrl->weint_mask + 0xC); 365 mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset);
407 exynos_irq_demux_eint(24, pend & ~mask, eintd->domain); 366 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
367 }
368
408 chained_irq_exit(chip, desc); 369 chained_irq_exit(chip, desc);
409} 370}
410 371
@@ -434,7 +395,11 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
434 struct device *dev = d->dev; 395 struct device *dev = d->dev;
435 struct device_node *wkup_np = NULL; 396 struct device_node *wkup_np = NULL;
436 struct device_node *np; 397 struct device_node *np;
398 struct samsung_pin_bank *bank;
437 struct exynos_weint_data *weint_data; 399 struct exynos_weint_data *weint_data;
400 struct exynos_muxed_weint_data *muxed_data;
401 unsigned int muxed_banks = 0;
402 unsigned int i;
438 int idx, irq; 403 int idx, irq;
439 404
440 for_each_child_of_node(dev->of_node, np) { 405 for_each_child_of_node(dev->of_node, np) {
@@ -446,90 +411,124 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
446 if (!wkup_np) 411 if (!wkup_np)
447 return -ENODEV; 412 return -ENODEV;
448 413
449 d->wkup_irqd = irq_domain_add_linear(wkup_np, d->ctrl->nr_wint, 414 bank = d->ctrl->pin_banks;
450 &exynos_wkup_irqd_ops, d); 415 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
451 if (!d->wkup_irqd) { 416 if (bank->eint_type != EINT_TYPE_WKUP)
452 dev_err(dev, "wakeup irq domain allocation failed\n"); 417 continue;
453 return -ENXIO;
454 }
455 418
456 weint_data = devm_kzalloc(dev, sizeof(*weint_data) * 17, GFP_KERNEL); 419 bank->irq_domain = irq_domain_add_linear(bank->of_node,
457 if (!weint_data) { 420 bank->nr_pins, &exynos_wkup_irqd_ops, bank);
458 dev_err(dev, "could not allocate memory for weint_data\n"); 421 if (!bank->irq_domain) {
459 return -ENOMEM; 422 dev_err(dev, "wkup irq domain add failed\n");
460 } 423 return -ENXIO;
424 }
461 425
462 irq = irq_of_parse_and_map(wkup_np, 16); 426 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
463 if (irq) { 427 bank->eint_type = EINT_TYPE_WKUP_MUX;
464 weint_data[16].domain = d->wkup_irqd; 428 ++muxed_banks;
465 irq_set_chained_handler(irq, exynos_irq_demux_eint16_31); 429 continue;
466 irq_set_handler_data(irq, &weint_data[16]); 430 }
467 } else {
468 dev_err(dev, "irq number for EINT16-32 not found\n");
469 }
470 431
471 for (idx = 0; idx < 16; idx++) { 432 weint_data = devm_kzalloc(dev, bank->nr_pins
472 weint_data[idx].domain = d->wkup_irqd; 433 * sizeof(*weint_data), GFP_KERNEL);
473 weint_data[idx].irq = idx; 434 if (!weint_data) {
435 dev_err(dev, "could not allocate memory for weint_data\n");
436 return -ENOMEM;
437 }
474 438
475 irq = irq_of_parse_and_map(wkup_np, idx); 439 for (idx = 0; idx < bank->nr_pins; ++idx) {
476 if (irq) { 440 irq = irq_of_parse_and_map(bank->of_node, idx);
441 if (!irq) {
442 dev_err(dev, "irq number for eint-%s-%d not found\n",
443 bank->name, idx);
444 continue;
445 }
446 weint_data[idx].irq = idx;
447 weint_data[idx].bank = bank;
477 irq_set_handler_data(irq, &weint_data[idx]); 448 irq_set_handler_data(irq, &weint_data[idx]);
478 irq_set_chained_handler(irq, exynos_irq_eint0_15); 449 irq_set_chained_handler(irq, exynos_irq_eint0_15);
479 } else {
480 dev_err(dev, "irq number for eint-%x not found\n", idx);
481 } 450 }
482 } 451 }
452
453 if (!muxed_banks)
454 return 0;
455
456 irq = irq_of_parse_and_map(wkup_np, 0);
457 if (!irq) {
458 dev_err(dev, "irq number for muxed EINTs not found\n");
459 return 0;
460 }
461
462 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
463 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
464 if (!muxed_data) {
465 dev_err(dev, "could not allocate memory for muxed_data\n");
466 return -ENOMEM;
467 }
468
469 irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
470 irq_set_handler_data(irq, muxed_data);
471
472 bank = d->ctrl->pin_banks;
473 idx = 0;
474 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
475 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
476 continue;
477
478 muxed_data->banks[idx++] = bank;
479 }
480 muxed_data->nr_banks = muxed_banks;
481
483 return 0; 482 return 0;
484} 483}
485 484
486/* pin banks of exynos4210 pin-controller 0 */ 485/* pin banks of exynos4210 pin-controller 0 */
487static struct samsung_pin_bank exynos4210_pin_banks0[] = { 486static struct samsung_pin_bank exynos4210_pin_banks0[] = {
488 EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_A0, "gpa0"), 487 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
489 EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_A1, "gpa1"), 488 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
490 EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_B, "gpb"), 489 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
491 EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_C0, "gpc0"), 490 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
492 EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_C1, "gpc1"), 491 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
493 EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_D0, "gpd0"), 492 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
494 EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_D1, "gpd1"), 493 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
495 EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_E0, "gpe0"), 494 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
496 EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_E1, "gpe1"), 495 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
497 EXYNOS_PIN_BANK_EINTG(0x120, EXYNOS4210_GPIO_E2, "gpe2"), 496 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
498 EXYNOS_PIN_BANK_EINTG(0x140, EXYNOS4210_GPIO_E3, "gpe3"), 497 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
499 EXYNOS_PIN_BANK_EINTG(0x160, EXYNOS4210_GPIO_E4, "gpe4"), 498 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
500 EXYNOS_PIN_BANK_EINTG(0x180, EXYNOS4210_GPIO_F0, "gpf0"), 499 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
501 EXYNOS_PIN_BANK_EINTG(0x1A0, EXYNOS4210_GPIO_F1, "gpf1"), 500 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
502 EXYNOS_PIN_BANK_EINTG(0x1C0, EXYNOS4210_GPIO_F2, "gpf2"), 501 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
503 EXYNOS_PIN_BANK_EINTG(0x1E0, EXYNOS4210_GPIO_F3, "gpf3"), 502 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
504}; 503};
505 504
506/* pin banks of exynos4210 pin-controller 1 */ 505/* pin banks of exynos4210 pin-controller 1 */
507static struct samsung_pin_bank exynos4210_pin_banks1[] = { 506static struct samsung_pin_bank exynos4210_pin_banks1[] = {
508 EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_J0, "gpj0"), 507 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
509 EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_J1, "gpj1"), 508 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
510 EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_K0, "gpk0"), 509 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
511 EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_K1, "gpk1"), 510 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
512 EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_K2, "gpk2"), 511 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
513 EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_K3, "gpk3"), 512 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
514 EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_L0, "gpl0"), 513 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
515 EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_L1, "gpl1"), 514 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
516 EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_L2, "gpl2"), 515 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
517 EXYNOS_PIN_BANK_EINTN(0x120, EXYNOS4210_GPIO_Y0, "gpy0"), 516 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
518 EXYNOS_PIN_BANK_EINTN(0x140, EXYNOS4210_GPIO_Y1, "gpy1"), 517 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
519 EXYNOS_PIN_BANK_EINTN(0x160, EXYNOS4210_GPIO_Y2, "gpy2"), 518 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
520 EXYNOS_PIN_BANK_EINTN(0x180, EXYNOS4210_GPIO_Y3, "gpy3"), 519 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
521 EXYNOS_PIN_BANK_EINTN(0x1A0, EXYNOS4210_GPIO_Y4, "gpy4"), 520 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
522 EXYNOS_PIN_BANK_EINTN(0x1C0, EXYNOS4210_GPIO_Y5, "gpy5"), 521 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
523 EXYNOS_PIN_BANK_EINTN(0x1E0, EXYNOS4210_GPIO_Y6, "gpy6"), 522 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
524 EXYNOS_PIN_BANK_EINTN(0xC00, EXYNOS4210_GPIO_X0, "gpx0"), 523 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
525 EXYNOS_PIN_BANK_EINTN(0xC20, EXYNOS4210_GPIO_X1, "gpx1"), 524 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
526 EXYNOS_PIN_BANK_EINTN(0xC40, EXYNOS4210_GPIO_X2, "gpx2"), 525 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
527 EXYNOS_PIN_BANK_EINTN(0xC60, EXYNOS4210_GPIO_X3, "gpx3"), 526 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
528}; 527};
529 528
530/* pin banks of exynos4210 pin-controller 2 */ 529/* pin banks of exynos4210 pin-controller 2 */
531static struct samsung_pin_bank exynos4210_pin_banks2[] = { 530static struct samsung_pin_bank exynos4210_pin_banks2[] = {
532 EXYNOS_PIN_BANK_EINTN(0x000, EXYNOS4210_GPIO_Z, "gpz"), 531 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
533}; 532};
534 533
535/* 534/*
@@ -541,9 +540,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
541 /* pin-controller instance 0 data */ 540 /* pin-controller instance 0 data */
542 .pin_banks = exynos4210_pin_banks0, 541 .pin_banks = exynos4210_pin_banks0,
543 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), 542 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
544 .base = EXYNOS4210_GPIO_A0_START,
545 .nr_pins = EXYNOS4210_GPIOA_NR_PINS,
546 .nr_gint = EXYNOS4210_GPIOA_NR_GINT,
547 .geint_con = EXYNOS_GPIO_ECON_OFFSET, 543 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
548 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, 544 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
549 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, 545 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
@@ -554,10 +550,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
554 /* pin-controller instance 1 data */ 550 /* pin-controller instance 1 data */
555 .pin_banks = exynos4210_pin_banks1, 551 .pin_banks = exynos4210_pin_banks1,
556 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), 552 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
557 .base = EXYNOS4210_GPIOA_NR_PINS,
558 .nr_pins = EXYNOS4210_GPIOB_NR_PINS,
559 .nr_gint = EXYNOS4210_GPIOB_NR_GINT,
560 .nr_wint = 32,
561 .geint_con = EXYNOS_GPIO_ECON_OFFSET, 553 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
562 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, 554 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
563 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, 555 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
@@ -572,9 +564,116 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
572 /* pin-controller instance 2 data */ 564 /* pin-controller instance 2 data */
573 .pin_banks = exynos4210_pin_banks2, 565 .pin_banks = exynos4210_pin_banks2,
574 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), 566 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
575 .base = EXYNOS4210_GPIOA_NR_PINS +
576 EXYNOS4210_GPIOB_NR_PINS,
577 .nr_pins = EXYNOS4210_GPIOC_NR_PINS,
578 .label = "exynos4210-gpio-ctrl2", 567 .label = "exynos4210-gpio-ctrl2",
579 }, 568 },
580}; 569};
570
571/* pin banks of exynos4x12 pin-controller 0 */
572static struct samsung_pin_bank exynos4x12_pin_banks0[] = {
573 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
574 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
575 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
576 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
577 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
578 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
579 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
580 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
581 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
582 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
583 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
584 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
585 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
586};
587
588/* pin banks of exynos4x12 pin-controller 1 */
589static struct samsung_pin_bank exynos4x12_pin_banks1[] = {
590 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
591 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
592 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
593 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
594 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
595 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
596 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
597 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
598 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
599 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
600 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
601 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
602 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
603 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
604 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
605 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
606 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
607 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
608 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
609 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
610 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
611 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
612 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
613};
614
615/* pin banks of exynos4x12 pin-controller 2 */
616static struct samsung_pin_bank exynos4x12_pin_banks2[] = {
617 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
618};
619
620/* pin banks of exynos4x12 pin-controller 3 */
621static struct samsung_pin_bank exynos4x12_pin_banks3[] = {
622 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
623 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
624 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
625 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
626 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
627};
628
629/*
630 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
631 * four gpio/pin-mux/pinconfig controllers.
632 */
633struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
634 {
635 /* pin-controller instance 0 data */
636 .pin_banks = exynos4x12_pin_banks0,
637 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
638 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
639 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
640 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
641 .svc = EXYNOS_SVC_OFFSET,
642 .eint_gpio_init = exynos_eint_gpio_init,
643 .label = "exynos4x12-gpio-ctrl0",
644 }, {
645 /* pin-controller instance 1 data */
646 .pin_banks = exynos4x12_pin_banks1,
647 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
648 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
649 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
650 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
651 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
652 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
653 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
654 .svc = EXYNOS_SVC_OFFSET,
655 .eint_gpio_init = exynos_eint_gpio_init,
656 .eint_wkup_init = exynos_eint_wkup_init,
657 .label = "exynos4x12-gpio-ctrl1",
658 }, {
659 /* pin-controller instance 2 data */
660 .pin_banks = exynos4x12_pin_banks2,
661 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
662 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
663 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
664 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
665 .svc = EXYNOS_SVC_OFFSET,
666 .eint_gpio_init = exynos_eint_gpio_init,
667 .label = "exynos4x12-gpio-ctrl2",
668 }, {
669 /* pin-controller instance 3 data */
670 .pin_banks = exynos4x12_pin_banks3,
671 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
672 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
673 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
674 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
675 .svc = EXYNOS_SVC_OFFSET,
676 .eint_gpio_init = exynos_eint_gpio_init,
677 .label = "exynos4x12-gpio-ctrl3",
678 },
679};
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
index 31d0a06174e4..0a708890d8b4 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -17,125 +17,6 @@
17 * (at your option) any later version. 17 * (at your option) any later version.
18 */ 18 */
19 19
20#define EXYNOS_GPIO_START(__gpio) ((__gpio##_START) + (__gpio##_NR))
21
22#define EXYNOS4210_GPIO_A0_NR (8)
23#define EXYNOS4210_GPIO_A1_NR (6)
24#define EXYNOS4210_GPIO_B_NR (8)
25#define EXYNOS4210_GPIO_C0_NR (5)
26#define EXYNOS4210_GPIO_C1_NR (5)
27#define EXYNOS4210_GPIO_D0_NR (4)
28#define EXYNOS4210_GPIO_D1_NR (4)
29#define EXYNOS4210_GPIO_E0_NR (5)
30#define EXYNOS4210_GPIO_E1_NR (8)
31#define EXYNOS4210_GPIO_E2_NR (6)
32#define EXYNOS4210_GPIO_E3_NR (8)
33#define EXYNOS4210_GPIO_E4_NR (8)
34#define EXYNOS4210_GPIO_F0_NR (8)
35#define EXYNOS4210_GPIO_F1_NR (8)
36#define EXYNOS4210_GPIO_F2_NR (8)
37#define EXYNOS4210_GPIO_F3_NR (6)
38#define EXYNOS4210_GPIO_J0_NR (8)
39#define EXYNOS4210_GPIO_J1_NR (5)
40#define EXYNOS4210_GPIO_K0_NR (7)
41#define EXYNOS4210_GPIO_K1_NR (7)
42#define EXYNOS4210_GPIO_K2_NR (7)
43#define EXYNOS4210_GPIO_K3_NR (7)
44#define EXYNOS4210_GPIO_L0_NR (8)
45#define EXYNOS4210_GPIO_L1_NR (3)
46#define EXYNOS4210_GPIO_L2_NR (8)
47#define EXYNOS4210_GPIO_Y0_NR (6)
48#define EXYNOS4210_GPIO_Y1_NR (4)
49#define EXYNOS4210_GPIO_Y2_NR (6)
50#define EXYNOS4210_GPIO_Y3_NR (8)
51#define EXYNOS4210_GPIO_Y4_NR (8)
52#define EXYNOS4210_GPIO_Y5_NR (8)
53#define EXYNOS4210_GPIO_Y6_NR (8)
54#define EXYNOS4210_GPIO_X0_NR (8)
55#define EXYNOS4210_GPIO_X1_NR (8)
56#define EXYNOS4210_GPIO_X2_NR (8)
57#define EXYNOS4210_GPIO_X3_NR (8)
58#define EXYNOS4210_GPIO_Z_NR (7)
59
60enum exynos4210_gpio_xa_start {
61 EXYNOS4210_GPIO_A0_START = 0,
62 EXYNOS4210_GPIO_A1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_A0),
63 EXYNOS4210_GPIO_B_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_A1),
64 EXYNOS4210_GPIO_C0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_B),
65 EXYNOS4210_GPIO_C1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_C0),
66 EXYNOS4210_GPIO_D0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_C1),
67 EXYNOS4210_GPIO_D1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_D0),
68 EXYNOS4210_GPIO_E0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_D1),
69 EXYNOS4210_GPIO_E1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E0),
70 EXYNOS4210_GPIO_E2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E1),
71 EXYNOS4210_GPIO_E3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E2),
72 EXYNOS4210_GPIO_E4_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E3),
73 EXYNOS4210_GPIO_F0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E4),
74 EXYNOS4210_GPIO_F1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F0),
75 EXYNOS4210_GPIO_F2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F1),
76 EXYNOS4210_GPIO_F3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F2),
77};
78
79enum exynos4210_gpio_xb_start {
80 EXYNOS4210_GPIO_J0_START = 0,
81 EXYNOS4210_GPIO_J1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_J0),
82 EXYNOS4210_GPIO_K0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_J1),
83 EXYNOS4210_GPIO_K1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K0),
84 EXYNOS4210_GPIO_K2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K1),
85 EXYNOS4210_GPIO_K3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K2),
86 EXYNOS4210_GPIO_L0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K3),
87 EXYNOS4210_GPIO_L1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L0),
88 EXYNOS4210_GPIO_L2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L1),
89 EXYNOS4210_GPIO_Y0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2),
90 EXYNOS4210_GPIO_Y1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y0),
91 EXYNOS4210_GPIO_Y2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y1),
92 EXYNOS4210_GPIO_Y3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y2),
93 EXYNOS4210_GPIO_Y4_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y3),
94 EXYNOS4210_GPIO_Y5_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y4),
95 EXYNOS4210_GPIO_Y6_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y5),
96 EXYNOS4210_GPIO_X0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y6),
97 EXYNOS4210_GPIO_X1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X0),
98 EXYNOS4210_GPIO_X2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X1),
99 EXYNOS4210_GPIO_X3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X2),
100};
101
102enum exynos4210_gpio_xc_start {
103 EXYNOS4210_GPIO_Z_START = 0,
104};
105
106#define EXYNOS4210_GPIO_A0_IRQ EXYNOS4210_GPIO_A0_START
107#define EXYNOS4210_GPIO_A1_IRQ EXYNOS4210_GPIO_A1_START
108#define EXYNOS4210_GPIO_B_IRQ EXYNOS4210_GPIO_B_START
109#define EXYNOS4210_GPIO_C0_IRQ EXYNOS4210_GPIO_C0_START
110#define EXYNOS4210_GPIO_C1_IRQ EXYNOS4210_GPIO_C1_START
111#define EXYNOS4210_GPIO_D0_IRQ EXYNOS4210_GPIO_D0_START
112#define EXYNOS4210_GPIO_D1_IRQ EXYNOS4210_GPIO_D1_START
113#define EXYNOS4210_GPIO_E0_IRQ EXYNOS4210_GPIO_E0_START
114#define EXYNOS4210_GPIO_E1_IRQ EXYNOS4210_GPIO_E1_START
115#define EXYNOS4210_GPIO_E2_IRQ EXYNOS4210_GPIO_E2_START
116#define EXYNOS4210_GPIO_E3_IRQ EXYNOS4210_GPIO_E3_START
117#define EXYNOS4210_GPIO_E4_IRQ EXYNOS4210_GPIO_E4_START
118#define EXYNOS4210_GPIO_F0_IRQ EXYNOS4210_GPIO_F0_START
119#define EXYNOS4210_GPIO_F1_IRQ EXYNOS4210_GPIO_F1_START
120#define EXYNOS4210_GPIO_F2_IRQ EXYNOS4210_GPIO_F2_START
121#define EXYNOS4210_GPIO_F3_IRQ EXYNOS4210_GPIO_F3_START
122#define EXYNOS4210_GPIO_J0_IRQ EXYNOS4210_GPIO_J0_START
123#define EXYNOS4210_GPIO_J1_IRQ EXYNOS4210_GPIO_J1_START
124#define EXYNOS4210_GPIO_K0_IRQ EXYNOS4210_GPIO_K0_START
125#define EXYNOS4210_GPIO_K1_IRQ EXYNOS4210_GPIO_K1_START
126#define EXYNOS4210_GPIO_K2_IRQ EXYNOS4210_GPIO_K2_START
127#define EXYNOS4210_GPIO_K3_IRQ EXYNOS4210_GPIO_K3_START
128#define EXYNOS4210_GPIO_L0_IRQ EXYNOS4210_GPIO_L0_START
129#define EXYNOS4210_GPIO_L1_IRQ EXYNOS4210_GPIO_L1_START
130#define EXYNOS4210_GPIO_L2_IRQ EXYNOS4210_GPIO_L2_START
131#define EXYNOS4210_GPIO_Z_IRQ EXYNOS4210_GPIO_Z_START
132
133#define EXYNOS4210_GPIOA_NR_PINS EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)
134#define EXYNOS4210_GPIOA_NR_GINT EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)
135#define EXYNOS4210_GPIOB_NR_PINS EXYNOS_GPIO_START(EXYNOS4210_GPIO_X3)
136#define EXYNOS4210_GPIOB_NR_GINT EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2)
137#define EXYNOS4210_GPIOC_NR_PINS EXYNOS_GPIO_START(EXYNOS4210_GPIO_Z)
138
139/* External GPIO and wakeup interrupt related definitions */ 20/* External GPIO and wakeup interrupt related definitions */
140#define EXYNOS_GPIO_ECON_OFFSET 0x700 21#define EXYNOS_GPIO_ECON_OFFSET 0x700
141#define EXYNOS_GPIO_EMASK_OFFSET 0x900 22#define EXYNOS_GPIO_EMASK_OFFSET 0x900
@@ -165,11 +46,10 @@ enum exynos4210_gpio_xc_start {
165#define EXYNOS_EINT_MAX_PER_BANK 8 46#define EXYNOS_EINT_MAX_PER_BANK 8
166#define EXYNOS_EINT_NR_WKUP_EINT 47#define EXYNOS_EINT_NR_WKUP_EINT
167 48
168#define EXYNOS_PIN_BANK_EINTN(reg, __gpio, id) \ 49#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
169 { \ 50 { \
170 .pctl_offset = reg, \ 51 .pctl_offset = reg, \
171 .pin_base = (__gpio##_START), \ 52 .nr_pins = pins, \
172 .nr_pins = (__gpio##_NR), \
173 .func_width = 4, \ 53 .func_width = 4, \
174 .pud_width = 2, \ 54 .pud_width = 2, \
175 .drv_width = 2, \ 55 .drv_width = 2, \
@@ -179,40 +59,50 @@ enum exynos4210_gpio_xc_start {
179 .name = id \ 59 .name = id \
180 } 60 }
181 61
182#define EXYNOS_PIN_BANK_EINTG(reg, __gpio, id) \ 62#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \
183 { \ 63 { \
184 .pctl_offset = reg, \ 64 .pctl_offset = reg, \
185 .pin_base = (__gpio##_START), \ 65 .nr_pins = pins, \
186 .nr_pins = (__gpio##_NR), \
187 .func_width = 4, \ 66 .func_width = 4, \
188 .pud_width = 2, \ 67 .pud_width = 2, \
189 .drv_width = 2, \ 68 .drv_width = 2, \
190 .conpdn_width = 2, \ 69 .conpdn_width = 2, \
191 .pudpdn_width = 2, \ 70 .pudpdn_width = 2, \
192 .eint_type = EINT_TYPE_GPIO, \ 71 .eint_type = EINT_TYPE_GPIO, \
193 .irq_base = (__gpio##_IRQ), \ 72 .eint_offset = offs, \
194 .name = id \ 73 .name = id \
195 } 74 }
196 75
197/** 76#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \
198 * struct exynos_geint_data: gpio eint specific data for irq_chip callbacks. 77 { \
199 * @bank: pin bank from which this gpio interrupt originates. 78 .pctl_offset = reg, \
200 * @pin: pin number within the bank. 79 .nr_pins = pins, \
201 * @eint_offset: offset to be added to the con/pend/mask register bank base. 80 .func_width = 4, \
202 */ 81 .pud_width = 2, \
203struct exynos_geint_data { 82 .drv_width = 2, \
204 struct samsung_pin_bank *bank; 83 .eint_type = EINT_TYPE_WKUP, \
205 u32 pin; 84 .eint_offset = offs, \
206 u32 eint_offset; 85 .name = id \
207}; 86 }
208 87
209/** 88/**
210 * struct exynos_weint_data: irq specific data for all the wakeup interrupts 89 * struct exynos_weint_data: irq specific data for all the wakeup interrupts
211 * generated by the external wakeup interrupt controller. 90 * generated by the external wakeup interrupt controller.
212 * @domain: irq domain representing the external wakeup interrupts
213 * @irq: interrupt number within the domain. 91 * @irq: interrupt number within the domain.
92 * @bank: bank responsible for this interrupt
214 */ 93 */
215struct exynos_weint_data { 94struct exynos_weint_data {
216 struct irq_domain *domain; 95 unsigned int irq;
217 u32 irq; 96 struct samsung_pin_bank *bank;
97};
98
99/**
100 * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts
101 * generated by the external wakeup interrupt controller.
102 * @nr_banks: count of banks being part of the mux
103 * @banks: array of banks being part of the mux
104 */
105struct exynos_muxed_weint_data {
106 unsigned int nr_banks;
107 struct samsung_pin_bank *banks[];
218}; 108};
diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c
new file mode 100644
index 000000000000..b8635f634e91
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-exynos5440.c
@@ -0,0 +1,919 @@
1/*
2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <linux/err.h>
18#include <linux/gpio.h>
19#include <linux/device.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22#include <linux/pinctrl/pinconf.h>
23#include "core.h"
24
25/* EXYNOS5440 GPIO and Pinctrl register offsets */
26#define GPIO_MUX 0x00
27#define GPIO_IE 0x04
28#define GPIO_INT 0x08
29#define GPIO_TYPE 0x0C
30#define GPIO_VAL 0x10
31#define GPIO_OE 0x14
32#define GPIO_IN 0x18
33#define GPIO_PE 0x1C
34#define GPIO_PS 0x20
35#define GPIO_SR 0x24
36#define GPIO_DS0 0x28
37#define GPIO_DS1 0x2C
38
39#define EXYNOS5440_MAX_PINS 23
40#define PIN_NAME_LENGTH 10
41
42#define GROUP_SUFFIX "-grp"
43#define GSUFFIX_LEN sizeof(GROUP_SUFFIX)
44#define FUNCTION_SUFFIX "-mux"
45#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX)
46
47/*
48 * pin configuration type and its value are packed together into a 16-bits.
49 * The upper 8-bits represent the configuration type and the lower 8-bits
50 * hold the value of the configuration type.
51 */
52#define PINCFG_TYPE_MASK 0xFF
53#define PINCFG_VALUE_SHIFT 8
54#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
55#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
56#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
57#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
58 PINCFG_VALUE_SHIFT)
59
60/**
61 * enum pincfg_type - possible pin configuration types supported.
62 * @PINCFG_TYPE_PUD: Pull up/down configuration.
63 * @PINCFG_TYPE_DRV: Drive strength configuration.
64 * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
65 * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
66 */
67enum pincfg_type {
68 PINCFG_TYPE_PUD,
69 PINCFG_TYPE_DRV,
70 PINCFG_TYPE_SKEW_RATE,
71 PINCFG_TYPE_INPUT_TYPE
72};
73
74/**
75 * struct exynos5440_pin_group: represent group of pins for pincfg setting.
76 * @name: name of the pin group, used to lookup the group.
77 * @pins: the pins included in this group.
78 * @num_pins: number of pins included in this group.
79 */
80struct exynos5440_pin_group {
81 const char *name;
82 const unsigned int *pins;
83 u8 num_pins;
84};
85
86/**
87 * struct exynos5440_pmx_func: represent a pin function.
88 * @name: name of the pin function, used to lookup the function.
89 * @groups: one or more names of pin groups that provide this function.
90 * @num_groups: number of groups included in @groups.
91 * @function: the function number to be programmed when selected.
92 */
93struct exynos5440_pmx_func {
94 const char *name;
95 const char **groups;
96 u8 num_groups;
97 unsigned long function;
98};
99
100/**
101 * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
102 * @reg_base: ioremapped based address of the register space.
103 * @gc: gpio chip registered with gpiolib.
104 * @pin_groups: list of pin groups parsed from device tree.
105 * @nr_groups: number of pin groups available.
106 * @pmx_functions: list of pin functions parsed from device tree.
107 * @nr_functions: number of pin functions available.
108 */
109struct exynos5440_pinctrl_priv_data {
110 void __iomem *reg_base;
111 struct gpio_chip *gc;
112
113 const struct exynos5440_pin_group *pin_groups;
114 unsigned int nr_groups;
115 const struct exynos5440_pmx_func *pmx_functions;
116 unsigned int nr_functions;
117};
118
119/* list of all possible config options supported */
120struct pin_config {
121 char *prop_cfg;
122 unsigned int cfg_type;
123} pcfgs[] = {
124 { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
125 { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
126 { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
127 { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
128};
129
130/* check if the selector is a valid pin group selector */
131static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
132{
133 struct exynos5440_pinctrl_priv_data *priv;
134
135 priv = pinctrl_dev_get_drvdata(pctldev);
136 return priv->nr_groups;
137}
138
139/* return the name of the group selected by the group selector */
140static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
141 unsigned selector)
142{
143 struct exynos5440_pinctrl_priv_data *priv;
144
145 priv = pinctrl_dev_get_drvdata(pctldev);
146 return priv->pin_groups[selector].name;
147}
148
149/* return the pin numbers associated with the specified group */
150static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
151 unsigned selector, const unsigned **pins, unsigned *num_pins)
152{
153 struct exynos5440_pinctrl_priv_data *priv;
154
155 priv = pinctrl_dev_get_drvdata(pctldev);
156 *pins = priv->pin_groups[selector].pins;
157 *num_pins = priv->pin_groups[selector].num_pins;
158 return 0;
159}
160
161/* create pinctrl_map entries by parsing device tree nodes */
162static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
163 struct device_node *np, struct pinctrl_map **maps,
164 unsigned *nmaps)
165{
166 struct device *dev = pctldev->dev;
167 struct pinctrl_map *map;
168 unsigned long *cfg = NULL;
169 char *gname, *fname;
170 int cfg_cnt = 0, map_cnt = 0, idx = 0;
171
172 /* count the number of config options specfied in the node */
173 for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
174 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
175 cfg_cnt++;
176
177 /*
178 * Find out the number of map entries to create. All the config options
179 * can be accomadated into a single config map entry.
180 */
181 if (cfg_cnt)
182 map_cnt = 1;
183 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
184 map_cnt++;
185 if (!map_cnt) {
186 dev_err(dev, "node %s does not have either config or function "
187 "configurations\n", np->name);
188 return -EINVAL;
189 }
190
191 /* Allocate memory for pin-map entries */
192 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
193 if (!map) {
194 dev_err(dev, "could not alloc memory for pin-maps\n");
195 return -ENOMEM;
196 }
197 *nmaps = 0;
198
199 /*
200 * Allocate memory for pin group name. The pin group name is derived
201 * from the node name from which these map entries are be created.
202 */
203 gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL);
204 if (!gname) {
205 dev_err(dev, "failed to alloc memory for group name\n");
206 goto free_map;
207 }
208 sprintf(gname, "%s%s", np->name, GROUP_SUFFIX);
209
210 /*
211 * don't have config options? then skip over to creating function
212 * map entries.
213 */
214 if (!cfg_cnt)
215 goto skip_cfgs;
216
217 /* Allocate memory for config entries */
218 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
219 if (!cfg) {
220 dev_err(dev, "failed to alloc memory for configs\n");
221 goto free_gname;
222 }
223
224 /* Prepare a list of config settings */
225 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
226 u32 value;
227 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
228 cfg[cfg_cnt++] =
229 PINCFG_PACK(pcfgs[idx].cfg_type, value);
230 }
231
232 /* create the config map entry */
233 map[*nmaps].data.configs.group_or_pin = gname;
234 map[*nmaps].data.configs.configs = cfg;
235 map[*nmaps].data.configs.num_configs = cfg_cnt;
236 map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
237 *nmaps += 1;
238
239skip_cfgs:
240 /* create the function map entry */
241 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
242 fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL);
243 if (!fname) {
244 dev_err(dev, "failed to alloc memory for func name\n");
245 goto free_cfg;
246 }
247 sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX);
248
249 map[*nmaps].data.mux.group = gname;
250 map[*nmaps].data.mux.function = fname;
251 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
252 *nmaps += 1;
253 }
254
255 *maps = map;
256 return 0;
257
258free_cfg:
259 kfree(cfg);
260free_gname:
261 kfree(gname);
262free_map:
263 kfree(map);
264 return -ENOMEM;
265}
266
267/* free the memory allocated to hold the pin-map table */
268static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
269 struct pinctrl_map *map, unsigned num_maps)
270{
271 int idx;
272
273 for (idx = 0; idx < num_maps; idx++) {
274 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
275 kfree(map[idx].data.mux.function);
276 if (!idx)
277 kfree(map[idx].data.mux.group);
278 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
279 kfree(map[idx].data.configs.configs);
280 if (!idx)
281 kfree(map[idx].data.configs.group_or_pin);
282 }
283 };
284
285 kfree(map);
286}
287
288/* list of pinctrl callbacks for the pinctrl core */
289static struct pinctrl_ops exynos5440_pctrl_ops = {
290 .get_groups_count = exynos5440_get_group_count,
291 .get_group_name = exynos5440_get_group_name,
292 .get_group_pins = exynos5440_get_group_pins,
293 .dt_node_to_map = exynos5440_dt_node_to_map,
294 .dt_free_map = exynos5440_dt_free_map,
295};
296
297/* check if the selector is a valid pin function selector */
298static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
299{
300 struct exynos5440_pinctrl_priv_data *priv;
301
302 priv = pinctrl_dev_get_drvdata(pctldev);
303 return priv->nr_functions;
304}
305
306/* return the name of the pin function specified */
307static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
308 unsigned selector)
309{
310 struct exynos5440_pinctrl_priv_data *priv;
311
312 priv = pinctrl_dev_get_drvdata(pctldev);
313 return priv->pmx_functions[selector].name;
314}
315
316/* return the groups associated for the specified function selector */
317static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
318 unsigned selector, const char * const **groups,
319 unsigned * const num_groups)
320{
321 struct exynos5440_pinctrl_priv_data *priv;
322
323 priv = pinctrl_dev_get_drvdata(pctldev);
324 *groups = priv->pmx_functions[selector].groups;
325 *num_groups = priv->pmx_functions[selector].num_groups;
326 return 0;
327}
328
329/* enable or disable a pinmux function */
330static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
331 unsigned group, bool enable)
332{
333 struct exynos5440_pinctrl_priv_data *priv;
334 void __iomem *base;
335 u32 function;
336 u32 data;
337
338 priv = pinctrl_dev_get_drvdata(pctldev);
339 base = priv->reg_base;
340 function = priv->pmx_functions[selector].function;
341
342 data = readl(base + GPIO_MUX);
343 if (enable)
344 data |= (1 << function);
345 else
346 data &= ~(1 << function);
347 writel(data, base + GPIO_MUX);
348}
349
350/* enable a specified pinmux by writing to registers */
351static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
352 unsigned group)
353{
354 exynos5440_pinmux_setup(pctldev, selector, group, true);
355 return 0;
356}
357
358/* disable a specified pinmux by writing to registers */
359static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev,
360 unsigned selector, unsigned group)
361{
362 exynos5440_pinmux_setup(pctldev, selector, group, false);
363}
364
365/*
366 * The calls to gpio_direction_output() and gpio_direction_input()
367 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
368 * function called from the gpiolib interface).
369 */
370static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
371 struct pinctrl_gpio_range *range, unsigned offset, bool input)
372{
373 return 0;
374}
375
376/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
377static struct pinmux_ops exynos5440_pinmux_ops = {
378 .get_functions_count = exynos5440_get_functions_count,
379 .get_function_name = exynos5440_pinmux_get_fname,
380 .get_function_groups = exynos5440_pinmux_get_groups,
381 .enable = exynos5440_pinmux_enable,
382 .disable = exynos5440_pinmux_disable,
383 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
384};
385
386/* set the pin config settings for a specified pin */
387static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
388 unsigned long config)
389{
390 struct exynos5440_pinctrl_priv_data *priv;
391 void __iomem *base;
392 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(config);
393 u32 cfg_value = PINCFG_UNPACK_VALUE(config);
394 u32 data;
395
396 priv = pinctrl_dev_get_drvdata(pctldev);
397 base = priv->reg_base;
398
399 switch (cfg_type) {
400 case PINCFG_TYPE_PUD:
401 /* first set pull enable/disable bit */
402 data = readl(base + GPIO_PE);
403 data &= ~(1 << pin);
404 if (cfg_value)
405 data |= (1 << pin);
406 writel(data, base + GPIO_PE);
407
408 /* then set pull up/down bit */
409 data = readl(base + GPIO_PS);
410 data &= ~(1 << pin);
411 if (cfg_value == 2)
412 data |= (1 << pin);
413 writel(data, base + GPIO_PS);
414 break;
415
416 case PINCFG_TYPE_DRV:
417 /* set the first bit of the drive strength */
418 data = readl(base + GPIO_DS0);
419 data &= ~(1 << pin);
420 data |= ((cfg_value & 1) << pin);
421 writel(data, base + GPIO_DS0);
422 cfg_value >>= 1;
423
424 /* set the second bit of the driver strength */
425 data = readl(base + GPIO_DS1);
426 data &= ~(1 << pin);
427 data |= ((cfg_value & 1) << pin);
428 writel(data, base + GPIO_DS1);
429 break;
430 case PINCFG_TYPE_SKEW_RATE:
431 data = readl(base + GPIO_SR);
432 data &= ~(1 << pin);
433 data |= ((cfg_value & 1) << pin);
434 writel(data, base + GPIO_SR);
435 break;
436 case PINCFG_TYPE_INPUT_TYPE:
437 data = readl(base + GPIO_TYPE);
438 data &= ~(1 << pin);
439 data |= ((cfg_value & 1) << pin);
440 writel(data, base + GPIO_TYPE);
441 break;
442 default:
443 WARN_ON(1);
444 return -EINVAL;
445 }
446
447 return 0;
448}
449
450/* get the pin config settings for a specified pin */
451static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
452 unsigned long *config)
453{
454 struct exynos5440_pinctrl_priv_data *priv;
455 void __iomem *base;
456 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
457 u32 data;
458
459 priv = pinctrl_dev_get_drvdata(pctldev);
460 base = priv->reg_base;
461
462 switch (cfg_type) {
463 case PINCFG_TYPE_PUD:
464 data = readl(base + GPIO_PE);
465 data = (data >> pin) & 1;
466 if (!data)
467 *config = 0;
468 else
469 *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
470 break;
471 case PINCFG_TYPE_DRV:
472 data = readl(base + GPIO_DS0);
473 data = (data >> pin) & 1;
474 *config = data;
475 data = readl(base + GPIO_DS1);
476 data = (data >> pin) & 1;
477 *config |= (data << 1);
478 break;
479 case PINCFG_TYPE_SKEW_RATE:
480 data = readl(base + GPIO_SR);
481 *config = (data >> pin) & 1;
482 break;
483 case PINCFG_TYPE_INPUT_TYPE:
484 data = readl(base + GPIO_TYPE);
485 *config = (data >> pin) & 1;
486 break;
487 default:
488 WARN_ON(1);
489 return -EINVAL;
490 }
491
492 return 0;
493}
494
495/* set the pin config settings for a specified pin group */
496static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
497 unsigned group, unsigned long config)
498{
499 struct exynos5440_pinctrl_priv_data *priv;
500 const unsigned int *pins;
501 unsigned int cnt;
502
503 priv = pinctrl_dev_get_drvdata(pctldev);
504 pins = priv->pin_groups[group].pins;
505
506 for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
507 exynos5440_pinconf_set(pctldev, pins[cnt], config);
508
509 return 0;
510}
511
512/* get the pin config settings for a specified pin group */
513static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
514 unsigned int group, unsigned long *config)
515{
516 struct exynos5440_pinctrl_priv_data *priv;
517 const unsigned int *pins;
518
519 priv = pinctrl_dev_get_drvdata(pctldev);
520 pins = priv->pin_groups[group].pins;
521 exynos5440_pinconf_get(pctldev, pins[0], config);
522 return 0;
523}
524
525/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
526static struct pinconf_ops exynos5440_pinconf_ops = {
527 .pin_config_get = exynos5440_pinconf_get,
528 .pin_config_set = exynos5440_pinconf_set,
529 .pin_config_group_get = exynos5440_pinconf_group_get,
530 .pin_config_group_set = exynos5440_pinconf_group_set,
531};
532
533/* gpiolib gpio_set callback function */
534static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
535{
536 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
537 void __iomem *base = priv->reg_base;
538 u32 data;
539
540 data = readl(base + GPIO_VAL);
541 data &= ~(1 << offset);
542 if (value)
543 data |= 1 << offset;
544 writel(data, base + GPIO_VAL);
545}
546
547/* gpiolib gpio_get callback function */
548static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
549{
550 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
551 void __iomem *base = priv->reg_base;
552 u32 data;
553
554 data = readl(base + GPIO_IN);
555 data >>= offset;
556 data &= 1;
557 return data;
558}
559
560/* gpiolib gpio_direction_input callback function */
561static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
562{
563 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
564 void __iomem *base = priv->reg_base;
565 u32 data;
566
567 /* first disable the data output enable on this pin */
568 data = readl(base + GPIO_OE);
569 data &= ~(1 << offset);
570 writel(data, base + GPIO_OE);
571
572 /* now enable input on this pin */
573 data = readl(base + GPIO_IE);
574 data |= 1 << offset;
575 writel(data, base + GPIO_IE);
576 return 0;
577}
578
579/* gpiolib gpio_direction_output callback function */
580static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
581 int value)
582{
583 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
584 void __iomem *base = priv->reg_base;
585 u32 data;
586
587 exynos5440_gpio_set(gc, offset, value);
588
589 /* first disable the data input enable on this pin */
590 data = readl(base + GPIO_IE);
591 data &= ~(1 << offset);
592 writel(data, base + GPIO_IE);
593
594 /* now enable output on this pin */
595 data = readl(base + GPIO_OE);
596 data |= 1 << offset;
597 writel(data, base + GPIO_OE);
598 return 0;
599}
600
601/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
602static int __init exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
603 struct device_node *cfg_np, unsigned int **pin_list,
604 unsigned int *npins)
605{
606 struct device *dev = &pdev->dev;
607 struct property *prop;
608
609 prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
610 if (!prop)
611 return -ENOENT;
612
613 *npins = prop->length / sizeof(unsigned long);
614 if (!*npins) {
615 dev_err(dev, "invalid pin list in %s node", cfg_np->name);
616 return -EINVAL;
617 }
618
619 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
620 if (!*pin_list) {
621 dev_err(dev, "failed to allocate memory for pin list\n");
622 return -ENOMEM;
623 }
624
625 return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
626 *pin_list, *npins);
627}
628
629/*
630 * Parse the information about all the available pin groups and pin functions
631 * from device node of the pin-controller.
632 */
633static int __init exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
634 struct exynos5440_pinctrl_priv_data *priv)
635{
636 struct device *dev = &pdev->dev;
637 struct device_node *dev_np = dev->of_node;
638 struct device_node *cfg_np;
639 struct exynos5440_pin_group *groups, *grp;
640 struct exynos5440_pmx_func *functions, *func;
641 unsigned *pin_list;
642 unsigned int npins, grp_cnt, func_idx = 0;
643 char *gname, *fname;
644 int ret;
645
646 grp_cnt = of_get_child_count(dev_np);
647 if (!grp_cnt)
648 return -EINVAL;
649
650 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
651 if (!groups) {
652 dev_err(dev, "failed allocate memory for ping group list\n");
653 return -EINVAL;
654 }
655 grp = groups;
656
657 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
658 if (!functions) {
659 dev_err(dev, "failed to allocate memory for function list\n");
660 return -EINVAL;
661 }
662 func = functions;
663
664 /*
665 * Iterate over all the child nodes of the pin controller node
666 * and create pin groups and pin function lists.
667 */
668 for_each_child_of_node(dev_np, cfg_np) {
669 u32 function;
670
671 ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
672 &pin_list, &npins);
673 if (ret)
674 return ret;
675
676 /* derive pin group name from the node name */
677 gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN,
678 GFP_KERNEL);
679 if (!gname) {
680 dev_err(dev, "failed to alloc memory for group name\n");
681 return -ENOMEM;
682 }
683 sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX);
684
685 grp->name = gname;
686 grp->pins = pin_list;
687 grp->num_pins = npins;
688 grp++;
689
690 ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
691 &function);
692 if (ret)
693 continue;
694
695 /* derive function name from the node name */
696 fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN,
697 GFP_KERNEL);
698 if (!fname) {
699 dev_err(dev, "failed to alloc memory for func name\n");
700 return -ENOMEM;
701 }
702 sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX);
703
704 func->name = fname;
705 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
706 if (!func->groups) {
707 dev_err(dev, "failed to alloc memory for group list "
708 "in pin function");
709 return -ENOMEM;
710 }
711 func->groups[0] = gname;
712 func->num_groups = 1;
713 func->function = function;
714 func++;
715 func_idx++;
716 }
717
718 priv->pin_groups = groups;
719 priv->nr_groups = grp_cnt;
720 priv->pmx_functions = functions;
721 priv->nr_functions = func_idx;
722 return 0;
723}
724
725/* register the pinctrl interface with the pinctrl subsystem */
726static int __init exynos5440_pinctrl_register(struct platform_device *pdev,
727 struct exynos5440_pinctrl_priv_data *priv)
728{
729 struct device *dev = &pdev->dev;
730 struct pinctrl_desc *ctrldesc;
731 struct pinctrl_dev *pctl_dev;
732 struct pinctrl_pin_desc *pindesc, *pdesc;
733 struct pinctrl_gpio_range grange;
734 char *pin_names;
735 int pin, ret;
736
737 ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
738 if (!ctrldesc) {
739 dev_err(dev, "could not allocate memory for pinctrl desc\n");
740 return -ENOMEM;
741 }
742
743 ctrldesc->name = "exynos5440-pinctrl";
744 ctrldesc->owner = THIS_MODULE;
745 ctrldesc->pctlops = &exynos5440_pctrl_ops;
746 ctrldesc->pmxops = &exynos5440_pinmux_ops;
747 ctrldesc->confops = &exynos5440_pinconf_ops;
748
749 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
750 EXYNOS5440_MAX_PINS, GFP_KERNEL);
751 if (!pindesc) {
752 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
753 return -ENOMEM;
754 }
755 ctrldesc->pins = pindesc;
756 ctrldesc->npins = EXYNOS5440_MAX_PINS;
757
758 /* dynamically populate the pin number and pin name for pindesc */
759 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
760 pdesc->number = pin;
761
762 /*
763 * allocate space for storing the dynamically generated names for all
764 * the pins which belong to this pin-controller.
765 */
766 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
767 ctrldesc->npins, GFP_KERNEL);
768 if (!pin_names) {
769 dev_err(&pdev->dev, "mem alloc for pin names failed\n");
770 return -ENOMEM;
771 }
772
773 /* for each pin, set the name of the pin */
774 for (pin = 0; pin < ctrldesc->npins; pin++) {
775 sprintf(pin_names, "gpio%02d", pin);
776 pdesc = pindesc + pin;
777 pdesc->name = pin_names;
778 pin_names += PIN_NAME_LENGTH;
779 }
780
781 ret = exynos5440_pinctrl_parse_dt(pdev, priv);
782 if (ret)
783 return ret;
784
785 pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv);
786 if (!pctl_dev) {
787 dev_err(&pdev->dev, "could not register pinctrl driver\n");
788 return -EINVAL;
789 }
790
791 grange.name = "exynos5440-pctrl-gpio-range";
792 grange.id = 0;
793 grange.base = 0;
794 grange.npins = EXYNOS5440_MAX_PINS;
795 grange.gc = priv->gc;
796 pinctrl_add_gpio_range(pctl_dev, &grange);
797 return 0;
798}
799
800/* register the gpiolib interface with the gpiolib subsystem */
801static int __init exynos5440_gpiolib_register(struct platform_device *pdev,
802 struct exynos5440_pinctrl_priv_data *priv)
803{
804 struct gpio_chip *gc;
805 int ret;
806
807 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
808 if (!gc) {
809 dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
810 return -ENOMEM;
811 }
812
813 priv->gc = gc;
814 gc->base = 0;
815 gc->ngpio = EXYNOS5440_MAX_PINS;
816 gc->dev = &pdev->dev;
817 gc->set = exynos5440_gpio_set;
818 gc->get = exynos5440_gpio_get;
819 gc->direction_input = exynos5440_gpio_direction_input;
820 gc->direction_output = exynos5440_gpio_direction_output;
821 gc->label = "gpiolib-exynos5440";
822 gc->owner = THIS_MODULE;
823 ret = gpiochip_add(gc);
824 if (ret) {
825 dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
826 "code: %d\n", gc->label, ret);
827 return ret;
828 }
829
830 return 0;
831}
832
833/* unregister the gpiolib interface with the gpiolib subsystem */
834static int __init exynos5440_gpiolib_unregister(struct platform_device *pdev,
835 struct exynos5440_pinctrl_priv_data *priv)
836{
837 int ret = gpiochip_remove(priv->gc);
838 if (ret) {
839 dev_err(&pdev->dev, "gpio chip remove failed\n");
840 return ret;
841 }
842 return 0;
843}
844
845static int __devinit exynos5440_pinctrl_probe(struct platform_device *pdev)
846{
847 struct device *dev = &pdev->dev;
848 struct exynos5440_pinctrl_priv_data *priv;
849 struct resource *res;
850 int ret;
851
852 if (!dev->of_node) {
853 dev_err(dev, "device tree node not found\n");
854 return -ENODEV;
855 }
856
857 priv = devm_kzalloc(dev, sizeof(priv), GFP_KERNEL);
858 if (!priv) {
859 dev_err(dev, "could not allocate memory for private data\n");
860 return -ENOMEM;
861 }
862
863 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
864 if (!res) {
865 dev_err(dev, "cannot find IO resource\n");
866 return -ENOENT;
867 }
868
869 priv->reg_base = devm_request_and_ioremap(&pdev->dev, res);
870 if (!priv->reg_base) {
871 dev_err(dev, "ioremap failed\n");
872 return -ENODEV;
873 }
874
875 ret = exynos5440_gpiolib_register(pdev, priv);
876 if (ret)
877 return ret;
878
879 ret = exynos5440_pinctrl_register(pdev, priv);
880 if (ret) {
881 exynos5440_gpiolib_unregister(pdev, priv);
882 return ret;
883 }
884
885 platform_set_drvdata(pdev, priv);
886 dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
887 return 0;
888}
889
890static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
891 { .compatible = "samsung,exynos5440-pinctrl" },
892 {},
893};
894MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match);
895
896static struct platform_driver exynos5440_pinctrl_driver = {
897 .probe = exynos5440_pinctrl_probe,
898 .driver = {
899 .name = "exynos5440-pinctrl",
900 .owner = THIS_MODULE,
901 .of_match_table = of_match_ptr(exynos5440_pinctrl_dt_match),
902 },
903};
904
905static int __init exynos5440_pinctrl_drv_register(void)
906{
907 return platform_driver_register(&exynos5440_pinctrl_driver);
908}
909postcore_initcall(exynos5440_pinctrl_drv_register);
910
911static void __exit exynos5440_pinctrl_drv_unregister(void)
912{
913 platform_driver_unregister(&exynos5440_pinctrl_driver);
914}
915module_exit(exynos5440_pinctrl_drv_unregister);
916
917MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
918MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver");
919MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 861cd5f04d5e..8f31b656c4e9 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -26,6 +26,7 @@
26#include <linux/slab.h> 26#include <linux/slab.h>
27#include <linux/err.h> 27#include <linux/err.h>
28#include <linux/gpio.h> 28#include <linux/gpio.h>
29#include <linux/irqdomain.h>
29 30
30#include "core.h" 31#include "core.h"
31#include "pinctrl-samsung.h" 32#include "pinctrl-samsung.h"
@@ -46,6 +47,13 @@ struct pin_config {
46 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN }, 47 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
47}; 48};
48 49
50static unsigned int pin_base;
51
52static inline struct samsung_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
53{
54 return container_of(gc, struct samsung_pin_bank, gpio_chip);
55}
56
49/* check if the selector is a valid pin group selector */ 57/* check if the selector is a valid pin group selector */
50static int samsung_get_group_count(struct pinctrl_dev *pctldev) 58static int samsung_get_group_count(struct pinctrl_dev *pctldev)
51{ 59{
@@ -250,14 +258,12 @@ static int samsung_pinmux_get_groups(struct pinctrl_dev *pctldev,
250 * given a pin number that is local to a pin controller, find out the pin bank 258 * given a pin number that is local to a pin controller, find out the pin bank
251 * and the register base of the pin bank. 259 * and the register base of the pin bank.
252 */ 260 */
253static void pin_to_reg_bank(struct gpio_chip *gc, unsigned pin, 261static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
254 void __iomem **reg, u32 *offset, 262 unsigned pin, void __iomem **reg, u32 *offset,
255 struct samsung_pin_bank **bank) 263 struct samsung_pin_bank **bank)
256{ 264{
257 struct samsung_pinctrl_drv_data *drvdata;
258 struct samsung_pin_bank *b; 265 struct samsung_pin_bank *b;
259 266
260 drvdata = dev_get_drvdata(gc->dev);
261 b = drvdata->ctrl->pin_banks; 267 b = drvdata->ctrl->pin_banks;
262 268
263 while ((pin >= b->pin_base) && 269 while ((pin >= b->pin_base) &&
@@ -292,7 +298,7 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
292 * pin function number in the config register. 298 * pin function number in the config register.
293 */ 299 */
294 for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) { 300 for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) {
295 pin_to_reg_bank(drvdata->gc, pins[cnt] - drvdata->ctrl->base, 301 pin_to_reg_bank(drvdata, pins[cnt] - drvdata->ctrl->base,
296 &reg, &pin_offset, &bank); 302 &reg, &pin_offset, &bank);
297 mask = (1 << bank->func_width) - 1; 303 mask = (1 << bank->func_width) - 1;
298 shift = pin_offset * bank->func_width; 304 shift = pin_offset * bank->func_width;
@@ -329,10 +335,16 @@ static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
329 struct pinctrl_gpio_range *range, unsigned offset, bool input) 335 struct pinctrl_gpio_range *range, unsigned offset, bool input)
330{ 336{
331 struct samsung_pin_bank *bank; 337 struct samsung_pin_bank *bank;
338 struct samsung_pinctrl_drv_data *drvdata;
332 void __iomem *reg; 339 void __iomem *reg;
333 u32 data, pin_offset, mask, shift; 340 u32 data, pin_offset, mask, shift;
334 341
335 pin_to_reg_bank(range->gc, offset, &reg, &pin_offset, &bank); 342 bank = gc_to_pin_bank(range->gc);
343 drvdata = pinctrl_dev_get_drvdata(pctldev);
344
345 pin_offset = offset - bank->pin_base;
346 reg = drvdata->virt_base + bank->pctl_offset;
347
336 mask = (1 << bank->func_width) - 1; 348 mask = (1 << bank->func_width) - 1;
337 shift = pin_offset * bank->func_width; 349 shift = pin_offset * bank->func_width;
338 350
@@ -366,7 +378,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
366 u32 cfg_value, cfg_reg; 378 u32 cfg_value, cfg_reg;
367 379
368 drvdata = pinctrl_dev_get_drvdata(pctldev); 380 drvdata = pinctrl_dev_get_drvdata(pctldev);
369 pin_to_reg_bank(drvdata->gc, pin - drvdata->ctrl->base, &reg_base, 381 pin_to_reg_bank(drvdata, pin - drvdata->ctrl->base, &reg_base,
370 &pin_offset, &bank); 382 &pin_offset, &bank);
371 383
372 switch (cfg_type) { 384 switch (cfg_type) {
@@ -391,6 +403,9 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
391 return -EINVAL; 403 return -EINVAL;
392 } 404 }
393 405
406 if (!width)
407 return -EINVAL;
408
394 mask = (1 << width) - 1; 409 mask = (1 << width) - 1;
395 shift = pin_offset * width; 410 shift = pin_offset * width;
396 data = readl(reg_base + cfg_reg); 411 data = readl(reg_base + cfg_reg);
@@ -463,14 +478,16 @@ static struct pinconf_ops samsung_pinconf_ops = {
463/* gpiolib gpio_set callback function */ 478/* gpiolib gpio_set callback function */
464static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 479static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
465{ 480{
481 struct samsung_pin_bank *bank = gc_to_pin_bank(gc);
466 void __iomem *reg; 482 void __iomem *reg;
467 u32 pin_offset, data; 483 u32 data;
484
485 reg = bank->drvdata->virt_base + bank->pctl_offset;
468 486
469 pin_to_reg_bank(gc, offset, &reg, &pin_offset, NULL);
470 data = readl(reg + DAT_REG); 487 data = readl(reg + DAT_REG);
471 data &= ~(1 << pin_offset); 488 data &= ~(1 << offset);
472 if (value) 489 if (value)
473 data |= 1 << pin_offset; 490 data |= 1 << offset;
474 writel(data, reg + DAT_REG); 491 writel(data, reg + DAT_REG);
475} 492}
476 493
@@ -478,11 +495,13 @@ static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
478static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset) 495static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
479{ 496{
480 void __iomem *reg; 497 void __iomem *reg;
481 u32 pin_offset, data; 498 u32 data;
499 struct samsung_pin_bank *bank = gc_to_pin_bank(gc);
500
501 reg = bank->drvdata->virt_base + bank->pctl_offset;
482 502
483 pin_to_reg_bank(gc, offset, &reg, &pin_offset, NULL);
484 data = readl(reg + DAT_REG); 503 data = readl(reg + DAT_REG);
485 data >>= pin_offset; 504 data >>= offset;
486 data &= 1; 505 data &= 1;
487 return data; 506 return data;
488} 507}
@@ -510,6 +529,23 @@ static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
510} 529}
511 530
512/* 531/*
532 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
533 * and a virtual IRQ, if not already present.
534 */
535static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
536{
537 struct samsung_pin_bank *bank = gc_to_pin_bank(gc);
538 unsigned int virq;
539
540 if (!bank->irq_domain)
541 return -ENXIO;
542
543 virq = irq_create_mapping(bank->irq_domain, offset);
544
545 return (virq) ? : -ENXIO;
546}
547
548/*
513 * Parse the pin names listed in the 'samsung,pins' property and convert it 549 * Parse the pin names listed in the 'samsung,pins' property and convert it
514 * into a list of gpio numbers are create a pin group from it. 550 * into a list of gpio numbers are create a pin group from it.
515 */ 551 */
@@ -524,7 +560,7 @@ static int __devinit samsung_pinctrl_parse_dt_pins(struct platform_device *pdev,
524 const char *pin_name; 560 const char *pin_name;
525 561
526 *npins = of_property_count_strings(cfg_np, "samsung,pins"); 562 *npins = of_property_count_strings(cfg_np, "samsung,pins");
527 if (*npins < 0) { 563 if (IS_ERR_VALUE(*npins)) {
528 dev_err(dev, "invalid pin list in %s node", cfg_np->name); 564 dev_err(dev, "invalid pin list in %s node", cfg_np->name);
529 return -EINVAL; 565 return -EINVAL;
530 } 566 }
@@ -597,7 +633,7 @@ static int __devinit samsung_pinctrl_parse_dt(struct platform_device *pdev,
597 */ 633 */
598 for_each_child_of_node(dev_np, cfg_np) { 634 for_each_child_of_node(dev_np, cfg_np) {
599 u32 function; 635 u32 function;
600 if (of_find_property(cfg_np, "interrupt-controller", NULL)) 636 if (!of_find_property(cfg_np, "samsung,pins", NULL))
601 continue; 637 continue;
602 638
603 ret = samsung_pinctrl_parse_dt_pins(pdev, cfg_np, 639 ret = samsung_pinctrl_parse_dt_pins(pdev, cfg_np,
@@ -712,12 +748,16 @@ static int __devinit samsung_pinctrl_register(struct platform_device *pdev,
712 return -EINVAL; 748 return -EINVAL;
713 } 749 }
714 750
715 drvdata->grange.name = "samsung-pctrl-gpio-range"; 751 for (bank = 0; bank < drvdata->ctrl->nr_banks; ++bank) {
716 drvdata->grange.id = 0; 752 pin_bank = &drvdata->ctrl->pin_banks[bank];
717 drvdata->grange.base = drvdata->ctrl->base; 753 pin_bank->grange.name = pin_bank->name;
718 drvdata->grange.npins = drvdata->ctrl->nr_pins; 754 pin_bank->grange.id = bank;
719 drvdata->grange.gc = drvdata->gc; 755 pin_bank->grange.pin_base = pin_bank->pin_base;
720 pinctrl_add_gpio_range(drvdata->pctl_dev, &drvdata->grange); 756 pin_bank->grange.base = pin_bank->gpio_chip.base;
757 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
758 pin_bank->grange.gc = &pin_bank->gpio_chip;
759 pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange);
760 }
721 761
722 ret = samsung_pinctrl_parse_dt(pdev, drvdata); 762 ret = samsung_pinctrl_parse_dt(pdev, drvdata);
723 if (ret) { 763 if (ret) {
@@ -728,68 +768,117 @@ static int __devinit samsung_pinctrl_register(struct platform_device *pdev,
728 return 0; 768 return 0;
729} 769}
730 770
771static const struct gpio_chip samsung_gpiolib_chip = {
772 .set = samsung_gpio_set,
773 .get = samsung_gpio_get,
774 .direction_input = samsung_gpio_direction_input,
775 .direction_output = samsung_gpio_direction_output,
776 .to_irq = samsung_gpio_to_irq,
777 .owner = THIS_MODULE,
778};
779
731/* register the gpiolib interface with the gpiolib subsystem */ 780/* register the gpiolib interface with the gpiolib subsystem */
732static int __devinit samsung_gpiolib_register(struct platform_device *pdev, 781static int __devinit samsung_gpiolib_register(struct platform_device *pdev,
733 struct samsung_pinctrl_drv_data *drvdata) 782 struct samsung_pinctrl_drv_data *drvdata)
734{ 783{
784 struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
785 struct samsung_pin_bank *bank = ctrl->pin_banks;
735 struct gpio_chip *gc; 786 struct gpio_chip *gc;
736 int ret; 787 int ret;
737 788 int i;
738 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); 789
739 if (!gc) { 790 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
740 dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n"); 791 bank->gpio_chip = samsung_gpiolib_chip;
741 return -ENOMEM; 792
742 } 793 gc = &bank->gpio_chip;
743 794 gc->base = ctrl->base + bank->pin_base;
744 drvdata->gc = gc; 795 gc->ngpio = bank->nr_pins;
745 gc->base = drvdata->ctrl->base; 796 gc->dev = &pdev->dev;
746 gc->ngpio = drvdata->ctrl->nr_pins; 797 gc->of_node = bank->of_node;
747 gc->dev = &pdev->dev; 798 gc->label = bank->name;
748 gc->set = samsung_gpio_set; 799
749 gc->get = samsung_gpio_get; 800 ret = gpiochip_add(gc);
750 gc->direction_input = samsung_gpio_direction_input; 801 if (ret) {
751 gc->direction_output = samsung_gpio_direction_output; 802 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
752 gc->label = drvdata->ctrl->label; 803 gc->label, ret);
753 gc->owner = THIS_MODULE; 804 goto fail;
754 ret = gpiochip_add(gc); 805 }
755 if (ret) {
756 dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
757 "code: %d\n", gc->label, ret);
758 return ret;
759 } 806 }
760 807
761 return 0; 808 return 0;
809
810fail:
811 for (--i, --bank; i >= 0; --i, --bank)
812 if (gpiochip_remove(&bank->gpio_chip))
813 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
814 bank->gpio_chip.label);
815 return ret;
762} 816}
763 817
764/* unregister the gpiolib interface with the gpiolib subsystem */ 818/* unregister the gpiolib interface with the gpiolib subsystem */
765static int __devinit samsung_gpiolib_unregister(struct platform_device *pdev, 819static int __devinit samsung_gpiolib_unregister(struct platform_device *pdev,
766 struct samsung_pinctrl_drv_data *drvdata) 820 struct samsung_pinctrl_drv_data *drvdata)
767{ 821{
768 int ret = gpiochip_remove(drvdata->gc); 822 struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
769 if (ret) { 823 struct samsung_pin_bank *bank = ctrl->pin_banks;
824 int ret = 0;
825 int i;
826
827 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank)
828 ret = gpiochip_remove(&bank->gpio_chip);
829
830 if (ret)
770 dev_err(&pdev->dev, "gpio chip remove failed\n"); 831 dev_err(&pdev->dev, "gpio chip remove failed\n");
771 return ret; 832
772 } 833 return ret;
773 return 0;
774} 834}
775 835
776static const struct of_device_id samsung_pinctrl_dt_match[]; 836static const struct of_device_id samsung_pinctrl_dt_match[];
777 837
778/* retrieve the soc specific data */ 838/* retrieve the soc specific data */
779static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data( 839static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
840 struct samsung_pinctrl_drv_data *d,
780 struct platform_device *pdev) 841 struct platform_device *pdev)
781{ 842{
782 int id; 843 int id;
783 const struct of_device_id *match; 844 const struct of_device_id *match;
784 const struct device_node *node = pdev->dev.of_node; 845 struct device_node *node = pdev->dev.of_node;
846 struct device_node *np;
847 struct samsung_pin_ctrl *ctrl;
848 struct samsung_pin_bank *bank;
849 int i;
785 850
786 id = of_alias_get_id(pdev->dev.of_node, "pinctrl"); 851 id = of_alias_get_id(node, "pinctrl");
787 if (id < 0) { 852 if (id < 0) {
788 dev_err(&pdev->dev, "failed to get alias id\n"); 853 dev_err(&pdev->dev, "failed to get alias id\n");
789 return NULL; 854 return NULL;
790 } 855 }
791 match = of_match_node(samsung_pinctrl_dt_match, node); 856 match = of_match_node(samsung_pinctrl_dt_match, node);
792 return (struct samsung_pin_ctrl *)match->data + id; 857 ctrl = (struct samsung_pin_ctrl *)match->data + id;
858
859 bank = ctrl->pin_banks;
860 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
861 bank->drvdata = d;
862 bank->pin_base = ctrl->nr_pins;
863 ctrl->nr_pins += bank->nr_pins;
864 }
865
866 for_each_child_of_node(node, np) {
867 if (!of_find_property(np, "gpio-controller", NULL))
868 continue;
869 bank = ctrl->pin_banks;
870 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
871 if (!strcmp(bank->name, np->name)) {
872 bank->of_node = np;
873 break;
874 }
875 }
876 }
877
878 ctrl->base = pin_base;
879 pin_base += ctrl->nr_pins;
880
881 return ctrl;
793} 882}
794 883
795static int __devinit samsung_pinctrl_probe(struct platform_device *pdev) 884static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
@@ -805,18 +894,18 @@ static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
805 return -ENODEV; 894 return -ENODEV;
806 } 895 }
807 896
808 ctrl = samsung_pinctrl_get_soc_data(pdev);
809 if (!ctrl) {
810 dev_err(&pdev->dev, "driver data not available\n");
811 return -EINVAL;
812 }
813
814 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 897 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
815 if (!drvdata) { 898 if (!drvdata) {
816 dev_err(dev, "failed to allocate memory for driver's " 899 dev_err(dev, "failed to allocate memory for driver's "
817 "private data\n"); 900 "private data\n");
818 return -ENOMEM; 901 return -ENOMEM;
819 } 902 }
903
904 ctrl = samsung_pinctrl_get_soc_data(drvdata, pdev);
905 if (!ctrl) {
906 dev_err(&pdev->dev, "driver data not available\n");
907 return -EINVAL;
908 }
820 drvdata->ctrl = ctrl; 909 drvdata->ctrl = ctrl;
821 drvdata->dev = dev; 910 drvdata->dev = dev;
822 911
@@ -858,6 +947,8 @@ static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
858static const struct of_device_id samsung_pinctrl_dt_match[] = { 947static const struct of_device_id samsung_pinctrl_dt_match[] = {
859 { .compatible = "samsung,pinctrl-exynos4210", 948 { .compatible = "samsung,pinctrl-exynos4210",
860 .data = (void *)exynos4210_pin_ctrl }, 949 .data = (void *)exynos4210_pin_ctrl },
950 { .compatible = "samsung,pinctrl-exynos4x12",
951 .data = (void *)exynos4x12_pin_ctrl },
861 {}, 952 {},
862}; 953};
863MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match); 954MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match);
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index b8956934cda6..5addfd16e3cc 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -23,6 +23,8 @@
23#include <linux/pinctrl/consumer.h> 23#include <linux/pinctrl/consumer.h>
24#include <linux/pinctrl/machine.h> 24#include <linux/pinctrl/machine.h>
25 25
26#include <linux/gpio.h>
27
26/* register offsets within a pin bank */ 28/* register offsets within a pin bank */
27#define DAT_REG 0x4 29#define DAT_REG 0x4
28#define PUD_REG 0x8 30#define PUD_REG 0x8
@@ -64,6 +66,7 @@ enum pincfg_type {
64 * @EINT_TYPE_NONE: bank does not support external interrupts 66 * @EINT_TYPE_NONE: bank does not support external interrupts
65 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts 67 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
66 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts 68 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
69 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
67 * 70 *
68 * Samsung GPIO controller groups all the available pins into banks. The pins 71 * Samsung GPIO controller groups all the available pins into banks. The pins
69 * in a pin bank can support external gpio interrupts or external wakeup 72 * in a pin bank can support external gpio interrupts or external wakeup
@@ -76,6 +79,7 @@ enum eint_type {
76 EINT_TYPE_NONE, 79 EINT_TYPE_NONE,
77 EINT_TYPE_GPIO, 80 EINT_TYPE_GPIO,
78 EINT_TYPE_WKUP, 81 EINT_TYPE_WKUP,
82 EINT_TYPE_WKUP_MUX,
79}; 83};
80 84
81/* maximum length of a pin in pin descriptor (example: "gpa0-0") */ 85/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
@@ -109,8 +113,12 @@ struct samsung_pinctrl_drv_data;
109 * @conpdn_width: width of the sleep mode function selector bin field. 113 * @conpdn_width: width of the sleep mode function selector bin field.
110 * @pudpdn_width: width of the sleep mode pull up/down selector bit field. 114 * @pudpdn_width: width of the sleep mode pull up/down selector bit field.
111 * @eint_type: type of the external interrupt supported by the bank. 115 * @eint_type: type of the external interrupt supported by the bank.
112 * @irq_base: starting controller local irq number of the bank.
113 * @name: name to be prefixed for each pin in this pin bank. 116 * @name: name to be prefixed for each pin in this pin bank.
117 * @of_node: OF node of the bank.
118 * @drvdata: link to controller driver data
119 * @irq_domain: IRQ domain of the bank.
120 * @gpio_chip: GPIO chip of the bank.
121 * @grange: linux gpio pin range supported by this bank.
114 */ 122 */
115struct samsung_pin_bank { 123struct samsung_pin_bank {
116 u32 pctl_offset; 124 u32 pctl_offset;
@@ -122,8 +130,13 @@ struct samsung_pin_bank {
122 u8 conpdn_width; 130 u8 conpdn_width;
123 u8 pudpdn_width; 131 u8 pudpdn_width;
124 enum eint_type eint_type; 132 enum eint_type eint_type;
125 u32 irq_base; 133 u32 eint_offset;
126 char *name; 134 char *name;
135 struct device_node *of_node;
136 struct samsung_pinctrl_drv_data *drvdata;
137 struct irq_domain *irq_domain;
138 struct gpio_chip gpio_chip;
139 struct pinctrl_gpio_range grange;
127}; 140};
128 141
129/** 142/**
@@ -132,8 +145,6 @@ struct samsung_pin_bank {
132 * @nr_banks: number of pin banks. 145 * @nr_banks: number of pin banks.
133 * @base: starting system wide pin number. 146 * @base: starting system wide pin number.
134 * @nr_pins: number of pins supported by the controller. 147 * @nr_pins: number of pins supported by the controller.
135 * @nr_gint: number of external gpio interrupts supported.
136 * @nr_wint: number of external wakeup interrupts supported.
137 * @geint_con: offset of the ext-gpio controller registers. 148 * @geint_con: offset of the ext-gpio controller registers.
138 * @geint_mask: offset of the ext-gpio interrupt mask registers. 149 * @geint_mask: offset of the ext-gpio interrupt mask registers.
139 * @geint_pend: offset of the ext-gpio interrupt pending registers. 150 * @geint_pend: offset of the ext-gpio interrupt pending registers.
@@ -153,8 +164,6 @@ struct samsung_pin_ctrl {
153 164
154 u32 base; 165 u32 base;
155 u32 nr_pins; 166 u32 nr_pins;
156 u32 nr_gint;
157 u32 nr_wint;
158 167
159 u32 geint_con; 168 u32 geint_con;
160 u32 geint_mask; 169 u32 geint_mask;
@@ -183,8 +192,6 @@ struct samsung_pin_ctrl {
183 * @nr_groups: number of such pin groups. 192 * @nr_groups: number of such pin groups.
184 * @pmx_functions: list of pin functions available to the driver. 193 * @pmx_functions: list of pin functions available to the driver.
185 * @nr_function: number of such pin functions. 194 * @nr_function: number of such pin functions.
186 * @gc: gpio_chip instance registered with gpiolib.
187 * @grange: linux gpio pin range supported by this controller.
188 */ 195 */
189struct samsung_pinctrl_drv_data { 196struct samsung_pinctrl_drv_data {
190 void __iomem *virt_base; 197 void __iomem *virt_base;
@@ -199,12 +206,6 @@ struct samsung_pinctrl_drv_data {
199 unsigned int nr_groups; 206 unsigned int nr_groups;
200 const struct samsung_pmx_func *pmx_functions; 207 const struct samsung_pmx_func *pmx_functions;
201 unsigned int nr_functions; 208 unsigned int nr_functions;
202
203 struct irq_domain *gpio_irqd;
204 struct irq_domain *wkup_irqd;
205
206 struct gpio_chip *gc;
207 struct pinctrl_gpio_range grange;
208}; 209};
209 210
210/** 211/**
@@ -235,5 +236,6 @@ struct samsung_pmx_func {
235 236
236/* list of all exported SoC specific data */ 237/* list of all exported SoC specific data */
237extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; 238extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
239extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
238 240
239#endif /* __PINCTRL_SAMSUNG_H */ 241#endif /* __PINCTRL_SAMSUNG_H */
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index 07e9fb4f8041..b3dc44146ca0 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -361,3 +361,89 @@ int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
361 return sh_clk_div_register_ops(clks, nr, table, 361 return sh_clk_div_register_ops(clks, nr, table,
362 &sh_clk_div4_reparent_clk_ops); 362 &sh_clk_div4_reparent_clk_ops);
363} 363}
364
365/* FSI-DIV */
366static unsigned long fsidiv_recalc(struct clk *clk)
367{
368 u32 value;
369
370 value = __raw_readl(clk->mapping->base);
371
372 value >>= 16;
373 if (value < 2)
374 return clk->parent->rate;
375
376 return clk->parent->rate / value;
377}
378
379static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
380{
381 return clk_rate_div_range_round(clk, 1, 0xffff, rate);
382}
383
384static void fsidiv_disable(struct clk *clk)
385{
386 __raw_writel(0, clk->mapping->base);
387}
388
389static int fsidiv_enable(struct clk *clk)
390{
391 u32 value;
392
393 value = __raw_readl(clk->mapping->base) >> 16;
394 if (value < 2)
395 return 0;
396
397 __raw_writel((value << 16) | 0x3, clk->mapping->base);
398
399 return 0;
400}
401
402static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
403{
404 u32 val;
405 int idx;
406
407 idx = (clk->parent->rate / rate) & 0xffff;
408 if (idx < 2)
409 __raw_writel(0, clk->mapping->base);
410 else
411 __raw_writel(idx << 16, clk->mapping->base);
412
413 return 0;
414}
415
416static struct sh_clk_ops fsidiv_clk_ops = {
417 .recalc = fsidiv_recalc,
418 .round_rate = fsidiv_round_rate,
419 .set_rate = fsidiv_set_rate,
420 .enable = fsidiv_enable,
421 .disable = fsidiv_disable,
422};
423
424int __init sh_clk_fsidiv_register(struct clk *clks, int nr)
425{
426 struct clk_mapping *map;
427 int i;
428
429 for (i = 0; i < nr; i++) {
430
431 map = kzalloc(sizeof(struct clk_mapping), GFP_KERNEL);
432 if (!map) {
433 pr_err("%s: unable to alloc memory\n", __func__);
434 return -ENOMEM;
435 }
436
437 /* clks[i].enable_reg came from SH_CLK_FSIDIV() */
438 map->phys = (phys_addr_t)clks[i].enable_reg;
439 map->len = 8;
440
441 clks[i].enable_reg = 0; /* remove .enable_reg */
442 clks[i].ops = &fsidiv_clk_ops;
443 clks[i].mapping = map;
444
445 clk_register(&clks[i]);
446 }
447
448 return 0;
449}
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index fb0e0f0bed0e..12e5249d053e 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1654,7 +1654,8 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1654#endif 1654#endif
1655 1655
1656#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \ 1656#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
1657 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) 1657 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
1658 defined(CONFIG_SOC_EXYNOS5440)
1658static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { 1659static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1659 .info = &(struct s3c24xx_uart_info) { 1660 .info = &(struct s3c24xx_uart_info) {
1660 .name = "Samsung Exynos4 UART", 1661 .name = "Samsung Exynos4 UART",
diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig
index 82e2b89d4480..f56d185790ea 100644
--- a/drivers/uio/Kconfig
+++ b/drivers/uio/Kconfig
@@ -113,6 +113,7 @@ config UIO_NETX
113config UIO_PRUSS 113config UIO_PRUSS
114 tristate "Texas Instruments PRUSS driver" 114 tristate "Texas Instruments PRUSS driver"
115 depends on ARCH_DAVINCI_DA850 115 depends on ARCH_DAVINCI_DA850
116 select GENERIC_ALLOCATOR
116 help 117 help
117 PRUSS driver for OMAPL138/DA850/AM18XX devices 118 PRUSS driver for OMAPL138/DA850/AM18XX devices
118 PRUSS driver requires user space components, examples and user space 119 PRUSS driver requires user space components, examples and user space
diff --git a/drivers/uio/uio_pruss.c b/drivers/uio/uio_pruss.c
index cce0f78341cc..6e2ab007fe9c 100644
--- a/drivers/uio/uio_pruss.c
+++ b/drivers/uio/uio_pruss.c
@@ -25,7 +25,7 @@
25#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/dma-mapping.h> 26#include <linux/dma-mapping.h>
27#include <linux/slab.h> 27#include <linux/slab.h>
28#include <mach/sram.h> 28#include <linux/genalloc.h>
29 29
30#define DRV_NAME "pruss_uio" 30#define DRV_NAME "pruss_uio"
31#define DRV_VERSION "1.0" 31#define DRV_VERSION "1.0"
@@ -65,10 +65,11 @@ struct uio_pruss_dev {
65 dma_addr_t sram_paddr; 65 dma_addr_t sram_paddr;
66 dma_addr_t ddr_paddr; 66 dma_addr_t ddr_paddr;
67 void __iomem *prussio_vaddr; 67 void __iomem *prussio_vaddr;
68 void *sram_vaddr; 68 unsigned long sram_vaddr;
69 void *ddr_vaddr; 69 void *ddr_vaddr;
70 unsigned int hostirq_start; 70 unsigned int hostirq_start;
71 unsigned int pintc_base; 71 unsigned int pintc_base;
72 struct gen_pool *sram_pool;
72}; 73};
73 74
74static irqreturn_t pruss_handler(int irq, struct uio_info *info) 75static irqreturn_t pruss_handler(int irq, struct uio_info *info)
@@ -106,7 +107,9 @@ static void pruss_cleanup(struct platform_device *dev,
106 gdev->ddr_paddr); 107 gdev->ddr_paddr);
107 } 108 }
108 if (gdev->sram_vaddr) 109 if (gdev->sram_vaddr)
109 sram_free(gdev->sram_vaddr, sram_pool_sz); 110 gen_pool_free(gdev->sram_pool,
111 gdev->sram_vaddr,
112 sram_pool_sz);
110 kfree(gdev->info); 113 kfree(gdev->info);
111 clk_put(gdev->pruss_clk); 114 clk_put(gdev->pruss_clk);
112 kfree(gdev); 115 kfree(gdev);
@@ -152,10 +155,17 @@ static int pruss_probe(struct platform_device *dev)
152 goto out_free; 155 goto out_free;
153 } 156 }
154 157
155 gdev->sram_vaddr = sram_alloc(sram_pool_sz, &(gdev->sram_paddr)); 158 if (pdata->sram_pool) {
156 if (!gdev->sram_vaddr) { 159 gdev->sram_pool = pdata->sram_pool;
157 dev_err(&dev->dev, "Could not allocate SRAM pool\n"); 160 gdev->sram_vaddr =
158 goto out_free; 161 gen_pool_alloc(gdev->sram_pool, sram_pool_sz);
162 if (!gdev->sram_vaddr) {
163 dev_err(&dev->dev, "Could not allocate SRAM pool\n");
164 goto out_free;
165 }
166 gdev->sram_paddr =
167 gen_pool_virt_to_phys(gdev->sram_pool,
168 gdev->sram_vaddr);
159 } 169 }
160 170
161 gdev->ddr_vaddr = dma_alloc_coherent(&dev->dev, extram_pool_sz, 171 gdev->ddr_vaddr = dma_alloc_coherent(&dev->dev, extram_pool_sz,
diff --git a/drivers/video/clps711xfb.c b/drivers/video/clps711xfb.c
index f994c8b8f10a..63ecdf8f7baf 100644
--- a/drivers/video/clps711xfb.c
+++ b/drivers/video/clps711xfb.c
@@ -22,19 +22,15 @@
22#include <linux/mm.h> 22#include <linux/mm.h>
23#include <linux/module.h> 23#include <linux/module.h>
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/seq_file.h>
26#include <linux/slab.h> 25#include <linux/slab.h>
27#include <linux/fb.h> 26#include <linux/fb.h>
28#include <linux/init.h> 27#include <linux/init.h>
29#include <linux/proc_fs.h>
30#include <linux/delay.h> 28#include <linux/delay.h>
31 29
32#include <mach/hardware.h> 30#include <mach/hardware.h>
33#include <asm/mach-types.h> 31#include <asm/mach-types.h>
34#include <linux/uaccess.h> 32#include <linux/uaccess.h>
35 33
36#include <mach/syspld.h>
37
38struct fb_info *cfb; 34struct fb_info *cfb;
39 35
40#define CMAP_MAX_SIZE 16 36#define CMAP_MAX_SIZE 16
@@ -162,44 +158,12 @@ clps7111fb_set_par(struct fb_info *info)
162 158
163static int clps7111fb_blank(int blank, struct fb_info *info) 159static int clps7111fb_blank(int blank, struct fb_info *info)
164{ 160{
165 if (blank) { 161 /* Enable/Disable LCD controller. */
166 if (machine_is_edb7211()) { 162 if (blank)
167 /* Turn off the LCD backlight. */ 163 clps_writel(clps_readl(SYSCON1) & ~SYSCON1_LCDEN, SYSCON1);
168 clps_writeb(clps_readb(PDDR) & ~EDB_PD3_LCDBL, PDDR); 164 else
169 165 clps_writel(clps_readl(SYSCON1) | SYSCON1_LCDEN, SYSCON1);
170 /* Power off the LCD DC-DC converter. */
171 clps_writeb(clps_readb(PDDR) & ~EDB_PD1_LCD_DC_DC_EN, PDDR);
172
173 /* Delay for a little while (half a second). */
174 udelay(100);
175
176 /* Power off the LCD panel. */
177 clps_writeb(clps_readb(PDDR) & ~EDB_PD2_LCDEN, PDDR);
178
179 /* Power off the LCD controller. */
180 clps_writel(clps_readl(SYSCON1) & ~SYSCON1_LCDEN,
181 SYSCON1);
182 }
183 } else {
184 if (machine_is_edb7211()) {
185 /* Power up the LCD controller. */
186 clps_writel(clps_readl(SYSCON1) | SYSCON1_LCDEN,
187 SYSCON1);
188
189 /* Power up the LCD panel. */
190 clps_writeb(clps_readb(PDDR) | EDB_PD2_LCDEN, PDDR);
191
192 /* Delay for a little while. */
193 udelay(100);
194 166
195 /* Power up the LCD DC-DC converter. */
196 clps_writeb(clps_readb(PDDR) | EDB_PD1_LCD_DC_DC_EN,
197 PDDR);
198
199 /* Turn on the LCD backlight. */
200 clps_writeb(clps_readb(PDDR) | EDB_PD3_LCDBL, PDDR);
201 }
202 }
203 return 0; 167 return 0;
204} 168}
205 169
@@ -214,63 +178,7 @@ static struct fb_ops clps7111fb_ops = {
214 .fb_imageblit = cfb_imageblit, 178 .fb_imageblit = cfb_imageblit,
215}; 179};
216 180
217static int backlight_proc_show(struct seq_file *m, void *v) 181static void __devinit clps711x_guess_lcd_params(struct fb_info *info)
218{
219 if (machine_is_edb7211()) {
220 seq_printf(m, "%d\n",
221 (clps_readb(PDDR) & EDB_PD3_LCDBL) ? 1 : 0);
222 }
223
224 return 0;
225}
226
227static int backlight_proc_open(struct inode *inode, struct file *file)
228{
229 return single_open(file, backlight_proc_show, NULL);
230}
231
232static ssize_t backlight_proc_write(struct file *file, const char *buffer,
233 size_t count, loff_t *pos)
234{
235 unsigned char char_value;
236 int value;
237
238 if (count < 1) {
239 return -EINVAL;
240 }
241
242 if (copy_from_user(&char_value, buffer, 1))
243 return -EFAULT;
244
245 value = char_value - '0';
246
247 if (machine_is_edb7211()) {
248 unsigned char port_d;
249
250 port_d = clps_readb(PDDR);
251
252 if (value) {
253 port_d |= EDB_PD3_LCDBL;
254 } else {
255 port_d &= ~EDB_PD3_LCDBL;
256 }
257
258 clps_writeb(port_d, PDDR);
259 }
260
261 return count;
262}
263
264static const struct file_operations backlight_proc_fops = {
265 .owner = THIS_MODULE,
266 .open = backlight_proc_open,
267 .read = seq_read,
268 .llseek = seq_lseek,
269 .release = single_release,
270 .write = backlight_proc_write,
271};
272
273static void __init clps711x_guess_lcd_params(struct fb_info *info)
274{ 182{
275 unsigned int lcdcon, syscon, size; 183 unsigned int lcdcon, syscon, size;
276 unsigned long phys_base = PAGE_OFFSET; 184 unsigned long phys_base = PAGE_OFFSET;
@@ -358,7 +266,7 @@ static void __init clps711x_guess_lcd_params(struct fb_info *info)
358 info->fix.type = FB_TYPE_PACKED_PIXELS; 266 info->fix.type = FB_TYPE_PACKED_PIXELS;
359} 267}
360 268
361int __init clps711xfb_init(void) 269static int __devinit clps711x_fb_probe(struct platform_device *pdev)
362{ 270{
363 int err = -ENOMEM; 271 int err = -ENOMEM;
364 272
@@ -378,55 +286,29 @@ int __init clps711xfb_init(void)
378 286
379 fb_alloc_cmap(&cfb->cmap, CMAP_MAX_SIZE, 0); 287 fb_alloc_cmap(&cfb->cmap, CMAP_MAX_SIZE, 0);
380 288
381 if (!proc_create("backlight", 0444, NULL, &backlight_proc_fops)) {
382 printk("Couldn't create the /proc entry for the backlight.\n");
383 return -EINVAL;
384 }
385
386 /*
387 * Power up the LCD
388 */
389 if (machine_is_p720t()) {
390 PLD_LCDEN = PLD_LCDEN_EN;
391 PLD_PWR |= (PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
392 }
393
394 if (machine_is_edb7211()) {
395 /* Power up the LCD panel. */
396 clps_writeb(clps_readb(PDDR) | EDB_PD2_LCDEN, PDDR);
397
398 /* Delay for a little while. */
399 udelay(100);
400
401 /* Power up the LCD DC-DC converter. */
402 clps_writeb(clps_readb(PDDR) | EDB_PD1_LCD_DC_DC_EN, PDDR);
403
404 /* Turn on the LCD backlight. */
405 clps_writeb(clps_readb(PDDR) | EDB_PD3_LCDBL, PDDR);
406 }
407
408 err = register_framebuffer(cfb); 289 err = register_framebuffer(cfb);
409 290
410out: return err; 291out: return err;
411} 292}
412 293
413static void __exit clps711xfb_exit(void) 294static int __devexit clps711x_fb_remove(struct platform_device *pdev)
414{ 295{
415 unregister_framebuffer(cfb); 296 unregister_framebuffer(cfb);
416 kfree(cfb); 297 kfree(cfb);
417 298
418 /* 299 return 0;
419 * Power down the LCD
420 */
421 if (machine_is_p720t()) {
422 PLD_LCDEN = 0;
423 PLD_PWR &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
424 }
425} 300}
426 301
427module_init(clps711xfb_init); 302static struct platform_driver clps711x_fb_driver = {
428module_exit(clps711xfb_exit); 303 .driver = {
304 .name = "video-clps711x",
305 .owner = THIS_MODULE,
306 },
307 .probe = clps711x_fb_probe,
308 .remove = __devexit_p(clps711x_fb_remove),
309};
310module_platform_driver(clps711x_fb_driver);
429 311
430MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); 312MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
431MODULE_DESCRIPTION("CLPS711x framebuffer driver"); 313MODULE_DESCRIPTION("CLPS711X framebuffer driver");
432MODULE_LICENSE("GPL"); 314MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 20:29:37 -0500