diff options
author | Kristian Høgsberg <krh@bitplanet.net> | 2009-12-16 15:16:16 -0500 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2009-12-16 16:52:53 -0500 |
commit | cfdf1fa23f4074c9f8766dc67a928bbf680b1ac9 (patch) | |
tree | 447930bfa2f30e0e77e6ec24ed748f927e96f455 /drivers | |
parent | 49ae35f2dd1ff78ee88d5f8a38d0af63c3ad9f71 (diff) |
drm/i915: Implement IS_* macros using static tables
Instead of using the IS_I9XX etc macros that expand to a ton of
comparisons, use new struct intel_device_info to capture the
capabilities of the different chipsets. The drm_i915_private struct
will be initialized to point to the device info that correspond to
the actual device and this way, testing for a specific capability is
just a matter of checking a bit field.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/i915/i915_dma.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 144 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 112 |
3 files changed, 161 insertions, 99 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 701bfeac7f57..549e46c1a979 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c | |||
@@ -1360,7 +1360,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) | |||
1360 | { | 1360 | { |
1361 | struct drm_i915_private *dev_priv = dev->dev_private; | 1361 | struct drm_i915_private *dev_priv = dev->dev_private; |
1362 | resource_size_t base, size; | 1362 | resource_size_t base, size; |
1363 | int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; | 1363 | int ret = 0, mmio_bar; |
1364 | uint32_t agp_size, prealloc_size, prealloc_start; | 1364 | uint32_t agp_size, prealloc_size, prealloc_start; |
1365 | 1365 | ||
1366 | /* i915 has 4 more counters */ | 1366 | /* i915 has 4 more counters */ |
@@ -1376,8 +1376,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) | |||
1376 | 1376 | ||
1377 | dev->dev_private = (void *)dev_priv; | 1377 | dev->dev_private = (void *)dev_priv; |
1378 | dev_priv->dev = dev; | 1378 | dev_priv->dev = dev; |
1379 | dev_priv->info = (struct intel_device_info *) flags; | ||
1379 | 1380 | ||
1380 | /* Add register map (needed for suspend/resume) */ | 1381 | /* Add register map (needed for suspend/resume) */ |
1382 | mmio_bar = IS_I9XX(dev) ? 0 : 1; | ||
1381 | base = drm_get_resource_start(dev, mmio_bar); | 1383 | base = drm_get_resource_start(dev, mmio_bar); |
1382 | size = drm_get_resource_len(dev, mmio_bar); | 1384 | size = drm_get_resource_len(dev, mmio_bar); |
1383 | 1385 | ||
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b6ec949361e2..1b256de24563 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
@@ -47,46 +47,122 @@ module_param_named(powersave, i915_powersave, int, 0400); | |||
47 | 47 | ||
48 | static struct drm_driver driver; | 48 | static struct drm_driver driver; |
49 | 49 | ||
50 | #define INTEL_VGA_DEVICE(id) { \ | 50 | #define INTEL_VGA_DEVICE(id, info) { \ |
51 | .class = PCI_CLASS_DISPLAY_VGA << 8, \ | 51 | .class = PCI_CLASS_DISPLAY_VGA << 8, \ |
52 | .class_mask = 0xffff00, \ | 52 | .class_mask = 0xffff00, \ |
53 | .vendor = 0x8086, \ | 53 | .vendor = 0x8086, \ |
54 | .device = id, \ | 54 | .device = id, \ |
55 | .subvendor = PCI_ANY_ID, \ | 55 | .subvendor = PCI_ANY_ID, \ |
56 | .subdevice = PCI_ANY_ID, \ | 56 | .subdevice = PCI_ANY_ID, \ |
57 | .driver_data = 0 } | 57 | .driver_data = (unsigned long) info } |
58 | 58 | ||
59 | static struct pci_device_id pciidlist[] = { | 59 | const static struct intel_device_info intel_i830_info = { |
60 | INTEL_VGA_DEVICE(0x3577), | 60 | .is_i8xx = 1, .is_mobile = 1, |
61 | INTEL_VGA_DEVICE(0x2562), | 61 | }; |
62 | INTEL_VGA_DEVICE(0x3582), | 62 | |
63 | INTEL_VGA_DEVICE(0x2572), | 63 | const static struct intel_device_info intel_845g_info = { |
64 | INTEL_VGA_DEVICE(0x2582), | 64 | .is_i8xx = 1, |
65 | INTEL_VGA_DEVICE(0x258a), | 65 | }; |
66 | INTEL_VGA_DEVICE(0x2592), | 66 | |
67 | INTEL_VGA_DEVICE(0x2772), | 67 | const static struct intel_device_info intel_i85x_info = { |
68 | INTEL_VGA_DEVICE(0x27a2), | 68 | .is_i8xx = 1, .is_mobile = 1, |
69 | INTEL_VGA_DEVICE(0x27ae), | 69 | }; |
70 | INTEL_VGA_DEVICE(0x2972), | 70 | |
71 | INTEL_VGA_DEVICE(0x2982), | 71 | const static struct intel_device_info intel_i865g_info = { |
72 | INTEL_VGA_DEVICE(0x2992), | 72 | .is_i8xx = 1, |
73 | INTEL_VGA_DEVICE(0x29a2), | 73 | }; |
74 | INTEL_VGA_DEVICE(0x29b2), | 74 | |
75 | INTEL_VGA_DEVICE(0x29c2), | 75 | const static struct intel_device_info intel_i915g_info = { |
76 | INTEL_VGA_DEVICE(0x29d2), | 76 | .is_i915g = 1, .is_i9xx = 1, |
77 | INTEL_VGA_DEVICE(0x2a02), | 77 | }; |
78 | INTEL_VGA_DEVICE(0x2a12), | 78 | const static struct intel_device_info intel_i915gm_info = { |
79 | INTEL_VGA_DEVICE(0x2a42), | 79 | .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1, |
80 | INTEL_VGA_DEVICE(0x2e02), | 80 | }; |
81 | INTEL_VGA_DEVICE(0x2e12), | 81 | const static struct intel_device_info intel_i945g_info = { |
82 | INTEL_VGA_DEVICE(0x2e22), | 82 | .is_i9xx = 1, .has_hotplug = 1, |
83 | INTEL_VGA_DEVICE(0x2e32), | 83 | }; |
84 | INTEL_VGA_DEVICE(0x2e42), | 84 | const static struct intel_device_info intel_i945gm_info = { |
85 | INTEL_VGA_DEVICE(0xa001), | 85 | .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1, |
86 | INTEL_VGA_DEVICE(0xa011), | 86 | .has_hotplug = 1, |
87 | INTEL_VGA_DEVICE(0x35e8), | 87 | }; |
88 | INTEL_VGA_DEVICE(0x0042), | 88 | |
89 | INTEL_VGA_DEVICE(0x0046), | 89 | const static struct intel_device_info intel_i965g_info = { |
90 | .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1, | ||
91 | }; | ||
92 | |||
93 | const static struct intel_device_info intel_i965gm_info = { | ||
94 | .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1, | ||
95 | .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, | ||
96 | .has_hotplug = 1, | ||
97 | }; | ||
98 | |||
99 | const static struct intel_device_info intel_g33_info = { | ||
100 | .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1, | ||
101 | .has_hotplug = 1, | ||
102 | }; | ||
103 | |||
104 | const static struct intel_device_info intel_g45_info = { | ||
105 | .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1, | ||
106 | .has_pipe_cxsr = 1, | ||
107 | .has_hotplug = 1, | ||
108 | }; | ||
109 | |||
110 | const static struct intel_device_info intel_gm45_info = { | ||
111 | .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1, | ||
112 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, | ||
113 | .has_pipe_cxsr = 1, | ||
114 | .has_hotplug = 1, | ||
115 | }; | ||
116 | |||
117 | const static struct intel_device_info intel_pineview_info = { | ||
118 | .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1, | ||
119 | .has_pipe_cxsr = 1, | ||
120 | .has_hotplug = 1, | ||
121 | }; | ||
122 | |||
123 | const static struct intel_device_info intel_ironlake_d_info = { | ||
124 | .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1, | ||
125 | .has_pipe_cxsr = 1, | ||
126 | .has_hotplug = 1, | ||
127 | }; | ||
128 | |||
129 | const static struct intel_device_info intel_ironlake_m_info = { | ||
130 | .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1, | ||
131 | .need_gfx_hws = 1, .has_rc6 = 1, | ||
132 | .has_hotplug = 1, | ||
133 | }; | ||
134 | |||
135 | const static struct pci_device_id pciidlist[] = { | ||
136 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), | ||
137 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), | ||
138 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), | ||
139 | INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info), | ||
140 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), | ||
141 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), | ||
142 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), | ||
143 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), | ||
144 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), | ||
145 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), | ||
146 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), | ||
147 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), | ||
148 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), | ||
149 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), | ||
150 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), | ||
151 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), | ||
152 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), | ||
153 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), | ||
154 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), | ||
155 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), | ||
156 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), | ||
157 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), | ||
158 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), | ||
159 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), | ||
160 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), | ||
161 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), | ||
162 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), | ||
163 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | ||
164 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | ||
165 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | ||
90 | {0, 0, 0} | 166 | {0, 0, 0} |
91 | }; | 167 | }; |
92 | 168 | ||
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 25c1047f6ecd..0d24e034dc23 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -172,9 +172,30 @@ struct drm_i915_display_funcs { | |||
172 | 172 | ||
173 | struct intel_overlay; | 173 | struct intel_overlay; |
174 | 174 | ||
175 | struct intel_device_info { | ||
176 | u8 is_mobile : 1; | ||
177 | u8 is_i8xx : 1; | ||
178 | u8 is_i915g : 1; | ||
179 | u8 is_i9xx : 1; | ||
180 | u8 is_i945gm : 1; | ||
181 | u8 is_i965g : 1; | ||
182 | u8 is_i965gm : 1; | ||
183 | u8 is_g33 : 1; | ||
184 | u8 need_gfx_hws : 1; | ||
185 | u8 is_g4x : 1; | ||
186 | u8 is_pineview : 1; | ||
187 | u8 is_ironlake : 1; | ||
188 | u8 has_fbc : 1; | ||
189 | u8 has_rc6 : 1; | ||
190 | u8 has_pipe_cxsr : 1; | ||
191 | u8 has_hotplug : 1; | ||
192 | }; | ||
193 | |||
175 | typedef struct drm_i915_private { | 194 | typedef struct drm_i915_private { |
176 | struct drm_device *dev; | 195 | struct drm_device *dev; |
177 | 196 | ||
197 | const struct intel_device_info *info; | ||
198 | |||
178 | int has_gem; | 199 | int has_gem; |
179 | 200 | ||
180 | void __iomem *regs; | 201 | void __iomem *regs; |
@@ -983,67 +1004,33 @@ extern void g4x_disable_fbc(struct drm_device *dev); | |||
983 | extern int i915_wrap_ring(struct drm_device * dev); | 1004 | extern int i915_wrap_ring(struct drm_device * dev); |
984 | extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); | 1005 | extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); |
985 | 1006 | ||
986 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | 1007 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
987 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | 1008 | |
988 | #define IS_I85X(dev) ((dev)->pci_device == 0x3582) | 1009 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) |
989 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | 1010 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) |
990 | #define IS_I8XX(dev) (IS_I830(dev) || IS_845G(dev) || IS_I85X(dev) || IS_I865G(dev)) | 1011 | #define IS_I85X(dev) ((dev)->pci_device == 0x3582) |
991 | 1012 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
992 | #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) | 1013 | #define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx) |
993 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | 1014 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
994 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | 1015 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
995 | #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ | 1016 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) |
996 | (dev)->pci_device == 0x27AE) | 1017 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
997 | #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ | 1018 | #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g) |
998 | (dev)->pci_device == 0x2982 || \ | 1019 | #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm) |
999 | (dev)->pci_device == 0x2992 || \ | 1020 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
1000 | (dev)->pci_device == 0x29A2 || \ | 1021 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
1001 | (dev)->pci_device == 0x2A02 || \ | 1022 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) |
1002 | (dev)->pci_device == 0x2A12 || \ | 1023 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) |
1003 | (dev)->pci_device == 0x2A42 || \ | 1024 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
1004 | (dev)->pci_device == 0x2E02 || \ | 1025 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
1005 | (dev)->pci_device == 0x2E12 || \ | ||
1006 | (dev)->pci_device == 0x2E22 || \ | ||
1007 | (dev)->pci_device == 0x2E32 || \ | ||
1008 | (dev)->pci_device == 0x2E42 || \ | ||
1009 | (dev)->pci_device == 0x0042 || \ | ||
1010 | (dev)->pci_device == 0x0046) | ||
1011 | |||
1012 | #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \ | ||
1013 | (dev)->pci_device == 0x2A12) | ||
1014 | |||
1015 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | ||
1016 | |||
1017 | #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ | ||
1018 | (dev)->pci_device == 0x2E12 || \ | ||
1019 | (dev)->pci_device == 0x2E22 || \ | ||
1020 | (dev)->pci_device == 0x2E32 || \ | ||
1021 | (dev)->pci_device == 0x2E42 || \ | ||
1022 | IS_GM45(dev)) | ||
1023 | |||
1024 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | ||
1025 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | ||
1026 | #define IS_PINEVIEW(dev) (IS_PINEVIEW_G(dev) || IS_PINEVIEW_M(dev)) | ||
1027 | |||
1028 | #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ | ||
1029 | (dev)->pci_device == 0x29B2 || \ | ||
1030 | (dev)->pci_device == 0x29D2 || \ | ||
1031 | (IS_PINEVIEW(dev))) | ||
1032 | |||
1033 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | 1026 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
1034 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | 1027 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) |
1035 | #define IS_IRONLAKE(dev) (IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev)) | 1028 | #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake) |
1036 | 1029 | #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) | |
1037 | #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ | 1030 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
1038 | IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \ | ||
1039 | IS_IRONLAKE(dev)) | ||
1040 | 1031 | ||
1041 | #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ | 1032 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1042 | IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \ | ||
1043 | IS_PINEVIEW(dev) || IS_IRONLAKE_M(dev)) | ||
1044 | 1033 | ||
1045 | #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \ | ||
1046 | IS_IRONLAKE(dev)) | ||
1047 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | 1034 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1048 | * rows, which changed the alignment requirements and fence programming. | 1035 | * rows, which changed the alignment requirements and fence programming. |
1049 | */ | 1036 | */ |
@@ -1055,17 +1042,14 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); | |||
1055 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | 1042 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) |
1056 | #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ | 1043 | #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ |
1057 | !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev)) | 1044 | !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev)) |
1058 | #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev)) | 1045 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
1059 | /* dsparb controlled by hw only */ | 1046 | /* dsparb controlled by hw only */ |
1060 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | 1047 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
1061 | 1048 | ||
1062 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) | 1049 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) |
1063 | #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | 1050 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
1064 | #define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \ | 1051 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
1065 | (IS_I9XX(dev) || IS_GM45(dev)) && \ | 1052 | #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) |
1066 | !IS_PINEVIEW(dev) && \ | ||
1067 | !IS_IRONLAKE(dev)) | ||
1068 | #define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IRONLAKE_M(dev)) | ||
1069 | 1053 | ||
1070 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) | 1054 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
1071 | 1055 | ||