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authorMaarten Maathuis <madman2003@gmail.com>2009-12-25 12:51:17 -0500
committerDave Airlie <airlied@redhat.com>2010-01-10 23:41:10 -0500
commitc2b82924bda0c3de2b49bd3a4d8b6725721820bc (patch)
tree52953304977301464772d800468e5998aafc6061 /drivers
parent8f71c29e442e013212a98e2b37eb1074c4d1134f (diff)
drm/nouveau: better alignment of bo sizes and use roundup instead of ALIGN
- Aligning to block size should ensure that the extra size is enough. - Using roundup, because not all sizes are powers of two. Signed-off-by: Maarten Maathuis <madman2003@gmail.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.c4
2 files changed, 8 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 5fd462f49407..a0c9e00e7062 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -73,6 +73,7 @@ nouveau_bo_fixup_align(struct drm_device *dev,
73 case 0x4800: 73 case 0x4800:
74 case 0x7a00: 74 case 0x7a00:
75 if (dev_priv->chipset >= 0xA0) { 75 if (dev_priv->chipset >= 0xA0) {
76 *size = roundup(*size, 28672);
76 /* This is based on high end cards with 448 bits 77 /* This is based on high end cards with 448 bits
77 * memory bus, could be different elsewhere.*/ 78 * memory bus, could be different elsewhere.*/
78 *size += 6 * 28672; 79 *size += 6 * 28672;
@@ -80,9 +81,11 @@ nouveau_bo_fixup_align(struct drm_device *dev,
80 * but we must also align to page size. */ 81 * but we must also align to page size. */
81 *align = 2 * 8 * 28672; 82 *align = 2 * 8 * 28672;
82 } else if (dev_priv->chipset >= 0x90) { 83 } else if (dev_priv->chipset >= 0x90) {
84 *size = roundup(*size, 16384);
83 *size += 3 * 16384; 85 *size += 3 * 16384;
84 *align = 12 * 16384; 86 *align = 12 * 16384;
85 } else { 87 } else {
88 *size = roundup(*size, 8192);
86 *size += 3 * 8192; 89 *size += 3 * 8192;
87 /* 12 * 8192 is the actual alignment requirement 90 /* 12 * 8192 is the actual alignment requirement
88 * but we must also align to page size. */ 91 * but we must also align to page size. */
@@ -114,10 +117,11 @@ nouveau_bo_fixup_align(struct drm_device *dev,
114 } 117 }
115 } 118 }
116 119
117 *size = ALIGN(*size, PAGE_SIZE); 120 /* ALIGN works only on powers of two. */
121 *size = roundup(*size, PAGE_SIZE);
118 122
119 if (dev_priv->card_type == NV_50) { 123 if (dev_priv->card_type == NV_50) {
120 *size = ALIGN(*size, 65536); 124 *size = roundup(*size, 65536);
121 *align = max(65536, *align); 125 *align = max(65536, *align);
122 } 126 }
123} 127}
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 84af25c238b6..44cbbeeb7745 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -212,11 +212,11 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width,
212 212
213 mode_cmd.bpp = surface_bpp; 213 mode_cmd.bpp = surface_bpp;
214 mode_cmd.pitch = mode_cmd.width * (mode_cmd.bpp >> 3); 214 mode_cmd.pitch = mode_cmd.width * (mode_cmd.bpp >> 3);
215 mode_cmd.pitch = ALIGN(mode_cmd.pitch, 256); 215 mode_cmd.pitch = roundup(mode_cmd.pitch, 256);
216 mode_cmd.depth = surface_depth; 216 mode_cmd.depth = surface_depth;
217 217
218 size = mode_cmd.pitch * mode_cmd.height; 218 size = mode_cmd.pitch * mode_cmd.height;
219 size = ALIGN(size, PAGE_SIZE); 219 size = roundup(size, PAGE_SIZE);
220 220
221 ret = nouveau_gem_new(dev, dev_priv->channel, size, 0, TTM_PL_FLAG_VRAM, 221 ret = nouveau_gem_new(dev, dev_priv->channel, size, 0, TTM_PL_FLAG_VRAM,
222 0, 0x0000, false, true, &nvbo); 222 0, 0x0000, false, true, &nvbo);