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authorTomas Winkler <tomas.winkler@intel.com>2008-12-18 21:37:01 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-01-29 15:58:50 -0500
commitbddadf86fb284f237d6e2d3496772c8f5c68370e (patch)
treef605f0b6c8fd77c73feefe645f31e3f78bd91650 /drivers
parent7cbf0ba5193d1f3bb3caaa06668e22bc86776e41 (diff)
iwlwifi: 3945 extract flow handler definitions into iwl-3945-fh.h
This patch moves 3945 definitions into iwl-3945-fh.h It renames FH_ to FH39 to help inclusion of 3945 into iwlcore framework Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Acked-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-fh.h178
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-hw.h101
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.c83
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.h3
-rw-r--r--drivers/net/wireless/iwlwifi/iwl3945-base.c10
5 files changed, 226 insertions, 149 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-fh.h b/drivers/net/wireless/iwlwifi/iwl-3945-fh.h
new file mode 100644
index 000000000000..bbcd0cefc724
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-fh.h
@@ -0,0 +1,178 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63#ifndef __iwl_3945_fh_h__
64#define __iwl_3945_fh_h__
65
66/************************************/
67/* iwl3945 Flow Handler Definitions */
68/************************************/
69
70/**
71 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
72 * Addresses are offsets from device's PCI hardware base address.
73 */
74#define FH39_MEM_LOWER_BOUND (0x0800)
75#define FH39_MEM_UPPER_BOUND (0x1000)
76
77#define FH39_CBCC_TABLE (FH39_MEM_LOWER_BOUND + 0x140)
78#define FH39_TFDB_TABLE (FH39_MEM_LOWER_BOUND + 0x180)
79#define FH39_RCSR_TABLE (FH39_MEM_LOWER_BOUND + 0x400)
80#define FH39_RSSR_TABLE (FH39_MEM_LOWER_BOUND + 0x4c0)
81#define FH39_TCSR_TABLE (FH39_MEM_LOWER_BOUND + 0x500)
82#define FH39_TSSR_TABLE (FH39_MEM_LOWER_BOUND + 0x680)
83
84/* TFDB (Transmit Frame Buffer Descriptor) */
85#define FH39_TFDB(_ch, buf) (FH39_TFDB_TABLE + \
86 ((_ch) * 2 + (buf)) * 0x28)
87#define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch) (FH39_TFDB_TABLE + 0x50 * (_ch))
88
89/* CBCC channel is [0,2] */
90#define FH39_CBCC(_ch) (FH39_CBCC_TABLE + (_ch) * 0x8)
91#define FH39_CBCC_CTRL(_ch) (FH39_CBCC(_ch) + 0x00)
92#define FH39_CBCC_BASE(_ch) (FH39_CBCC(_ch) + 0x04)
93
94/* RCSR channel is [0,2] */
95#define FH39_RCSR(_ch) (FH39_RCSR_TABLE + (_ch) * 0x40)
96#define FH39_RCSR_CONFIG(_ch) (FH39_RCSR(_ch) + 0x00)
97#define FH39_RCSR_RBD_BASE(_ch) (FH39_RCSR(_ch) + 0x04)
98#define FH39_RCSR_WPTR(_ch) (FH39_RCSR(_ch) + 0x20)
99#define FH39_RCSR_RPTR_ADDR(_ch) (FH39_RCSR(_ch) + 0x24)
100
101#define FH39_RSCSR_CHNL0_WPTR (FH39_RCSR_WPTR(0))
102
103/* RSSR */
104#define FH39_RSSR_CTRL (FH39_RSSR_TABLE + 0x000)
105#define FH39_RSSR_STATUS (FH39_RSSR_TABLE + 0x004)
106
107/* TCSR */
108#define FH39_TCSR(_ch) (FH39_TCSR_TABLE + (_ch) * 0x20)
109#define FH39_TCSR_CONFIG(_ch) (FH39_TCSR(_ch) + 0x00)
110#define FH39_TCSR_CREDIT(_ch) (FH39_TCSR(_ch) + 0x04)
111#define FH39_TCSR_BUFF_STTS(_ch) (FH39_TCSR(_ch) + 0x08)
112
113/* TSSR */
114#define FH39_TSSR_CBB_BASE (FH39_TSSR_TABLE + 0x000)
115#define FH39_TSSR_MSG_CONFIG (FH39_TSSR_TABLE + 0x008)
116#define FH39_TSSR_TX_STATUS (FH39_TSSR_TABLE + 0x010)
117
118
119/* DBM */
120
121#define FH39_SRVC_CHNL (6)
122
123#define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
124#define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
125
126#define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
127
128#define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
129
130#define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
131
132#define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
133
134#define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
135
136#define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
137
138#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
139#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
140
141#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
142#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
143
144#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
145
146#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
147
148#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
149#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
150
151#define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
152
153#define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
154
155#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
156#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
157
158#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
159
160#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
161#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
162
163#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
164#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
165
166#define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) (BIT(_ch) << 24)
167#define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch) (BIT(_ch) << 16)
168
169#define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) \
170 (FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) | \
171 FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch))
172
173#define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
174
175#define TFD_QUEUE_SIZE_MAX (256)
176
177#endif /* __iwl_3945_fh_h__ */
178
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-hw.h b/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
index 94ea0e60c410..1df385b7c39e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
@@ -288,107 +288,6 @@ struct iwl3945_eeprom {
288#define PCI_REG_WUM8 0x0E8 288#define PCI_REG_WUM8 0x0E8
289#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) 289#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
290 290
291/*=== FH (data Flow Handler) ===*/
292#define FH_BASE (0x800)
293
294#define FH_CBCC_TABLE (FH_BASE+0x140)
295#define FH_TFDB_TABLE (FH_BASE+0x180)
296#define FH_RCSR_TABLE (FH_BASE+0x400)
297#define FH_RSSR_TABLE (FH_BASE+0x4c0)
298#define FH_TCSR_TABLE (FH_BASE+0x500)
299#define FH_TSSR_TABLE (FH_BASE+0x680)
300
301/* TFDB (Transmit Frame Buffer Descriptor) */
302#define FH_TFDB(_channel, buf) \
303 (FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
304#define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
305 (FH_TFDB_TABLE + 0x50 * _channel)
306/* CBCC _channel is [0,2] */
307#define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8)
308#define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00)
309#define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04)
310
311/* RCSR _channel is [0,2] */
312#define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40)
313#define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00)
314#define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04)
315#define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20)
316#define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
317
318#define FH_RSCSR_CHNL0_WPTR (FH_RCSR_WPTR(0))
319
320/* RSSR */
321#define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000)
322#define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004)
323#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
324/* TCSR */
325#define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20)
326#define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00)
327#define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04)
328#define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
329/* TSSR */
330#define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000)
331#define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008)
332#define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010)
333
334
335/* DBM */
336
337#define ALM_FH_SRVC_CHNL (6)
338
339#define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
340#define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
341
342#define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
343
344#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
345
346#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
347
348#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
349
350#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
351
352#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
353
354#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
355#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
356
357#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
358#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
359
360#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
361
362#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
363
364#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
365#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
366
367#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
368
369#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
370
371#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
372#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
373
374#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
375
376#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
377#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
378
379#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
380#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
381
382#define ALM_TB_MAX_BYTES_COUNT (0xFFF0)
383
384#define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
385 ((1LU << _channel) << 24)
386#define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
387 ((1LU << _channel) << 16)
388
389#define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
390 (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
391 ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
392#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */ 291#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
393#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */ 292#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
394 293
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index 45cfa1cf194a..f4fee0a91b66 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -39,6 +39,7 @@
39#include <net/mac80211.h> 39#include <net/mac80211.h>
40 40
41#include "iwl-3945-core.h" 41#include "iwl-3945-core.h"
42#include "iwl-3945-fh.h"
42#include "iwl-3945.h" 43#include "iwl-3945.h"
43#include "iwl-helpers.h" 44#include "iwl-helpers.h"
44#include "iwl-3945-rs.h" 45#include "iwl-3945-rs.h"
@@ -984,23 +985,23 @@ static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *r
984 return rc; 985 return rc;
985 } 986 }
986 987
987 iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr); 988 iwl3945_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
988 iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0), 989 iwl3945_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0),
989 priv->hw_setting.shared_phys + 990 priv->hw_setting.shared_phys +
990 offsetof(struct iwl3945_shared, rx_read_ptr[0])); 991 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
991 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0); 992 iwl3945_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
992 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 993 iwl3945_write_direct32(priv, FH39_RCSR_CONFIG(0),
993 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | 994 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
994 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | 995 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
995 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | 996 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
996 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 | 997 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
997 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) | 998 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
998 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST | 999 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
999 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) | 1000 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
1000 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH); 1001 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
1001 1002
1002 /* fake read to flush all prev I/O */ 1003 /* fake read to flush all prev I/O */
1003 iwl3945_read_direct32(priv, FH_RSSR_CTRL); 1004 iwl3945_read_direct32(priv, FH39_RSSR_CTRL);
1004 1005
1005 iwl3945_release_nic_access(priv); 1006 iwl3945_release_nic_access(priv);
1006 spin_unlock_irqrestore(&priv->lock, flags); 1007 spin_unlock_irqrestore(&priv->lock, flags);
@@ -1034,17 +1035,17 @@ static int iwl3945_tx_reset(struct iwl3945_priv *priv)
1034 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004); 1035 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1035 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005); 1036 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1036 1037
1037 iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE, 1038 iwl3945_write_direct32(priv, FH39_TSSR_CBB_BASE,
1038 priv->hw_setting.shared_phys); 1039 priv->hw_setting.shared_phys);
1039 1040
1040 iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG, 1041 iwl3945_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
1041 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | 1042 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1042 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | 1043 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1043 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | 1044 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1044 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON | 1045 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1045 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON | 1046 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1046 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH | 1047 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1047 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH); 1048 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1048 1049
1049 iwl3945_release_nic_access(priv); 1050 iwl3945_release_nic_access(priv);
1050 spin_unlock_irqrestore(&priv->lock, flags); 1051 spin_unlock_irqrestore(&priv->lock, flags);
@@ -1210,7 +1211,7 @@ int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
1210 spin_unlock_irqrestore(&priv->lock, flags); 1211 spin_unlock_irqrestore(&priv->lock, flags);
1211 return rc; 1212 return rc;
1212 } 1213 }
1213 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7); 1214 iwl3945_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1214 iwl3945_release_nic_access(priv); 1215 iwl3945_release_nic_access(priv);
1215 1216
1216 spin_unlock_irqrestore(&priv->lock, flags); 1217 spin_unlock_irqrestore(&priv->lock, flags);
@@ -1240,7 +1241,7 @@ void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
1240 1241
1241void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv) 1242void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
1242{ 1243{
1243 int queue; 1244 int txq_id;
1244 unsigned long flags; 1245 unsigned long flags;
1245 1246
1246 spin_lock_irqsave(&priv->lock, flags); 1247 spin_lock_irqsave(&priv->lock, flags);
@@ -1254,10 +1255,10 @@ void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
1254 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0); 1255 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
1255 1256
1256 /* reset TFD queues */ 1257 /* reset TFD queues */
1257 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) { 1258 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1258 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0); 1259 iwl3945_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1259 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS, 1260 iwl3945_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1260 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue), 1261 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1261 1000); 1262 1000);
1262 } 1263 }
1263 1264
@@ -2307,9 +2308,9 @@ int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
2307 return rc; 2308 return rc;
2308 } 2309 }
2309 2310
2310 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0); 2311 iwl3945_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2311 rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, 2312 rc = iwl3945_poll_direct_bit(priv, FH39_RSSR_STATUS,
2312 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); 2313 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2313 if (rc < 0) 2314 if (rc < 0)
2314 IWL_ERROR("Can't stop Rx DMA.\n"); 2315 IWL_ERROR("Can't stop Rx DMA.\n");
2315 2316
@@ -2335,19 +2336,19 @@ int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue
2335 spin_unlock_irqrestore(&priv->lock, flags); 2336 spin_unlock_irqrestore(&priv->lock, flags);
2336 return rc; 2337 return rc;
2337 } 2338 }
2338 iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0); 2339 iwl3945_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2339 iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0); 2340 iwl3945_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2340 2341
2341 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id), 2342 iwl3945_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2342 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | 2343 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2343 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | 2344 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2344 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | 2345 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2345 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | 2346 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2346 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); 2347 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2347 iwl3945_release_nic_access(priv); 2348 iwl3945_release_nic_access(priv);
2348 2349
2349 /* fake read to flush all prev. writes */ 2350 /* fake read to flush all prev. writes */
2350 iwl3945_read32(priv, FH_TSSR_CBB_BASE); 2351 iwl3945_read32(priv, FH39_TSSR_CBB_BASE);
2351 spin_unlock_irqrestore(&priv->lock, flags); 2352 spin_unlock_irqrestore(&priv->lock, flags);
2352 2353
2353 return 0; 2354 return 0;
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.h b/drivers/net/wireless/iwlwifi/iwl-3945.h
index 2c0ddc5110c6..d8f40bdb3167 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.h
@@ -691,7 +691,6 @@ static inline void iwl3945_rfkill_unregister(struct iwl3945_priv *priv) {}
691static inline int iwl3945_rfkill_init(struct iwl3945_priv *priv) { return 0; } 691static inline int iwl3945_rfkill_init(struct iwl3945_priv *priv) { return 0; }
692#endif 692#endif
693 693
694#define IWL_MAX_NUM_QUEUES IWL39_MAX_NUM_QUEUES
695 694
696struct iwl3945_priv { 695struct iwl3945_priv {
697 696
@@ -815,7 +814,7 @@ struct iwl3945_priv {
815 814
816 /* Rx and Tx DMA processing queues */ 815 /* Rx and Tx DMA processing queues */
817 struct iwl3945_rx_queue rxq; 816 struct iwl3945_rx_queue rxq;
818 struct iwl3945_tx_queue txq[IWL_MAX_NUM_QUEUES]; 817 struct iwl3945_tx_queue txq[IWL39_MAX_NUM_QUEUES];
819 818
820 unsigned long status; 819 unsigned long status;
821 820
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index 95d01984c80e..fee3e93ca564 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -48,6 +48,7 @@
48 48
49#include "iwl-3945-core.h" 49#include "iwl-3945-core.h"
50#include "iwl-3945.h" 50#include "iwl-3945.h"
51#include "iwl-3945-fh.h"
51#include "iwl-helpers.h" 52#include "iwl-helpers.h"
52 53
53#ifdef CONFIG_IWL3945_DEBUG 54#ifdef CONFIG_IWL3945_DEBUG
@@ -3479,14 +3480,14 @@ int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_
3479 goto exit_unlock; 3480 goto exit_unlock;
3480 3481
3481 /* Device expects a multiple of 8 */ 3482 /* Device expects a multiple of 8 */
3482 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, 3483 iwl3945_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
3483 q->write & ~0x7); 3484 q->write & ~0x7);
3484 iwl3945_release_nic_access(priv); 3485 iwl3945_release_nic_access(priv);
3485 3486
3486 /* Else device is assumed to be awake */ 3487 /* Else device is assumed to be awake */
3487 } else 3488 } else
3488 /* Device expects a multiple of 8 */ 3489 /* Device expects a multiple of 8 */
3489 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7); 3490 iwl3945_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
3490 3491
3491 3492
3492 q->need_update = 0; 3493 q->need_update = 0;
@@ -4339,9 +4340,8 @@ static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
4339 4340
4340 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); 4341 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4341 if (!iwl3945_grab_nic_access(priv)) { 4342 if (!iwl3945_grab_nic_access(priv)) {
4342 iwl3945_write_direct32(priv, 4343 iwl3945_write_direct32(priv, FH39_TCSR_CREDIT
4343 FH_TCSR_CREDIT 4344 (FH39_SRVC_CHNL), 0x0);
4344 (ALM_FH_SRVC_CHNL), 0x0);
4345 iwl3945_release_nic_access(priv); 4345 iwl3945_release_nic_access(priv);
4346 } 4346 }
4347 handled |= CSR_INT_BIT_FH_TX; 4347 handled |= CSR_INT_BIT_FH_TX;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:33:39 -0500