diff options
| author | Lennert Buytenhek <buytenh@wantstofly.org> | 2007-10-18 22:11:38 -0400 |
|---|---|---|
| committer | Dale Farnsworth <dale@farnsworth.org> | 2007-10-23 11:23:11 -0400 |
| commit | 5688fe87a458a73d5066eee3d5c9891459ba70bf (patch) | |
| tree | 20841cd7060c89467ba4b6c3238968f71547559c /drivers | |
| parent | e4d00fa9bfed733051652a32686b9911e8549ac8 (diff) | |
mv643xx_eth: Clean up mv643xx_eth.h
Apply the following cleanups to drivers/net/mv643xx_eth.h:
* Change "#define<tab>" to "#define<space>".
* Fix comment block style.
* Wrap lines to fit in 80 columns.
* Change "foo<<1" to "foo << 1".
* Align addresses in the same column.
* Parenthesize macro arguments.
* Replace "(1<<24) | (1<<23) | (1<<22)" type constructs with "(7 << 22)".
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Tzachi Perelstein <tzachi@marvell.com>
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/mv643xx_eth.h | 533 |
1 files changed, 250 insertions, 283 deletions
diff --git a/drivers/net/mv643xx_eth.h b/drivers/net/mv643xx_eth.h index 90362714be39..ed8539762a64 100644 --- a/drivers/net/mv643xx_eth.h +++ b/drivers/net/mv643xx_eth.h | |||
| @@ -14,9 +14,9 @@ | |||
| 14 | /* Checksum offload for Tx works for most packets, but | 14 | /* Checksum offload for Tx works for most packets, but |
| 15 | * fails if previous packet sent did not use hw csum | 15 | * fails if previous packet sent did not use hw csum |
| 16 | */ | 16 | */ |
| 17 | #define MV643XX_CHECKSUM_OFFLOAD_TX | 17 | #define MV643XX_CHECKSUM_OFFLOAD_TX |
| 18 | #define MV643XX_NAPI | 18 | #define MV643XX_NAPI |
| 19 | #define MV643XX_TX_FAST_REFILL | 19 | #define MV643XX_TX_FAST_REFILL |
| 20 | #undef MV643XX_COAL | 20 | #undef MV643XX_COAL |
| 21 | 21 | ||
| 22 | /* | 22 | /* |
| @@ -49,230 +49,199 @@ | |||
| 49 | #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ | 49 | #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ |
| 50 | #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \ | 50 | #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \ |
| 51 | ETH_VLAN_HLEN + ETH_FCS_LEN) | 51 | ETH_VLAN_HLEN + ETH_FCS_LEN) |
| 52 | #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + dma_get_cache_alignment()) | 52 | #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \ |
| 53 | 53 | dma_get_cache_alignment()) | |
| 54 | /****************************************/ | 54 | |
| 55 | /* Ethernet Unit Registers */ | 55 | /* |
| 56 | /****************************************/ | 56 | * Registers shared between all ports. |
| 57 | 57 | */ | |
| 58 | #define PHY_ADDR_REG 0x0000 | 58 | #define PHY_ADDR_REG 0x0000 |
| 59 | #define SMI_REG 0x0004 | 59 | #define SMI_REG 0x0004 |
| 60 | #define UNIT_DEFAULT_ADDR_REG 0x0008 | 60 | #define UNIT_DEFAULT_ADDR_REG 0x0008 |
| 61 | #define UNIT_DEFAULTID_REG 0x000c | 61 | #define UNIT_DEFAULTID_REG 0x000c |
| 62 | #define UNIT_INTERRUPT_CAUSE_REG 0x0080 | 62 | #define UNIT_INTERRUPT_CAUSE_REG 0x0080 |
| 63 | #define UNIT_INTERRUPT_MASK_REG 0x0084 | 63 | #define UNIT_INTERRUPT_MASK_REG 0x0084 |
| 64 | #define UNIT_INTERNAL_USE_REG 0x04fc | 64 | #define UNIT_INTERNAL_USE_REG 0x04fc |
| 65 | #define UNIT_ERROR_ADDR_REG 0x0094 | 65 | #define UNIT_ERROR_ADDR_REG 0x0094 |
| 66 | #define BAR_0 0x0200 | 66 | #define BAR_0 0x0200 |
| 67 | #define BAR_1 0x0208 | 67 | #define BAR_1 0x0208 |
| 68 | #define BAR_2 0x0210 | 68 | #define BAR_2 0x0210 |
| 69 | #define BAR_3 0x0218 | 69 | #define BAR_3 0x0218 |
| 70 | #define BAR_4 0x0220 | 70 | #define BAR_4 0x0220 |
| 71 | #define BAR_5 0x0228 | 71 | #define BAR_5 0x0228 |
| 72 | #define SIZE_REG_0 0x0204 | 72 | #define SIZE_REG_0 0x0204 |
| 73 | #define SIZE_REG_1 0x020c | 73 | #define SIZE_REG_1 0x020c |
| 74 | #define SIZE_REG_2 0x0214 | 74 | #define SIZE_REG_2 0x0214 |
| 75 | #define SIZE_REG_3 0x021c | 75 | #define SIZE_REG_3 0x021c |
| 76 | #define SIZE_REG_4 0x0224 | 76 | #define SIZE_REG_4 0x0224 |
| 77 | #define SIZE_REG_5 0x022c | 77 | #define SIZE_REG_5 0x022c |
| 78 | #define HEADERS_RETARGET_BASE_REG 0x0230 | 78 | #define HEADERS_RETARGET_BASE_REG 0x0230 |
| 79 | #define HEADERS_RETARGET_CONTROL_REG 0x0234 | 79 | #define HEADERS_RETARGET_CONTROL_REG 0x0234 |
| 80 | #define HIGH_ADDR_REMAP_REG_0 0x0280 | 80 | #define HIGH_ADDR_REMAP_REG_0 0x0280 |
| 81 | #define HIGH_ADDR_REMAP_REG_1 0x0284 | 81 | #define HIGH_ADDR_REMAP_REG_1 0x0284 |
| 82 | #define HIGH_ADDR_REMAP_REG_2 0x0288 | 82 | #define HIGH_ADDR_REMAP_REG_2 0x0288 |
| 83 | #define HIGH_ADDR_REMAP_REG_3 0x028c | 83 | #define HIGH_ADDR_REMAP_REG_3 0x028c |
| 84 | #define BASE_ADDR_ENABLE_REG 0x0290 | 84 | #define BASE_ADDR_ENABLE_REG 0x0290 |
| 85 | #define ACCESS_PROTECTION_REG(port) (0x0294 + (port<<2)) | 85 | |
| 86 | #define MIB_COUNTERS_BASE(port) (0x1000 + (port<<7)) | 86 | |
| 87 | #define PORT_CONFIG_REG(port) (0x0400 + (port<<10)) | 87 | /* |
| 88 | #define PORT_CONFIG_EXTEND_REG(port) (0x0404 + (port<<10)) | 88 | * Per-port registers. |
| 89 | #define MII_SERIAL_PARAMETRS_REG(port) (0x0408 + (port<<10)) | 89 | */ |
| 90 | #define GMII_SERIAL_PARAMETRS_REG(port) (0x040c + (port<<10)) | 90 | #define ACCESS_PROTECTION_REG(p) (0x0294 + ((p) << 2)) |
| 91 | #define VLAN_ETHERTYPE_REG(port) (0x0410 + (port<<10)) | 91 | #define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10)) |
| 92 | #define MAC_ADDR_LOW(port) (0x0414 + (port<<10)) | 92 | #define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10)) |
| 93 | #define MAC_ADDR_HIGH(port) (0x0418 + (port<<10)) | 93 | #define MII_SERIAL_PARAMETRS_REG(p) (0x0408 + ((p) << 10)) |
| 94 | #define SDMA_CONFIG_REG(port) (0x041c + (port<<10)) | 94 | #define GMII_SERIAL_PARAMETRS_REG(p) (0x040c + ((p) << 10)) |
| 95 | #define DSCP_0(port) (0x0420 + (port<<10)) | 95 | #define VLAN_ETHERTYPE_REG(p) (0x0410 + ((p) << 10)) |
| 96 | #define DSCP_1(port) (0x0424 + (port<<10)) | 96 | #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) |
| 97 | #define DSCP_2(port) (0x0428 + (port<<10)) | 97 | #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) |
| 98 | #define DSCP_3(port) (0x042c + (port<<10)) | 98 | #define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10)) |
| 99 | #define DSCP_4(port) (0x0430 + (port<<10)) | 99 | #define DSCP_0(p) (0x0420 + ((p) << 10)) |
| 100 | #define DSCP_5(port) (0x0434 + (port<<10)) | 100 | #define DSCP_1(p) (0x0424 + ((p) << 10)) |
| 101 | #define DSCP_6(port) (0x0438 + (port<<10)) | 101 | #define DSCP_2(p) (0x0428 + ((p) << 10)) |
| 102 | #define PORT_SERIAL_CONTROL_REG(port) (0x043c + (port<<10)) | 102 | #define DSCP_3(p) (0x042c + ((p) << 10)) |
| 103 | #define VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x0440 + (port<<10)) | 103 | #define DSCP_4(p) (0x0430 + ((p) << 10)) |
| 104 | #define PORT_STATUS_REG(port) (0x0444 + (port<<10)) | 104 | #define DSCP_5(p) (0x0434 + ((p) << 10)) |
| 105 | #define TRANSMIT_QUEUE_COMMAND_REG(port) (0x0448 + (port<<10)) | 105 | #define DSCP_6(p) (0x0438 + ((p) << 10)) |
| 106 | #define TX_QUEUE_FIXED_PRIORITY(port) (0x044c + (port<<10)) | 106 | #define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10)) |
| 107 | #define PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x0450 + (port<<10)) | 107 | #define VLAN_PRIORITY_TAG_TO_PRIORITY(p) (0x0440 + ((p) << 10)) |
| 108 | #define MAXIMUM_TRANSMIT_UNIT(port) (0x0458 + (port<<10)) | 108 | #define PORT_STATUS_REG(p) (0x0444 + ((p) << 10)) |
| 109 | #define PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x045c + (port<<10)) | 109 | #define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10)) |
| 110 | #define INTERRUPT_CAUSE_REG(port) (0x0460 + (port<<10)) | 110 | #define TX_QUEUE_FIXED_PRIORITY(p) (0x044c + ((p) << 10)) |
| 111 | #define INTERRUPT_CAUSE_EXTEND_REG(port) (0x0464 + (port<<10)) | 111 | #define PORT_TX_TOKEN_BUCKET_RATE_CONFIG(p) (0x0450 + ((p) << 10)) |
| 112 | #define INTERRUPT_MASK_REG(port) (0x0468 + (port<<10)) | 112 | #define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10)) |
| 113 | #define INTERRUPT_EXTEND_MASK_REG(port) (0x046c + (port<<10)) | 113 | #define PORT_MAXIMUM_TOKEN_BUCKET_SIZE(p) (0x045c + ((p) << 10)) |
| 114 | #define RX_FIFO_URGENT_THRESHOLD_REG(port) (0x0470 + (port<<10)) | 114 | #define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10)) |
| 115 | #define TX_FIFO_URGENT_THRESHOLD_REG(port) (0x0474 + (port<<10)) | 115 | #define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10)) |
| 116 | #define RX_MINIMAL_FRAME_SIZE_REG(port) (0x047c + (port<<10)) | 116 | #define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10)) |
| 117 | #define RX_DISCARDED_FRAMES_COUNTER(port) (0x0484 + (port<<10)) | 117 | #define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10)) |
| 118 | #define PORT_DEBUG_0_REG(port) (0x048c + (port<<10)) | 118 | #define RX_FIFO_URGENT_THRESHOLD_REG(p) (0x0470 + ((p) << 10)) |
| 119 | #define PORT_DEBUG_1_REG(port) (0x0490 + (port<<10)) | 119 | #define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10)) |
| 120 | #define PORT_INTERNAL_ADDR_ERROR_REG(port) (0x0494 + (port<<10)) | 120 | #define RX_MINIMAL_FRAME_SIZE_REG(p) (0x047c + ((p) << 10)) |
| 121 | #define INTERNAL_USE_REG(port) (0x04fc + (port<<10)) | 121 | #define RX_DISCARDED_FRAMES_COUNTER(p) (0x0484 + ((p) << 10)) |
| 122 | #define RECEIVE_QUEUE_COMMAND_REG(port) (0x0680 + (port<<10)) | 122 | #define PORT_DEBUG_0_REG(p) (0x048c + ((p) << 10)) |
| 123 | #define CURRENT_SERVED_TX_DESC_PTR(port) (0x0684 + (port<<10)) | 123 | #define PORT_DEBUG_1_REG(p) (0x0490 + ((p) << 10)) |
| 124 | #define RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x060c + (port<<10)) | 124 | #define PORT_INTERNAL_ADDR_ERROR_REG(p) (0x0494 + ((p) << 10)) |
| 125 | #define RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x061c + (port<<10)) | 125 | #define INTERNAL_USE_REG(p) (0x04fc + ((p) << 10)) |
| 126 | #define RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x062c + (port<<10)) | 126 | #define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10)) |
| 127 | #define RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x063c + (port<<10)) | 127 | #define RX_CURRENT_QUEUE_DESC_PTR_1(p) (0x061c + ((p) << 10)) |
| 128 | #define RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x064c + (port<<10)) | 128 | #define RX_CURRENT_QUEUE_DESC_PTR_2(p) (0x062c + ((p) << 10)) |
| 129 | #define RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x065c + (port<<10)) | 129 | #define RX_CURRENT_QUEUE_DESC_PTR_3(p) (0x063c + ((p) << 10)) |
| 130 | #define RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x066c + (port<<10)) | 130 | #define RX_CURRENT_QUEUE_DESC_PTR_4(p) (0x064c + ((p) << 10)) |
| 131 | #define RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x067c + (port<<10)) | 131 | #define RX_CURRENT_QUEUE_DESC_PTR_5(p) (0x065c + ((p) << 10)) |
| 132 | #define TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x06c0 + (port<<10)) | 132 | #define RX_CURRENT_QUEUE_DESC_PTR_6(p) (0x066c + ((p) << 10)) |
| 133 | #define TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x06c4 + (port<<10)) | 133 | #define RX_CURRENT_QUEUE_DESC_PTR_7(p) (0x067c + ((p) << 10)) |
| 134 | #define TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x06c8 + (port<<10)) | 134 | #define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10)) |
| 135 | #define TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x06cc + (port<<10)) | 135 | #define CURRENT_SERVED_TX_DESC_PTR(p) (0x0684 + ((p) << 10)) |
| 136 | #define TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x06d0 + (port<<10)) | 136 | #define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10)) |
| 137 | #define TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x06d4 + (port<<10)) | 137 | #define TX_CURRENT_QUEUE_DESC_PTR_1(p) (0x06c4 + ((p) << 10)) |
| 138 | #define TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x06d8 + (port<<10)) | 138 | #define TX_CURRENT_QUEUE_DESC_PTR_2(p) (0x06c8 + ((p) << 10)) |
| 139 | #define TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x06dc + (port<<10)) | 139 | #define TX_CURRENT_QUEUE_DESC_PTR_3(p) (0x06cc + ((p) << 10)) |
| 140 | #define TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x0700 + (port<<10)) | 140 | #define TX_CURRENT_QUEUE_DESC_PTR_4(p) (0x06d0 + ((p) << 10)) |
| 141 | #define TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x0710 + (port<<10)) | 141 | #define TX_CURRENT_QUEUE_DESC_PTR_5(p) (0x06d4 + ((p) << 10)) |
| 142 | #define TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x0720 + (port<<10)) | 142 | #define TX_CURRENT_QUEUE_DESC_PTR_6(p) (0x06d8 + ((p) << 10)) |
| 143 | #define TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x0730 + (port<<10)) | 143 | #define TX_CURRENT_QUEUE_DESC_PTR_7(p) (0x06dc + ((p) << 10)) |
| 144 | #define TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x0740 + (port<<10)) | 144 | #define TX_QUEUE_0_TOKEN_BUCKET_COUNT(p) (0x0700 + ((p) << 10)) |
| 145 | #define TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x0750 + (port<<10)) | 145 | #define TX_QUEUE_0_TOKEN_BUCKET_CONFIG(p) (0x0704 + ((p) << 10)) |
| 146 | #define TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x0760 + (port<<10)) | 146 | #define TX_QUEUE_0_ARBITER_CONFIG(p) (0x0708 + ((p) << 10)) |
| 147 | #define TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x0770 + (port<<10)) | 147 | #define TX_QUEUE_1_TOKEN_BUCKET_COUNT(p) (0x0710 + ((p) << 10)) |
| 148 | #define TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x0704 + (port<<10)) | 148 | #define TX_QUEUE_1_TOKEN_BUCKET_CONFIG(p) (0x0714 + ((p) << 10)) |
| 149 | #define TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x0714 + (port<<10)) | 149 | #define TX_QUEUE_1_ARBITER_CONFIG(p) (0x0718 + ((p) << 10)) |
| 150 | #define TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x0724 + (port<<10)) | 150 | #define TX_QUEUE_2_TOKEN_BUCKET_COUNT(p) (0x0720 + ((p) << 10)) |
| 151 | #define TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x0734 + (port<<10)) | 151 | #define TX_QUEUE_2_TOKEN_BUCKET_CONFIG(p) (0x0724 + ((p) << 10)) |
| 152 | #define TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x0744 + (port<<10)) | 152 | #define TX_QUEUE_2_ARBITER_CONFIG(p) (0x0728 + ((p) << 10)) |
| 153 | #define TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x0754 + (port<<10)) | 153 | #define TX_QUEUE_3_TOKEN_BUCKET_COUNT(p) (0x0730 + ((p) << 10)) |
| 154 | #define TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x0764 + (port<<10)) | 154 | #define TX_QUEUE_3_TOKEN_BUCKET_CONFIG(p) (0x0734 + ((p) << 10)) |
| 155 | #define TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x0774 + (port<<10)) | 155 | #define TX_QUEUE_3_ARBITER_CONFIG(p) (0x0738 + ((p) << 10)) |
| 156 | #define TX_QUEUE_0_ARBITER_CONFIG(port) (0x0708 + (port<<10)) | 156 | #define TX_QUEUE_4_TOKEN_BUCKET_COUNT(p) (0x0740 + ((p) << 10)) |
| 157 | #define TX_QUEUE_1_ARBITER_CONFIG(port) (0x0718 + (port<<10)) | 157 | #define TX_QUEUE_4_TOKEN_BUCKET_CONFIG(p) (0x0744 + ((p) << 10)) |
| 158 | #define TX_QUEUE_2_ARBITER_CONFIG(port) (0x0728 + (port<<10)) | 158 | #define TX_QUEUE_4_ARBITER_CONFIG(p) (0x0748 + ((p) << 10)) |
| 159 | #define TX_QUEUE_3_ARBITER_CONFIG(port) (0x0738 + (port<<10)) | 159 | #define TX_QUEUE_5_TOKEN_BUCKET_COUNT(p) (0x0750 + ((p) << 10)) |
| 160 | #define TX_QUEUE_4_ARBITER_CONFIG(port) (0x0748 + (port<<10)) | 160 | #define TX_QUEUE_5_TOKEN_BUCKET_CONFIG(p) (0x0754 + ((p) << 10)) |
| 161 | #define TX_QUEUE_5_ARBITER_CONFIG(port) (0x0758 + (port<<10)) | 161 | #define TX_QUEUE_5_ARBITER_CONFIG(p) (0x0758 + ((p) << 10)) |
| 162 | #define TX_QUEUE_6_ARBITER_CONFIG(port) (0x0768 + (port<<10)) | 162 | #define TX_QUEUE_6_TOKEN_BUCKET_COUNT(p) (0x0760 + ((p) << 10)) |
| 163 | #define TX_QUEUE_7_ARBITER_CONFIG(port) (0x0778 + (port<<10)) | 163 | #define TX_QUEUE_6_TOKEN_BUCKET_CONFIG(p) (0x0764 + ((p) << 10)) |
| 164 | #define PORT_TX_TOKEN_BUCKET_COUNT(port) (0x0780 + (port<<10)) | 164 | #define TX_QUEUE_6_ARBITER_CONFIG(p) (0x0768 + ((p) << 10)) |
| 165 | #define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x1400 + (port<<10)) | 165 | #define TX_QUEUE_7_TOKEN_BUCKET_COUNT(p) (0x0770 + ((p) << 10)) |
| 166 | #define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x1500 + (port<<10)) | 166 | #define TX_QUEUE_7_TOKEN_BUCKET_CONFIG(p) (0x0774 + ((p) << 10)) |
| 167 | #define DA_FILTER_UNICAST_TABLE_BASE(port) (0x1600 + (port<<10)) | 167 | #define TX_QUEUE_7_ARBITER_CONFIG(p) (0x0778 + ((p) << 10)) |
| 168 | #define PORT_TX_TOKEN_BUCKET_COUNT(p) (0x0780 + ((p) << 10)) | ||
| 169 | #define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7)) | ||
| 170 | #define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10)) | ||
| 171 | #define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10)) | ||
| 172 | #define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10)) | ||
| 168 | 173 | ||
| 169 | /* These macros describe Ethernet Port configuration reg (Px_cR) bits */ | 174 | /* These macros describe Ethernet Port configuration reg (Px_cR) bits */ |
| 170 | #define UNICAST_NORMAL_MODE 0 | 175 | #define UNICAST_NORMAL_MODE (0 << 0) |
| 171 | #define UNICAST_PROMISCUOUS_MODE (1<<0) | 176 | #define UNICAST_PROMISCUOUS_MODE (1 << 0) |
| 172 | #define DEFAULT_RX_QUEUE_0 0 | 177 | #define DEFAULT_RX_QUEUE(queue) ((queue) << 1) |
| 173 | #define DEFAULT_RX_QUEUE_1 (1<<1) | 178 | #define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4) |
| 174 | #define DEFAULT_RX_QUEUE_2 (1<<2) | 179 | #define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7) |
| 175 | #define DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1)) | 180 | #define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) |
| 176 | #define DEFAULT_RX_QUEUE_4 (1<<3) | 181 | #define RECEIVE_BC_IF_IP (0 << 8) |
| 177 | #define DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1)) | 182 | #define REJECT_BC_IF_IP (1 << 8) |
| 178 | #define DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2)) | 183 | #define RECEIVE_BC_IF_ARP (0 << 9) |
| 179 | #define DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1)) | 184 | #define REJECT_BC_IF_ARP (1 << 9) |
| 180 | #define DEFAULT_RX_ARP_QUEUE_0 0 | 185 | #define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12) |
| 181 | #define DEFAULT_RX_ARP_QUEUE_1 (1<<4) | 186 | #define CAPTURE_TCP_FRAMES_DIS (0 << 14) |
| 182 | #define DEFAULT_RX_ARP_QUEUE_2 (1<<5) | 187 | #define CAPTURE_TCP_FRAMES_EN (1 << 14) |
| 183 | #define DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4)) | 188 | #define CAPTURE_UDP_FRAMES_DIS (0 << 15) |
| 184 | #define DEFAULT_RX_ARP_QUEUE_4 (1<<6) | 189 | #define CAPTURE_UDP_FRAMES_EN (1 << 15) |
| 185 | #define DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4)) | 190 | #define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16) |
| 186 | #define DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5)) | 191 | #define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19) |
| 187 | #define DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4)) | 192 | #define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22) |
| 188 | #define RECEIVE_BC_IF_NOT_IP_OR_ARP 0 | 193 | |
| 189 | #define REJECT_BC_IF_NOT_IP_OR_ARP (1<<7) | 194 | #define PORT_CONFIG_DEFAULT_VALUE \ |
| 190 | #define RECEIVE_BC_IF_IP 0 | ||
| 191 | #define REJECT_BC_IF_IP (1<<8) | ||
| 192 | #define RECEIVE_BC_IF_ARP 0 | ||
| 193 | #define REJECT_BC_IF_ARP (1<<9) | ||
| 194 | #define TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12) | ||
| 195 | #define CAPTURE_TCP_FRAMES_DIS 0 | ||
| 196 | #define CAPTURE_TCP_FRAMES_EN (1<<14) | ||
| 197 | #define CAPTURE_UDP_FRAMES_DIS 0 | ||
| 198 | #define CAPTURE_UDP_FRAMES_EN (1<<15) | ||
| 199 | #define DEFAULT_RX_TCP_QUEUE_0 0 | ||
| 200 | #define DEFAULT_RX_TCP_QUEUE_1 (1<<16) | ||
| 201 | #define DEFAULT_RX_TCP_QUEUE_2 (1<<17) | ||
| 202 | #define DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16)) | ||
| 203 | #define DEFAULT_RX_TCP_QUEUE_4 (1<<18) | ||
| 204 | #define DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16)) | ||
| 205 | #define DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17)) | ||
| 206 | #define DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16)) | ||
| 207 | #define DEFAULT_RX_UDP_QUEUE_0 0 | ||
| 208 | #define DEFAULT_RX_UDP_QUEUE_1 (1<<19) | ||
| 209 | #define DEFAULT_RX_UDP_QUEUE_2 (1<<20) | ||
| 210 | #define DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19)) | ||
| 211 | #define DEFAULT_RX_UDP_QUEUE_4 (1<<21) | ||
| 212 | #define DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19)) | ||
| 213 | #define DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20)) | ||
| 214 | #define DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19)) | ||
| 215 | #define DEFAULT_RX_BPDU_QUEUE_0 0 | ||
| 216 | #define DEFAULT_RX_BPDU_QUEUE_1 (1<<22) | ||
| 217 | #define DEFAULT_RX_BPDU_QUEUE_2 (1<<23) | ||
| 218 | #define DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22)) | ||
| 219 | #define DEFAULT_RX_BPDU_QUEUE_4 (1<<24) | ||
| 220 | #define DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22)) | ||
| 221 | #define DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23)) | ||
| 222 | #define DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22)) | ||
| 223 | |||
| 224 | #define PORT_CONFIG_DEFAULT_VALUE \ | ||
| 225 | UNICAST_NORMAL_MODE | \ | 195 | UNICAST_NORMAL_MODE | \ |
| 226 | DEFAULT_RX_QUEUE_0 | \ | 196 | DEFAULT_RX_QUEUE(0) | \ |
| 227 | DEFAULT_RX_ARP_QUEUE_0 | \ | 197 | DEFAULT_RX_ARP_QUEUE(0) | \ |
| 228 | RECEIVE_BC_IF_NOT_IP_OR_ARP | \ | 198 | RECEIVE_BC_IF_NOT_IP_OR_ARP | \ |
| 229 | RECEIVE_BC_IF_IP | \ | 199 | RECEIVE_BC_IF_IP | \ |
| 230 | RECEIVE_BC_IF_ARP | \ | 200 | RECEIVE_BC_IF_ARP | \ |
| 231 | CAPTURE_TCP_FRAMES_DIS | \ | 201 | CAPTURE_TCP_FRAMES_DIS | \ |
| 232 | CAPTURE_UDP_FRAMES_DIS | \ | 202 | CAPTURE_UDP_FRAMES_DIS | \ |
| 233 | DEFAULT_RX_TCP_QUEUE_0 | \ | 203 | DEFAULT_RX_TCP_QUEUE(0) | \ |
| 234 | DEFAULT_RX_UDP_QUEUE_0 | \ | 204 | DEFAULT_RX_UDP_QUEUE(0) | \ |
| 235 | DEFAULT_RX_BPDU_QUEUE_0 | 205 | DEFAULT_RX_BPDU_QUEUE(0) |
| 236 | 206 | ||
| 237 | /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/ | 207 | /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/ |
| 238 | #define CLASSIFY_EN (1<<0) | 208 | #define CLASSIFY_EN (1 << 0) |
| 239 | #define SPAN_BPDU_PACKETS_AS_NORMAL 0 | 209 | #define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1) |
| 240 | #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1) | 210 | #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1) |
| 241 | #define PARTITION_DISABLE 0 | 211 | #define PARTITION_DISABLE (0 << 2) |
| 242 | #define PARTITION_ENABLE (1<<2) | 212 | #define PARTITION_ENABLE (1 << 2) |
| 243 | 213 | ||
| 244 | #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \ | 214 | #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \ |
| 245 | SPAN_BPDU_PACKETS_AS_NORMAL | \ | 215 | SPAN_BPDU_PACKETS_AS_NORMAL | \ |
| 246 | PARTITION_DISABLE | 216 | PARTITION_DISABLE |
| 247 | 217 | ||
| 248 | /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */ | 218 | /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */ |
| 249 | #define RIFB (1<<0) | 219 | #define RIFB (1 << 0) |
| 250 | #define RX_BURST_SIZE_1_64BIT 0 | 220 | #define RX_BURST_SIZE_1_64BIT (0 << 1) |
| 251 | #define RX_BURST_SIZE_2_64BIT (1<<1) | 221 | #define RX_BURST_SIZE_2_64BIT (1 << 1) |
| 252 | #define RX_BURST_SIZE_4_64BIT (1<<2) | 222 | #define RX_BURST_SIZE_4_64BIT (2 << 1) |
| 253 | #define RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1)) | 223 | #define RX_BURST_SIZE_8_64BIT (3 << 1) |
| 254 | #define RX_BURST_SIZE_16_64BIT (1<<3) | 224 | #define RX_BURST_SIZE_16_64BIT (4 << 1) |
| 255 | #define BLM_RX_NO_SWAP (1<<4) | 225 | #define BLM_RX_NO_SWAP (1 << 4) |
| 256 | #define BLM_RX_BYTE_SWAP 0 | 226 | #define BLM_RX_BYTE_SWAP (0 << 4) |
| 257 | #define BLM_TX_NO_SWAP (1<<5) | 227 | #define BLM_TX_NO_SWAP (1 << 5) |
| 258 | #define BLM_TX_BYTE_SWAP 0 | 228 | #define BLM_TX_BYTE_SWAP (0 << 5) |
| 259 | #define DESCRIPTORS_BYTE_SWAP (1<<6) | 229 | #define DESCRIPTORS_BYTE_SWAP (1 << 6) |
| 260 | #define DESCRIPTORS_NO_SWAP 0 | 230 | #define DESCRIPTORS_NO_SWAP (0 << 6) |
| 261 | #define TX_BURST_SIZE_1_64BIT 0 | 231 | #define IPG_INT_RX(value) (((value) & 0x3fff) << 8) |
| 262 | #define TX_BURST_SIZE_2_64BIT (1<<22) | 232 | #define TX_BURST_SIZE_1_64BIT (0 << 22) |
| 263 | #define TX_BURST_SIZE_4_64BIT (1<<23) | 233 | #define TX_BURST_SIZE_2_64BIT (1 << 22) |
| 264 | #define TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22)) | 234 | #define TX_BURST_SIZE_4_64BIT (2 << 22) |
| 265 | #define TX_BURST_SIZE_16_64BIT (1<<24) | 235 | #define TX_BURST_SIZE_8_64BIT (3 << 22) |
| 266 | 236 | #define TX_BURST_SIZE_16_64BIT (4 << 22) | |
| 267 | #define IPG_INT_RX(value) ((value & 0x3fff) << 8) | ||
| 268 | 237 | ||
| 269 | #if defined(__BIG_ENDIAN) | 238 | #if defined(__BIG_ENDIAN) |
| 270 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | 239 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ |
| 271 | RX_BURST_SIZE_4_64BIT | \ | 240 | RX_BURST_SIZE_4_64BIT | \ |
| 272 | IPG_INT_RX(0) | \ | 241 | IPG_INT_RX(0) | \ |
| 273 | TX_BURST_SIZE_4_64BIT | 242 | TX_BURST_SIZE_4_64BIT |
| 274 | #elif defined(__LITTLE_ENDIAN) | 243 | #elif defined(__LITTLE_ENDIAN) |
| 275 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | 244 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ |
| 276 | RX_BURST_SIZE_4_64BIT | \ | 245 | RX_BURST_SIZE_4_64BIT | \ |
| 277 | BLM_RX_NO_SWAP | \ | 246 | BLM_RX_NO_SWAP | \ |
| 278 | BLM_TX_NO_SWAP | \ | 247 | BLM_TX_NO_SWAP | \ |
| @@ -283,88 +252,87 @@ | |||
| 283 | #endif | 252 | #endif |
| 284 | 253 | ||
| 285 | /* These macros describe Ethernet Port serial control reg (PSCR) bits */ | 254 | /* These macros describe Ethernet Port serial control reg (PSCR) bits */ |
| 286 | #define SERIAL_PORT_DISABLE 0 | 255 | #define SERIAL_PORT_DISABLE (0 << 0) |
| 287 | #define SERIAL_PORT_ENABLE (1<<0) | 256 | #define SERIAL_PORT_ENABLE (1 << 0) |
| 288 | #define FORCE_LINK_PASS (1<<1) | 257 | #define DO_NOT_FORCE_LINK_PASS (0 << 1) |
| 289 | #define DO_NOT_FORCE_LINK_PASS 0 | 258 | #define FORCE_LINK_PASS (1 << 1) |
| 290 | #define ENABLE_AUTO_NEG_FOR_DUPLX 0 | 259 | #define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2) |
| 291 | #define DISABLE_AUTO_NEG_FOR_DUPLX (1<<2) | 260 | #define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2) |
| 292 | #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 | 261 | #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3) |
| 293 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3) | 262 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) |
| 294 | #define ADV_NO_FLOW_CTRL 0 | 263 | #define ADV_NO_FLOW_CTRL (0 << 4) |
| 295 | #define ADV_SYMMETRIC_FLOW_CTRL (1<<4) | 264 | #define ADV_SYMMETRIC_FLOW_CTRL (1 << 4) |
| 296 | #define FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 | 265 | #define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5) |
| 297 | #define FORCE_FC_MODE_TX_PAUSE_DIS (1<<5) | 266 | #define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) |
| 298 | #define FORCE_BP_MODE_NO_JAM 0 | 267 | #define FORCE_BP_MODE_NO_JAM (0 << 7) |
| 299 | #define FORCE_BP_MODE_JAM_TX (1<<7) | 268 | #define FORCE_BP_MODE_JAM_TX (1 << 7) |
| 300 | #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8) | 269 | #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7) |
| 301 | #define SERIAL_PORT_CONTROL_RESERVED (1<<9) | 270 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) |
| 302 | #define FORCE_LINK_FAIL 0 | 271 | #define FORCE_LINK_FAIL (0 << 10) |
| 303 | #define DO_NOT_FORCE_LINK_FAIL (1<<10) | 272 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) |
| 304 | #define RETRANSMIT_16_ATTEMPTS 0 | 273 | #define RETRANSMIT_16_ATTEMPTS (0 << 11) |
| 305 | #define RETRANSMIT_FOREVER (1<<11) | 274 | #define RETRANSMIT_FOREVER (1 << 11) |
| 306 | #define DISABLE_AUTO_NEG_SPEED_GMII (1<<13) | 275 | #define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13) |
| 307 | #define ENABLE_AUTO_NEG_SPEED_GMII 0 | 276 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) |
| 308 | #define DTE_ADV_0 0 | 277 | #define DTE_ADV_0 (0 << 14) |
| 309 | #define DTE_ADV_1 (1<<14) | 278 | #define DTE_ADV_1 (1 << 14) |
| 310 | #define DISABLE_AUTO_NEG_BYPASS 0 | 279 | #define DISABLE_AUTO_NEG_BYPASS (0 << 15) |
| 311 | #define ENABLE_AUTO_NEG_BYPASS (1<<15) | 280 | #define ENABLE_AUTO_NEG_BYPASS (1 << 15) |
| 312 | #define AUTO_NEG_NO_CHANGE 0 | 281 | #define AUTO_NEG_NO_CHANGE (0 << 16) |
| 313 | #define RESTART_AUTO_NEG (1<<16) | 282 | #define RESTART_AUTO_NEG (1 << 16) |
| 314 | #define MAX_RX_PACKET_1518BYTE 0 | 283 | #define MAX_RX_PACKET_1518BYTE (0 << 17) |
| 315 | #define MAX_RX_PACKET_1522BYTE (1<<17) | 284 | #define MAX_RX_PACKET_1522BYTE (1 << 17) |
| 316 | #define MAX_RX_PACKET_1552BYTE (1<<18) | 285 | #define MAX_RX_PACKET_1552BYTE (2 << 17) |
| 317 | #define MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17)) | 286 | #define MAX_RX_PACKET_9022BYTE (3 << 17) |
| 318 | #define MAX_RX_PACKET_9192BYTE (1<<19) | 287 | #define MAX_RX_PACKET_9192BYTE (4 << 17) |
| 319 | #define MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17)) | 288 | #define MAX_RX_PACKET_9700BYTE (5 << 17) |
| 320 | #define SET_EXT_LOOPBACK (1<<20) | 289 | #define MAX_RX_PACKET_MASK (7 << 17) |
| 321 | #define CLR_EXT_LOOPBACK 0 | 290 | #define CLR_EXT_LOOPBACK (0 << 20) |
| 322 | #define SET_FULL_DUPLEX_MODE (1<<21) | 291 | #define SET_EXT_LOOPBACK (1 << 20) |
| 323 | #define SET_HALF_DUPLEX_MODE 0 | 292 | #define SET_HALF_DUPLEX_MODE (0 << 21) |
| 324 | #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22) | 293 | #define SET_FULL_DUPLEX_MODE (1 << 21) |
| 325 | #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 | 294 | #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22) |
| 326 | #define SET_GMII_SPEED_TO_10_100 0 | 295 | #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) |
| 327 | #define SET_GMII_SPEED_TO_1000 (1<<23) | 296 | #define SET_GMII_SPEED_TO_10_100 (0 << 23) |
| 328 | #define SET_MII_SPEED_TO_10 0 | 297 | #define SET_GMII_SPEED_TO_1000 (1 << 23) |
| 329 | #define SET_MII_SPEED_TO_100 (1<<24) | 298 | #define SET_MII_SPEED_TO_10 (0 << 24) |
| 330 | 299 | #define SET_MII_SPEED_TO_100 (1 << 24) | |
| 331 | #define MAX_RX_PACKET_MASK (0x7<<17) | 300 | |
| 332 | 301 | #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \ | |
| 333 | #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \ | 302 | DO_NOT_FORCE_LINK_PASS | \ |
| 334 | DO_NOT_FORCE_LINK_PASS | \ | ||
| 335 | ENABLE_AUTO_NEG_FOR_DUPLX | \ | 303 | ENABLE_AUTO_NEG_FOR_DUPLX | \ |
| 336 | DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ | 304 | DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ |
| 337 | ADV_SYMMETRIC_FLOW_CTRL | \ | 305 | ADV_SYMMETRIC_FLOW_CTRL | \ |
| 338 | FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ | 306 | FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ |
| 339 | FORCE_BP_MODE_NO_JAM | \ | 307 | FORCE_BP_MODE_NO_JAM | \ |
| 340 | (1<<9) /* reserved */ | \ | 308 | (1 << 9) /* reserved */ | \ |
| 341 | DO_NOT_FORCE_LINK_FAIL | \ | 309 | DO_NOT_FORCE_LINK_FAIL | \ |
| 342 | RETRANSMIT_16_ATTEMPTS | \ | 310 | RETRANSMIT_16_ATTEMPTS | \ |
| 343 | ENABLE_AUTO_NEG_SPEED_GMII | \ | 311 | ENABLE_AUTO_NEG_SPEED_GMII | \ |
| 344 | DTE_ADV_0 | \ | 312 | DTE_ADV_0 | \ |
| 345 | DISABLE_AUTO_NEG_BYPASS | \ | 313 | DISABLE_AUTO_NEG_BYPASS | \ |
| 346 | AUTO_NEG_NO_CHANGE | \ | 314 | AUTO_NEG_NO_CHANGE | \ |
| 347 | MAX_RX_PACKET_9700BYTE | \ | 315 | MAX_RX_PACKET_9700BYTE | \ |
| 348 | CLR_EXT_LOOPBACK | \ | 316 | CLR_EXT_LOOPBACK | \ |
| 349 | SET_FULL_DUPLEX_MODE | \ | 317 | SET_FULL_DUPLEX_MODE | \ |
| 350 | ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX | 318 | ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |
| 351 | 319 | ||
| 352 | /* These macros describe Ethernet Serial Status reg (PSR) bits */ | 320 | /* These macros describe Ethernet Serial Status reg (PSR) bits */ |
| 353 | #define PORT_STATUS_MODE_10_BIT (1<<0) | 321 | #define PORT_STATUS_MODE_10_BIT (1 << 0) |
| 354 | #define PORT_STATUS_LINK_UP (1<<1) | 322 | #define PORT_STATUS_LINK_UP (1 << 1) |
| 355 | #define PORT_STATUS_FULL_DUPLEX (1<<2) | 323 | #define PORT_STATUS_FULL_DUPLEX (1 << 2) |
| 356 | #define PORT_STATUS_FLOW_CONTROL (1<<3) | 324 | #define PORT_STATUS_FLOW_CONTROL (1 << 3) |
| 357 | #define PORT_STATUS_GMII_1000 (1<<4) | 325 | #define PORT_STATUS_GMII_1000 (1 << 4) |
| 358 | #define PORT_STATUS_MII_100 (1<<5) | 326 | #define PORT_STATUS_MII_100 (1 << 5) |
| 359 | /* PSR bit 6 is undocumented */ | 327 | /* PSR bit 6 is undocumented */ |
| 360 | #define PORT_STATUS_TX_IN_PROGRESS (1<<7) | 328 | #define PORT_STATUS_TX_IN_PROGRESS (1 << 7) |
| 361 | #define PORT_STATUS_AUTONEG_BYPASSED (1<<8) | 329 | #define PORT_STATUS_AUTONEG_BYPASSED (1 << 8) |
| 362 | #define PORT_STATUS_PARTITION (1<<9) | 330 | #define PORT_STATUS_PARTITION (1 << 9) |
| 363 | #define PORT_STATUS_TX_FIFO_EMPTY (1<<10) | 331 | #define PORT_STATUS_TX_FIFO_EMPTY (1 << 10) |
| 364 | /* PSR bits 11-31 are reserved */ | 332 | /* PSR bits 11-31 are reserved */ |
| 365 | 333 | ||
| 366 | #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800 | 334 | #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800 |
| 367 | #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400 | 335 | #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400 |
| 368 | 336 | ||
| 369 | #define DESC_SIZE 64 | 337 | #define DESC_SIZE 64 |
| 370 | 338 | ||
| @@ -446,7 +414,7 @@ | |||
| 446 | #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */ | 414 | #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */ |
| 447 | #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */ | 415 | #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */ |
| 448 | #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */ | 416 | #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */ |
| 449 | #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */ | 417 | #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */ |
| 450 | 418 | ||
| 451 | /* Interrupt Cause Register Bit Definitions */ | 419 | /* Interrupt Cause Register Bit Definitions */ |
| 452 | 420 | ||
| @@ -537,7 +505,6 @@ struct eth_tx_desc { | |||
| 537 | u32 next_desc_ptr; /* Pointer to next descriptor */ | 505 | u32 next_desc_ptr; /* Pointer to next descriptor */ |
| 538 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | 506 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ |
| 539 | }; | 507 | }; |
| 540 | |||
| 541 | #elif defined(__LITTLE_ENDIAN) | 508 | #elif defined(__LITTLE_ENDIAN) |
| 542 | struct eth_rx_desc { | 509 | struct eth_rx_desc { |
| 543 | u32 cmd_sts; /* Descriptor command status */ | 510 | u32 cmd_sts; /* Descriptor command status */ |
| @@ -569,7 +536,6 @@ struct pkt_info { | |||
| 569 | }; | 536 | }; |
| 570 | 537 | ||
| 571 | /* Ethernet port specific information */ | 538 | /* Ethernet port specific information */ |
| 572 | |||
| 573 | struct mv643xx_mib_counters { | 539 | struct mv643xx_mib_counters { |
| 574 | u64 good_octets_received; | 540 | u64 good_octets_received; |
| 575 | u32 bad_octets_received; | 541 | u32 bad_octets_received; |
| @@ -684,4 +650,5 @@ static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, | |||
| 684 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, | 650 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, |
| 685 | struct pkt_info *p_pkt_info); | 651 | struct pkt_info *p_pkt_info); |
| 686 | 652 | ||
| 687 | #endif /* __MV643XX_ETH_H__ */ | 653 | |
| 654 | #endif | ||