diff options
author | Felix Fietkau <nbd@openwrt.org> | 2010-12-02 04:27:01 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2010-12-02 15:17:50 -0500 |
commit | 4aa5d783c9e1c72e4950ff34f388077ccecac74a (patch) | |
tree | 13e54573b8e38fa8f012d55dbbadddd503683e6e /drivers | |
parent | e5b046d86fac609f636d127a38de94a175c7e83b (diff) |
ath5k: Use generic eeprom read from common ath_bus_opts struct.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@neratec.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/wireless/ath/ath5k/ath5k.h | 6 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/eeprom.c | 38 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/eeprom.h | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/pci.c | 36 |
4 files changed, 45 insertions, 37 deletions
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h index ee3c0af3ab3c..5d9fdc2ccfaa 100644 --- a/drivers/net/wireless/ath/ath5k/ath5k.h +++ b/drivers/net/wireless/ath/ath5k/ath5k.h | |||
@@ -1342,6 +1342,12 @@ static inline void ath5k_read_cachesize(struct ath_common *common, int *csz) | |||
1342 | common->bus_ops->read_cachesize(common, csz); | 1342 | common->bus_ops->read_cachesize(common, csz); |
1343 | } | 1343 | } |
1344 | 1344 | ||
1345 | static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data) | ||
1346 | { | ||
1347 | struct ath_common *common = ath5k_hw_common(ah); | ||
1348 | return common->bus_ops->eeprom_read(common, off, data); | ||
1349 | } | ||
1350 | |||
1345 | static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) | 1351 | static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) |
1346 | { | 1352 | { |
1347 | u32 retval = 0, bit, i; | 1353 | u32 retval = 0, bit, i; |
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.c b/drivers/net/wireless/ath/ath5k/eeprom.c index a648957501e2..97eaa9a4415e 100644 --- a/drivers/net/wireless/ath/ath5k/eeprom.c +++ b/drivers/net/wireless/ath/ath5k/eeprom.c | |||
@@ -66,40 +66,6 @@ static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin, | |||
66 | \*********/ | 66 | \*********/ |
67 | 67 | ||
68 | /* | 68 | /* |
69 | * Read from eeprom | ||
70 | */ | ||
71 | static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data) | ||
72 | { | ||
73 | u32 status, timeout; | ||
74 | |||
75 | /* | ||
76 | * Initialize EEPROM access | ||
77 | */ | ||
78 | if (ah->ah_version == AR5K_AR5210) { | ||
79 | AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); | ||
80 | (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset)); | ||
81 | } else { | ||
82 | ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE); | ||
83 | AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, | ||
84 | AR5K_EEPROM_CMD_READ); | ||
85 | } | ||
86 | |||
87 | for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { | ||
88 | status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); | ||
89 | if (status & AR5K_EEPROM_STAT_RDDONE) { | ||
90 | if (status & AR5K_EEPROM_STAT_RDERR) | ||
91 | return -EIO; | ||
92 | *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) & | ||
93 | 0xffff); | ||
94 | return 0; | ||
95 | } | ||
96 | udelay(15); | ||
97 | } | ||
98 | |||
99 | return -ETIMEDOUT; | ||
100 | } | ||
101 | |||
102 | /* | ||
103 | * Initialize eeprom & capabilities structs | 69 | * Initialize eeprom & capabilities structs |
104 | */ | 70 | */ |
105 | static int | 71 | static int |
@@ -1769,12 +1735,12 @@ int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac) | |||
1769 | u16 data; | 1735 | u16 data; |
1770 | int octet, ret; | 1736 | int octet, ret; |
1771 | 1737 | ||
1772 | ret = ath5k_hw_eeprom_read(ah, 0x20, &data); | 1738 | ret = ath5k_hw_nvram_read(ah, 0x20, &data); |
1773 | if (ret) | 1739 | if (ret) |
1774 | return ret; | 1740 | return ret; |
1775 | 1741 | ||
1776 | for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { | 1742 | for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { |
1777 | ret = ath5k_hw_eeprom_read(ah, offset, &data); | 1743 | ret = ath5k_hw_nvram_read(ah, offset, &data); |
1778 | if (ret) | 1744 | if (ret) |
1779 | return ret; | 1745 | return ret; |
1780 | 1746 | ||
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.h b/drivers/net/wireless/ath/ath5k/eeprom.h index c4a6d5f26af4..0017006be841 100644 --- a/drivers/net/wireless/ath/ath5k/eeprom.h +++ b/drivers/net/wireless/ath/ath5k/eeprom.h | |||
@@ -241,7 +241,7 @@ enum ath5k_eeprom_freq_bands{ | |||
241 | #define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz 6250 | 241 | #define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz 6250 |
242 | 242 | ||
243 | #define AR5K_EEPROM_READ(_o, _v) do { \ | 243 | #define AR5K_EEPROM_READ(_o, _v) do { \ |
244 | ret = ath5k_hw_eeprom_read(ah, (_o), &(_v)); \ | 244 | ret = ath5k_hw_nvram_read(ah, (_o), &(_v)); \ |
245 | if (ret) \ | 245 | if (ret) \ |
246 | return ret; \ | 246 | return ret; \ |
247 | } while (0) | 247 | } while (0) |
diff --git a/drivers/net/wireless/ath/ath5k/pci.c b/drivers/net/wireless/ath/ath5k/pci.c index 9f7d3ca6ea21..3f26cf200196 100644 --- a/drivers/net/wireless/ath/ath5k/pci.c +++ b/drivers/net/wireless/ath/ath5k/pci.c | |||
@@ -65,10 +65,46 @@ static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz) | |||
65 | *csz = L1_CACHE_BYTES >> 2; /* Use the default size */ | 65 | *csz = L1_CACHE_BYTES >> 2; /* Use the default size */ |
66 | } | 66 | } |
67 | 67 | ||
68 | /* | ||
69 | * Read from eeprom | ||
70 | */ | ||
71 | bool ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data) | ||
72 | { | ||
73 | struct ath5k_hw *ah = (struct ath5k_hw *) common->ah; | ||
74 | u32 status, timeout; | ||
75 | |||
76 | /* | ||
77 | * Initialize EEPROM access | ||
78 | */ | ||
79 | if (ah->ah_version == AR5K_AR5210) { | ||
80 | AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); | ||
81 | (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset)); | ||
82 | } else { | ||
83 | ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE); | ||
84 | AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, | ||
85 | AR5K_EEPROM_CMD_READ); | ||
86 | } | ||
87 | |||
88 | for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { | ||
89 | status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); | ||
90 | if (status & AR5K_EEPROM_STAT_RDDONE) { | ||
91 | if (status & AR5K_EEPROM_STAT_RDERR) | ||
92 | return -EIO; | ||
93 | *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) & | ||
94 | 0xffff); | ||
95 | return 0; | ||
96 | } | ||
97 | udelay(15); | ||
98 | } | ||
99 | |||
100 | return -ETIMEDOUT; | ||
101 | } | ||
102 | |||
68 | /* Common ath_bus_opts structure */ | 103 | /* Common ath_bus_opts structure */ |
69 | static const struct ath_bus_ops ath_pci_bus_ops = { | 104 | static const struct ath_bus_ops ath_pci_bus_ops = { |
70 | .ath_bus_type = ATH_PCI, | 105 | .ath_bus_type = ATH_PCI, |
71 | .read_cachesize = ath5k_pci_read_cachesize, | 106 | .read_cachesize = ath5k_pci_read_cachesize, |
107 | .eeprom_read = ath5k_pci_eeprom_read, | ||
72 | }; | 108 | }; |
73 | 109 | ||
74 | /********************\ | 110 | /********************\ |