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authorLinus Torvalds <torvalds@linux-foundation.org>2012-07-30 15:41:17 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-07-30 15:41:17 -0400
commit3e701cdfe601306817604ca7f79f1d1c1088007c (patch)
tree1b0a4088a091f035d8be06758a604ca449223fc0 /drivers
parent7d3d09b01a028e9dd1282149fdcd2a6e0edd73e4 (diff)
parent3c1534c7ecffeb4330bba4c55d17f301528195b6 (diff)
Merge tag 'mfd-3.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
Pull MFD bits from Samuel Ortiz: "We have support for a few new drivers: - Samsung s2mps11 - Wolfson Microelectronics wm5102 and wm5110 - Marvell 88PM800 and 88PM805 - TI twl6041 We also have our regular driver improvements: - Device tree and IRQ domain support for STE AB8500 - Regmap and devm_* API conversion for TI tps6586x - Device tree support for Samsung max77686 - devm_* API conversion for STE AB3100 Besides that, quite a lot of fixing and cleanup for mc13xxx, tps65910, tps65090, da9052 and twl-core." Fix up mostly trivial conflicts, with the exception of drivers/usb/host/ehci-omap.c in particular, which had some re-organization of the reset sequence (commit 1a49e2ac9651: "EHCI: centralize controller initialization") that clashed with commit 2761a6394516 ("mfd: USB: Fix the omap-usb EHCI ULPI PHY reset fix issues"). In particular, commit 2761a6394516 moved the usb_add_hcd() to the *middle* of the reset sequence, which clashes fairly badly with the reset sequence re-organization (although it could have been done inside the new omap_ehci_init() function). I left that part of commit 2761a6394516 just undone. * tag 'mfd-3.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (110 commits) mfd: Ensure AB8500 platform data is passed through db8500-prcmu to MFD Core mfd: Arizone core should select MFD_CORE mfd: Fix arizona-irq.c build by selecting REGMAP_IRQ mfd: Add debug trace on entering and leaving arizone runtime suspend mfd: Correct tps65090 cell names mfd: Remove gpio support from tps6586x core driver ARM: tegra: defconfig: Enable tps6586x gpio gpio: tps6586x: Add gpio support through platform driver mfd: Cache tps6586x register through regmap mfd: Use regmap for tps6586x register access. mfd: Use devm managed resources for tps6586x input: Add onkey support for 88PM80X PMIC mfd: Add support for twl6041 mfd: Fix twl6040 revision information mfd: Matches should be NULL when populate anatop child devices input: ab8500-ponkey: Create AB8500 domain IRQ mapping mfd: Add missing out of memory check for pcf50633 Documentation: Describe the AB8500 Device Tree bindings mfd: Add tps65910 32-kHz-crystal-input init mfd: Drop modifying mc13xxx driver's id_table in probe ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/extcon/Kconfig2
-rw-r--r--drivers/extcon/extcon-max8997.c29
-rw-r--r--drivers/gpio/Kconfig7
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/gpio-tps6586x.c158
-rw-r--r--drivers/input/misc/88pm80x_onkey.c168
-rw-r--r--drivers/input/misc/Kconfig10
-rw-r--r--drivers/input/misc/Makefile1
-rw-r--r--drivers/input/misc/ab8500-ponkey.c4
-rw-r--r--drivers/mfd/88pm800.c596
-rw-r--r--drivers/mfd/88pm805.c301
-rw-r--r--drivers/mfd/88pm80x.c145
-rw-r--r--drivers/mfd/88pm860x-core.c23
-rw-r--r--drivers/mfd/Kconfig98
-rw-r--r--drivers/mfd/Makefile15
-rw-r--r--drivers/mfd/ab3100-core.c23
-rw-r--r--drivers/mfd/ab8500-core.c242
-rw-r--r--drivers/mfd/ab8500-debugfs.c12
-rw-r--r--drivers/mfd/ab8500-gpadc.c9
-rw-r--r--drivers/mfd/ab8500-sysctrl.c6
-rw-r--r--drivers/mfd/adp5520.c2
-rw-r--r--drivers/mfd/anatop-mfd.c2
-rw-r--r--drivers/mfd/arizona-core.c566
-rw-r--r--drivers/mfd/arizona-i2c.c97
-rw-r--r--drivers/mfd/arizona-irq.c275
-rw-r--r--drivers/mfd/arizona-spi.c97
-rw-r--r--drivers/mfd/arizona.h40
-rw-r--r--drivers/mfd/da9052-core.c1
-rw-r--r--drivers/mfd/db8500-prcmu.c92
-rw-r--r--drivers/mfd/dbx500-prcmu-regs.h1
-rw-r--r--drivers/mfd/max77686-irq.c319
-rw-r--r--drivers/mfd/max77686.c187
-rw-r--r--drivers/mfd/max77693.c11
-rw-r--r--drivers/mfd/max8925-core.c8
-rw-r--r--drivers/mfd/max8997-irq.c62
-rw-r--r--drivers/mfd/max8997.c9
-rw-r--r--drivers/mfd/mc13xxx-core.c4
-rw-r--r--drivers/mfd/mc13xxx-i2c.c12
-rw-r--r--drivers/mfd/mc13xxx-spi.c15
-rw-r--r--drivers/mfd/mfd-core.c30
-rw-r--r--drivers/mfd/pcf50633-core.c9
-rw-r--r--drivers/mfd/s5m-core.c206
-rw-r--r--drivers/mfd/s5m-irq.c495
-rw-r--r--drivers/mfd/sec-core.c216
-rw-r--r--drivers/mfd/sec-irq.c317
-rw-r--r--drivers/mfd/tc3589x.c9
-rw-r--r--drivers/mfd/tps65090.c4
-rw-r--r--drivers/mfd/tps6586x.c296
-rw-r--r--drivers/mfd/tps65910.c23
-rw-r--r--drivers/mfd/twl-core.c3
-rw-r--r--drivers/mfd/twl6040-core.c24
-rw-r--r--drivers/mfd/wm5102-tables.c2399
-rw-r--r--drivers/mfd/wm5110-tables.c2281
-rw-r--r--drivers/mfd/wm8350-core.c354
-rw-r--r--drivers/mfd/wm8350-i2c.c5
-rw-r--r--drivers/mfd/wm8350-irq.c8
-rw-r--r--drivers/mfd/wm8350-regmap.c3222
-rw-r--r--drivers/mfd/wm8994-core.c17
-rw-r--r--drivers/mfd/wm8994-irq.c10
-rw-r--r--drivers/misc/ab8500-pwm.c6
-rw-r--r--drivers/regulator/Kconfig2
-rw-r--r--drivers/regulator/ab8500.c6
-rw-r--r--drivers/regulator/db8500-prcmu.c6
-rw-r--r--drivers/regulator/s5m8767.c72
-rw-r--r--drivers/rtc/Kconfig10
-rw-r--r--drivers/rtc/Makefile1
-rw-r--r--drivers/rtc/rtc-88pm80x.c371
-rw-r--r--drivers/rtc/rtc-max8925.c13
-rw-r--r--drivers/usb/host/ehci-omap.c8
69 files changed, 9293 insertions, 4780 deletions
diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
index 16716356d1fe..e175c8ed4ec4 100644
--- a/drivers/extcon/Kconfig
+++ b/drivers/extcon/Kconfig
@@ -33,7 +33,7 @@ config EXTCON_MAX77693
33 33
34config EXTCON_MAX8997 34config EXTCON_MAX8997
35 tristate "MAX8997 EXTCON Support" 35 tristate "MAX8997 EXTCON Support"
36 depends on MFD_MAX8997 36 depends on MFD_MAX8997 && IRQ_DOMAIN
37 help 37 help
38 If you say yes here you get support for the MUIC device of 38 If you say yes here you get support for the MUIC device of
39 Maxim MAX8997 PMIC. The MAX8997 MUIC is a USB port accessory 39 Maxim MAX8997 PMIC. The MAX8997 MUIC is a USB port accessory
diff --git a/drivers/extcon/extcon-max8997.c b/drivers/extcon/extcon-max8997.c
index a4ed30bd9a41..ef9090a4271d 100644
--- a/drivers/extcon/extcon-max8997.c
+++ b/drivers/extcon/extcon-max8997.c
@@ -26,6 +26,7 @@
26#include <linux/mfd/max8997.h> 26#include <linux/mfd/max8997.h>
27#include <linux/mfd/max8997-private.h> 27#include <linux/mfd/max8997-private.h>
28#include <linux/extcon.h> 28#include <linux/extcon.h>
29#include <linux/irqdomain.h>
29 30
30#define DEV_NAME "max8997-muic" 31#define DEV_NAME "max8997-muic"
31 32
@@ -77,6 +78,7 @@
77struct max8997_muic_irq { 78struct max8997_muic_irq {
78 unsigned int irq; 79 unsigned int irq;
79 const char *name; 80 const char *name;
81 unsigned int virq;
80}; 82};
81 83
82static struct max8997_muic_irq muic_irqs[] = { 84static struct max8997_muic_irq muic_irqs[] = {
@@ -343,12 +345,10 @@ static void max8997_muic_irq_work(struct work_struct *work)
343{ 345{
344 struct max8997_muic_info *info = container_of(work, 346 struct max8997_muic_info *info = container_of(work,
345 struct max8997_muic_info, irq_work); 347 struct max8997_muic_info, irq_work);
346 struct max8997_dev *max8997 = i2c_get_clientdata(info->muic);
347 u8 status[2]; 348 u8 status[2];
348 u8 adc, chg_type; 349 u8 adc, chg_type;
349 350 int irq_type = 0;
350 int irq_type = info->irq - max8997->irq_base; 351 int i, ret;
351 int ret;
352 352
353 mutex_lock(&info->mutex); 353 mutex_lock(&info->mutex);
354 354
@@ -363,6 +363,10 @@ static void max8997_muic_irq_work(struct work_struct *work)
363 dev_dbg(info->dev, "%s: STATUS1:0x%x, 2:0x%x\n", __func__, 363 dev_dbg(info->dev, "%s: STATUS1:0x%x, 2:0x%x\n", __func__,
364 status[0], status[1]); 364 status[0], status[1]);
365 365
366 for (i = 0 ; i < ARRAY_SIZE(muic_irqs) ; i++)
367 if (info->irq == muic_irqs[i].virq)
368 irq_type = muic_irqs[i].irq;
369
366 switch (irq_type) { 370 switch (irq_type) {
367 case MAX8997_MUICIRQ_ADC: 371 case MAX8997_MUICIRQ_ADC:
368 adc = status[0] & STATUS1_ADC_MASK; 372 adc = status[0] & STATUS1_ADC_MASK;
@@ -448,11 +452,15 @@ static int __devinit max8997_muic_probe(struct platform_device *pdev)
448 452
449 for (i = 0; i < ARRAY_SIZE(muic_irqs); i++) { 453 for (i = 0; i < ARRAY_SIZE(muic_irqs); i++) {
450 struct max8997_muic_irq *muic_irq = &muic_irqs[i]; 454 struct max8997_muic_irq *muic_irq = &muic_irqs[i];
455 int virq = 0;
456
457 virq = irq_create_mapping(max8997->irq_domain, muic_irq->irq);
458 if (!virq)
459 goto err_irq;
460 muic_irq->virq = virq;
451 461
452 ret = request_threaded_irq(pdata->irq_base + muic_irq->irq, 462 ret = request_threaded_irq(virq, NULL,max8997_muic_irq_handler,
453 NULL, max8997_muic_irq_handler, 463 0, muic_irq->name, info);
454 0, muic_irq->name,
455 info);
456 if (ret) { 464 if (ret) {
457 dev_err(&pdev->dev, 465 dev_err(&pdev->dev,
458 "failed: irq request (IRQ: %d," 466 "failed: irq request (IRQ: %d,"
@@ -496,7 +504,7 @@ err_extcon:
496 kfree(info->edev); 504 kfree(info->edev);
497err_irq: 505err_irq:
498 while (--i >= 0) 506 while (--i >= 0)
499 free_irq(pdata->irq_base + muic_irqs[i].irq, info); 507 free_irq(muic_irqs[i].virq, info);
500 kfree(info); 508 kfree(info);
501err_kfree: 509err_kfree:
502 return ret; 510 return ret;
@@ -505,11 +513,10 @@ err_kfree:
505static int __devexit max8997_muic_remove(struct platform_device *pdev) 513static int __devexit max8997_muic_remove(struct platform_device *pdev)
506{ 514{
507 struct max8997_muic_info *info = platform_get_drvdata(pdev); 515 struct max8997_muic_info *info = platform_get_drvdata(pdev);
508 struct max8997_dev *max8997 = i2c_get_clientdata(info->muic);
509 int i; 516 int i;
510 517
511 for (i = 0; i < ARRAY_SIZE(muic_irqs); i++) 518 for (i = 0; i < ARRAY_SIZE(muic_irqs); i++)
512 free_irq(max8997->irq_base + muic_irqs[i].irq, info); 519 free_irq(muic_irqs[i].virq, info);
513 cancel_work_sync(&info->irq_work); 520 cancel_work_sync(&info->irq_work);
514 521
515 extcon_dev_unregister(info->edev); 522 extcon_dev_unregister(info->edev);
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 502b5ea43f4f..b16c8a72a2e2 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -597,6 +597,13 @@ config GPIO_AB8500
597 help 597 help
598 Select this to enable the AB8500 IC GPIO driver 598 Select this to enable the AB8500 IC GPIO driver
599 599
600config GPIO_TPS6586X
601 bool "TPS6586X GPIO"
602 depends on MFD_TPS6586X
603 help
604 Select this option to enable GPIO driver for the TPS6586X
605 chip family.
606
600config GPIO_TPS65910 607config GPIO_TPS65910
601 bool "TPS65910 GPIO" 608 bool "TPS65910 GPIO"
602 depends on MFD_TPS65910 609 depends on MFD_TPS65910
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index d37048105a87..153caceeb053 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o
63obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o 63obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o
64obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o 64obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o
65obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += gpio-tnetv107x.o 65obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += gpio-tnetv107x.o
66obj-$(CONFIG_GPIO_TPS6586X) += gpio-tps6586x.o
66obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o 67obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o
67obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o 68obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o
68obj-$(CONFIG_GPIO_TWL4030) += gpio-twl4030.o 69obj-$(CONFIG_GPIO_TWL4030) += gpio-twl4030.o
diff --git a/drivers/gpio/gpio-tps6586x.c b/drivers/gpio/gpio-tps6586x.c
new file mode 100644
index 000000000000..2526b3bb0fae
--- /dev/null
+++ b/drivers/gpio/gpio-tps6586x.c
@@ -0,0 +1,158 @@
1/*
2 * TI TPS6586x GPIO driver
3 *
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * Author: Laxman dewangan <ldewangan@nvidia.com>
6 *
7 * Based on tps6586x.c
8 * Copyright (c) 2010 CompuLab Ltd.
9 * Mike Rapoport <mike@compulab.co.il>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 */
23
24#include <linux/errno.h>
25#include <linux/gpio.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/mfd/tps6586x.h>
29#include <linux/of_device.h>
30#include <linux/platform_device.h>
31
32/* GPIO control registers */
33#define TPS6586X_GPIOSET1 0x5d
34#define TPS6586X_GPIOSET2 0x5e
35
36struct tps6586x_gpio {
37 struct gpio_chip gpio_chip;
38 struct device *parent;
39};
40
41static inline struct tps6586x_gpio *to_tps6586x_gpio(struct gpio_chip *chip)
42{
43 return container_of(chip, struct tps6586x_gpio, gpio_chip);
44}
45
46static int tps6586x_gpio_get(struct gpio_chip *gc, unsigned offset)
47{
48 struct tps6586x_gpio *tps6586x_gpio = to_tps6586x_gpio(gc);
49 uint8_t val;
50 int ret;
51
52 ret = tps6586x_read(tps6586x_gpio->parent, TPS6586X_GPIOSET2, &val);
53 if (ret)
54 return ret;
55
56 return !!(val & (1 << offset));
57}
58
59static void tps6586x_gpio_set(struct gpio_chip *gc, unsigned offset,
60 int value)
61{
62 struct tps6586x_gpio *tps6586x_gpio = to_tps6586x_gpio(gc);
63
64 tps6586x_update(tps6586x_gpio->parent, TPS6586X_GPIOSET2,
65 value << offset, 1 << offset);
66}
67
68static int tps6586x_gpio_output(struct gpio_chip *gc, unsigned offset,
69 int value)
70{
71 struct tps6586x_gpio *tps6586x_gpio = to_tps6586x_gpio(gc);
72 uint8_t val, mask;
73
74 tps6586x_gpio_set(gc, offset, value);
75
76 val = 0x1 << (offset * 2);
77 mask = 0x3 << (offset * 2);
78
79 return tps6586x_update(tps6586x_gpio->parent, TPS6586X_GPIOSET1,
80 val, mask);
81}
82
83static int __devinit tps6586x_gpio_probe(struct platform_device *pdev)
84{
85 struct tps6586x_platform_data *pdata;
86 struct tps6586x_gpio *tps6586x_gpio;
87 int ret;
88
89 pdata = dev_get_platdata(pdev->dev.parent);
90 tps6586x_gpio = devm_kzalloc(&pdev->dev,
91 sizeof(*tps6586x_gpio), GFP_KERNEL);
92 if (!tps6586x_gpio) {
93 dev_err(&pdev->dev, "Could not allocate tps6586x_gpio\n");
94 return -ENOMEM;
95 }
96
97 tps6586x_gpio->parent = pdev->dev.parent;
98
99 tps6586x_gpio->gpio_chip.owner = THIS_MODULE;
100 tps6586x_gpio->gpio_chip.label = pdev->name;
101 tps6586x_gpio->gpio_chip.dev = &pdev->dev;
102 tps6586x_gpio->gpio_chip.ngpio = 4;
103 tps6586x_gpio->gpio_chip.can_sleep = 1;
104
105 /* FIXME: add handling of GPIOs as dedicated inputs */
106 tps6586x_gpio->gpio_chip.direction_output = tps6586x_gpio_output;
107 tps6586x_gpio->gpio_chip.set = tps6586x_gpio_set;
108 tps6586x_gpio->gpio_chip.get = tps6586x_gpio_get;
109
110#ifdef CONFIG_OF_GPIO
111 tps6586x_gpio->gpio_chip.of_node = pdev->dev.parent->of_node;
112#endif
113 if (pdata && pdata->gpio_base)
114 tps6586x_gpio->gpio_chip.base = pdata->gpio_base;
115 else
116 tps6586x_gpio->gpio_chip.base = -1;
117
118 ret = gpiochip_add(&tps6586x_gpio->gpio_chip);
119 if (ret < 0) {
120 dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
121 return ret;
122 }
123
124 platform_set_drvdata(pdev, tps6586x_gpio);
125
126 return ret;
127}
128
129static int __devexit tps6586x_gpio_remove(struct platform_device *pdev)
130{
131 struct tps6586x_gpio *tps6586x_gpio = platform_get_drvdata(pdev);
132
133 return gpiochip_remove(&tps6586x_gpio->gpio_chip);
134}
135
136static struct platform_driver tps6586x_gpio_driver = {
137 .driver.name = "tps6586x-gpio",
138 .driver.owner = THIS_MODULE,
139 .probe = tps6586x_gpio_probe,
140 .remove = __devexit_p(tps6586x_gpio_remove),
141};
142
143static int __init tps6586x_gpio_init(void)
144{
145 return platform_driver_register(&tps6586x_gpio_driver);
146}
147subsys_initcall(tps6586x_gpio_init);
148
149static void __exit tps6586x_gpio_exit(void)
150{
151 platform_driver_unregister(&tps6586x_gpio_driver);
152}
153module_exit(tps6586x_gpio_exit);
154
155MODULE_ALIAS("platform:tps6586x-gpio");
156MODULE_DESCRIPTION("GPIO interface for TPS6586X PMIC");
157MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
158MODULE_LICENSE("GPL");
diff --git a/drivers/input/misc/88pm80x_onkey.c b/drivers/input/misc/88pm80x_onkey.c
new file mode 100644
index 000000000000..7f26e7b6c228
--- /dev/null
+++ b/drivers/input/misc/88pm80x_onkey.c
@@ -0,0 +1,168 @@
1/*
2 * Marvell 88PM80x ONKEY driver
3 *
4 * Copyright (C) 2012 Marvell International Ltd.
5 * Haojian Zhuang <haojian.zhuang@marvell.com>
6 * Qiao Zhou <zhouqiao@marvell.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file "COPYING" in the main directory of this
10 * archive for more details.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/input.h>
25#include <linux/mfd/88pm80x.h>
26#include <linux/regmap.h>
27#include <linux/slab.h>
28
29#define PM800_LONG_ONKEY_EN (1 << 0)
30#define PM800_LONG_KEY_DELAY (8) /* 1 .. 16 seconds */
31#define PM800_LONKEY_PRESS_TIME ((PM800_LONG_KEY_DELAY-1) << 4)
32#define PM800_LONKEY_PRESS_TIME_MASK (0xF0)
33#define PM800_SW_PDOWN (1 << 5)
34
35struct pm80x_onkey_info {
36 struct input_dev *idev;
37 struct pm80x_chip *pm80x;
38 struct regmap *map;
39 int irq;
40};
41
42/* 88PM80x gives us an interrupt when ONKEY is held */
43static irqreturn_t pm80x_onkey_handler(int irq, void *data)
44{
45 struct pm80x_onkey_info *info = data;
46 int ret = 0;
47 unsigned int val;
48
49 ret = regmap_read(info->map, PM800_STATUS_1, &val);
50 if (ret < 0) {
51 dev_err(info->idev->dev.parent, "failed to read status: %d\n", ret);
52 return IRQ_NONE;
53 }
54 val &= PM800_ONKEY_STS1;
55
56 input_report_key(info->idev, KEY_POWER, val);
57 input_sync(info->idev);
58
59 return IRQ_HANDLED;
60}
61
62static SIMPLE_DEV_PM_OPS(pm80x_onkey_pm_ops, pm80x_dev_suspend,
63 pm80x_dev_resume);
64
65static int __devinit pm80x_onkey_probe(struct platform_device *pdev)
66{
67
68 struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
69 struct pm80x_onkey_info *info;
70 int err;
71
72 info = kzalloc(sizeof(struct pm80x_onkey_info), GFP_KERNEL);
73 if (!info)
74 return -ENOMEM;
75
76 info->pm80x = chip;
77
78 info->irq = platform_get_irq(pdev, 0);
79 if (info->irq < 0) {
80 dev_err(&pdev->dev, "No IRQ resource!\n");
81 err = -EINVAL;
82 goto out;
83 }
84
85 info->map = info->pm80x->regmap;
86 if (!info->map) {
87 dev_err(&pdev->dev, "no regmap!\n");
88 err = -EINVAL;
89 goto out;
90 }
91
92 info->idev = input_allocate_device();
93 if (!info->idev) {
94 dev_err(&pdev->dev, "Failed to allocate input dev\n");
95 err = -ENOMEM;
96 goto out;
97 }
98
99 info->idev->name = "88pm80x_on";
100 info->idev->phys = "88pm80x_on/input0";
101 info->idev->id.bustype = BUS_I2C;
102 info->idev->dev.parent = &pdev->dev;
103 info->idev->evbit[0] = BIT_MASK(EV_KEY);
104 __set_bit(KEY_POWER, info->idev->keybit);
105
106 err = pm80x_request_irq(info->pm80x, info->irq, pm80x_onkey_handler,
107 IRQF_ONESHOT, "onkey", info);
108 if (err < 0) {
109 dev_err(&pdev->dev, "Failed to request IRQ: #%d: %d\n",
110 info->irq, err);
111 goto out_reg;
112 }
113
114 err = input_register_device(info->idev);
115 if (err) {
116 dev_err(&pdev->dev, "Can't register input device: %d\n", err);
117 goto out_irq;
118 }
119
120 platform_set_drvdata(pdev, info);
121
122 /* Enable long onkey detection */
123 regmap_update_bits(info->map, PM800_RTC_MISC4, PM800_LONG_ONKEY_EN,
124 PM800_LONG_ONKEY_EN);
125 /* Set 8-second interval */
126 regmap_update_bits(info->map, PM800_RTC_MISC3,
127 PM800_LONKEY_PRESS_TIME_MASK,
128 PM800_LONKEY_PRESS_TIME);
129
130 device_init_wakeup(&pdev->dev, 1);
131 return 0;
132
133out_irq:
134 pm80x_free_irq(info->pm80x, info->irq, info);
135out_reg:
136 input_free_device(info->idev);
137out:
138 kfree(info);
139 return err;
140}
141
142static int __devexit pm80x_onkey_remove(struct platform_device *pdev)
143{
144 struct pm80x_onkey_info *info = platform_get_drvdata(pdev);
145
146 device_init_wakeup(&pdev->dev, 0);
147 pm80x_free_irq(info->pm80x, info->irq, info);
148 input_unregister_device(info->idev);
149 kfree(info);
150 return 0;
151}
152
153static struct platform_driver pm80x_onkey_driver = {
154 .driver = {
155 .name = "88pm80x-onkey",
156 .owner = THIS_MODULE,
157 .pm = &pm80x_onkey_pm_ops,
158 },
159 .probe = pm80x_onkey_probe,
160 .remove = __devexit_p(pm80x_onkey_remove),
161};
162
163module_platform_driver(pm80x_onkey_driver);
164
165MODULE_LICENSE("GPL");
166MODULE_DESCRIPTION("Marvell 88PM80x ONKEY driver");
167MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
168MODULE_ALIAS("platform:88pm80x-onkey");
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 7faf4a7fcaa9..7c0f1ecfdd7a 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -22,6 +22,16 @@ config INPUT_88PM860X_ONKEY
22 To compile this driver as a module, choose M here: the module 22 To compile this driver as a module, choose M here: the module
23 will be called 88pm860x_onkey. 23 will be called 88pm860x_onkey.
24 24
25config INPUT_88PM80X_ONKEY
26 tristate "88PM80x ONKEY support"
27 depends on MFD_88PM800
28 help
29 Support the ONKEY of Marvell 88PM80x PMICs as an input device
30 reporting power button status.
31
32 To compile this driver as a module, choose M here: the module
33 will be called 88pm80x_onkey.
34
25config INPUT_AB8500_PONKEY 35config INPUT_AB8500_PONKEY
26 tristate "AB8500 Pon (PowerOn) Key" 36 tristate "AB8500 Pon (PowerOn) Key"
27 depends on AB8500_CORE 37 depends on AB8500_CORE
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index f55cdf4916fa..83fe6f5b77d1 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -5,6 +5,7 @@
5# Each configuration option enables a list of files. 5# Each configuration option enables a list of files.
6 6
7obj-$(CONFIG_INPUT_88PM860X_ONKEY) += 88pm860x_onkey.o 7obj-$(CONFIG_INPUT_88PM860X_ONKEY) += 88pm860x_onkey.o
8obj-$(CONFIG_INPUT_88PM80X_ONKEY) += 88pm80x_onkey.o
8obj-$(CONFIG_INPUT_AB8500_PONKEY) += ab8500-ponkey.o 9obj-$(CONFIG_INPUT_AB8500_PONKEY) += ab8500-ponkey.o
9obj-$(CONFIG_INPUT_AD714X) += ad714x.o 10obj-$(CONFIG_INPUT_AD714X) += ad714x.o
10obj-$(CONFIG_INPUT_AD714X_I2C) += ad714x-i2c.o 11obj-$(CONFIG_INPUT_AD714X_I2C) += ad714x-i2c.o
diff --git a/drivers/input/misc/ab8500-ponkey.c b/drivers/input/misc/ab8500-ponkey.c
index 84ec691c05aa..f06231b7cab1 100644
--- a/drivers/input/misc/ab8500-ponkey.c
+++ b/drivers/input/misc/ab8500-ponkey.c
@@ -74,8 +74,8 @@ static int __devinit ab8500_ponkey_probe(struct platform_device *pdev)
74 74
75 ponkey->idev = input; 75 ponkey->idev = input;
76 ponkey->ab8500 = ab8500; 76 ponkey->ab8500 = ab8500;
77 ponkey->irq_dbf = irq_dbf; 77 ponkey->irq_dbf = ab8500_irq_get_virq(ab8500, irq_dbf);
78 ponkey->irq_dbr = irq_dbr; 78 ponkey->irq_dbr = ab8500_irq_get_virq(ab8500, irq_dbr);
79 79
80 input->name = "AB8500 POn(PowerOn) Key"; 80 input->name = "AB8500 POn(PowerOn) Key";
81 input->dev.parent = &pdev->dev; 81 input->dev.parent = &pdev->dev;
diff --git a/drivers/mfd/88pm800.c b/drivers/mfd/88pm800.c
new file mode 100644
index 000000000000..b67a3018b136
--- /dev/null
+++ b/drivers/mfd/88pm800.c
@@ -0,0 +1,596 @@
1/*
2 * Base driver for Marvell 88PM800
3 *
4 * Copyright (C) 2012 Marvell International Ltd.
5 * Haojian Zhuang <haojian.zhuang@marvell.com>
6 * Joseph(Yossi) Hanin <yhanin@marvell.com>
7 * Qiao Zhou <zhouqiao@marvell.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file "COPYING" in the main directory of this
11 * archive for more details.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/i2c.h>
26#include <linux/mfd/core.h>
27#include <linux/mfd/88pm80x.h>
28#include <linux/slab.h>
29
30#define PM800_CHIP_ID (0x00)
31
32/* Interrupt Registers */
33#define PM800_INT_STATUS1 (0x05)
34#define PM800_ONKEY_INT_STS1 (1 << 0)
35#define PM800_EXTON_INT_STS1 (1 << 1)
36#define PM800_CHG_INT_STS1 (1 << 2)
37#define PM800_BAT_INT_STS1 (1 << 3)
38#define PM800_RTC_INT_STS1 (1 << 4)
39#define PM800_CLASSD_OC_INT_STS1 (1 << 5)
40
41#define PM800_INT_STATUS2 (0x06)
42#define PM800_VBAT_INT_STS2 (1 << 0)
43#define PM800_VSYS_INT_STS2 (1 << 1)
44#define PM800_VCHG_INT_STS2 (1 << 2)
45#define PM800_TINT_INT_STS2 (1 << 3)
46#define PM800_GPADC0_INT_STS2 (1 << 4)
47#define PM800_TBAT_INT_STS2 (1 << 5)
48#define PM800_GPADC2_INT_STS2 (1 << 6)
49#define PM800_GPADC3_INT_STS2 (1 << 7)
50
51#define PM800_INT_STATUS3 (0x07)
52
53#define PM800_INT_STATUS4 (0x08)
54#define PM800_GPIO0_INT_STS4 (1 << 0)
55#define PM800_GPIO1_INT_STS4 (1 << 1)
56#define PM800_GPIO2_INT_STS4 (1 << 2)
57#define PM800_GPIO3_INT_STS4 (1 << 3)
58#define PM800_GPIO4_INT_STS4 (1 << 4)
59
60#define PM800_INT_ENA_1 (0x09)
61#define PM800_ONKEY_INT_ENA1 (1 << 0)
62#define PM800_EXTON_INT_ENA1 (1 << 1)
63#define PM800_CHG_INT_ENA1 (1 << 2)
64#define PM800_BAT_INT_ENA1 (1 << 3)
65#define PM800_RTC_INT_ENA1 (1 << 4)
66#define PM800_CLASSD_OC_INT_ENA1 (1 << 5)
67
68#define PM800_INT_ENA_2 (0x0A)
69#define PM800_VBAT_INT_ENA2 (1 << 0)
70#define PM800_VSYS_INT_ENA2 (1 << 1)
71#define PM800_VCHG_INT_ENA2 (1 << 2)
72#define PM800_TINT_INT_ENA2 (1 << 3)
73
74#define PM800_INT_ENA_3 (0x0B)
75#define PM800_GPADC0_INT_ENA3 (1 << 0)
76#define PM800_GPADC1_INT_ENA3 (1 << 1)
77#define PM800_GPADC2_INT_ENA3 (1 << 2)
78#define PM800_GPADC3_INT_ENA3 (1 << 3)
79#define PM800_GPADC4_INT_ENA3 (1 << 4)
80
81#define PM800_INT_ENA_4 (0x0C)
82#define PM800_GPIO0_INT_ENA4 (1 << 0)
83#define PM800_GPIO1_INT_ENA4 (1 << 1)
84#define PM800_GPIO2_INT_ENA4 (1 << 2)
85#define PM800_GPIO3_INT_ENA4 (1 << 3)
86#define PM800_GPIO4_INT_ENA4 (1 << 4)
87
88/* number of INT_ENA & INT_STATUS regs */
89#define PM800_INT_REG_NUM (4)
90
91/* Interrupt Number in 88PM800 */
92enum {
93 PM800_IRQ_ONKEY, /*EN1b0 *//*0 */
94 PM800_IRQ_EXTON, /*EN1b1 */
95 PM800_IRQ_CHG, /*EN1b2 */
96 PM800_IRQ_BAT, /*EN1b3 */
97 PM800_IRQ_RTC, /*EN1b4 */
98 PM800_IRQ_CLASSD, /*EN1b5 *//*5 */
99 PM800_IRQ_VBAT, /*EN2b0 */
100 PM800_IRQ_VSYS, /*EN2b1 */
101 PM800_IRQ_VCHG, /*EN2b2 */
102 PM800_IRQ_TINT, /*EN2b3 */
103 PM800_IRQ_GPADC0, /*EN3b0 *//*10 */
104 PM800_IRQ_GPADC1, /*EN3b1 */
105 PM800_IRQ_GPADC2, /*EN3b2 */
106 PM800_IRQ_GPADC3, /*EN3b3 */
107 PM800_IRQ_GPADC4, /*EN3b4 */
108 PM800_IRQ_GPIO0, /*EN4b0 *//*15 */
109 PM800_IRQ_GPIO1, /*EN4b1 */
110 PM800_IRQ_GPIO2, /*EN4b2 */
111 PM800_IRQ_GPIO3, /*EN4b3 */
112 PM800_IRQ_GPIO4, /*EN4b4 *//*19 */
113 PM800_MAX_IRQ,
114};
115
116enum {
117 /* Procida */
118 PM800_CHIP_A0 = 0x60,
119 PM800_CHIP_A1 = 0x61,
120 PM800_CHIP_B0 = 0x62,
121 PM800_CHIP_C0 = 0x63,
122 PM800_CHIP_END = PM800_CHIP_C0,
123
124 /* Make sure to update this to the last stepping */
125 PM8XXX_CHIP_END = PM800_CHIP_END
126};
127
128static const struct i2c_device_id pm80x_id_table[] = {
129 {"88PM800", CHIP_PM800},
130 {} /* NULL terminated */
131};
132MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
133
134static struct resource rtc_resources[] = {
135 {
136 .name = "88pm80x-rtc",
137 .start = PM800_IRQ_RTC,
138 .end = PM800_IRQ_RTC,
139 .flags = IORESOURCE_IRQ,
140 },
141};
142
143static struct mfd_cell rtc_devs[] = {
144 {
145 .name = "88pm80x-rtc",
146 .num_resources = ARRAY_SIZE(rtc_resources),
147 .resources = &rtc_resources[0],
148 .id = -1,
149 },
150};
151
152static struct resource onkey_resources[] = {
153 {
154 .name = "88pm80x-onkey",
155 .start = PM800_IRQ_ONKEY,
156 .end = PM800_IRQ_ONKEY,
157 .flags = IORESOURCE_IRQ,
158 },
159};
160
161static struct mfd_cell onkey_devs[] = {
162 {
163 .name = "88pm80x-onkey",
164 .num_resources = 1,
165 .resources = &onkey_resources[0],
166 .id = -1,
167 },
168};
169
170static const struct regmap_irq pm800_irqs[] = {
171 /* INT0 */
172 [PM800_IRQ_ONKEY] = {
173 .mask = PM800_ONKEY_INT_ENA1,
174 },
175 [PM800_IRQ_EXTON] = {
176 .mask = PM800_EXTON_INT_ENA1,
177 },
178 [PM800_IRQ_CHG] = {
179 .mask = PM800_CHG_INT_ENA1,
180 },
181 [PM800_IRQ_BAT] = {
182 .mask = PM800_BAT_INT_ENA1,
183 },
184 [PM800_IRQ_RTC] = {
185 .mask = PM800_RTC_INT_ENA1,
186 },
187 [PM800_IRQ_CLASSD] = {
188 .mask = PM800_CLASSD_OC_INT_ENA1,
189 },
190 /* INT1 */
191 [PM800_IRQ_VBAT] = {
192 .reg_offset = 1,
193 .mask = PM800_VBAT_INT_ENA2,
194 },
195 [PM800_IRQ_VSYS] = {
196 .reg_offset = 1,
197 .mask = PM800_VSYS_INT_ENA2,
198 },
199 [PM800_IRQ_VCHG] = {
200 .reg_offset = 1,
201 .mask = PM800_VCHG_INT_ENA2,
202 },
203 [PM800_IRQ_TINT] = {
204 .reg_offset = 1,
205 .mask = PM800_TINT_INT_ENA2,
206 },
207 /* INT2 */
208 [PM800_IRQ_GPADC0] = {
209 .reg_offset = 2,
210 .mask = PM800_GPADC0_INT_ENA3,
211 },
212 [PM800_IRQ_GPADC1] = {
213 .reg_offset = 2,
214 .mask = PM800_GPADC1_INT_ENA3,
215 },
216 [PM800_IRQ_GPADC2] = {
217 .reg_offset = 2,
218 .mask = PM800_GPADC2_INT_ENA3,
219 },
220 [PM800_IRQ_GPADC3] = {
221 .reg_offset = 2,
222 .mask = PM800_GPADC3_INT_ENA3,
223 },
224 [PM800_IRQ_GPADC4] = {
225 .reg_offset = 2,
226 .mask = PM800_GPADC4_INT_ENA3,
227 },
228 /* INT3 */
229 [PM800_IRQ_GPIO0] = {
230 .reg_offset = 3,
231 .mask = PM800_GPIO0_INT_ENA4,
232 },
233 [PM800_IRQ_GPIO1] = {
234 .reg_offset = 3,
235 .mask = PM800_GPIO1_INT_ENA4,
236 },
237 [PM800_IRQ_GPIO2] = {
238 .reg_offset = 3,
239 .mask = PM800_GPIO2_INT_ENA4,
240 },
241 [PM800_IRQ_GPIO3] = {
242 .reg_offset = 3,
243 .mask = PM800_GPIO3_INT_ENA4,
244 },
245 [PM800_IRQ_GPIO4] = {
246 .reg_offset = 3,
247 .mask = PM800_GPIO4_INT_ENA4,
248 },
249};
250
251static int __devinit device_gpadc_init(struct pm80x_chip *chip,
252 struct pm80x_platform_data *pdata)
253{
254 struct pm80x_subchip *subchip = chip->subchip;
255 struct regmap *map = subchip->regmap_gpadc;
256 int data = 0, mask = 0, ret = 0;
257
258 if (!map) {
259 dev_warn(chip->dev,
260 "Warning: gpadc regmap is not available!\n");
261 return -EINVAL;
262 }
263 /*
264 * initialize GPADC without activating it turn on GPADC
265 * measurments
266 */
267 ret = regmap_update_bits(map,
268 PM800_GPADC_MISC_CONFIG2,
269 PM800_GPADC_MISC_GPFSM_EN,
270 PM800_GPADC_MISC_GPFSM_EN);
271 if (ret < 0)
272 goto out;
273 /*
274 * This function configures the ADC as requires for
275 * CP implementation.CP does not "own" the ADC configuration
276 * registers and relies on AP.
277 * Reason: enable automatic ADC measurements needed
278 * for CP to get VBAT and RF temperature readings.
279 */
280 ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN1,
281 PM800_MEAS_EN1_VBAT, PM800_MEAS_EN1_VBAT);
282 if (ret < 0)
283 goto out;
284 ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN2,
285 (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN),
286 (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN));
287 if (ret < 0)
288 goto out;
289
290 /*
291 * the defult of PM800 is GPADC operates at 100Ks/s rate
292 * and Number of GPADC slots with active current bias prior
293 * to GPADC sampling = 1 slot for all GPADCs set for
294 * Temprature mesurmants
295 */
296 mask = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
297 PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
298
299 if (pdata && (pdata->batt_det == 0))
300 data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
301 PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
302 else
303 data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN2 |
304 PM800_GPADC_GP_BIAS_EN3);
305
306 ret = regmap_update_bits(map, PM800_GP_BIAS_ENA1, mask, data);
307 if (ret < 0)
308 goto out;
309
310 dev_info(chip->dev, "pm800 device_gpadc_init: Done\n");
311 return 0;
312
313out:
314 dev_info(chip->dev, "pm800 device_gpadc_init: Failed!\n");
315 return ret;
316}
317
318static int __devinit device_irq_init_800(struct pm80x_chip *chip)
319{
320 struct regmap *map = chip->regmap;
321 unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
322 int data, mask, ret = -EINVAL;
323
324 if (!map || !chip->irq) {
325 dev_err(chip->dev, "incorrect parameters\n");
326 return -EINVAL;
327 }
328
329 /*
330 * irq_mode defines the way of clearing interrupt. it's read-clear by
331 * default.
332 */
333 mask =
334 PM800_WAKEUP2_INV_INT | PM800_WAKEUP2_INT_CLEAR |
335 PM800_WAKEUP2_INT_MASK;
336
337 data = PM800_WAKEUP2_INT_CLEAR;
338 ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data);
339
340 if (ret < 0)
341 goto out;
342
343 ret =
344 regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
345 chip->regmap_irq_chip, &chip->irq_data);
346
347out:
348 return ret;
349}
350
351static void device_irq_exit_800(struct pm80x_chip *chip)
352{
353 regmap_del_irq_chip(chip->irq, chip->irq_data);
354}
355
356static struct regmap_irq_chip pm800_irq_chip = {
357 .name = "88pm800",
358 .irqs = pm800_irqs,
359 .num_irqs = ARRAY_SIZE(pm800_irqs),
360
361 .num_regs = 4,
362 .status_base = PM800_INT_STATUS1,
363 .mask_base = PM800_INT_ENA_1,
364 .ack_base = PM800_INT_STATUS1,
365};
366
367static int pm800_pages_init(struct pm80x_chip *chip)
368{
369 struct pm80x_subchip *subchip;
370 struct i2c_client *client = chip->client;
371
372 subchip = chip->subchip;
373 /* PM800 block power: i2c addr 0x31 */
374 if (subchip->power_page_addr) {
375 subchip->power_page =
376 i2c_new_dummy(client->adapter, subchip->power_page_addr);
377 subchip->regmap_power =
378 devm_regmap_init_i2c(subchip->power_page,
379 &pm80x_regmap_config);
380 i2c_set_clientdata(subchip->power_page, chip);
381 } else
382 dev_info(chip->dev,
383 "PM800 block power 0x31: No power_page_addr\n");
384
385 /* PM800 block GPADC: i2c addr 0x32 */
386 if (subchip->gpadc_page_addr) {
387 subchip->gpadc_page = i2c_new_dummy(client->adapter,
388 subchip->gpadc_page_addr);
389 subchip->regmap_gpadc =
390 devm_regmap_init_i2c(subchip->gpadc_page,
391 &pm80x_regmap_config);
392 i2c_set_clientdata(subchip->gpadc_page, chip);
393 } else
394 dev_info(chip->dev,
395 "PM800 block GPADC 0x32: No gpadc_page_addr\n");
396
397 return 0;
398}
399
400static void pm800_pages_exit(struct pm80x_chip *chip)
401{
402 struct pm80x_subchip *subchip;
403
404 regmap_exit(chip->regmap);
405 i2c_unregister_device(chip->client);
406
407 subchip = chip->subchip;
408 if (subchip->power_page) {
409 regmap_exit(subchip->regmap_power);
410 i2c_unregister_device(subchip->power_page);
411 }
412 if (subchip->gpadc_page) {
413 regmap_exit(subchip->regmap_gpadc);
414 i2c_unregister_device(subchip->gpadc_page);
415 }
416}
417
418static int __devinit device_800_init(struct pm80x_chip *chip,
419 struct pm80x_platform_data *pdata)
420{
421 int ret, pmic_id;
422 unsigned int val;
423
424 ret = regmap_read(chip->regmap, PM800_CHIP_ID, &val);
425 if (ret < 0) {
426 dev_err(chip->dev, "Failed to read CHIP ID: %d\n", ret);
427 goto out;
428 }
429
430 pmic_id = val & PM80X_VERSION_MASK;
431
432 if ((pmic_id >= PM800_CHIP_A0) && (pmic_id <= PM800_CHIP_END)) {
433 chip->version = val;
434 dev_info(chip->dev,
435 "88PM80x:Marvell 88PM800 (ID:0x%x) detected\n", val);
436 } else {
437 dev_err(chip->dev,
438 "Failed to detect Marvell 88PM800:ChipID[0x%x]\n", val);
439 ret = -EINVAL;
440 goto out;
441 }
442
443 /*
444 * alarm wake up bit will be clear in device_irq_init(),
445 * read before that
446 */
447 ret = regmap_read(chip->regmap, PM800_RTC_CONTROL, &val);
448 if (ret < 0) {
449 dev_err(chip->dev, "Failed to read RTC register: %d\n", ret);
450 goto out;
451 }
452 if (val & PM800_ALARM_WAKEUP) {
453 if (pdata && pdata->rtc)
454 pdata->rtc->rtc_wakeup = 1;
455 }
456
457 ret = device_gpadc_init(chip, pdata);
458 if (ret < 0) {
459 dev_err(chip->dev, "[%s]Failed to init gpadc\n", __func__);
460 goto out;
461 }
462
463 chip->regmap_irq_chip = &pm800_irq_chip;
464
465 ret = device_irq_init_800(chip);
466 if (ret < 0) {
467 dev_err(chip->dev, "[%s]Failed to init pm800 irq\n", __func__);
468 goto out;
469 }
470
471 ret =
472 mfd_add_devices(chip->dev, 0, &onkey_devs[0],
473 ARRAY_SIZE(onkey_devs), &onkey_resources[0], 0);
474 if (ret < 0) {
475 dev_err(chip->dev, "Failed to add onkey subdev\n");
476 goto out_dev;
477 } else
478 dev_info(chip->dev, "[%s]:Added mfd onkey_devs\n", __func__);
479
480 if (pdata && pdata->rtc) {
481 rtc_devs[0].platform_data = pdata->rtc;
482 rtc_devs[0].pdata_size = sizeof(struct pm80x_rtc_pdata);
483 ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
484 ARRAY_SIZE(rtc_devs), NULL, 0);
485 if (ret < 0) {
486 dev_err(chip->dev, "Failed to add rtc subdev\n");
487 goto out_dev;
488 } else
489 dev_info(chip->dev,
490 "[%s]:Added mfd rtc_devs\n", __func__);
491 }
492
493 return 0;
494out_dev:
495 mfd_remove_devices(chip->dev);
496 device_irq_exit_800(chip);
497out:
498 return ret;
499}
500
501static int __devinit pm800_probe(struct i2c_client *client,
502 const struct i2c_device_id *id)
503{
504 int ret = 0;
505 struct pm80x_chip *chip;
506 struct pm80x_platform_data *pdata = client->dev.platform_data;
507 struct pm80x_subchip *subchip;
508
509 ret = pm80x_init(client, id);
510 if (ret) {
511 dev_err(&client->dev, "pm800_init fail\n");
512 goto out_init;
513 }
514
515 chip = i2c_get_clientdata(client);
516
517 /* init subchip for PM800 */
518 subchip =
519 devm_kzalloc(&client->dev, sizeof(struct pm80x_subchip),
520 GFP_KERNEL);
521 if (!subchip) {
522 ret = -ENOMEM;
523 goto err_subchip_alloc;
524 }
525
526 subchip->power_page_addr = pdata->power_page_addr;
527 subchip->gpadc_page_addr = pdata->gpadc_page_addr;
528 chip->subchip = subchip;
529
530 ret = device_800_init(chip, pdata);
531 if (ret) {
532 dev_err(chip->dev, "%s id 0x%x failed!\n", __func__, chip->id);
533 goto err_800_init;
534 }
535
536 ret = pm800_pages_init(chip);
537 if (ret) {
538 dev_err(&client->dev, "pm800_pages_init failed!\n");
539 goto err_page_init;
540 }
541
542 if (pdata->plat_config)
543 pdata->plat_config(chip, pdata);
544
545err_page_init:
546 mfd_remove_devices(chip->dev);
547 device_irq_exit_800(chip);
548err_800_init:
549 devm_kfree(&client->dev, subchip);
550err_subchip_alloc:
551 pm80x_deinit(client);
552out_init:
553 return ret;
554}
555
556static int __devexit pm800_remove(struct i2c_client *client)
557{
558 struct pm80x_chip *chip = i2c_get_clientdata(client);
559
560 mfd_remove_devices(chip->dev);
561 device_irq_exit_800(chip);
562
563 pm800_pages_exit(chip);
564 devm_kfree(&client->dev, chip->subchip);
565
566 pm80x_deinit(client);
567
568 return 0;
569}
570
571static struct i2c_driver pm800_driver = {
572 .driver = {
573 .name = "88PM80X",
574 .owner = THIS_MODULE,
575 .pm = &pm80x_pm_ops,
576 },
577 .probe = pm800_probe,
578 .remove = __devexit_p(pm800_remove),
579 .id_table = pm80x_id_table,
580};
581
582static int __init pm800_i2c_init(void)
583{
584 return i2c_add_driver(&pm800_driver);
585}
586subsys_initcall(pm800_i2c_init);
587
588static void __exit pm800_i2c_exit(void)
589{
590 i2c_del_driver(&pm800_driver);
591}
592module_exit(pm800_i2c_exit);
593
594MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM800");
595MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
596MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/88pm805.c b/drivers/mfd/88pm805.c
new file mode 100644
index 000000000000..6146583589f6
--- /dev/null
+++ b/drivers/mfd/88pm805.c
@@ -0,0 +1,301 @@
1/*
2 * Base driver for Marvell 88PM805
3 *
4 * Copyright (C) 2012 Marvell International Ltd.
5 * Haojian Zhuang <haojian.zhuang@marvell.com>
6 * Joseph(Yossi) Hanin <yhanin@marvell.com>
7 * Qiao Zhou <zhouqiao@marvell.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file "COPYING" in the main directory of this
11 * archive for more details.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/i2c.h>
26#include <linux/irq.h>
27#include <linux/mfd/core.h>
28#include <linux/mfd/88pm80x.h>
29#include <linux/slab.h>
30#include <linux/delay.h>
31
32#define PM805_CHIP_ID (0x00)
33
34static const struct i2c_device_id pm80x_id_table[] = {
35 {"88PM805", CHIP_PM805},
36 {} /* NULL terminated */
37};
38MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
39
40/* Interrupt Number in 88PM805 */
41enum {
42 PM805_IRQ_LDO_OFF, /*0 */
43 PM805_IRQ_SRC_DPLL_LOCK, /*1 */
44 PM805_IRQ_CLIP_FAULT,
45 PM805_IRQ_MIC_CONFLICT,
46 PM805_IRQ_HP2_SHRT,
47 PM805_IRQ_HP1_SHRT, /*5 */
48 PM805_IRQ_FINE_PLL_FAULT,
49 PM805_IRQ_RAW_PLL_FAULT,
50 PM805_IRQ_VOLP_BTN_DET,
51 PM805_IRQ_VOLM_BTN_DET,
52 PM805_IRQ_SHRT_BTN_DET, /*10 */
53 PM805_IRQ_MIC_DET, /*11 */
54
55 PM805_MAX_IRQ,
56};
57
58static struct resource codec_resources[] = {
59 {
60 /* Headset microphone insertion or removal */
61 .name = "micin",
62 .start = PM805_IRQ_MIC_DET,
63 .end = PM805_IRQ_MIC_DET,
64 .flags = IORESOURCE_IRQ,
65 },
66 {
67 /* Audio short HP1 */
68 .name = "audio-short1",
69 .start = PM805_IRQ_HP1_SHRT,
70 .end = PM805_IRQ_HP1_SHRT,
71 .flags = IORESOURCE_IRQ,
72 },
73 {
74 /* Audio short HP2 */
75 .name = "audio-short2",
76 .start = PM805_IRQ_HP2_SHRT,
77 .end = PM805_IRQ_HP2_SHRT,
78 .flags = IORESOURCE_IRQ,
79 },
80};
81
82static struct mfd_cell codec_devs[] = {
83 {
84 .name = "88pm80x-codec",
85 .num_resources = ARRAY_SIZE(codec_resources),
86 .resources = &codec_resources[0],
87 .id = -1,
88 },
89};
90
91static struct regmap_irq pm805_irqs[] = {
92 /* INT0 */
93 [PM805_IRQ_LDO_OFF] = {
94 .mask = PM805_INT1_HP1_SHRT,
95 },
96 [PM805_IRQ_SRC_DPLL_LOCK] = {
97 .mask = PM805_INT1_HP2_SHRT,
98 },
99 [PM805_IRQ_CLIP_FAULT] = {
100 .mask = PM805_INT1_MIC_CONFLICT,
101 },
102 [PM805_IRQ_MIC_CONFLICT] = {
103 .mask = PM805_INT1_CLIP_FAULT,
104 },
105 [PM805_IRQ_HP2_SHRT] = {
106 .mask = PM805_INT1_LDO_OFF,
107 },
108 [PM805_IRQ_HP1_SHRT] = {
109 .mask = PM805_INT1_SRC_DPLL_LOCK,
110 },
111 /* INT1 */
112 [PM805_IRQ_FINE_PLL_FAULT] = {
113 .reg_offset = 1,
114 .mask = PM805_INT2_MIC_DET,
115 },
116 [PM805_IRQ_RAW_PLL_FAULT] = {
117 .reg_offset = 1,
118 .mask = PM805_INT2_SHRT_BTN_DET,
119 },
120 [PM805_IRQ_VOLP_BTN_DET] = {
121 .reg_offset = 1,
122 .mask = PM805_INT2_VOLM_BTN_DET,
123 },
124 [PM805_IRQ_VOLM_BTN_DET] = {
125 .reg_offset = 1,
126 .mask = PM805_INT2_VOLP_BTN_DET,
127 },
128 [PM805_IRQ_SHRT_BTN_DET] = {
129 .reg_offset = 1,
130 .mask = PM805_INT2_RAW_PLL_FAULT,
131 },
132 [PM805_IRQ_MIC_DET] = {
133 .reg_offset = 1,
134 .mask = PM805_INT2_FINE_PLL_FAULT,
135 },
136};
137
138static int __devinit device_irq_init_805(struct pm80x_chip *chip)
139{
140 struct regmap *map = chip->regmap;
141 unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
142 int data, mask, ret = -EINVAL;
143
144 if (!map || !chip->irq) {
145 dev_err(chip->dev, "incorrect parameters\n");
146 return -EINVAL;
147 }
148
149 /*
150 * irq_mode defines the way of clearing interrupt. it's read-clear by
151 * default.
152 */
153 mask =
154 PM805_STATUS0_INT_CLEAR | PM805_STATUS0_INV_INT |
155 PM800_STATUS0_INT_MASK;
156
157 data = PM805_STATUS0_INT_CLEAR;
158 ret = regmap_update_bits(map, PM805_INT_STATUS0, mask, data);
159 /*
160 * PM805_INT_STATUS is under 32K clock domain, so need to
161 * add proper delay before the next I2C register access.
162 */
163 msleep(1);
164
165 if (ret < 0)
166 goto out;
167
168 ret =
169 regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
170 chip->regmap_irq_chip, &chip->irq_data);
171
172out:
173 return ret;
174}
175
176static void device_irq_exit_805(struct pm80x_chip *chip)
177{
178 regmap_del_irq_chip(chip->irq, chip->irq_data);
179}
180
181static struct regmap_irq_chip pm805_irq_chip = {
182 .name = "88pm805",
183 .irqs = pm805_irqs,
184 .num_irqs = ARRAY_SIZE(pm805_irqs),
185
186 .num_regs = 2,
187 .status_base = PM805_INT_STATUS1,
188 .mask_base = PM805_INT_MASK1,
189 .ack_base = PM805_INT_STATUS1,
190};
191
192static int __devinit device_805_init(struct pm80x_chip *chip)
193{
194 int ret = 0;
195 unsigned int val;
196 struct regmap *map = chip->regmap;
197
198 if (!map) {
199 dev_err(chip->dev, "regmap is invalid\n");
200 return -EINVAL;
201 }
202
203 ret = regmap_read(map, PM805_CHIP_ID, &val);
204 if (ret < 0) {
205 dev_err(chip->dev, "Failed to read CHIP ID: %d\n", ret);
206 goto out_irq_init;
207 }
208 chip->version = val;
209
210 chip->regmap_irq_chip = &pm805_irq_chip;
211
212 ret = device_irq_init_805(chip);
213 if (ret < 0) {
214 dev_err(chip->dev, "Failed to init pm805 irq!\n");
215 goto out_irq_init;
216 }
217
218 ret = mfd_add_devices(chip->dev, 0, &codec_devs[0],
219 ARRAY_SIZE(codec_devs), &codec_resources[0], 0);
220 if (ret < 0) {
221 dev_err(chip->dev, "Failed to add codec subdev\n");
222 goto out_codec;
223 } else
224 dev_info(chip->dev, "[%s]:Added mfd codec_devs\n", __func__);
225
226 return 0;
227
228out_codec:
229 device_irq_exit_805(chip);
230out_irq_init:
231 return ret;
232}
233
234static int __devinit pm805_probe(struct i2c_client *client,
235 const struct i2c_device_id *id)
236{
237 int ret = 0;
238 struct pm80x_chip *chip;
239 struct pm80x_platform_data *pdata = client->dev.platform_data;
240
241 ret = pm80x_init(client, id);
242 if (ret) {
243 dev_err(&client->dev, "pm805_init fail!\n");
244 goto out_init;
245 }
246
247 chip = i2c_get_clientdata(client);
248
249 ret = device_805_init(chip);
250 if (ret) {
251 dev_err(chip->dev, "%s id 0x%x failed!\n", __func__, chip->id);
252 goto err_805_init;
253 }
254
255 if (pdata->plat_config)
256 pdata->plat_config(chip, pdata);
257
258err_805_init:
259 pm80x_deinit(client);
260out_init:
261 return ret;
262}
263
264static int __devexit pm805_remove(struct i2c_client *client)
265{
266 struct pm80x_chip *chip = i2c_get_clientdata(client);
267
268 mfd_remove_devices(chip->dev);
269 device_irq_exit_805(chip);
270
271 pm80x_deinit(client);
272
273 return 0;
274}
275
276static struct i2c_driver pm805_driver = {
277 .driver = {
278 .name = "88PM80X",
279 .owner = THIS_MODULE,
280 .pm = &pm80x_pm_ops,
281 },
282 .probe = pm805_probe,
283 .remove = __devexit_p(pm805_remove),
284 .id_table = pm80x_id_table,
285};
286
287static int __init pm805_i2c_init(void)
288{
289 return i2c_add_driver(&pm805_driver);
290}
291subsys_initcall(pm805_i2c_init);
292
293static void __exit pm805_i2c_exit(void)
294{
295 i2c_del_driver(&pm805_driver);
296}
297module_exit(pm805_i2c_exit);
298
299MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM805");
300MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
301MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/88pm80x.c b/drivers/mfd/88pm80x.c
new file mode 100644
index 000000000000..cd0bf527d764
--- /dev/null
+++ b/drivers/mfd/88pm80x.c
@@ -0,0 +1,145 @@
1/*
2 * I2C driver for Marvell 88PM80x
3 *
4 * Copyright (C) 2012 Marvell International Ltd.
5 * Haojian Zhuang <haojian.zhuang@marvell.com>
6 * Joseph(Yossi) Hanin <yhanin@marvell.com>
7 * Qiao Zhou <zhouqiao@marvell.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/i2c.h>
16#include <linux/mfd/88pm80x.h>
17#include <linux/slab.h>
18#include <linux/uaccess.h>
19#include <linux/err.h>
20
21/*
22 * workaround: some registers needed by pm805 are defined in pm800, so
23 * need to use this global variable to maintain the relation between
24 * pm800 and pm805. would remove it after HW chip fixes the issue.
25 */
26static struct pm80x_chip *g_pm80x_chip;
27
28const struct regmap_config pm80x_regmap_config = {
29 .reg_bits = 8,
30 .val_bits = 8,
31};
32EXPORT_SYMBOL_GPL(pm80x_regmap_config);
33
34int __devinit pm80x_init(struct i2c_client *client,
35 const struct i2c_device_id *id)
36{
37 struct pm80x_chip *chip;
38 struct regmap *map;
39 int ret = 0;
40
41 chip =
42 devm_kzalloc(&client->dev, sizeof(struct pm80x_chip), GFP_KERNEL);
43 if (!chip)
44 return -ENOMEM;
45
46 map = devm_regmap_init_i2c(client, &pm80x_regmap_config);
47 if (IS_ERR(map)) {
48 ret = PTR_ERR(map);
49 dev_err(&client->dev, "Failed to allocate register map: %d\n",
50 ret);
51 goto err_regmap_init;
52 }
53
54 chip->id = id->driver_data;
55 if (chip->id < CHIP_PM800 || chip->id > CHIP_PM805) {
56 ret = -EINVAL;
57 goto err_chip_id;
58 }
59
60 chip->client = client;
61 chip->regmap = map;
62
63 chip->irq = client->irq;
64
65 chip->dev = &client->dev;
66 dev_set_drvdata(chip->dev, chip);
67 i2c_set_clientdata(chip->client, chip);
68
69 device_init_wakeup(&client->dev, 1);
70
71 /*
72 * workaround: set g_pm80x_chip to the first probed chip. if the
73 * second chip is probed, just point to the companion to each
74 * other so that pm805 can access those specific register. would
75 * remove it after HW chip fixes the issue.
76 */
77 if (!g_pm80x_chip)
78 g_pm80x_chip = chip;
79 else {
80 chip->companion = g_pm80x_chip->client;
81 g_pm80x_chip->companion = chip->client;
82 }
83
84 return 0;
85
86err_chip_id:
87 regmap_exit(map);
88err_regmap_init:
89 devm_kfree(&client->dev, chip);
90 return ret;
91}
92EXPORT_SYMBOL_GPL(pm80x_init);
93
94int pm80x_deinit(struct i2c_client *client)
95{
96 struct pm80x_chip *chip = i2c_get_clientdata(client);
97
98 /*
99 * workaround: clear the dependency between pm800 and pm805.
100 * would remove it after HW chip fixes the issue.
101 */
102 if (g_pm80x_chip->companion)
103 g_pm80x_chip->companion = NULL;
104 else
105 g_pm80x_chip = NULL;
106
107 regmap_exit(chip->regmap);
108 devm_kfree(&client->dev, chip);
109
110 return 0;
111}
112EXPORT_SYMBOL_GPL(pm80x_deinit);
113
114#ifdef CONFIG_PM_SLEEP
115static int pm80x_suspend(struct device *dev)
116{
117 struct i2c_client *client = container_of(dev, struct i2c_client, dev);
118 struct pm80x_chip *chip = i2c_get_clientdata(client);
119
120 if (chip && chip->wu_flag)
121 if (device_may_wakeup(chip->dev))
122 enable_irq_wake(chip->irq);
123
124 return 0;
125}
126
127static int pm80x_resume(struct device *dev)
128{
129 struct i2c_client *client = container_of(dev, struct i2c_client, dev);
130 struct pm80x_chip *chip = i2c_get_clientdata(client);
131
132 if (chip && chip->wu_flag)
133 if (device_may_wakeup(chip->dev))
134 disable_irq_wake(chip->irq);
135
136 return 0;
137}
138#endif
139
140SIMPLE_DEV_PM_OPS(pm80x_pm_ops, pm80x_suspend, pm80x_resume);
141EXPORT_SYMBOL_GPL(pm80x_pm_ops);
142
143MODULE_DESCRIPTION("I2C Driver for Marvell 88PM80x");
144MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
145MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c
index 87bd5ba38d5b..d09918cf1b15 100644
--- a/drivers/mfd/88pm860x-core.c
+++ b/drivers/mfd/88pm860x-core.c
@@ -90,6 +90,10 @@ static struct resource charger_resources[] __devinitdata = {
90 {PM8607_IRQ_VCHG, PM8607_IRQ_VCHG, "vchg voltage", IORESOURCE_IRQ,}, 90 {PM8607_IRQ_VCHG, PM8607_IRQ_VCHG, "vchg voltage", IORESOURCE_IRQ,},
91}; 91};
92 92
93static struct resource preg_resources[] __devinitdata = {
94 {PM8606_ID_PREG, PM8606_ID_PREG, "preg", IORESOURCE_IO,},
95};
96
93static struct resource rtc_resources[] __devinitdata = { 97static struct resource rtc_resources[] __devinitdata = {
94 {PM8607_IRQ_RTC, PM8607_IRQ_RTC, "rtc", IORESOURCE_IRQ,}, 98 {PM8607_IRQ_RTC, PM8607_IRQ_RTC, "rtc", IORESOURCE_IRQ,},
95}; 99};
@@ -142,9 +146,19 @@ static struct mfd_cell codec_devs[] = {
142 {"88pm860x-codec", -1,}, 146 {"88pm860x-codec", -1,},
143}; 147};
144 148
149static struct regulator_consumer_supply preg_supply[] = {
150 REGULATOR_SUPPLY("preg", "charger-manager"),
151};
152
153static struct regulator_init_data preg_init_data = {
154 .num_consumer_supplies = ARRAY_SIZE(preg_supply),
155 .consumer_supplies = &preg_supply[0],
156};
157
145static struct mfd_cell power_devs[] = { 158static struct mfd_cell power_devs[] = {
146 {"88pm860x-battery", -1,}, 159 {"88pm860x-battery", -1,},
147 {"88pm860x-charger", -1,}, 160 {"88pm860x-charger", -1,},
161 {"88pm860x-preg", -1,},
148}; 162};
149 163
150static struct mfd_cell rtc_devs[] = { 164static struct mfd_cell rtc_devs[] = {
@@ -768,6 +782,15 @@ static void __devinit device_power_init(struct pm860x_chip *chip,
768 &charger_resources[0], chip->irq_base); 782 &charger_resources[0], chip->irq_base);
769 if (ret < 0) 783 if (ret < 0)
770 dev_err(chip->dev, "Failed to add charger subdev\n"); 784 dev_err(chip->dev, "Failed to add charger subdev\n");
785
786 power_devs[2].platform_data = &preg_init_data;
787 power_devs[2].pdata_size = sizeof(struct regulator_init_data);
788 power_devs[2].num_resources = ARRAY_SIZE(preg_resources);
789 power_devs[2].resources = &preg_resources[0],
790 ret = mfd_add_devices(chip->dev, 0, &power_devs[2], 1,
791 &preg_resources[0], chip->irq_base);
792 if (ret < 0)
793 dev_err(chip->dev, "Failed to add preg subdev\n");
771} 794}
772 795
773static void __devinit device_onkey_init(struct pm860x_chip *chip, 796static void __devinit device_onkey_init(struct pm860x_chip *chip,
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4fdc04ef37c2..d1facef28a60 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -7,6 +7,7 @@ menu "Multifunction device drivers"
7 7
8config MFD_CORE 8config MFD_CORE
9 tristate 9 tristate
10 select IRQ_DOMAIN
10 default n 11 default n
11 12
12config MFD_88PM860X 13config MFD_88PM860X
@@ -20,6 +21,30 @@ config MFD_88PM860X
20 select individual components like voltage regulators, RTC and 21 select individual components like voltage regulators, RTC and
21 battery-charger under the corresponding menus. 22 battery-charger under the corresponding menus.
22 23
24config MFD_88PM800
25 tristate "Support Marvell 88PM800"
26 depends on I2C=y && GENERIC_HARDIRQS
27 select REGMAP_I2C
28 select REGMAP_IRQ
29 select MFD_CORE
30 help
31 This supports for Marvell 88PM800 Power Management IC.
32 This includes the I2C driver and the core APIs _only_, you have to
33 select individual components like voltage regulators, RTC and
34 battery-charger under the corresponding menus.
35
36config MFD_88PM805
37 tristate "Support Marvell 88PM805"
38 depends on I2C=y && GENERIC_HARDIRQS
39 select REGMAP_I2C
40 select REGMAP_IRQ
41 select MFD_CORE
42 help
43 This supports for Marvell 88PM805 Power Management IC. This includes
44 the I2C driver and the core APIs _only_, you have to select individual
45 components like codec device, headset/Mic device under the
46 corresponding menus.
47
23config MFD_SM501 48config MFD_SM501
24 tristate "Support for Silicon Motion SM501" 49 tristate "Support for Silicon Motion SM501"
25 ---help--- 50 ---help---
@@ -173,8 +198,9 @@ config MFD_TPS65217
173 198
174config MFD_TPS6586X 199config MFD_TPS6586X
175 bool "TPS6586x Power Management chips" 200 bool "TPS6586x Power Management chips"
176 depends on I2C=y && GPIOLIB && GENERIC_HARDIRQS 201 depends on I2C=y && GENERIC_HARDIRQS
177 select MFD_CORE 202 select MFD_CORE
203 select REGMAP_I2C
178 depends on REGULATOR 204 depends on REGULATOR
179 help 205 help
180 If you say yes here you get support for the TPS6586X series of 206 If you say yes here you get support for the TPS6586X series of
@@ -424,6 +450,19 @@ config PMIC_ADP5520
424 individual components like LCD backlight, LEDs, GPIOs and Kepad 450 individual components like LCD backlight, LEDs, GPIOs and Kepad
425 under the corresponding menus. 451 under the corresponding menus.
426 452
453config MFD_MAX77686
454 bool "Maxim Semiconductor MAX77686 PMIC Support"
455 depends on I2C=y && GENERIC_HARDIRQS
456 select MFD_CORE
457 select REGMAP_I2C
458 select IRQ_DOMAIN
459 help
460 Say yes here to support for Maxim Semiconductor MAX77686.
461 This is a Power Management IC with RTC on chip.
462 This driver provides common support for accessing the device;
463 additional drivers must be enabled in order to use the functionality
464 of the device.
465
427config MFD_MAX77693 466config MFD_MAX77693
428 bool "Maxim Semiconductor MAX77693 PMIC Support" 467 bool "Maxim Semiconductor MAX77693 PMIC Support"
429 depends on I2C=y && GENERIC_HARDIRQS 468 depends on I2C=y && GENERIC_HARDIRQS
@@ -451,6 +490,7 @@ config MFD_MAX8997
451 bool "Maxim Semiconductor MAX8997/8966 PMIC Support" 490 bool "Maxim Semiconductor MAX8997/8966 PMIC Support"
452 depends on I2C=y && GENERIC_HARDIRQS 491 depends on I2C=y && GENERIC_HARDIRQS
453 select MFD_CORE 492 select MFD_CORE
493 select IRQ_DOMAIN
454 help 494 help
455 Say yes here to support for Maxim Semiconductor MAX8997/8966. 495 Say yes here to support for Maxim Semiconductor MAX8997/8966.
456 This is a Power Management IC with RTC, Flash, Fuel Gauge, Haptic, 496 This is a Power Management IC with RTC, Flash, Fuel Gauge, Haptic,
@@ -470,17 +510,56 @@ config MFD_MAX8998
470 additional drivers must be enabled in order to use the functionality 510 additional drivers must be enabled in order to use the functionality
471 of the device. 511 of the device.
472 512
473config MFD_S5M_CORE 513config MFD_SEC_CORE
474 bool "SAMSUNG S5M Series Support" 514 bool "SAMSUNG Electronics PMIC Series Support"
475 depends on I2C=y && GENERIC_HARDIRQS 515 depends on I2C=y && GENERIC_HARDIRQS
476 select MFD_CORE 516 select MFD_CORE
477 select REGMAP_I2C 517 select REGMAP_I2C
518 select REGMAP_IRQ
478 help 519 help
479 Support for the Samsung Electronics S5M MFD series. 520 Support for the Samsung Electronics MFD series.
480 This driver provides common support for accessing the device, 521 This driver provides common support for accessing the device,
481 additional drivers must be enabled in order to use the functionality 522 additional drivers must be enabled in order to use the functionality
482 of the device 523 of the device
483 524
525config MFD_ARIZONA
526 select REGMAP
527 select REGMAP_IRQ
528 select MFD_CORE
529 bool
530
531config MFD_ARIZONA_I2C
532 tristate "Support Wolfson Microelectronics Arizona platform with I2C"
533 select MFD_ARIZONA
534 select MFD_CORE
535 select REGMAP_I2C
536 depends on I2C
537 help
538 Support for the Wolfson Microelectronics Arizona platform audio SoC
539 core functionality controlled via I2C.
540
541config MFD_ARIZONA_SPI
542 tristate "Support Wolfson Microelectronics Arizona platform with SPI"
543 select MFD_ARIZONA
544 select MFD_CORE
545 select REGMAP_SPI
546 depends on SPI_MASTER
547 help
548 Support for the Wolfson Microelectronics Arizona platform audio SoC
549 core functionality controlled via I2C.
550
551config MFD_WM5102
552 bool "Support Wolfson Microelectronics WM5102"
553 depends on MFD_ARIZONA
554 help
555 Support for Wolfson Microelectronics WM5102 low power audio SoC
556
557config MFD_WM5110
558 bool "Support Wolfson Microelectronics WM5110"
559 depends on MFD_ARIZONA
560 help
561 Support for Wolfson Microelectronics WM5110 low power audio SoC
562
484config MFD_WM8400 563config MFD_WM8400
485 bool "Support Wolfson Microelectronics WM8400" 564 bool "Support Wolfson Microelectronics WM8400"
486 select MFD_CORE 565 select MFD_CORE
@@ -698,6 +777,7 @@ config AB8500_CORE
698 bool "ST-Ericsson AB8500 Mixed Signal Power Management chip" 777 bool "ST-Ericsson AB8500 Mixed Signal Power Management chip"
699 depends on GENERIC_HARDIRQS && ABX500_CORE && MFD_DB8500_PRCMU 778 depends on GENERIC_HARDIRQS && ABX500_CORE && MFD_DB8500_PRCMU
700 select MFD_CORE 779 select MFD_CORE
780 select IRQ_DOMAIN
701 help 781 help
702 Select this option to enable access to AB8500 power management 782 Select this option to enable access to AB8500 power management
703 chip. This connects to U8500 either on the SSP/SPI bus (deprecated 783 chip. This connects to U8500 either on the SSP/SPI bus (deprecated
@@ -705,16 +785,6 @@ config AB8500_CORE
705 the irq_chip parts for handling the Mixed Signal chip events. 785 the irq_chip parts for handling the Mixed Signal chip events.
706 This chip embeds various other multimedia funtionalities as well. 786 This chip embeds various other multimedia funtionalities as well.
707 787
708config AB8500_I2C_CORE
709 bool "AB8500 register access via PRCMU I2C"
710 depends on AB8500_CORE && MFD_DB8500_PRCMU
711 default y
712 help
713 This enables register access to the AB8500 chip via PRCMU I2C.
714 The AB8500 chip can be accessed via SPI or I2C. On DB8500 hardware
715 the I2C bus is connected to the Power Reset
716 and Mangagement Unit, PRCMU.
717
718config AB8500_DEBUG 788config AB8500_DEBUG
719 bool "Enable debug info via debugfs" 789 bool "Enable debug info via debugfs"
720 depends on AB8500_CORE && DEBUG_FS 790 depends on AB8500_CORE && DEBUG_FS
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 75f6ed68a4b9..79dd22d1dc3d 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -4,6 +4,8 @@
4 4
588pm860x-objs := 88pm860x-core.o 88pm860x-i2c.o 588pm860x-objs := 88pm860x-core.o 88pm860x-i2c.o
6obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o 6obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o
7obj-$(CONFIG_MFD_88PM800) += 88pm800.o 88pm80x.o
8obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o
7obj-$(CONFIG_MFD_SM501) += sm501.o 9obj-$(CONFIG_MFD_SM501) += sm501.o
8obj-$(CONFIG_MFD_ASIC3) += asic3.o tmio_core.o 10obj-$(CONFIG_MFD_ASIC3) += asic3.o tmio_core.o
9 11
@@ -24,6 +26,16 @@ obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o tmio_core.o
24obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o tmio_core.o 26obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o tmio_core.o
25obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o tmio_core.o 27obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o tmio_core.o
26 28
29obj-$(CONFIG_MFD_ARIZONA) += arizona-core.o
30obj-$(CONFIG_MFD_ARIZONA) += arizona-irq.o
31obj-$(CONFIG_MFD_ARIZONA_I2C) += arizona-i2c.o
32obj-$(CONFIG_MFD_ARIZONA_SPI) += arizona-spi.o
33ifneq ($(CONFIG_MFD_WM5102),n)
34obj-$(CONFIG_MFD_ARIZONA) += wm5102-tables.o
35endif
36ifneq ($(CONFIG_MFD_WM5110),n)
37obj-$(CONFIG_MFD_ARIZONA) += wm5110-tables.o
38endif
27obj-$(CONFIG_MFD_WM8400) += wm8400-core.o 39obj-$(CONFIG_MFD_WM8400) += wm8400-core.o
28wm831x-objs := wm831x-core.o wm831x-irq.o wm831x-otp.o 40wm831x-objs := wm831x-core.o wm831x-irq.o wm831x-otp.o
29wm831x-objs += wm831x-auxadc.o 41wm831x-objs += wm831x-auxadc.o
@@ -78,6 +90,7 @@ obj-$(CONFIG_PMIC_DA9052) += da9052-core.o
78obj-$(CONFIG_MFD_DA9052_SPI) += da9052-spi.o 90obj-$(CONFIG_MFD_DA9052_SPI) += da9052-spi.o
79obj-$(CONFIG_MFD_DA9052_I2C) += da9052-i2c.o 91obj-$(CONFIG_MFD_DA9052_I2C) += da9052-i2c.o
80 92
93obj-$(CONFIG_MFD_MAX77686) += max77686.o max77686-irq.o
81obj-$(CONFIG_MFD_MAX77693) += max77693.o max77693-irq.o 94obj-$(CONFIG_MFD_MAX77693) += max77693.o max77693-irq.o
82max8925-objs := max8925-core.o max8925-i2c.o 95max8925-objs := max8925-core.o max8925-i2c.o
83obj-$(CONFIG_MFD_MAX8925) += max8925.o 96obj-$(CONFIG_MFD_MAX8925) += max8925.o
@@ -116,6 +129,6 @@ obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o
116obj-$(CONFIG_MFD_INTEL_MSIC) += intel_msic.o 129obj-$(CONFIG_MFD_INTEL_MSIC) += intel_msic.o
117obj-$(CONFIG_MFD_PALMAS) += palmas.o 130obj-$(CONFIG_MFD_PALMAS) += palmas.o
118obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o 131obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o
119obj-$(CONFIG_MFD_S5M_CORE) += s5m-core.o s5m-irq.o 132obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o
120obj-$(CONFIG_MFD_ANATOP) += anatop-mfd.o 133obj-$(CONFIG_MFD_ANATOP) += anatop-mfd.o
121obj-$(CONFIG_MFD_LM3533) += lm3533-core.o lm3533-ctrlbank.o 134obj-$(CONFIG_MFD_LM3533) += lm3533-core.o lm3533-ctrlbank.o
diff --git a/drivers/mfd/ab3100-core.c b/drivers/mfd/ab3100-core.c
index 1efad20fb175..4276aab4f196 100644
--- a/drivers/mfd/ab3100-core.c
+++ b/drivers/mfd/ab3100-core.c
@@ -867,7 +867,7 @@ static int __devinit ab3100_probe(struct i2c_client *client,
867 int err; 867 int err;
868 int i; 868 int i;
869 869
870 ab3100 = kzalloc(sizeof(struct ab3100), GFP_KERNEL); 870 ab3100 = devm_kzalloc(&client->dev, sizeof(struct ab3100), GFP_KERNEL);
871 if (!ab3100) { 871 if (!ab3100) {
872 dev_err(&client->dev, "could not allocate AB3100 device\n"); 872 dev_err(&client->dev, "could not allocate AB3100 device\n");
873 return -ENOMEM; 873 return -ENOMEM;
@@ -921,7 +921,7 @@ static int __devinit ab3100_probe(struct i2c_client *client,
921 921
922 /* Attach a second dummy i2c_client to the test register address */ 922 /* Attach a second dummy i2c_client to the test register address */
923 ab3100->testreg_client = i2c_new_dummy(client->adapter, 923 ab3100->testreg_client = i2c_new_dummy(client->adapter,
924 client->addr + 1); 924 client->addr + 1);
925 if (!ab3100->testreg_client) { 925 if (!ab3100->testreg_client) {
926 err = -ENOMEM; 926 err = -ENOMEM;
927 goto exit_no_testreg_client; 927 goto exit_no_testreg_client;
@@ -931,13 +931,13 @@ static int __devinit ab3100_probe(struct i2c_client *client,
931 if (err) 931 if (err)
932 goto exit_no_setup; 932 goto exit_no_setup;
933 933
934 err = request_threaded_irq(client->irq, NULL, ab3100_irq_handler, 934 err = devm_request_threaded_irq(&client->dev,
935 IRQF_ONESHOT, "ab3100-core", ab3100); 935 client->irq, NULL, ab3100_irq_handler,
936 /* This real unpredictable IRQ is of course sampled for entropy */ 936 IRQF_ONESHOT, "ab3100-core", ab3100);
937 rand_initialize_irq(client->irq);
938
939 if (err) 937 if (err)
940 goto exit_no_irq; 938 goto exit_no_irq;
939 /* This real unpredictable IRQ is of course sampled for entropy */
940 rand_initialize_irq(client->irq);
941 941
942 err = abx500_register_ops(&client->dev, &ab3100_ops); 942 err = abx500_register_ops(&client->dev, &ab3100_ops);
943 if (err) 943 if (err)
@@ -962,7 +962,6 @@ static int __devinit ab3100_probe(struct i2c_client *client,
962 i2c_unregister_device(ab3100->testreg_client); 962 i2c_unregister_device(ab3100->testreg_client);
963 exit_no_testreg_client: 963 exit_no_testreg_client:
964 exit_no_detect: 964 exit_no_detect:
965 kfree(ab3100);
966 return err; 965 return err;
967} 966}
968 967
@@ -972,16 +971,8 @@ static int __devexit ab3100_remove(struct i2c_client *client)
972 971
973 /* Unregister subdevices */ 972 /* Unregister subdevices */
974 mfd_remove_devices(&client->dev); 973 mfd_remove_devices(&client->dev);
975
976 ab3100_remove_debugfs(); 974 ab3100_remove_debugfs();
977 i2c_unregister_device(ab3100->testreg_client); 975 i2c_unregister_device(ab3100->testreg_client);
978
979 /*
980 * At this point, all subscribers should have unregistered
981 * their notifiers so deactivate IRQ
982 */
983 free_irq(client->irq, ab3100);
984 kfree(ab3100);
985 return 0; 976 return 0;
986} 977}
987 978
diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c
index dac0e2998603..626b4ecaf647 100644
--- a/drivers/mfd/ab8500-core.c
+++ b/drivers/mfd/ab8500-core.c
@@ -11,6 +11,7 @@
11#include <linux/slab.h> 11#include <linux/slab.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/irqdomain.h>
14#include <linux/delay.h> 15#include <linux/delay.h>
15#include <linux/interrupt.h> 16#include <linux/interrupt.h>
16#include <linux/module.h> 17#include <linux/module.h>
@@ -140,7 +141,7 @@ static const char ab8500_version_str[][7] = {
140 [AB8500_VERSION_AB8540] = "AB8540", 141 [AB8500_VERSION_AB8540] = "AB8540",
141}; 142};
142 143
143static int ab8500_i2c_write(struct ab8500 *ab8500, u16 addr, u8 data) 144static int ab8500_prcmu_write(struct ab8500 *ab8500, u16 addr, u8 data)
144{ 145{
145 int ret; 146 int ret;
146 147
@@ -150,7 +151,7 @@ static int ab8500_i2c_write(struct ab8500 *ab8500, u16 addr, u8 data)
150 return ret; 151 return ret;
151} 152}
152 153
153static int ab8500_i2c_write_masked(struct ab8500 *ab8500, u16 addr, u8 mask, 154static int ab8500_prcmu_write_masked(struct ab8500 *ab8500, u16 addr, u8 mask,
154 u8 data) 155 u8 data)
155{ 156{
156 int ret; 157 int ret;
@@ -162,7 +163,7 @@ static int ab8500_i2c_write_masked(struct ab8500 *ab8500, u16 addr, u8 mask,
162 return ret; 163 return ret;
163} 164}
164 165
165static int ab8500_i2c_read(struct ab8500 *ab8500, u16 addr) 166static int ab8500_prcmu_read(struct ab8500 *ab8500, u16 addr)
166{ 167{
167 int ret; 168 int ret;
168 u8 data; 169 u8 data;
@@ -361,7 +362,7 @@ static void ab8500_irq_sync_unlock(struct irq_data *data)
361static void ab8500_irq_mask(struct irq_data *data) 362static void ab8500_irq_mask(struct irq_data *data)
362{ 363{
363 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data); 364 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
364 int offset = data->irq - ab8500->irq_base; 365 int offset = data->hwirq;
365 int index = offset / 8; 366 int index = offset / 8;
366 int mask = 1 << (offset % 8); 367 int mask = 1 << (offset % 8);
367 368
@@ -371,7 +372,7 @@ static void ab8500_irq_mask(struct irq_data *data)
371static void ab8500_irq_unmask(struct irq_data *data) 372static void ab8500_irq_unmask(struct irq_data *data)
372{ 373{
373 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data); 374 struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
374 int offset = data->irq - ab8500->irq_base; 375 int offset = data->hwirq;
375 int index = offset / 8; 376 int index = offset / 8;
376 int mask = 1 << (offset % 8); 377 int mask = 1 << (offset % 8);
377 378
@@ -510,38 +511,51 @@ static irqreturn_t ab8500_irq(int irq, void *dev)
510 return IRQ_HANDLED; 511 return IRQ_HANDLED;
511} 512}
512 513
513static int ab8500_irq_init(struct ab8500 *ab8500) 514/**
515 * ab8500_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
516 *
517 * @ab8500: ab8500_irq controller to operate on.
518 * @irq: index of the interrupt requested in the chip IRQs
519 *
520 * Useful for drivers to request their own IRQs.
521 */
522int ab8500_irq_get_virq(struct ab8500 *ab8500, int irq)
514{ 523{
515 int base = ab8500->irq_base; 524 if (!ab8500)
516 int irq; 525 return -EINVAL;
517 int num_irqs;
518 526
519 if (is_ab9540(ab8500)) 527 return irq_create_mapping(ab8500->domain, irq);
520 num_irqs = AB9540_NR_IRQS; 528}
521 else if (is_ab8505(ab8500)) 529EXPORT_SYMBOL_GPL(ab8500_irq_get_virq);
522 num_irqs = AB8505_NR_IRQS; 530
523 else 531static int ab8500_irq_map(struct irq_domain *d, unsigned int virq,
524 num_irqs = AB8500_NR_IRQS; 532 irq_hw_number_t hwirq)
533{
534 struct ab8500 *ab8500 = d->host_data;
525 535
526 for (irq = base; irq < base + num_irqs; irq++) { 536 if (!ab8500)
527 irq_set_chip_data(irq, ab8500); 537 return -EINVAL;
528 irq_set_chip_and_handler(irq, &ab8500_irq_chip, 538
529 handle_simple_irq); 539 irq_set_chip_data(virq, ab8500);
530 irq_set_nested_thread(irq, 1); 540 irq_set_chip_and_handler(virq, &ab8500_irq_chip,
541 handle_simple_irq);
542 irq_set_nested_thread(virq, 1);
531#ifdef CONFIG_ARM 543#ifdef CONFIG_ARM
532 set_irq_flags(irq, IRQF_VALID); 544 set_irq_flags(virq, IRQF_VALID);
533#else 545#else
534 irq_set_noprobe(irq); 546 irq_set_noprobe(virq);
535#endif 547#endif
536 }
537 548
538 return 0; 549 return 0;
539} 550}
540 551
541static void ab8500_irq_remove(struct ab8500 *ab8500) 552static struct irq_domain_ops ab8500_irq_ops = {
553 .map = ab8500_irq_map,
554 .xlate = irq_domain_xlate_twocell,
555};
556
557static int ab8500_irq_init(struct ab8500 *ab8500, struct device_node *np)
542{ 558{
543 int base = ab8500->irq_base;
544 int irq;
545 int num_irqs; 559 int num_irqs;
546 560
547 if (is_ab9540(ab8500)) 561 if (is_ab9540(ab8500))
@@ -551,13 +565,22 @@ static void ab8500_irq_remove(struct ab8500 *ab8500)
551 else 565 else
552 num_irqs = AB8500_NR_IRQS; 566 num_irqs = AB8500_NR_IRQS;
553 567
554 for (irq = base; irq < base + num_irqs; irq++) { 568 if (ab8500->irq_base) {
555#ifdef CONFIG_ARM 569 ab8500->domain = irq_domain_add_legacy(
556 set_irq_flags(irq, 0); 570 NULL, num_irqs, ab8500->irq_base,
557#endif 571 0, &ab8500_irq_ops, ab8500);
558 irq_set_chip_and_handler(irq, NULL, NULL); 572 }
559 irq_set_chip_data(irq, NULL); 573 else {
574 ab8500->domain = irq_domain_add_linear(
575 np, num_irqs, &ab8500_irq_ops, ab8500);
576 }
577
578 if (!ab8500->domain) {
579 dev_err(ab8500->dev, "Failed to create irqdomain\n");
580 return -ENOSYS;
560 } 581 }
582
583 return 0;
561} 584}
562 585
563int ab8500_suspend(struct ab8500 *ab8500) 586int ab8500_suspend(struct ab8500 *ab8500)
@@ -947,54 +970,69 @@ static struct mfd_cell __devinitdata abx500_common_devs[] = {
947#ifdef CONFIG_DEBUG_FS 970#ifdef CONFIG_DEBUG_FS
948 { 971 {
949 .name = "ab8500-debug", 972 .name = "ab8500-debug",
973 .of_compatible = "stericsson,ab8500-debug",
950 .num_resources = ARRAY_SIZE(ab8500_debug_resources), 974 .num_resources = ARRAY_SIZE(ab8500_debug_resources),
951 .resources = ab8500_debug_resources, 975 .resources = ab8500_debug_resources,
952 }, 976 },
953#endif 977#endif
954 { 978 {
955 .name = "ab8500-sysctrl", 979 .name = "ab8500-sysctrl",
980 .of_compatible = "stericsson,ab8500-sysctrl",
956 }, 981 },
957 { 982 {
958 .name = "ab8500-regulator", 983 .name = "ab8500-regulator",
984 .of_compatible = "stericsson,ab8500-regulator",
959 }, 985 },
960 { 986 {
961 .name = "ab8500-gpadc", 987 .name = "ab8500-gpadc",
988 .of_compatible = "stericsson,ab8500-gpadc",
962 .num_resources = ARRAY_SIZE(ab8500_gpadc_resources), 989 .num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
963 .resources = ab8500_gpadc_resources, 990 .resources = ab8500_gpadc_resources,
964 }, 991 },
965 { 992 {
966 .name = "ab8500-rtc", 993 .name = "ab8500-rtc",
994 .of_compatible = "stericsson,ab8500-rtc",
967 .num_resources = ARRAY_SIZE(ab8500_rtc_resources), 995 .num_resources = ARRAY_SIZE(ab8500_rtc_resources),
968 .resources = ab8500_rtc_resources, 996 .resources = ab8500_rtc_resources,
969 }, 997 },
970 { 998 {
971 .name = "ab8500-acc-det", 999 .name = "ab8500-acc-det",
1000 .of_compatible = "stericsson,ab8500-acc-det",
972 .num_resources = ARRAY_SIZE(ab8500_av_acc_detect_resources), 1001 .num_resources = ARRAY_SIZE(ab8500_av_acc_detect_resources),
973 .resources = ab8500_av_acc_detect_resources, 1002 .resources = ab8500_av_acc_detect_resources,
974 }, 1003 },
975 { 1004 {
976 .name = "ab8500-poweron-key", 1005 .name = "ab8500-poweron-key",
1006 .of_compatible = "stericsson,ab8500-poweron-key",
977 .num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources), 1007 .num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources),
978 .resources = ab8500_poweronkey_db_resources, 1008 .resources = ab8500_poweronkey_db_resources,
979 }, 1009 },
980 { 1010 {
981 .name = "ab8500-pwm", 1011 .name = "ab8500-pwm",
1012 .of_compatible = "stericsson,ab8500-pwm",
982 .id = 1, 1013 .id = 1,
983 }, 1014 },
984 { 1015 {
985 .name = "ab8500-pwm", 1016 .name = "ab8500-pwm",
1017 .of_compatible = "stericsson,ab8500-pwm",
986 .id = 2, 1018 .id = 2,
987 }, 1019 },
988 { 1020 {
989 .name = "ab8500-pwm", 1021 .name = "ab8500-pwm",
1022 .of_compatible = "stericsson,ab8500-pwm",
990 .id = 3, 1023 .id = 3,
991 }, 1024 },
992 { .name = "ab8500-leds", }, 1025 {
1026 .name = "ab8500-leds",
1027 .of_compatible = "stericsson,ab8500-leds",
1028 },
993 { 1029 {
994 .name = "ab8500-denc", 1030 .name = "ab8500-denc",
1031 .of_compatible = "stericsson,ab8500-denc",
995 }, 1032 },
996 { 1033 {
997 .name = "ab8500-temp", 1034 .name = "ab8500-temp",
1035 .of_compatible = "stericsson,ab8500-temp",
998 .num_resources = ARRAY_SIZE(ab8500_temp_resources), 1036 .num_resources = ARRAY_SIZE(ab8500_temp_resources),
999 .resources = ab8500_temp_resources, 1037 .resources = ab8500_temp_resources,
1000 }, 1038 },
@@ -1026,11 +1064,13 @@ static struct mfd_cell __devinitdata ab8500_bm_devs[] = {
1026static struct mfd_cell __devinitdata ab8500_devs[] = { 1064static struct mfd_cell __devinitdata ab8500_devs[] = {
1027 { 1065 {
1028 .name = "ab8500-gpio", 1066 .name = "ab8500-gpio",
1067 .of_compatible = "stericsson,ab8500-gpio",
1029 .num_resources = ARRAY_SIZE(ab8500_gpio_resources), 1068 .num_resources = ARRAY_SIZE(ab8500_gpio_resources),
1030 .resources = ab8500_gpio_resources, 1069 .resources = ab8500_gpio_resources,
1031 }, 1070 },
1032 { 1071 {
1033 .name = "ab8500-usb", 1072 .name = "ab8500-usb",
1073 .of_compatible = "stericsson,ab8500-usb",
1034 .num_resources = ARRAY_SIZE(ab8500_usb_resources), 1074 .num_resources = ARRAY_SIZE(ab8500_usb_resources),
1035 .resources = ab8500_usb_resources, 1075 .resources = ab8500_usb_resources,
1036 }, 1076 },
@@ -1207,16 +1247,17 @@ static struct attribute_group ab9540_attr_group = {
1207 .attrs = ab9540_sysfs_entries, 1247 .attrs = ab9540_sysfs_entries,
1208}; 1248};
1209 1249
1210static const struct of_device_id ab8500_match[] = {
1211 {
1212 .compatible = "stericsson,ab8500",
1213 .data = (void *)AB8500_VERSION_AB8500,
1214 },
1215 {},
1216};
1217
1218static int __devinit ab8500_probe(struct platform_device *pdev) 1250static int __devinit ab8500_probe(struct platform_device *pdev)
1219{ 1251{
1252 static char *switch_off_status[] = {
1253 "Swoff bit programming",
1254 "Thermal protection activation",
1255 "Vbat lower then BattOk falling threshold",
1256 "Watchdog expired",
1257 "Non presence of 32kHz clock",
1258 "Battery level lower than power on reset threshold",
1259 "Power on key 1 pressed longer than 10 seconds",
1260 "DB8500 thermal shutdown"};
1220 struct ab8500_platform_data *plat = dev_get_platdata(&pdev->dev); 1261 struct ab8500_platform_data *plat = dev_get_platdata(&pdev->dev);
1221 const struct platform_device_id *platid = platform_get_device_id(pdev); 1262 const struct platform_device_id *platid = platform_get_device_id(pdev);
1222 enum ab8500_version version = AB8500_VERSION_UNDEFINED; 1263 enum ab8500_version version = AB8500_VERSION_UNDEFINED;
@@ -1233,14 +1274,6 @@ static int __devinit ab8500_probe(struct platform_device *pdev)
1233 1274
1234 if (plat) 1275 if (plat)
1235 ab8500->irq_base = plat->irq_base; 1276 ab8500->irq_base = plat->irq_base;
1236 else if (np)
1237 ret = of_property_read_u32(np, "stericsson,irq-base", &ab8500->irq_base);
1238
1239 if (!ab8500->irq_base) {
1240 dev_info(&pdev->dev, "couldn't find irq-base\n");
1241 ret = -EINVAL;
1242 goto out_free_ab8500;
1243 }
1244 1277
1245 ab8500->dev = &pdev->dev; 1278 ab8500->dev = &pdev->dev;
1246 1279
@@ -1252,9 +1285,9 @@ static int __devinit ab8500_probe(struct platform_device *pdev)
1252 1285
1253 ab8500->irq = resource->start; 1286 ab8500->irq = resource->start;
1254 1287
1255 ab8500->read = ab8500_i2c_read; 1288 ab8500->read = ab8500_prcmu_read;
1256 ab8500->write = ab8500_i2c_write; 1289 ab8500->write = ab8500_prcmu_write;
1257 ab8500->write_masked = ab8500_i2c_write_masked; 1290 ab8500->write_masked = ab8500_prcmu_write_masked;
1258 1291
1259 mutex_init(&ab8500->lock); 1292 mutex_init(&ab8500->lock);
1260 mutex_init(&ab8500->irq_lock); 1293 mutex_init(&ab8500->irq_lock);
@@ -1264,9 +1297,6 @@ static int __devinit ab8500_probe(struct platform_device *pdev)
1264 1297
1265 if (platid) 1298 if (platid)
1266 version = platid->driver_data; 1299 version = platid->driver_data;
1267 else if (np)
1268 version = (unsigned int)
1269 of_match_device(ab8500_match, &pdev->dev)->data;
1270 1300
1271 if (version != AB8500_VERSION_UNDEFINED) 1301 if (version != AB8500_VERSION_UNDEFINED)
1272 ab8500->version = version; 1302 ab8500->version = version;
@@ -1323,7 +1353,20 @@ static int __devinit ab8500_probe(struct platform_device *pdev)
1323 AB8500_SWITCH_OFF_STATUS, &value); 1353 AB8500_SWITCH_OFF_STATUS, &value);
1324 if (ret < 0) 1354 if (ret < 0)
1325 return ret; 1355 return ret;
1326 dev_info(ab8500->dev, "switch off status: %#x", value); 1356 dev_info(ab8500->dev, "switch off cause(s) (%#x): ", value);
1357
1358 if (value) {
1359 for (i = 0; i < ARRAY_SIZE(switch_off_status); i++) {
1360 if (value & 1)
1361 printk(KERN_CONT " \"%s\"",
1362 switch_off_status[i]);
1363 value = value >> 1;
1364
1365 }
1366 printk(KERN_CONT "\n");
1367 } else {
1368 printk(KERN_CONT " None\n");
1369 }
1327 1370
1328 if (plat && plat->init) 1371 if (plat && plat->init)
1329 plat->init(ab8500); 1372 plat->init(ab8500);
@@ -1352,53 +1395,50 @@ static int __devinit ab8500_probe(struct platform_device *pdev)
1352 for (i = 0; i < ab8500->mask_size; i++) 1395 for (i = 0; i < ab8500->mask_size; i++)
1353 ab8500->mask[i] = ab8500->oldmask[i] = 0xff; 1396 ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
1354 1397
1355 if (ab8500->irq_base) { 1398 ret = ab8500_irq_init(ab8500, np);
1356 ret = ab8500_irq_init(ab8500); 1399 if (ret)
1357 if (ret) 1400 goto out_freeoldmask;
1358 goto out_freeoldmask;
1359 1401
1360 /* Activate this feature only in ab9540 */ 1402 /* Activate this feature only in ab9540 */
1361 /* till tests are done on ab8500 1p2 or later*/ 1403 /* till tests are done on ab8500 1p2 or later*/
1362 if (is_ab9540(ab8500)) 1404 if (is_ab9540(ab8500)) {
1363 ret = request_threaded_irq(ab8500->irq, NULL, 1405 ret = request_threaded_irq(ab8500->irq, NULL,
1364 ab8500_hierarchical_irq, 1406 ab8500_hierarchical_irq,
1365 IRQF_ONESHOT | IRQF_NO_SUSPEND, 1407 IRQF_ONESHOT | IRQF_NO_SUSPEND,
1366 "ab8500", ab8500); 1408 "ab8500", ab8500);
1367 else 1409 }
1368 ret = request_threaded_irq(ab8500->irq, NULL, 1410 else {
1411 ret = request_threaded_irq(ab8500->irq, NULL,
1369 ab8500_irq, 1412 ab8500_irq,
1370 IRQF_ONESHOT | IRQF_NO_SUSPEND, 1413 IRQF_ONESHOT | IRQF_NO_SUSPEND,
1371 "ab8500", ab8500); 1414 "ab8500", ab8500);
1372 if (ret) 1415 if (ret)
1373 goto out_removeirq; 1416 goto out_freeoldmask;
1374 } 1417 }
1375 1418
1376 if (!np) { 1419 ret = mfd_add_devices(ab8500->dev, 0, abx500_common_devs,
1377 ret = mfd_add_devices(ab8500->dev, 0, abx500_common_devs, 1420 ARRAY_SIZE(abx500_common_devs), NULL,
1378 ARRAY_SIZE(abx500_common_devs), NULL, 1421 ab8500->irq_base);
1379 ab8500->irq_base); 1422 if (ret)
1423 goto out_freeirq;
1380 1424
1381 if (ret) 1425 if (is_ab9540(ab8500))
1382 goto out_freeirq; 1426 ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs,
1383 1427 ARRAY_SIZE(ab9540_devs), NULL,
1384 if (is_ab9540(ab8500)) 1428 ab8500->irq_base);
1385 ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs, 1429 else
1386 ARRAY_SIZE(ab9540_devs), NULL, 1430 ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
1387 ab8500->irq_base); 1431 ARRAY_SIZE(ab8500_devs), NULL,
1388 else 1432 ab8500->irq_base);
1389 ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs, 1433 if (ret)
1390 ARRAY_SIZE(ab8500_devs), NULL, 1434 goto out_freeirq;
1391 ab8500->irq_base);
1392 if (ret)
1393 goto out_freeirq;
1394 1435
1395 if (is_ab9540(ab8500) || is_ab8505(ab8500)) 1436 if (is_ab9540(ab8500) || is_ab8505(ab8500))
1396 ret = mfd_add_devices(ab8500->dev, 0, ab9540_ab8505_devs, 1437 ret = mfd_add_devices(ab8500->dev, 0, ab9540_ab8505_devs,
1397 ARRAY_SIZE(ab9540_ab8505_devs), NULL, 1438 ARRAY_SIZE(ab9540_ab8505_devs), NULL,
1398 ab8500->irq_base); 1439 ab8500->irq_base);
1399 if (ret) 1440 if (ret)
1400 goto out_freeirq; 1441 goto out_freeirq;
1401 }
1402 1442
1403 if (!no_bm) { 1443 if (!no_bm) {
1404 /* Add battery management devices */ 1444 /* Add battery management devices */
@@ -1417,15 +1457,11 @@ static int __devinit ab8500_probe(struct platform_device *pdev)
1417 &ab8500_attr_group); 1457 &ab8500_attr_group);
1418 if (ret) 1458 if (ret)
1419 dev_err(ab8500->dev, "error creating sysfs entries\n"); 1459 dev_err(ab8500->dev, "error creating sysfs entries\n");
1420 else 1460
1421 return ret; 1461 return ret;
1422 1462
1423out_freeirq: 1463out_freeirq:
1424 if (ab8500->irq_base) 1464 free_irq(ab8500->irq, ab8500);
1425 free_irq(ab8500->irq, ab8500);
1426out_removeirq:
1427 if (ab8500->irq_base)
1428 ab8500_irq_remove(ab8500);
1429out_freeoldmask: 1465out_freeoldmask:
1430 kfree(ab8500->oldmask); 1466 kfree(ab8500->oldmask);
1431out_freemask: 1467out_freemask:
@@ -1444,11 +1480,10 @@ static int __devexit ab8500_remove(struct platform_device *pdev)
1444 sysfs_remove_group(&ab8500->dev->kobj, &ab9540_attr_group); 1480 sysfs_remove_group(&ab8500->dev->kobj, &ab9540_attr_group);
1445 else 1481 else
1446 sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group); 1482 sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group);
1483
1447 mfd_remove_devices(ab8500->dev); 1484 mfd_remove_devices(ab8500->dev);
1448 if (ab8500->irq_base) { 1485 free_irq(ab8500->irq, ab8500);
1449 free_irq(ab8500->irq, ab8500); 1486
1450 ab8500_irq_remove(ab8500);
1451 }
1452 kfree(ab8500->oldmask); 1487 kfree(ab8500->oldmask);
1453 kfree(ab8500->mask); 1488 kfree(ab8500->mask);
1454 kfree(ab8500); 1489 kfree(ab8500);
@@ -1468,7 +1503,6 @@ static struct platform_driver ab8500_core_driver = {
1468 .driver = { 1503 .driver = {
1469 .name = "ab8500-core", 1504 .name = "ab8500-core",
1470 .owner = THIS_MODULE, 1505 .owner = THIS_MODULE,
1471 .of_match_table = ab8500_match,
1472 }, 1506 },
1473 .probe = ab8500_probe, 1507 .probe = ab8500_probe,
1474 .remove = __devexit_p(ab8500_remove), 1508 .remove = __devexit_p(ab8500_remove),
@@ -1484,7 +1518,7 @@ static void __exit ab8500_core_exit(void)
1484{ 1518{
1485 platform_driver_unregister(&ab8500_core_driver); 1519 platform_driver_unregister(&ab8500_core_driver);
1486} 1520}
1487arch_initcall(ab8500_core_init); 1521core_initcall(ab8500_core_init);
1488module_exit(ab8500_core_exit); 1522module_exit(ab8500_core_exit);
1489 1523
1490MODULE_AUTHOR("Mattias Wallin, Srinidhi Kasagar, Rabin Vincent"); 1524MODULE_AUTHOR("Mattias Wallin, Srinidhi Kasagar, Rabin Vincent");
diff --git a/drivers/mfd/ab8500-debugfs.c b/drivers/mfd/ab8500-debugfs.c
index 50c4c89ab220..c4cb806978ac 100644
--- a/drivers/mfd/ab8500-debugfs.c
+++ b/drivers/mfd/ab8500-debugfs.c
@@ -31,12 +31,12 @@ struct ab8500_reg_range {
31}; 31};
32 32
33/** 33/**
34 * struct ab8500_i2c_ranges 34 * struct ab8500_prcmu_ranges
35 * @num_ranges: the number of ranges in the list 35 * @num_ranges: the number of ranges in the list
36 * @bankid: bank identifier 36 * @bankid: bank identifier
37 * @range: the list of register ranges 37 * @range: the list of register ranges
38 */ 38 */
39struct ab8500_i2c_ranges { 39struct ab8500_prcmu_ranges {
40 u8 num_ranges; 40 u8 num_ranges;
41 u8 bankid; 41 u8 bankid;
42 const struct ab8500_reg_range *range; 42 const struct ab8500_reg_range *range;
@@ -47,7 +47,7 @@ struct ab8500_i2c_ranges {
47 47
48#define AB8500_REV_REG 0x80 48#define AB8500_REV_REG 0x80
49 49
50static struct ab8500_i2c_ranges debug_ranges[AB8500_NUM_BANKS] = { 50static struct ab8500_prcmu_ranges debug_ranges[AB8500_NUM_BANKS] = {
51 [0x0] = { 51 [0x0] = {
52 .num_ranges = 0, 52 .num_ranges = 0,
53 .range = 0, 53 .range = 0,
@@ -608,16 +608,10 @@ static int __devexit ab8500_debug_remove(struct platform_device *plf)
608 return 0; 608 return 0;
609} 609}
610 610
611static const struct of_device_id ab8500_debug_match[] = {
612 { .compatible = "stericsson,ab8500-debug", },
613 {}
614};
615
616static struct platform_driver ab8500_debug_driver = { 611static struct platform_driver ab8500_debug_driver = {
617 .driver = { 612 .driver = {
618 .name = "ab8500-debug", 613 .name = "ab8500-debug",
619 .owner = THIS_MODULE, 614 .owner = THIS_MODULE,
620 .of_match_table = ab8500_debug_match,
621 }, 615 },
622 .probe = ab8500_debug_probe, 616 .probe = ab8500_debug_probe,
623 .remove = __devexit_p(ab8500_debug_remove) 617 .remove = __devexit_p(ab8500_debug_remove)
diff --git a/drivers/mfd/ab8500-gpadc.c b/drivers/mfd/ab8500-gpadc.c
index b86fd8e1ec3f..866f95960b4b 100644
--- a/drivers/mfd/ab8500-gpadc.c
+++ b/drivers/mfd/ab8500-gpadc.c
@@ -599,7 +599,8 @@ static int __devinit ab8500_gpadc_probe(struct platform_device *pdev)
599 /* Register interrupt - SwAdcComplete */ 599 /* Register interrupt - SwAdcComplete */
600 ret = request_threaded_irq(gpadc->irq, NULL, 600 ret = request_threaded_irq(gpadc->irq, NULL,
601 ab8500_bm_gpswadcconvend_handler, 601 ab8500_bm_gpswadcconvend_handler,
602 IRQF_NO_SUSPEND | IRQF_SHARED, "ab8500-gpadc", gpadc); 602 IRQF_ONESHOT | IRQF_NO_SUSPEND | IRQF_SHARED,
603 "ab8500-gpadc", gpadc);
603 if (ret < 0) { 604 if (ret < 0) {
604 dev_err(gpadc->dev, "Failed to register interrupt, irq: %d\n", 605 dev_err(gpadc->dev, "Failed to register interrupt, irq: %d\n",
605 gpadc->irq); 606 gpadc->irq);
@@ -648,18 +649,12 @@ static int __devexit ab8500_gpadc_remove(struct platform_device *pdev)
648 return 0; 649 return 0;
649} 650}
650 651
651static const struct of_device_id ab8500_gpadc_match[] = {
652 { .compatible = "stericsson,ab8500-gpadc", },
653 {}
654};
655
656static struct platform_driver ab8500_gpadc_driver = { 652static struct platform_driver ab8500_gpadc_driver = {
657 .probe = ab8500_gpadc_probe, 653 .probe = ab8500_gpadc_probe,
658 .remove = __devexit_p(ab8500_gpadc_remove), 654 .remove = __devexit_p(ab8500_gpadc_remove),
659 .driver = { 655 .driver = {
660 .name = "ab8500-gpadc", 656 .name = "ab8500-gpadc",
661 .owner = THIS_MODULE, 657 .owner = THIS_MODULE,
662 .of_match_table = ab8500_gpadc_match,
663 }, 658 },
664}; 659};
665 660
diff --git a/drivers/mfd/ab8500-sysctrl.c b/drivers/mfd/ab8500-sysctrl.c
index 5a3e51ccf258..c28d4eb1eff0 100644
--- a/drivers/mfd/ab8500-sysctrl.c
+++ b/drivers/mfd/ab8500-sysctrl.c
@@ -61,16 +61,10 @@ static int __devexit ab8500_sysctrl_remove(struct platform_device *pdev)
61 return 0; 61 return 0;
62} 62}
63 63
64static const struct of_device_id ab8500_sysctrl_match[] = {
65 { .compatible = "stericsson,ab8500-sysctrl", },
66 {}
67};
68
69static struct platform_driver ab8500_sysctrl_driver = { 64static struct platform_driver ab8500_sysctrl_driver = {
70 .driver = { 65 .driver = {
71 .name = "ab8500-sysctrl", 66 .name = "ab8500-sysctrl",
72 .owner = THIS_MODULE, 67 .owner = THIS_MODULE,
73 .of_match_table = ab8500_sysctrl_match,
74 }, 68 },
75 .probe = ab8500_sysctrl_probe, 69 .probe = ab8500_sysctrl_probe,
76 .remove = __devexit_p(ab8500_sysctrl_remove), 70 .remove = __devexit_p(ab8500_sysctrl_remove),
diff --git a/drivers/mfd/adp5520.c b/drivers/mfd/adp5520.c
index 8d816cce8322..ea8b9475731d 100644
--- a/drivers/mfd/adp5520.c
+++ b/drivers/mfd/adp5520.c
@@ -320,7 +320,7 @@ static int __devexit adp5520_remove(struct i2c_client *client)
320 return 0; 320 return 0;
321} 321}
322 322
323#ifdef CONFIG_PM 323#ifdef CONFIG_PM_SLEEP
324static int adp5520_suspend(struct device *dev) 324static int adp5520_suspend(struct device *dev)
325{ 325{
326 struct i2c_client *client = to_i2c_client(dev); 326 struct i2c_client *client = to_i2c_client(dev);
diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
index 6da06341f6c9..5576e07576de 100644
--- a/drivers/mfd/anatop-mfd.c
+++ b/drivers/mfd/anatop-mfd.c
@@ -83,7 +83,7 @@ static int __devinit of_anatop_probe(struct platform_device *pdev)
83 drvdata->ioreg = ioreg; 83 drvdata->ioreg = ioreg;
84 spin_lock_init(&drvdata->reglock); 84 spin_lock_init(&drvdata->reglock);
85 platform_set_drvdata(pdev, drvdata); 85 platform_set_drvdata(pdev, drvdata);
86 of_platform_populate(np, of_anatop_match, NULL, dev); 86 of_platform_populate(np, NULL, NULL, dev);
87 87
88 return 0; 88 return 0;
89} 89}
diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c
new file mode 100644
index 000000000000..c7983e862549
--- /dev/null
+++ b/drivers/mfd/arizona-core.c
@@ -0,0 +1,566 @@
1/*
2 * Arizona core driver
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/gpio.h>
16#include <linux/interrupt.h>
17#include <linux/mfd/core.h>
18#include <linux/module.h>
19#include <linux/pm_runtime.h>
20#include <linux/regmap.h>
21#include <linux/regulator/consumer.h>
22#include <linux/slab.h>
23
24#include <linux/mfd/arizona/core.h>
25#include <linux/mfd/arizona/registers.h>
26
27#include "arizona.h"
28
29static const char *wm5102_core_supplies[] = {
30 "AVDD",
31 "DBVDD1",
32};
33
34int arizona_clk32k_enable(struct arizona *arizona)
35{
36 int ret = 0;
37
38 mutex_lock(&arizona->clk_lock);
39
40 arizona->clk32k_ref++;
41
42 if (arizona->clk32k_ref == 1)
43 ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
44 ARIZONA_CLK_32K_ENA,
45 ARIZONA_CLK_32K_ENA);
46
47 if (ret != 0)
48 arizona->clk32k_ref--;
49
50 mutex_unlock(&arizona->clk_lock);
51
52 return ret;
53}
54EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
55
56int arizona_clk32k_disable(struct arizona *arizona)
57{
58 int ret = 0;
59
60 mutex_lock(&arizona->clk_lock);
61
62 BUG_ON(arizona->clk32k_ref <= 0);
63
64 arizona->clk32k_ref--;
65
66 if (arizona->clk32k_ref == 0)
67 regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
68 ARIZONA_CLK_32K_ENA, 0);
69
70 mutex_unlock(&arizona->clk_lock);
71
72 return ret;
73}
74EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
75
76static irqreturn_t arizona_clkgen_err(int irq, void *data)
77{
78 struct arizona *arizona = data;
79
80 dev_err(arizona->dev, "CLKGEN error\n");
81
82 return IRQ_HANDLED;
83}
84
85static irqreturn_t arizona_underclocked(int irq, void *data)
86{
87 struct arizona *arizona = data;
88 unsigned int val;
89 int ret;
90
91 ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
92 &val);
93 if (ret != 0) {
94 dev_err(arizona->dev, "Failed to read underclock status: %d\n",
95 ret);
96 return IRQ_NONE;
97 }
98
99 if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
100 dev_err(arizona->dev, "AIF3 underclocked\n");
101 if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
102 dev_err(arizona->dev, "AIF3 underclocked\n");
103 if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
104 dev_err(arizona->dev, "AIF1 underclocked\n");
105 if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
106 dev_err(arizona->dev, "ISRC2 underclocked\n");
107 if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
108 dev_err(arizona->dev, "ISRC1 underclocked\n");
109 if (val & ARIZONA_FX_UNDERCLOCKED_STS)
110 dev_err(arizona->dev, "FX underclocked\n");
111 if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
112 dev_err(arizona->dev, "ASRC underclocked\n");
113 if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
114 dev_err(arizona->dev, "DAC underclocked\n");
115 if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
116 dev_err(arizona->dev, "ADC underclocked\n");
117 if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
118 dev_err(arizona->dev, "Mixer underclocked\n");
119
120 return IRQ_HANDLED;
121}
122
123static irqreturn_t arizona_overclocked(int irq, void *data)
124{
125 struct arizona *arizona = data;
126 unsigned int val[2];
127 int ret;
128
129 ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
130 &val[0], 2);
131 if (ret != 0) {
132 dev_err(arizona->dev, "Failed to read overclock status: %d\n",
133 ret);
134 return IRQ_NONE;
135 }
136
137 if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
138 dev_err(arizona->dev, "PWM overclocked\n");
139 if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
140 dev_err(arizona->dev, "FX core overclocked\n");
141 if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
142 dev_err(arizona->dev, "DAC SYS overclocked\n");
143 if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
144 dev_err(arizona->dev, "DAC WARP overclocked\n");
145 if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
146 dev_err(arizona->dev, "ADC overclocked\n");
147 if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
148 dev_err(arizona->dev, "Mixer overclocked\n");
149 if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
150 dev_err(arizona->dev, "AIF3 overclocked\n");
151 if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
152 dev_err(arizona->dev, "AIF2 overclocked\n");
153 if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
154 dev_err(arizona->dev, "AIF1 overclocked\n");
155 if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
156 dev_err(arizona->dev, "Pad control overclocked\n");
157
158 if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
159 dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
160 if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
161 dev_err(arizona->dev, "Slimbus async overclocked\n");
162 if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
163 dev_err(arizona->dev, "Slimbus sync overclocked\n");
164 if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
165 dev_err(arizona->dev, "ASRC async system overclocked\n");
166 if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
167 dev_err(arizona->dev, "ASRC async WARP overclocked\n");
168 if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
169 dev_err(arizona->dev, "ASRC sync system overclocked\n");
170 if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
171 dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
172 if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
173 dev_err(arizona->dev, "DSP1 overclocked\n");
174 if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
175 dev_err(arizona->dev, "ISRC2 overclocked\n");
176 if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
177 dev_err(arizona->dev, "ISRC1 overclocked\n");
178
179 return IRQ_HANDLED;
180}
181
182static int arizona_wait_for_boot(struct arizona *arizona)
183{
184 unsigned int reg;
185 int ret, i;
186
187 /*
188 * We can't use an interrupt as we need to runtime resume to do so,
189 * we won't race with the interrupt handler as it'll be blocked on
190 * runtime resume.
191 */
192 for (i = 0; i < 5; i++) {
193 msleep(1);
194
195 ret = regmap_read(arizona->regmap,
196 ARIZONA_INTERRUPT_RAW_STATUS_5, &reg);
197 if (ret != 0) {
198 dev_err(arizona->dev, "Failed to read boot state: %d\n",
199 ret);
200 continue;
201 }
202
203 if (reg & ARIZONA_BOOT_DONE_STS)
204 break;
205 }
206
207 if (reg & ARIZONA_BOOT_DONE_STS) {
208 regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
209 ARIZONA_BOOT_DONE_STS);
210 } else {
211 dev_err(arizona->dev, "Device boot timed out: %x\n", reg);
212 return -ETIMEDOUT;
213 }
214
215 pm_runtime_mark_last_busy(arizona->dev);
216
217 return 0;
218}
219
220#ifdef CONFIG_PM_RUNTIME
221static int arizona_runtime_resume(struct device *dev)
222{
223 struct arizona *arizona = dev_get_drvdata(dev);
224 int ret;
225
226 dev_dbg(arizona->dev, "Leaving AoD mode\n");
227
228 ret = regulator_enable(arizona->dcvdd);
229 if (ret != 0) {
230 dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret);
231 return ret;
232 }
233
234 regcache_cache_only(arizona->regmap, false);
235
236 ret = arizona_wait_for_boot(arizona);
237 if (ret != 0) {
238 regulator_disable(arizona->dcvdd);
239 return ret;
240 }
241
242 regcache_sync(arizona->regmap);
243
244 return 0;
245}
246
247static int arizona_runtime_suspend(struct device *dev)
248{
249 struct arizona *arizona = dev_get_drvdata(dev);
250
251 dev_dbg(arizona->dev, "Entering AoD mode\n");
252
253 regulator_disable(arizona->dcvdd);
254 regcache_cache_only(arizona->regmap, true);
255 regcache_mark_dirty(arizona->regmap);
256
257 return 0;
258}
259#endif
260
261const struct dev_pm_ops arizona_pm_ops = {
262 SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
263 arizona_runtime_resume,
264 NULL)
265};
266EXPORT_SYMBOL_GPL(arizona_pm_ops);
267
268static struct mfd_cell early_devs[] = {
269 { .name = "arizona-ldo1" },
270};
271
272static struct mfd_cell wm5102_devs[] = {
273 { .name = "arizona-extcon" },
274 { .name = "arizona-gpio" },
275 { .name = "arizona-micsupp" },
276 { .name = "arizona-pwm" },
277 { .name = "wm5102-codec" },
278};
279
280static struct mfd_cell wm5110_devs[] = {
281 { .name = "arizona-extcon" },
282 { .name = "arizona-gpio" },
283 { .name = "arizona-micsupp" },
284 { .name = "arizona-pwm" },
285 { .name = "wm5110-codec" },
286};
287
288int __devinit arizona_dev_init(struct arizona *arizona)
289{
290 struct device *dev = arizona->dev;
291 const char *type_name;
292 unsigned int reg, val;
293 int ret, i;
294
295 dev_set_drvdata(arizona->dev, arizona);
296 mutex_init(&arizona->clk_lock);
297
298 if (dev_get_platdata(arizona->dev))
299 memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
300 sizeof(arizona->pdata));
301
302 regcache_cache_only(arizona->regmap, true);
303
304 switch (arizona->type) {
305 case WM5102:
306 case WM5110:
307 for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
308 arizona->core_supplies[i].supply
309 = wm5102_core_supplies[i];
310 arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
311 break;
312 default:
313 dev_err(arizona->dev, "Unknown device type %d\n",
314 arizona->type);
315 return -EINVAL;
316 }
317
318 ret = mfd_add_devices(arizona->dev, -1, early_devs,
319 ARRAY_SIZE(early_devs), NULL, 0);
320 if (ret != 0) {
321 dev_err(dev, "Failed to add early children: %d\n", ret);
322 return ret;
323 }
324
325 ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
326 arizona->core_supplies);
327 if (ret != 0) {
328 dev_err(dev, "Failed to request core supplies: %d\n",
329 ret);
330 goto err_early;
331 }
332
333 arizona->dcvdd = devm_regulator_get(arizona->dev, "DCVDD");
334 if (IS_ERR(arizona->dcvdd)) {
335 ret = PTR_ERR(arizona->dcvdd);
336 dev_err(dev, "Failed to request DCVDD: %d\n", ret);
337 goto err_early;
338 }
339
340 ret = regulator_bulk_enable(arizona->num_core_supplies,
341 arizona->core_supplies);
342 if (ret != 0) {
343 dev_err(dev, "Failed to enable core supplies: %d\n",
344 ret);
345 goto err_early;
346 }
347
348 ret = regulator_enable(arizona->dcvdd);
349 if (ret != 0) {
350 dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
351 goto err_enable;
352 }
353
354 if (arizona->pdata.reset) {
355 /* Start out with /RESET low to put the chip into reset */
356 ret = gpio_request_one(arizona->pdata.reset,
357 GPIOF_DIR_OUT | GPIOF_INIT_LOW,
358 "arizona /RESET");
359 if (ret != 0) {
360 dev_err(dev, "Failed to request /RESET: %d\n", ret);
361 goto err_dcvdd;
362 }
363
364 gpio_set_value_cansleep(arizona->pdata.reset, 1);
365 }
366
367 regcache_cache_only(arizona->regmap, false);
368
369 ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
370 if (ret != 0) {
371 dev_err(dev, "Failed to read ID register: %d\n", ret);
372 goto err_reset;
373 }
374
375 ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
376 &arizona->rev);
377 if (ret != 0) {
378 dev_err(dev, "Failed to read revision register: %d\n", ret);
379 goto err_reset;
380 }
381 arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
382
383 switch (reg) {
384#ifdef CONFIG_MFD_WM5102
385 case 0x5102:
386 type_name = "WM5102";
387 if (arizona->type != WM5102) {
388 dev_err(arizona->dev, "WM5102 registered as %d\n",
389 arizona->type);
390 arizona->type = WM5102;
391 }
392 ret = wm5102_patch(arizona);
393 break;
394#endif
395#ifdef CONFIG_MFD_WM5110
396 case 0x5110:
397 type_name = "WM5110";
398 if (arizona->type != WM5110) {
399 dev_err(arizona->dev, "WM5110 registered as %d\n",
400 arizona->type);
401 arizona->type = WM5110;
402 }
403 ret = wm5110_patch(arizona);
404 break;
405#endif
406 default:
407 dev_err(arizona->dev, "Unknown device ID %x\n", reg);
408 goto err_reset;
409 }
410
411 dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
412
413 if (ret != 0)
414 dev_err(arizona->dev, "Failed to apply patch: %d\n", ret);
415
416 /* If we have a /RESET GPIO we'll already be reset */
417 if (!arizona->pdata.reset) {
418 ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
419 if (ret != 0) {
420 dev_err(dev, "Failed to reset device: %d\n", ret);
421 goto err_reset;
422 }
423 }
424
425 ret = arizona_wait_for_boot(arizona);
426 if (ret != 0) {
427 dev_err(arizona->dev, "Device failed initial boot: %d\n", ret);
428 goto err_reset;
429 }
430
431 for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
432 if (!arizona->pdata.gpio_defaults[i])
433 continue;
434
435 regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
436 arizona->pdata.gpio_defaults[i]);
437 }
438
439 pm_runtime_set_autosuspend_delay(arizona->dev, 100);
440 pm_runtime_use_autosuspend(arizona->dev);
441 pm_runtime_enable(arizona->dev);
442
443 /* Chip default */
444 if (!arizona->pdata.clk32k_src)
445 arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
446
447 switch (arizona->pdata.clk32k_src) {
448 case ARIZONA_32KZ_MCLK1:
449 case ARIZONA_32KZ_MCLK2:
450 regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
451 ARIZONA_CLK_32K_SRC_MASK,
452 arizona->pdata.clk32k_src - 1);
453 break;
454 case ARIZONA_32KZ_NONE:
455 regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
456 ARIZONA_CLK_32K_SRC_MASK, 2);
457 break;
458 default:
459 dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
460 arizona->pdata.clk32k_src);
461 ret = -EINVAL;
462 goto err_reset;
463 }
464
465 for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
466 /* Default for both is 0 so noop with defaults */
467 val = arizona->pdata.dmic_ref[i]
468 << ARIZONA_IN1_DMIC_SUP_SHIFT;
469 val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT;
470
471 regmap_update_bits(arizona->regmap,
472 ARIZONA_IN1L_CONTROL + (i * 8),
473 ARIZONA_IN1_DMIC_SUP_MASK |
474 ARIZONA_IN1_MODE_MASK, val);
475 }
476
477 for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
478 /* Default is 0 so noop with defaults */
479 if (arizona->pdata.out_mono[i])
480 val = ARIZONA_OUT1_MONO;
481 else
482 val = 0;
483
484 regmap_update_bits(arizona->regmap,
485 ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
486 ARIZONA_OUT1_MONO, val);
487 }
488
489 for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
490 if (arizona->pdata.spk_mute[i])
491 regmap_update_bits(arizona->regmap,
492 ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
493 ARIZONA_SPK1_MUTE_ENDIAN_MASK |
494 ARIZONA_SPK1_MUTE_SEQ1_MASK,
495 arizona->pdata.spk_mute[i]);
496
497 if (arizona->pdata.spk_fmt[i])
498 regmap_update_bits(arizona->regmap,
499 ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
500 ARIZONA_SPK1_FMT_MASK,
501 arizona->pdata.spk_fmt[i]);
502 }
503
504 /* Set up for interrupts */
505 ret = arizona_irq_init(arizona);
506 if (ret != 0)
507 goto err_reset;
508
509 arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
510 arizona_clkgen_err, arizona);
511 arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
512 arizona_overclocked, arizona);
513 arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
514 arizona_underclocked, arizona);
515
516 switch (arizona->type) {
517 case WM5102:
518 ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
519 ARRAY_SIZE(wm5102_devs), NULL, 0);
520 break;
521 case WM5110:
522 ret = mfd_add_devices(arizona->dev, -1, wm5110_devs,
523 ARRAY_SIZE(wm5102_devs), NULL, 0);
524 break;
525 }
526
527 if (ret != 0) {
528 dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
529 goto err_irq;
530 }
531
532#ifdef CONFIG_PM_RUNTIME
533 regulator_disable(arizona->dcvdd);
534#endif
535
536 return 0;
537
538err_irq:
539 arizona_irq_exit(arizona);
540err_reset:
541 if (arizona->pdata.reset) {
542 gpio_set_value_cansleep(arizona->pdata.reset, 1);
543 gpio_free(arizona->pdata.reset);
544 }
545err_dcvdd:
546 regulator_disable(arizona->dcvdd);
547err_enable:
548 regulator_bulk_disable(arizona->num_core_supplies,
549 arizona->core_supplies);
550err_early:
551 mfd_remove_devices(dev);
552 return ret;
553}
554EXPORT_SYMBOL_GPL(arizona_dev_init);
555
556int __devexit arizona_dev_exit(struct arizona *arizona)
557{
558 mfd_remove_devices(arizona->dev);
559 arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
560 arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
561 arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
562 pm_runtime_disable(arizona->dev);
563 arizona_irq_exit(arizona);
564 return 0;
565}
566EXPORT_SYMBOL_GPL(arizona_dev_exit);
diff --git a/drivers/mfd/arizona-i2c.c b/drivers/mfd/arizona-i2c.c
new file mode 100644
index 000000000000..570c4b438086
--- /dev/null
+++ b/drivers/mfd/arizona-i2c.c
@@ -0,0 +1,97 @@
1/*
2 * Arizona-i2c.c -- Arizona I2C bus interface
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/i2c.h>
15#include <linux/module.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18#include <linux/regulator/consumer.h>
19#include <linux/slab.h>
20
21#include <linux/mfd/arizona/core.h>
22
23#include "arizona.h"
24
25static __devinit int arizona_i2c_probe(struct i2c_client *i2c,
26 const struct i2c_device_id *id)
27{
28 struct arizona *arizona;
29 const struct regmap_config *regmap_config;
30 int ret;
31
32 switch (id->driver_data) {
33#ifdef CONFIG_MFD_WM5102
34 case WM5102:
35 regmap_config = &wm5102_i2c_regmap;
36 break;
37#endif
38#ifdef CONFIG_MFD_WM5110
39 case WM5110:
40 regmap_config = &wm5110_i2c_regmap;
41 break;
42#endif
43 default:
44 dev_err(&i2c->dev, "Unknown device type %ld\n",
45 id->driver_data);
46 return -EINVAL;
47 }
48
49 arizona = devm_kzalloc(&i2c->dev, sizeof(*arizona), GFP_KERNEL);
50 if (arizona == NULL)
51 return -ENOMEM;
52
53 arizona->regmap = devm_regmap_init_i2c(i2c, regmap_config);
54 if (IS_ERR(arizona->regmap)) {
55 ret = PTR_ERR(arizona->regmap);
56 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
57 ret);
58 return ret;
59 }
60
61 arizona->type = id->driver_data;
62 arizona->dev = &i2c->dev;
63 arizona->irq = i2c->irq;
64
65 return arizona_dev_init(arizona);
66}
67
68static int __devexit arizona_i2c_remove(struct i2c_client *i2c)
69{
70 struct arizona *arizona = dev_get_drvdata(&i2c->dev);
71 arizona_dev_exit(arizona);
72 return 0;
73}
74
75static const struct i2c_device_id arizona_i2c_id[] = {
76 { "wm5102", WM5102 },
77 { "wm5110", WM5110 },
78 { }
79};
80MODULE_DEVICE_TABLE(i2c, arizona_i2c_id);
81
82static struct i2c_driver arizona_i2c_driver = {
83 .driver = {
84 .name = "arizona",
85 .owner = THIS_MODULE,
86 .pm = &arizona_pm_ops,
87 },
88 .probe = arizona_i2c_probe,
89 .remove = __devexit_p(arizona_i2c_remove),
90 .id_table = arizona_i2c_id,
91};
92
93module_i2c_driver(arizona_i2c_driver);
94
95MODULE_DESCRIPTION("Arizona I2C bus interface");
96MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
97MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/arizona-irq.c b/drivers/mfd/arizona-irq.c
new file mode 100644
index 000000000000..98ac345f468e
--- /dev/null
+++ b/drivers/mfd/arizona-irq.c
@@ -0,0 +1,275 @@
1/*
2 * Arizona interrupt support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/delay.h>
14#include <linux/gpio.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/irqdomain.h>
18#include <linux/module.h>
19#include <linux/pm_runtime.h>
20#include <linux/regmap.h>
21#include <linux/regulator/consumer.h>
22#include <linux/slab.h>
23
24#include <linux/mfd/arizona/core.h>
25#include <linux/mfd/arizona/registers.h>
26
27#include "arizona.h"
28
29static int arizona_map_irq(struct arizona *arizona, int irq)
30{
31 int ret;
32
33 ret = regmap_irq_get_virq(arizona->aod_irq_chip, irq);
34 if (ret < 0)
35 ret = regmap_irq_get_virq(arizona->irq_chip, irq);
36
37 return ret;
38}
39
40int arizona_request_irq(struct arizona *arizona, int irq, char *name,
41 irq_handler_t handler, void *data)
42{
43 irq = arizona_map_irq(arizona, irq);
44 if (irq < 0)
45 return irq;
46
47 return request_threaded_irq(irq, NULL, handler, IRQF_ONESHOT,
48 name, data);
49}
50EXPORT_SYMBOL_GPL(arizona_request_irq);
51
52void arizona_free_irq(struct arizona *arizona, int irq, void *data)
53{
54 irq = arizona_map_irq(arizona, irq);
55 if (irq < 0)
56 return;
57
58 free_irq(irq, data);
59}
60EXPORT_SYMBOL_GPL(arizona_free_irq);
61
62int arizona_set_irq_wake(struct arizona *arizona, int irq, int on)
63{
64 irq = arizona_map_irq(arizona, irq);
65 if (irq < 0)
66 return irq;
67
68 return irq_set_irq_wake(irq, on);
69}
70EXPORT_SYMBOL_GPL(arizona_set_irq_wake);
71
72static irqreturn_t arizona_boot_done(int irq, void *data)
73{
74 struct arizona *arizona = data;
75
76 dev_dbg(arizona->dev, "Boot done\n");
77
78 return IRQ_HANDLED;
79}
80
81static irqreturn_t arizona_ctrlif_err(int irq, void *data)
82{
83 struct arizona *arizona = data;
84
85 /*
86 * For pretty much all potential sources a register cache sync
87 * won't help, we've just got a software bug somewhere.
88 */
89 dev_err(arizona->dev, "Control interface error\n");
90
91 return IRQ_HANDLED;
92}
93
94static irqreturn_t arizona_irq_thread(int irq, void *data)
95{
96 struct arizona *arizona = data;
97 int i, ret;
98
99 ret = pm_runtime_get_sync(arizona->dev);
100 if (ret < 0) {
101 dev_err(arizona->dev, "Failed to resume device: %d\n", ret);
102 return IRQ_NONE;
103 }
104
105 /* Check both domains */
106 for (i = 0; i < 2; i++)
107 handle_nested_irq(irq_find_mapping(arizona->virq, i));
108
109 pm_runtime_mark_last_busy(arizona->dev);
110 pm_runtime_put_autosuspend(arizona->dev);
111
112 return IRQ_HANDLED;
113}
114
115static void arizona_irq_enable(struct irq_data *data)
116{
117}
118
119static void arizona_irq_disable(struct irq_data *data)
120{
121}
122
123static struct irq_chip arizona_irq_chip = {
124 .name = "arizona",
125 .irq_disable = arizona_irq_disable,
126 .irq_enable = arizona_irq_enable,
127};
128
129static int arizona_irq_map(struct irq_domain *h, unsigned int virq,
130 irq_hw_number_t hw)
131{
132 struct regmap_irq_chip_data *data = h->host_data;
133
134 irq_set_chip_data(virq, data);
135 irq_set_chip_and_handler(virq, &arizona_irq_chip, handle_edge_irq);
136 irq_set_nested_thread(virq, 1);
137
138 /* ARM needs us to explicitly flag the IRQ as valid
139 * and will set them noprobe when we do so. */
140#ifdef CONFIG_ARM
141 set_irq_flags(virq, IRQF_VALID);
142#else
143 irq_set_noprobe(virq);
144#endif
145
146 return 0;
147}
148
149static struct irq_domain_ops arizona_domain_ops = {
150 .map = arizona_irq_map,
151 .xlate = irq_domain_xlate_twocell,
152};
153
154int arizona_irq_init(struct arizona *arizona)
155{
156 int flags = IRQF_ONESHOT;
157 int ret, i;
158 const struct regmap_irq_chip *aod, *irq;
159
160 switch (arizona->type) {
161#ifdef CONFIG_MFD_WM5102
162 case WM5102:
163 aod = &wm5102_aod;
164 irq = &wm5102_irq;
165 break;
166#endif
167#ifdef CONFIG_MFD_WM5110
168 case WM5110:
169 aod = &wm5110_aod;
170 irq = &wm5110_irq;
171 break;
172#endif
173 default:
174 BUG_ON("Unknown Arizona class device" == NULL);
175 return -EINVAL;
176 }
177
178 if (arizona->pdata.irq_active_high) {
179 ret = regmap_update_bits(arizona->regmap, ARIZONA_IRQ_CTRL_1,
180 ARIZONA_IRQ_POL, 0);
181 if (ret != 0) {
182 dev_err(arizona->dev, "Couldn't set IRQ polarity: %d\n",
183 ret);
184 goto err;
185 }
186
187 flags |= IRQF_TRIGGER_HIGH;
188 } else {
189 flags |= IRQF_TRIGGER_LOW;
190 }
191
192 /* Allocate a virtual IRQ domain to distribute to the regmap domains */
193 arizona->virq = irq_domain_add_linear(NULL, 2, &arizona_domain_ops,
194 arizona);
195 if (!arizona->virq) {
196 ret = -EINVAL;
197 goto err;
198 }
199
200 ret = regmap_add_irq_chip(arizona->regmap,
201 irq_create_mapping(arizona->virq, 0),
202 IRQF_ONESHOT, -1, aod,
203 &arizona->aod_irq_chip);
204 if (ret != 0) {
205 dev_err(arizona->dev, "Failed to add AOD IRQs: %d\n", ret);
206 goto err_domain;
207 }
208
209 ret = regmap_add_irq_chip(arizona->regmap,
210 irq_create_mapping(arizona->virq, 1),
211 IRQF_ONESHOT, -1, irq,
212 &arizona->irq_chip);
213 if (ret != 0) {
214 dev_err(arizona->dev, "Failed to add AOD IRQs: %d\n", ret);
215 goto err_aod;
216 }
217
218 /* Make sure the boot done IRQ is unmasked for resumes */
219 i = arizona_map_irq(arizona, ARIZONA_IRQ_BOOT_DONE);
220 ret = request_threaded_irq(i, NULL, arizona_boot_done, IRQF_ONESHOT,
221 "Boot done", arizona);
222 if (ret != 0) {
223 dev_err(arizona->dev, "Failed to request boot done %d: %d\n",
224 arizona->irq, ret);
225 goto err_boot_done;
226 }
227
228 /* Handle control interface errors in the core */
229 i = arizona_map_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR);
230 ret = request_threaded_irq(i, NULL, arizona_ctrlif_err, IRQF_ONESHOT,
231 "Control interface error", arizona);
232 if (ret != 0) {
233 dev_err(arizona->dev, "Failed to request boot done %d: %d\n",
234 arizona->irq, ret);
235 goto err_ctrlif;
236 }
237
238 ret = request_threaded_irq(arizona->irq, NULL, arizona_irq_thread,
239 flags, "arizona", arizona);
240
241 if (ret != 0) {
242 dev_err(arizona->dev, "Failed to request IRQ %d: %d\n",
243 arizona->irq, ret);
244 goto err_main_irq;
245 }
246
247 return 0;
248
249err_main_irq:
250 free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR), arizona);
251err_ctrlif:
252 free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_BOOT_DONE), arizona);
253err_boot_done:
254 regmap_del_irq_chip(irq_create_mapping(arizona->virq, 1),
255 arizona->irq_chip);
256err_aod:
257 regmap_del_irq_chip(irq_create_mapping(arizona->virq, 0),
258 arizona->aod_irq_chip);
259err_domain:
260err:
261 return ret;
262}
263
264int arizona_irq_exit(struct arizona *arizona)
265{
266 free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR), arizona);
267 free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_BOOT_DONE), arizona);
268 regmap_del_irq_chip(irq_create_mapping(arizona->virq, 1),
269 arizona->irq_chip);
270 regmap_del_irq_chip(irq_create_mapping(arizona->virq, 0),
271 arizona->aod_irq_chip);
272 free_irq(arizona->irq, arizona);
273
274 return 0;
275}
diff --git a/drivers/mfd/arizona-spi.c b/drivers/mfd/arizona-spi.c
new file mode 100644
index 000000000000..df2e5a8bee28
--- /dev/null
+++ b/drivers/mfd/arizona-spi.c
@@ -0,0 +1,97 @@
1/*
2 * arizona-spi.c -- Arizona SPI bus interface
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/module.h>
15#include <linux/pm_runtime.h>
16#include <linux/regmap.h>
17#include <linux/regulator/consumer.h>
18#include <linux/slab.h>
19#include <linux/spi/spi.h>
20
21#include <linux/mfd/arizona/core.h>
22
23#include "arizona.h"
24
25static int __devinit arizona_spi_probe(struct spi_device *spi)
26{
27 const struct spi_device_id *id = spi_get_device_id(spi);
28 struct arizona *arizona;
29 const struct regmap_config *regmap_config;
30 int ret;
31
32 switch (id->driver_data) {
33#ifdef CONFIG_MFD_WM5102
34 case WM5102:
35 regmap_config = &wm5102_spi_regmap;
36 break;
37#endif
38#ifdef CONFIG_MFD_WM5110
39 case WM5110:
40 regmap_config = &wm5110_spi_regmap;
41 break;
42#endif
43 default:
44 dev_err(&spi->dev, "Unknown device type %ld\n",
45 id->driver_data);
46 return -EINVAL;
47 }
48
49 arizona = devm_kzalloc(&spi->dev, sizeof(*arizona), GFP_KERNEL);
50 if (arizona == NULL)
51 return -ENOMEM;
52
53 arizona->regmap = devm_regmap_init_spi(spi, regmap_config);
54 if (IS_ERR(arizona->regmap)) {
55 ret = PTR_ERR(arizona->regmap);
56 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
57 ret);
58 return ret;
59 }
60
61 arizona->type = id->driver_data;
62 arizona->dev = &spi->dev;
63 arizona->irq = spi->irq;
64
65 return arizona_dev_init(arizona);
66}
67
68static int __devexit arizona_spi_remove(struct spi_device *spi)
69{
70 struct arizona *arizona = dev_get_drvdata(&spi->dev);
71 arizona_dev_exit(arizona);
72 return 0;
73}
74
75static const struct spi_device_id arizona_spi_ids[] = {
76 { "wm5102", WM5102 },
77 { "wm5110", WM5110 },
78 { },
79};
80MODULE_DEVICE_TABLE(spi, arizona_spi_ids);
81
82static struct spi_driver arizona_spi_driver = {
83 .driver = {
84 .name = "arizona",
85 .owner = THIS_MODULE,
86 .pm = &arizona_pm_ops,
87 },
88 .probe = arizona_spi_probe,
89 .remove = __devexit_p(arizona_spi_remove),
90 .id_table = arizona_spi_ids,
91};
92
93module_spi_driver(arizona_spi_driver);
94
95MODULE_DESCRIPTION("Arizona SPI bus interface");
96MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
97MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/arizona.h b/drivers/mfd/arizona.h
new file mode 100644
index 000000000000..9798ae5da67b
--- /dev/null
+++ b/drivers/mfd/arizona.h
@@ -0,0 +1,40 @@
1/*
2 * wm5102.h -- WM5102 MFD internals
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _WM5102_H
14#define _WM5102_H
15
16#include <linux/regmap.h>
17#include <linux/pm.h>
18
19struct wm_arizona;
20
21extern const struct regmap_config wm5102_i2c_regmap;
22extern const struct regmap_config wm5102_spi_regmap;
23
24extern const struct regmap_config wm5110_i2c_regmap;
25extern const struct regmap_config wm5110_spi_regmap;
26
27extern const struct dev_pm_ops arizona_pm_ops;
28
29extern const struct regmap_irq_chip wm5102_aod;
30extern const struct regmap_irq_chip wm5102_irq;
31
32extern const struct regmap_irq_chip wm5110_aod;
33extern const struct regmap_irq_chip wm5110_irq;
34
35int arizona_dev_init(struct arizona *arizona);
36int arizona_dev_exit(struct arizona *arizona);
37int arizona_irq_init(struct arizona *arizona);
38int arizona_irq_exit(struct arizona *arizona);
39
40#endif
diff --git a/drivers/mfd/da9052-core.c b/drivers/mfd/da9052-core.c
index 1f1313c90573..2544910e1fd6 100644
--- a/drivers/mfd/da9052-core.c
+++ b/drivers/mfd/da9052-core.c
@@ -772,7 +772,6 @@ EXPORT_SYMBOL_GPL(da9052_regmap_config);
772int __devinit da9052_device_init(struct da9052 *da9052, u8 chip_id) 772int __devinit da9052_device_init(struct da9052 *da9052, u8 chip_id)
773{ 773{
774 struct da9052_pdata *pdata = da9052->dev->platform_data; 774 struct da9052_pdata *pdata = da9052->dev->platform_data;
775 struct irq_desc *desc;
776 int ret; 775 int ret;
777 776
778 mutex_init(&da9052->auxadc_lock); 777 mutex_init(&da9052->auxadc_lock);
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 50e83dc5dc49..7040a0081130 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -28,6 +28,7 @@
28#include <linux/uaccess.h> 28#include <linux/uaccess.h>
29#include <linux/mfd/core.h> 29#include <linux/mfd/core.h>
30#include <linux/mfd/dbx500-prcmu.h> 30#include <linux/mfd/dbx500-prcmu.h>
31#include <linux/mfd/abx500/ab8500.h>
31#include <linux/regulator/db8500-prcmu.h> 32#include <linux/regulator/db8500-prcmu.h>
32#include <linux/regulator/machine.h> 33#include <linux/regulator/machine.h>
33#include <asm/hardware/gic.h> 34#include <asm/hardware/gic.h>
@@ -2269,10 +2270,10 @@ int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2269/** 2270/**
2270 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem 2271 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2271 */ 2272 */
2272void prcmu_ac_wake_req(void) 2273int prcmu_ac_wake_req(void)
2273{ 2274{
2274 u32 val; 2275 u32 val;
2275 u32 status; 2276 int ret = 0;
2276 2277
2277 mutex_lock(&mb0_transfer.ac_wake_lock); 2278 mutex_lock(&mb0_transfer.ac_wake_lock);
2278 2279
@@ -2282,39 +2283,32 @@ void prcmu_ac_wake_req(void)
2282 2283
2283 atomic_set(&ac_wake_req_state, 1); 2284 atomic_set(&ac_wake_req_state, 1);
2284 2285
2285retry: 2286 /*
2286 writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ); 2287 * Force Modem Wake-up before hostaccess_req ping-pong.
2288 * It prevents Modem to enter in Sleep while acking the hostaccess
2289 * request. The 31us delay has been calculated by HWI.
2290 */
2291 val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2292 writel(val, PRCM_HOSTACCESS_REQ);
2293
2294 udelay(31);
2295
2296 val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2297 writel(val, PRCM_HOSTACCESS_REQ);
2287 2298
2288 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2299 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2289 msecs_to_jiffies(5000))) { 2300 msecs_to_jiffies(5000))) {
2301#if defined(CONFIG_DBX500_PRCMU_DEBUG)
2302 db8500_prcmu_debug_dump(__func__, true, true);
2303#endif
2290 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2304 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2291 __func__); 2305 __func__);
2292 goto unlock_and_return; 2306 ret = -EFAULT;
2293 }
2294
2295 /*
2296 * The modem can generate an AC_WAKE_ACK, and then still go to sleep.
2297 * As a workaround, we wait, and then check that the modem is indeed
2298 * awake (in terms of the value of the PRCM_MOD_AWAKE_STATUS
2299 * register, which may not be the whole truth).
2300 */
2301 udelay(400);
2302 status = (readl(PRCM_MOD_AWAKE_STATUS) & BITS(0, 2));
2303 if (status != (PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE |
2304 PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE)) {
2305 pr_err("prcmu: %s received ack, but modem not awake (0x%X).\n",
2306 __func__, status);
2307 udelay(1200);
2308 writel(val, PRCM_HOSTACCESS_REQ);
2309 if (wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2310 msecs_to_jiffies(5000)))
2311 goto retry;
2312 pr_crit("prcmu: %s timed out (5 s) waiting for AC_SLEEP_ACK.\n",
2313 __func__);
2314 } 2307 }
2315 2308
2316unlock_and_return: 2309unlock_and_return:
2317 mutex_unlock(&mb0_transfer.ac_wake_lock); 2310 mutex_unlock(&mb0_transfer.ac_wake_lock);
2311 return ret;
2318} 2312}
2319 2313
2320/** 2314/**
@@ -2945,14 +2939,31 @@ static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2945 }, 2939 },
2946}; 2940};
2947 2941
2942static struct resource ab8500_resources[] = {
2943 [0] = {
2944 .start = IRQ_DB8500_AB8500,
2945 .end = IRQ_DB8500_AB8500,
2946 .flags = IORESOURCE_IRQ
2947 }
2948};
2949
2948static struct mfd_cell db8500_prcmu_devs[] = { 2950static struct mfd_cell db8500_prcmu_devs[] = {
2949 { 2951 {
2950 .name = "db8500-prcmu-regulators", 2952 .name = "db8500-prcmu-regulators",
2953 .of_compatible = "stericsson,db8500-prcmu-regulator",
2951 .platform_data = &db8500_regulators, 2954 .platform_data = &db8500_regulators,
2952 .pdata_size = sizeof(db8500_regulators), 2955 .pdata_size = sizeof(db8500_regulators),
2953 }, 2956 },
2954 { 2957 {
2955 .name = "cpufreq-u8500", 2958 .name = "cpufreq-u8500",
2959 .of_compatible = "stericsson,cpufreq-u8500",
2960 },
2961 {
2962 .name = "ab8500-core",
2963 .of_compatible = "stericsson,ab8500",
2964 .num_resources = ARRAY_SIZE(ab8500_resources),
2965 .resources = ab8500_resources,
2966 .id = AB8500_VERSION_AB8500,
2956 }, 2967 },
2957}; 2968};
2958 2969
@@ -2962,8 +2973,9 @@ static struct mfd_cell db8500_prcmu_devs[] = {
2962 */ 2973 */
2963static int __devinit db8500_prcmu_probe(struct platform_device *pdev) 2974static int __devinit db8500_prcmu_probe(struct platform_device *pdev)
2964{ 2975{
2976 struct ab8500_platform_data *ab8500_platdata = pdev->dev.platform_data;
2965 struct device_node *np = pdev->dev.of_node; 2977 struct device_node *np = pdev->dev.of_node;
2966 int irq = 0, err = 0; 2978 int irq = 0, err = 0, i;
2967 2979
2968 if (ux500_is_svp()) 2980 if (ux500_is_svp())
2969 return -ENODEV; 2981 return -ENODEV;
@@ -2987,16 +2999,21 @@ static int __devinit db8500_prcmu_probe(struct platform_device *pdev)
2987 goto no_irq_return; 2999 goto no_irq_return;
2988 } 3000 }
2989 3001
3002 for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) {
3003 if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) {
3004 db8500_prcmu_devs[i].platform_data = ab8500_platdata;
3005 db8500_prcmu_devs[i].pdata_size = sizeof(struct ab8500_platform_data);
3006 }
3007 }
3008
2990 if (cpu_is_u8500v20_or_later()) 3009 if (cpu_is_u8500v20_or_later())
2991 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 3010 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
2992 3011
2993 if (!np) { 3012 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
2994 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 3013 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0);
2995 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0); 3014 if (err) {
2996 if (err) { 3015 pr_err("prcmu: Failed to add subdevices\n");
2997 pr_err("prcmu: Failed to add subdevices\n"); 3016 return err;
2998 return err;
2999 }
3000 } 3017 }
3001 3018
3002 pr_info("DB8500 PRCMU initialized\n"); 3019 pr_info("DB8500 PRCMU initialized\n");
@@ -3004,11 +3021,16 @@ static int __devinit db8500_prcmu_probe(struct platform_device *pdev)
3004no_irq_return: 3021no_irq_return:
3005 return err; 3022 return err;
3006} 3023}
3024static const struct of_device_id db8500_prcmu_match[] = {
3025 { .compatible = "stericsson,db8500-prcmu"},
3026 { },
3027};
3007 3028
3008static struct platform_driver db8500_prcmu_driver = { 3029static struct platform_driver db8500_prcmu_driver = {
3009 .driver = { 3030 .driver = {
3010 .name = "db8500-prcmu", 3031 .name = "db8500-prcmu",
3011 .owner = THIS_MODULE, 3032 .owner = THIS_MODULE,
3033 .of_match_table = db8500_prcmu_match,
3012 }, 3034 },
3013 .probe = db8500_prcmu_probe, 3035 .probe = db8500_prcmu_probe,
3014}; 3036};
@@ -3018,7 +3040,7 @@ static int __init db8500_prcmu_init(void)
3018 return platform_driver_register(&db8500_prcmu_driver); 3040 return platform_driver_register(&db8500_prcmu_driver);
3019} 3041}
3020 3042
3021arch_initcall(db8500_prcmu_init); 3043core_initcall(db8500_prcmu_init);
3022 3044
3023MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); 3045MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3024MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); 3046MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index 3a0bf91d7780..23108a6e3167 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -106,6 +106,7 @@
106 106
107#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334) 107#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
108#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1 108#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1
109#define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16)
109#define ARM_WAKEUP_MODEM 0x1 110#define ARM_WAKEUP_MODEM 0x1
110 111
111#define PRCM_ARM_IT1_CLR (_PRCMU_BASE + 0x48C) 112#define PRCM_ARM_IT1_CLR (_PRCMU_BASE + 0x48C)
diff --git a/drivers/mfd/max77686-irq.c b/drivers/mfd/max77686-irq.c
new file mode 100644
index 000000000000..cdc3280e2ec7
--- /dev/null
+++ b/drivers/mfd/max77686-irq.c
@@ -0,0 +1,319 @@
1/*
2 * max77686-irq.c - Interrupt controller support for MAX77686
3 *
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * Chiwoong Byun <woong.byun@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * This driver is based on max8997-irq.c
22 */
23
24#include <linux/err.h>
25#include <linux/irq.h>
26#include <linux/interrupt.h>
27#include <linux/gpio.h>
28#include <linux/mfd/max77686.h>
29#include <linux/mfd/max77686-private.h>
30#include <linux/irqdomain.h>
31#include <linux/regmap.h>
32
33enum {
34 MAX77686_DEBUG_IRQ_INFO = 1 << 0,
35 MAX77686_DEBUG_IRQ_MASK = 1 << 1,
36 MAX77686_DEBUG_IRQ_INT = 1 << 2,
37};
38
39static int debug_mask = 0;
40module_param(debug_mask, int, 0);
41MODULE_PARM_DESC(debug_mask, "Set debug_mask : 0x0=off 0x1=IRQ_INFO 0x2=IRQ_MASK 0x4=IRQ_INI)");
42
43static const u8 max77686_mask_reg[] = {
44 [PMIC_INT1] = MAX77686_REG_INT1MSK,
45 [PMIC_INT2] = MAX77686_REG_INT2MSK,
46 [RTC_INT] = MAX77686_RTC_INTM,
47};
48
49static struct regmap *max77686_get_regmap(struct max77686_dev *max77686,
50 enum max77686_irq_source src)
51{
52 switch (src) {
53 case PMIC_INT1 ... PMIC_INT2:
54 return max77686->regmap;
55 case RTC_INT:
56 return max77686->rtc_regmap;
57 default:
58 return ERR_PTR(-EINVAL);
59 }
60}
61
62struct max77686_irq_data {
63 int mask;
64 enum max77686_irq_source group;
65};
66
67#define DECLARE_IRQ(idx, _group, _mask) \
68 [(idx)] = { .group = (_group), .mask = (_mask) }
69static const struct max77686_irq_data max77686_irqs[] = {
70 DECLARE_IRQ(MAX77686_PMICIRQ_PWRONF, PMIC_INT1, 1 << 0),
71 DECLARE_IRQ(MAX77686_PMICIRQ_PWRONR, PMIC_INT1, 1 << 1),
72 DECLARE_IRQ(MAX77686_PMICIRQ_JIGONBF, PMIC_INT1, 1 << 2),
73 DECLARE_IRQ(MAX77686_PMICIRQ_JIGONBR, PMIC_INT1, 1 << 3),
74 DECLARE_IRQ(MAX77686_PMICIRQ_ACOKBF, PMIC_INT1, 1 << 4),
75 DECLARE_IRQ(MAX77686_PMICIRQ_ACOKBR, PMIC_INT1, 1 << 5),
76 DECLARE_IRQ(MAX77686_PMICIRQ_ONKEY1S, PMIC_INT1, 1 << 6),
77 DECLARE_IRQ(MAX77686_PMICIRQ_MRSTB, PMIC_INT1, 1 << 7),
78 DECLARE_IRQ(MAX77686_PMICIRQ_140C, PMIC_INT2, 1 << 0),
79 DECLARE_IRQ(MAX77686_PMICIRQ_120C, PMIC_INT2, 1 << 1),
80 DECLARE_IRQ(MAX77686_RTCIRQ_RTC60S, RTC_INT, 1 << 0),
81 DECLARE_IRQ(MAX77686_RTCIRQ_RTCA1, RTC_INT, 1 << 1),
82 DECLARE_IRQ(MAX77686_RTCIRQ_RTCA2, RTC_INT, 1 << 2),
83 DECLARE_IRQ(MAX77686_RTCIRQ_SMPL, RTC_INT, 1 << 3),
84 DECLARE_IRQ(MAX77686_RTCIRQ_RTC1S, RTC_INT, 1 << 4),
85 DECLARE_IRQ(MAX77686_RTCIRQ_WTSR, RTC_INT, 1 << 5),
86};
87
88static void max77686_irq_lock(struct irq_data *data)
89{
90 struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
91
92 if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
93 pr_info("%s\n", __func__);
94
95 mutex_lock(&max77686->irqlock);
96}
97
98static void max77686_irq_sync_unlock(struct irq_data *data)
99{
100 struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
101 int i;
102
103 for (i = 0; i < MAX77686_IRQ_GROUP_NR; i++) {
104 u8 mask_reg = max77686_mask_reg[i];
105 struct regmap *map = max77686_get_regmap(max77686, i);
106
107 if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
108 pr_debug("%s: mask_reg[%d]=0x%x, cur=0x%x\n",
109 __func__, i, mask_reg, max77686->irq_masks_cur[i]);
110
111 if (mask_reg == MAX77686_REG_INVALID ||
112 IS_ERR_OR_NULL(map))
113 continue;
114
115 max77686->irq_masks_cache[i] = max77686->irq_masks_cur[i];
116
117 regmap_write(map, max77686_mask_reg[i],
118 max77686->irq_masks_cur[i]);
119 }
120
121 mutex_unlock(&max77686->irqlock);
122}
123
124static const inline struct max77686_irq_data *to_max77686_irq(int irq)
125{
126 struct irq_data *data = irq_get_irq_data(irq);
127 return &max77686_irqs[data->hwirq];
128}
129
130static void max77686_irq_mask(struct irq_data *data)
131{
132 struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
133 const struct max77686_irq_data *irq_data = to_max77686_irq(data->irq);
134
135 max77686->irq_masks_cur[irq_data->group] |= irq_data->mask;
136
137 if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
138 pr_info("%s: group=%d, cur=0x%x\n",
139 __func__, irq_data->group,
140 max77686->irq_masks_cur[irq_data->group]);
141}
142
143static void max77686_irq_unmask(struct irq_data *data)
144{
145 struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
146 const struct max77686_irq_data *irq_data = to_max77686_irq(data->irq);
147
148 max77686->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
149
150 if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
151 pr_info("%s: group=%d, cur=0x%x\n",
152 __func__, irq_data->group,
153 max77686->irq_masks_cur[irq_data->group]);
154}
155
156static struct irq_chip max77686_irq_chip = {
157 .name = "max77686",
158 .irq_bus_lock = max77686_irq_lock,
159 .irq_bus_sync_unlock = max77686_irq_sync_unlock,
160 .irq_mask = max77686_irq_mask,
161 .irq_unmask = max77686_irq_unmask,
162};
163
164static irqreturn_t max77686_irq_thread(int irq, void *data)
165{
166 struct max77686_dev *max77686 = data;
167 unsigned int irq_reg[MAX77686_IRQ_GROUP_NR] = {};
168 unsigned int irq_src;
169 int ret;
170 int i, cur_irq;
171
172 ret = regmap_read(max77686->regmap, MAX77686_REG_INTSRC, &irq_src);
173 if (ret < 0) {
174 dev_err(max77686->dev, "Failed to read interrupt source: %d\n",
175 ret);
176 return IRQ_NONE;
177 }
178
179 if (debug_mask & MAX77686_DEBUG_IRQ_INT)
180 pr_info("%s: irq_src=0x%x\n", __func__, irq_src);
181
182 if (irq_src == MAX77686_IRQSRC_PMIC) {
183 ret = regmap_bulk_read(max77686->regmap,
184 MAX77686_REG_INT1, irq_reg, 2);
185 if (ret < 0) {
186 dev_err(max77686->dev, "Failed to read interrupt source: %d\n",
187 ret);
188 return IRQ_NONE;
189 }
190
191 if (debug_mask & MAX77686_DEBUG_IRQ_INT)
192 pr_info("%s: int1=0x%x, int2=0x%x\n", __func__,
193 irq_reg[PMIC_INT1], irq_reg[PMIC_INT2]);
194 }
195
196 if (irq_src & MAX77686_IRQSRC_RTC) {
197 ret = regmap_read(max77686->rtc_regmap,
198 MAX77686_RTC_INT, &irq_reg[RTC_INT]);
199 if (ret < 0) {
200 dev_err(max77686->dev, "Failed to read interrupt source: %d\n",
201 ret);
202 return IRQ_NONE;
203 }
204
205 if (debug_mask & MAX77686_DEBUG_IRQ_INT)
206 pr_info("%s: rtc int=0x%x\n", __func__,
207 irq_reg[RTC_INT]);
208
209 }
210
211 for (i = 0; i < MAX77686_IRQ_GROUP_NR; i++)
212 irq_reg[i] &= ~max77686->irq_masks_cur[i];
213
214 for (i = 0; i < MAX77686_IRQ_NR; i++) {
215 if (irq_reg[max77686_irqs[i].group] & max77686_irqs[i].mask) {
216 cur_irq = irq_find_mapping(max77686->irq_domain, i);
217 if (cur_irq)
218 handle_nested_irq(cur_irq);
219 }
220 }
221
222 return IRQ_HANDLED;
223}
224
225static int max77686_irq_domain_map(struct irq_domain *d, unsigned int irq,
226 irq_hw_number_t hw)
227{
228 struct max77686_dev *max77686 = d->host_data;
229
230 irq_set_chip_data(irq, max77686);
231 irq_set_chip_and_handler(irq, &max77686_irq_chip, handle_edge_irq);
232 irq_set_nested_thread(irq, 1);
233#ifdef CONFIG_ARM
234 set_irq_flags(irq, IRQF_VALID);
235#else
236 irq_set_noprobe(irq);
237#endif
238 return 0;
239}
240
241static struct irq_domain_ops max77686_irq_domain_ops = {
242 .map = max77686_irq_domain_map,
243};
244
245int max77686_irq_init(struct max77686_dev *max77686)
246{
247 struct irq_domain *domain;
248 int i;
249 int ret;
250 int val;
251 struct regmap *map;
252
253 mutex_init(&max77686->irqlock);
254
255 if (max77686->irq_gpio && !max77686->irq) {
256 max77686->irq = gpio_to_irq(max77686->irq_gpio);
257
258 if (debug_mask & MAX77686_DEBUG_IRQ_INT) {
259 ret = gpio_request(max77686->irq_gpio, "pmic_irq");
260 if (ret < 0) {
261 dev_err(max77686->dev,
262 "Failed to request gpio %d with ret:"
263 "%d\n", max77686->irq_gpio, ret);
264 return IRQ_NONE;
265 }
266
267 gpio_direction_input(max77686->irq_gpio);
268 val = gpio_get_value(max77686->irq_gpio);
269 gpio_free(max77686->irq_gpio);
270 pr_info("%s: gpio_irq=%x\n", __func__, val);
271 }
272 }
273
274 if (!max77686->irq) {
275 dev_err(max77686->dev, "irq is not specified\n");
276 return -ENODEV;
277 }
278
279 /* Mask individual interrupt sources */
280 for (i = 0; i < MAX77686_IRQ_GROUP_NR; i++) {
281 max77686->irq_masks_cur[i] = 0xff;
282 max77686->irq_masks_cache[i] = 0xff;
283 map = max77686_get_regmap(max77686, i);
284
285 if (IS_ERR_OR_NULL(map))
286 continue;
287 if (max77686_mask_reg[i] == MAX77686_REG_INVALID)
288 continue;
289
290 regmap_write(map, max77686_mask_reg[i], 0xff);
291 }
292 domain = irq_domain_add_linear(NULL, MAX77686_IRQ_NR,
293 &max77686_irq_domain_ops, max77686);
294 if (!domain) {
295 dev_err(max77686->dev, "could not create irq domain\n");
296 return -ENODEV;
297 }
298 max77686->irq_domain = domain;
299
300 ret = request_threaded_irq(max77686->irq, NULL, max77686_irq_thread,
301 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
302 "max77686-irq", max77686);
303
304 if (ret)
305 dev_err(max77686->dev, "Failed to request IRQ %d: %d\n",
306 max77686->irq, ret);
307
308
309 if (debug_mask & MAX77686_DEBUG_IRQ_INFO)
310 pr_info("%s-\n", __func__);
311
312 return 0;
313}
314
315void max77686_irq_exit(struct max77686_dev *max77686)
316{
317 if (max77686->irq)
318 free_irq(max77686->irq, max77686);
319}
diff --git a/drivers/mfd/max77686.c b/drivers/mfd/max77686.c
new file mode 100644
index 000000000000..c03e12b51924
--- /dev/null
+++ b/drivers/mfd/max77686.c
@@ -0,0 +1,187 @@
1/*
2 * max77686.c - mfd core driver for the Maxim 77686
3 *
4 * Copyright (C) 2012 Samsung Electronics
5 * Chiwoong Byun <woong.byun@smasung.com>
6 * Jonghwa Lee <jonghwa3.lee@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * This driver is based on max8997.c
23 */
24
25#include <linux/export.h>
26#include <linux/slab.h>
27#include <linux/i2c.h>
28#include <linux/pm_runtime.h>
29#include <linux/module.h>
30#include <linux/mfd/core.h>
31#include <linux/mfd/max77686.h>
32#include <linux/mfd/max77686-private.h>
33#include <linux/err.h>
34
35#define I2C_ADDR_RTC (0x0C >> 1)
36
37static struct mfd_cell max77686_devs[] = {
38 { .name = "max77686-pmic", },
39 { .name = "max77686-rtc", },
40};
41
42static struct regmap_config max77686_regmap_config = {
43 .reg_bits = 8,
44 .val_bits = 8,
45};
46
47#ifdef CONFIG_OF
48static struct of_device_id __devinitdata max77686_pmic_dt_match[] = {
49 {.compatible = "maxim,max77686", .data = 0},
50 {},
51};
52
53static struct max77686_platform_data *max77686_i2c_parse_dt_pdata(struct device
54 *dev)
55{
56 struct max77686_platform_data *pd;
57
58 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
59 if (!pd) {
60 dev_err(dev, "could not allocate memory for pdata\n");
61 return NULL;
62 }
63
64 dev->platform_data = pd;
65 return pd;
66}
67#else
68static struct max77686_platform_data *max77686_i2c_parse_dt_pdata(struct device
69 *dev)
70{
71 return 0;
72}
73#endif
74
75static int max77686_i2c_probe(struct i2c_client *i2c,
76 const struct i2c_device_id *id)
77{
78 struct max77686_dev *max77686 = NULL;
79 struct max77686_platform_data *pdata = i2c->dev.platform_data;
80 unsigned int data;
81 int ret = 0;
82
83 if (i2c->dev.of_node)
84 pdata = max77686_i2c_parse_dt_pdata(&i2c->dev);
85
86 if (!pdata) {
87 ret = -EIO;
88 dev_err(&i2c->dev, "No platform data found.\n");
89 goto err;
90 }
91
92 max77686 = kzalloc(sizeof(struct max77686_dev), GFP_KERNEL);
93 if (max77686 == NULL)
94 return -ENOMEM;
95
96 max77686->regmap = regmap_init_i2c(i2c, &max77686_regmap_config);
97 if (IS_ERR(max77686->regmap)) {
98 ret = PTR_ERR(max77686->regmap);
99 dev_err(max77686->dev, "Failed to allocate register map: %d\n",
100 ret);
101 kfree(max77686);
102 return ret;
103 }
104
105 i2c_set_clientdata(i2c, max77686);
106 max77686->dev = &i2c->dev;
107 max77686->i2c = i2c;
108 max77686->type = id->driver_data;
109
110 max77686->wakeup = pdata->wakeup;
111 max77686->irq_gpio = pdata->irq_gpio;
112 max77686->irq = i2c->irq;
113
114 if (regmap_read(max77686->regmap,
115 MAX77686_REG_DEVICE_ID, &data) < 0) {
116 dev_err(max77686->dev,
117 "device not found on this channel (this is not an error)\n");
118 ret = -ENODEV;
119 goto err;
120 } else
121 dev_info(max77686->dev, "device found\n");
122
123 max77686->rtc = i2c_new_dummy(i2c->adapter, I2C_ADDR_RTC);
124 i2c_set_clientdata(max77686->rtc, max77686);
125
126 max77686_irq_init(max77686);
127
128 ret = mfd_add_devices(max77686->dev, -1, max77686_devs,
129 ARRAY_SIZE(max77686_devs), NULL, 0);
130
131 if (ret < 0)
132 goto err_mfd;
133
134 return ret;
135
136err_mfd:
137 mfd_remove_devices(max77686->dev);
138 i2c_unregister_device(max77686->rtc);
139err:
140 kfree(max77686);
141 return ret;
142}
143
144static int max77686_i2c_remove(struct i2c_client *i2c)
145{
146 struct max77686_dev *max77686 = i2c_get_clientdata(i2c);
147
148 mfd_remove_devices(max77686->dev);
149 i2c_unregister_device(max77686->rtc);
150 kfree(max77686);
151
152 return 0;
153}
154
155static const struct i2c_device_id max77686_i2c_id[] = {
156 { "max77686", TYPE_MAX77686 },
157 { }
158};
159MODULE_DEVICE_TABLE(i2c, max77686_i2c_id);
160
161static struct i2c_driver max77686_i2c_driver = {
162 .driver = {
163 .name = "max77686",
164 .owner = THIS_MODULE,
165 .of_match_table = of_match_ptr(max77686_pmic_dt_match),
166 },
167 .probe = max77686_i2c_probe,
168 .remove = max77686_i2c_remove,
169 .id_table = max77686_i2c_id,
170};
171
172static int __init max77686_i2c_init(void)
173{
174 return i2c_add_driver(&max77686_i2c_driver);
175}
176/* init early so consumer devices can complete system boot */
177subsys_initcall(max77686_i2c_init);
178
179static void __exit max77686_i2c_exit(void)
180{
181 i2c_del_driver(&max77686_i2c_driver);
182}
183module_exit(max77686_i2c_exit);
184
185MODULE_DESCRIPTION("MAXIM 77686 multi-function core driver");
186MODULE_AUTHOR("Chiwoong Byun <woong.byun@samsung.com>");
187MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/max77693.c b/drivers/mfd/max77693.c
index e9e4278722f3..a1811cb50ec7 100644
--- a/drivers/mfd/max77693.c
+++ b/drivers/mfd/max77693.c
@@ -138,8 +138,6 @@ static int max77693_i2c_probe(struct i2c_client *i2c,
138 138
139 max77693->wakeup = pdata->wakeup; 139 max77693->wakeup = pdata->wakeup;
140 140
141 mutex_init(&max77693->iolock);
142
143 if (max77693_read_reg(max77693->regmap, 141 if (max77693_read_reg(max77693->regmap,
144 MAX77693_PMIC_REG_PMIC_ID2, &reg_data) < 0) { 142 MAX77693_PMIC_REG_PMIC_ID2, &reg_data) < 0) {
145 dev_err(max77693->dev, "device not found on this channel\n"); 143 dev_err(max77693->dev, "device not found on this channel\n");
@@ -156,7 +154,7 @@ static int max77693_i2c_probe(struct i2c_client *i2c,
156 154
157 ret = max77693_irq_init(max77693); 155 ret = max77693_irq_init(max77693);
158 if (ret < 0) 156 if (ret < 0)
159 goto err_mfd; 157 goto err_irq;
160 158
161 pm_runtime_set_active(max77693->dev); 159 pm_runtime_set_active(max77693->dev);
162 160
@@ -170,11 +168,11 @@ static int max77693_i2c_probe(struct i2c_client *i2c,
170 return ret; 168 return ret;
171 169
172err_mfd: 170err_mfd:
171 max77693_irq_exit(max77693);
172err_irq:
173 i2c_unregister_device(max77693->muic); 173 i2c_unregister_device(max77693->muic);
174 i2c_unregister_device(max77693->haptic); 174 i2c_unregister_device(max77693->haptic);
175err_regmap: 175err_regmap:
176 kfree(max77693);
177
178 return ret; 176 return ret;
179} 177}
180 178
@@ -183,6 +181,7 @@ static int max77693_i2c_remove(struct i2c_client *i2c)
183 struct max77693_dev *max77693 = i2c_get_clientdata(i2c); 181 struct max77693_dev *max77693 = i2c_get_clientdata(i2c);
184 182
185 mfd_remove_devices(max77693->dev); 183 mfd_remove_devices(max77693->dev);
184 max77693_irq_exit(max77693);
186 i2c_unregister_device(max77693->muic); 185 i2c_unregister_device(max77693->muic);
187 i2c_unregister_device(max77693->haptic); 186 i2c_unregister_device(max77693->haptic);
188 187
@@ -215,7 +214,7 @@ static int max77693_resume(struct device *dev)
215 return max77693_irq_resume(max77693); 214 return max77693_irq_resume(max77693);
216} 215}
217 216
218const struct dev_pm_ops max77693_pm = { 217static const struct dev_pm_ops max77693_pm = {
219 .suspend = max77693_suspend, 218 .suspend = max77693_suspend,
220 .resume = max77693_resume, 219 .resume = max77693_resume,
221}; 220};
diff --git a/drivers/mfd/max8925-core.c b/drivers/mfd/max8925-core.c
index ca881efedf75..825a7f06d9ba 100644
--- a/drivers/mfd/max8925-core.c
+++ b/drivers/mfd/max8925-core.c
@@ -75,9 +75,9 @@ static struct mfd_cell power_devs[] = {
75static struct resource rtc_resources[] = { 75static struct resource rtc_resources[] = {
76 { 76 {
77 .name = "max8925-rtc", 77 .name = "max8925-rtc",
78 .start = MAX8925_RTC_IRQ, 78 .start = MAX8925_IRQ_RTC_ALARM0,
79 .end = MAX8925_RTC_IRQ_MASK, 79 .end = MAX8925_IRQ_RTC_ALARM0,
80 .flags = IORESOURCE_IO, 80 .flags = IORESOURCE_IRQ,
81 }, 81 },
82}; 82};
83 83
@@ -598,7 +598,7 @@ int __devinit max8925_device_init(struct max8925_chip *chip,
598 598
599 ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0], 599 ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
600 ARRAY_SIZE(rtc_devs), 600 ARRAY_SIZE(rtc_devs),
601 &rtc_resources[0], 0); 601 &rtc_resources[0], chip->irq_base);
602 if (ret < 0) { 602 if (ret < 0) {
603 dev_err(chip->dev, "Failed to add rtc subdev\n"); 603 dev_err(chip->dev, "Failed to add rtc subdev\n");
604 goto out; 604 goto out;
diff --git a/drivers/mfd/max8997-irq.c b/drivers/mfd/max8997-irq.c
index 09274cf7c33b..43fa61413e93 100644
--- a/drivers/mfd/max8997-irq.c
+++ b/drivers/mfd/max8997-irq.c
@@ -142,7 +142,8 @@ static void max8997_irq_sync_unlock(struct irq_data *data)
142static const inline struct max8997_irq_data * 142static const inline struct max8997_irq_data *
143irq_to_max8997_irq(struct max8997_dev *max8997, int irq) 143irq_to_max8997_irq(struct max8997_dev *max8997, int irq)
144{ 144{
145 return &max8997_irqs[irq - max8997->irq_base]; 145 struct irq_data *data = irq_get_irq_data(irq);
146 return &max8997_irqs[data->hwirq];
146} 147}
147 148
148static void max8997_irq_mask(struct irq_data *data) 149static void max8997_irq_mask(struct irq_data *data)
@@ -182,7 +183,7 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
182 u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {}; 183 u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
183 u8 irq_src; 184 u8 irq_src;
184 int ret; 185 int ret;
185 int i; 186 int i, cur_irq;
186 187
187 ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src); 188 ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
188 if (ret < 0) { 189 if (ret < 0) {
@@ -269,8 +270,11 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
269 270
270 /* Report */ 271 /* Report */
271 for (i = 0; i < MAX8997_IRQ_NR; i++) { 272 for (i = 0; i < MAX8997_IRQ_NR; i++) {
272 if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) 273 if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
273 handle_nested_irq(max8997->irq_base + i); 274 cur_irq = irq_find_mapping(max8997->irq_domain, i);
275 if (cur_irq)
276 handle_nested_irq(cur_irq);
277 }
274 } 278 }
275 279
276 return IRQ_HANDLED; 280 return IRQ_HANDLED;
@@ -278,26 +282,40 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
278 282
279int max8997_irq_resume(struct max8997_dev *max8997) 283int max8997_irq_resume(struct max8997_dev *max8997)
280{ 284{
281 if (max8997->irq && max8997->irq_base) 285 if (max8997->irq && max8997->irq_domain)
282 max8997_irq_thread(max8997->irq_base, max8997); 286 max8997_irq_thread(0, max8997);
287 return 0;
288}
289
290static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
291 irq_hw_number_t hw)
292{
293 struct max8997_dev *max8997 = d->host_data;
294
295 irq_set_chip_data(irq, max8997);
296 irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
297 irq_set_nested_thread(irq, 1);
298#ifdef CONFIG_ARM
299 set_irq_flags(irq, IRQF_VALID);
300#else
301 irq_set_noprobe(irq);
302#endif
283 return 0; 303 return 0;
284} 304}
285 305
306static struct irq_domain_ops max8997_irq_domain_ops = {
307 .map = max8997_irq_domain_map,
308};
309
286int max8997_irq_init(struct max8997_dev *max8997) 310int max8997_irq_init(struct max8997_dev *max8997)
287{ 311{
312 struct irq_domain *domain;
288 int i; 313 int i;
289 int cur_irq;
290 int ret; 314 int ret;
291 u8 val; 315 u8 val;
292 316
293 if (!max8997->irq) { 317 if (!max8997->irq) {
294 dev_warn(max8997->dev, "No interrupt specified.\n"); 318 dev_warn(max8997->dev, "No interrupt specified.\n");
295 max8997->irq_base = 0;
296 return 0;
297 }
298
299 if (!max8997->irq_base) {
300 dev_err(max8997->dev, "No interrupt base specified.\n");
301 return 0; 319 return 0;
302 } 320 }
303 321
@@ -327,19 +345,13 @@ int max8997_irq_init(struct max8997_dev *max8997)
327 true : false; 345 true : false;
328 } 346 }
329 347
330 /* Register with genirq */ 348 domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR,
331 for (i = 0; i < MAX8997_IRQ_NR; i++) { 349 &max8997_irq_domain_ops, max8997);
332 cur_irq = i + max8997->irq_base; 350 if (!domain) {
333 irq_set_chip_data(cur_irq, max8997); 351 dev_err(max8997->dev, "could not create irq domain\n");
334 irq_set_chip_and_handler(cur_irq, &max8997_irq_chip, 352 return -ENODEV;
335 handle_edge_irq);
336 irq_set_nested_thread(cur_irq, 1);
337#ifdef CONFIG_ARM
338 set_irq_flags(cur_irq, IRQF_VALID);
339#else
340 irq_set_noprobe(cur_irq);
341#endif
342 } 353 }
354 max8997->irq_domain = domain;
343 355
344 ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread, 356 ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread,
345 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 357 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
diff --git a/drivers/mfd/max8997.c b/drivers/mfd/max8997.c
index cb83a7ab53e7..10b629c245b6 100644
--- a/drivers/mfd/max8997.c
+++ b/drivers/mfd/max8997.c
@@ -143,7 +143,6 @@ static int max8997_i2c_probe(struct i2c_client *i2c,
143 if (!pdata) 143 if (!pdata)
144 goto err; 144 goto err;
145 145
146 max8997->irq_base = pdata->irq_base;
147 max8997->ono = pdata->ono; 146 max8997->ono = pdata->ono;
148 147
149 mutex_init(&max8997->iolock); 148 mutex_init(&max8997->iolock);
@@ -206,7 +205,7 @@ static const struct i2c_device_id max8997_i2c_id[] = {
206}; 205};
207MODULE_DEVICE_TABLE(i2c, max8998_i2c_id); 206MODULE_DEVICE_TABLE(i2c, max8998_i2c_id);
208 207
209u8 max8997_dumpaddr_pmic[] = { 208static u8 max8997_dumpaddr_pmic[] = {
210 MAX8997_REG_INT1MSK, 209 MAX8997_REG_INT1MSK,
211 MAX8997_REG_INT2MSK, 210 MAX8997_REG_INT2MSK,
212 MAX8997_REG_INT3MSK, 211 MAX8997_REG_INT3MSK,
@@ -331,7 +330,7 @@ u8 max8997_dumpaddr_pmic[] = {
331 MAX8997_REG_DVSOKTIMER5, 330 MAX8997_REG_DVSOKTIMER5,
332}; 331};
333 332
334u8 max8997_dumpaddr_muic[] = { 333static u8 max8997_dumpaddr_muic[] = {
335 MAX8997_MUIC_REG_INTMASK1, 334 MAX8997_MUIC_REG_INTMASK1,
336 MAX8997_MUIC_REG_INTMASK2, 335 MAX8997_MUIC_REG_INTMASK2,
337 MAX8997_MUIC_REG_INTMASK3, 336 MAX8997_MUIC_REG_INTMASK3,
@@ -341,7 +340,7 @@ u8 max8997_dumpaddr_muic[] = {
341 MAX8997_MUIC_REG_CONTROL3, 340 MAX8997_MUIC_REG_CONTROL3,
342}; 341};
343 342
344u8 max8997_dumpaddr_haptic[] = { 343static u8 max8997_dumpaddr_haptic[] = {
345 MAX8997_HAPTIC_REG_CONF1, 344 MAX8997_HAPTIC_REG_CONF1,
346 MAX8997_HAPTIC_REG_CONF2, 345 MAX8997_HAPTIC_REG_CONF2,
347 MAX8997_HAPTIC_REG_DRVCONF, 346 MAX8997_HAPTIC_REG_DRVCONF,
@@ -423,7 +422,7 @@ static int max8997_resume(struct device *dev)
423 return max8997_irq_resume(max8997); 422 return max8997_irq_resume(max8997);
424} 423}
425 424
426const struct dev_pm_ops max8997_pm = { 425static const struct dev_pm_ops max8997_pm = {
427 .suspend = max8997_suspend, 426 .suspend = max8997_suspend,
428 .resume = max8997_resume, 427 .resume = max8997_resume,
429 .freeze = max8997_freeze, 428 .freeze = max8997_freeze,
diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index f0ea3b8b3e4a..b801dc72f041 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -723,10 +723,6 @@ void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
723 free_irq(mc13xxx->irq, mc13xxx); 723 free_irq(mc13xxx->irq, mc13xxx);
724 724
725 mfd_remove_devices(mc13xxx->dev); 725 mfd_remove_devices(mc13xxx->dev);
726
727 regmap_exit(mc13xxx->regmap);
728
729 kfree(mc13xxx);
730} 726}
731EXPORT_SYMBOL_GPL(mc13xxx_common_cleanup); 727EXPORT_SYMBOL_GPL(mc13xxx_common_cleanup);
732 728
diff --git a/drivers/mfd/mc13xxx-i2c.c b/drivers/mfd/mc13xxx-i2c.c
index d22501dad6a6..9d18dde3cd2a 100644
--- a/drivers/mfd/mc13xxx-i2c.c
+++ b/drivers/mfd/mc13xxx-i2c.c
@@ -53,17 +53,11 @@ static struct regmap_config mc13xxx_regmap_i2c_config = {
53static int mc13xxx_i2c_probe(struct i2c_client *client, 53static int mc13xxx_i2c_probe(struct i2c_client *client,
54 const struct i2c_device_id *id) 54 const struct i2c_device_id *id)
55{ 55{
56 const struct of_device_id *of_id;
57 struct i2c_driver *idrv = to_i2c_driver(client->dev.driver);
58 struct mc13xxx *mc13xxx; 56 struct mc13xxx *mc13xxx;
59 struct mc13xxx_platform_data *pdata = dev_get_platdata(&client->dev); 57 struct mc13xxx_platform_data *pdata = dev_get_platdata(&client->dev);
60 int ret; 58 int ret;
61 59
62 of_id = of_match_device(mc13xxx_dt_ids, &client->dev); 60 mc13xxx = devm_kzalloc(&client->dev, sizeof(*mc13xxx), GFP_KERNEL);
63 if (of_id)
64 idrv->id_table = (const struct i2c_device_id*) of_id->data;
65
66 mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
67 if (!mc13xxx) 61 if (!mc13xxx)
68 return -ENOMEM; 62 return -ENOMEM;
69 63
@@ -72,13 +66,13 @@ static int mc13xxx_i2c_probe(struct i2c_client *client,
72 mc13xxx->dev = &client->dev; 66 mc13xxx->dev = &client->dev;
73 mutex_init(&mc13xxx->lock); 67 mutex_init(&mc13xxx->lock);
74 68
75 mc13xxx->regmap = regmap_init_i2c(client, &mc13xxx_regmap_i2c_config); 69 mc13xxx->regmap = devm_regmap_init_i2c(client,
70 &mc13xxx_regmap_i2c_config);
76 if (IS_ERR(mc13xxx->regmap)) { 71 if (IS_ERR(mc13xxx->regmap)) {
77 ret = PTR_ERR(mc13xxx->regmap); 72 ret = PTR_ERR(mc13xxx->regmap);
78 dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n", 73 dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n",
79 ret); 74 ret);
80 dev_set_drvdata(&client->dev, NULL); 75 dev_set_drvdata(&client->dev, NULL);
81 kfree(mc13xxx);
82 return ret; 76 return ret;
83 } 77 }
84 78
diff --git a/drivers/mfd/mc13xxx-spi.c b/drivers/mfd/mc13xxx-spi.c
index 03df422feb76..0bdb43a0aff0 100644
--- a/drivers/mfd/mc13xxx-spi.c
+++ b/drivers/mfd/mc13xxx-spi.c
@@ -119,17 +119,11 @@ static struct regmap_bus regmap_mc13xxx_bus = {
119 119
120static int mc13xxx_spi_probe(struct spi_device *spi) 120static int mc13xxx_spi_probe(struct spi_device *spi)
121{ 121{
122 const struct of_device_id *of_id;
123 struct spi_driver *sdrv = to_spi_driver(spi->dev.driver);
124 struct mc13xxx *mc13xxx; 122 struct mc13xxx *mc13xxx;
125 struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev); 123 struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
126 int ret; 124 int ret;
127 125
128 of_id = of_match_device(mc13xxx_dt_ids, &spi->dev); 126 mc13xxx = devm_kzalloc(&spi->dev, sizeof(*mc13xxx), GFP_KERNEL);
129 if (of_id)
130 sdrv->id_table = &mc13xxx_device_id[(enum mc13xxx_id) of_id->data];
131
132 mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
133 if (!mc13xxx) 127 if (!mc13xxx)
134 return -ENOMEM; 128 return -ENOMEM;
135 129
@@ -139,15 +133,14 @@ static int mc13xxx_spi_probe(struct spi_device *spi)
139 mc13xxx->dev = &spi->dev; 133 mc13xxx->dev = &spi->dev;
140 mutex_init(&mc13xxx->lock); 134 mutex_init(&mc13xxx->lock);
141 135
142 mc13xxx->regmap = regmap_init(&spi->dev, &regmap_mc13xxx_bus, &spi->dev, 136 mc13xxx->regmap = devm_regmap_init(&spi->dev, &regmap_mc13xxx_bus,
143 &mc13xxx_regmap_spi_config); 137 &spi->dev,
144 138 &mc13xxx_regmap_spi_config);
145 if (IS_ERR(mc13xxx->regmap)) { 139 if (IS_ERR(mc13xxx->regmap)) {
146 ret = PTR_ERR(mc13xxx->regmap); 140 ret = PTR_ERR(mc13xxx->regmap);
147 dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n", 141 dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n",
148 ret); 142 ret);
149 dev_set_drvdata(&spi->dev, NULL); 143 dev_set_drvdata(&spi->dev, NULL);
150 kfree(mc13xxx);
151 return ret; 144 return ret;
152 } 145 }
153 146
diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
index ffc3d48676ae..0c3a01cde2f7 100644
--- a/drivers/mfd/mfd-core.c
+++ b/drivers/mfd/mfd-core.c
@@ -18,6 +18,8 @@
18#include <linux/pm_runtime.h> 18#include <linux/pm_runtime.h>
19#include <linux/slab.h> 19#include <linux/slab.h>
20#include <linux/module.h> 20#include <linux/module.h>
21#include <linux/irqdomain.h>
22#include <linux/of.h>
21 23
22int mfd_cell_enable(struct platform_device *pdev) 24int mfd_cell_enable(struct platform_device *pdev)
23{ 25{
@@ -76,6 +78,8 @@ static int mfd_add_device(struct device *parent, int id,
76{ 78{
77 struct resource *res; 79 struct resource *res;
78 struct platform_device *pdev; 80 struct platform_device *pdev;
81 struct device_node *np = NULL;
82 struct irq_domain *domain = NULL;
79 int ret = -ENOMEM; 83 int ret = -ENOMEM;
80 int r; 84 int r;
81 85
@@ -89,6 +93,16 @@ static int mfd_add_device(struct device *parent, int id,
89 93
90 pdev->dev.parent = parent; 94 pdev->dev.parent = parent;
91 95
96 if (parent->of_node && cell->of_compatible) {
97 for_each_child_of_node(parent->of_node, np) {
98 if (of_device_is_compatible(np, cell->of_compatible)) {
99 pdev->dev.of_node = np;
100 domain = irq_find_host(parent->of_node);
101 break;
102 }
103 }
104 }
105
92 if (cell->pdata_size) { 106 if (cell->pdata_size) {
93 ret = platform_device_add_data(pdev, 107 ret = platform_device_add_data(pdev,
94 cell->platform_data, cell->pdata_size); 108 cell->platform_data, cell->pdata_size);
@@ -112,10 +126,18 @@ static int mfd_add_device(struct device *parent, int id,
112 res[r].end = mem_base->start + 126 res[r].end = mem_base->start +
113 cell->resources[r].end; 127 cell->resources[r].end;
114 } else if (cell->resources[r].flags & IORESOURCE_IRQ) { 128 } else if (cell->resources[r].flags & IORESOURCE_IRQ) {
115 res[r].start = irq_base + 129 if (domain) {
116 cell->resources[r].start; 130 /* Unable to create mappings for IRQ ranges. */
117 res[r].end = irq_base + 131 WARN_ON(cell->resources[r].start !=
118 cell->resources[r].end; 132 cell->resources[r].end);
133 res[r].start = res[r].end = irq_create_mapping(
134 domain, cell->resources[r].start);
135 } else {
136 res[r].start = irq_base +
137 cell->resources[r].start;
138 res[r].end = irq_base +
139 cell->resources[r].end;
140 }
119 } else { 141 } else {
120 res[r].parent = cell->resources[r].parent; 142 res[r].parent = cell->resources[r].parent;
121 res[r].start = cell->resources[r].start; 143 res[r].start = cell->resources[r].start;
diff --git a/drivers/mfd/pcf50633-core.c b/drivers/mfd/pcf50633-core.c
index 29c122bf28ea..45ce1fb5a549 100644
--- a/drivers/mfd/pcf50633-core.c
+++ b/drivers/mfd/pcf50633-core.c
@@ -253,8 +253,13 @@ static int __devinit pcf50633_probe(struct i2c_client *client,
253 } 253 }
254 254
255 pdev->dev.parent = pcf->dev; 255 pdev->dev.parent = pcf->dev;
256 platform_device_add_data(pdev, &pdata->reg_init_data[i], 256 if (platform_device_add_data(pdev, &pdata->reg_init_data[i],
257 sizeof(pdata->reg_init_data[i])); 257 sizeof(pdata->reg_init_data[i])) < 0) {
258 platform_device_put(pdev);
259 dev_err(pcf->dev, "Out of memory for regulator parameters %d\n",
260 i);
261 continue;
262 }
258 pcf->regulator_pdev[i] = pdev; 263 pcf->regulator_pdev[i] = pdev;
259 264
260 platform_device_add(pdev); 265 platform_device_add(pdev);
diff --git a/drivers/mfd/s5m-core.c b/drivers/mfd/s5m-core.c
deleted file mode 100644
index dd170307e60e..000000000000
--- a/drivers/mfd/s5m-core.c
+++ /dev/null
@@ -1,206 +0,0 @@
1/*
2 * s5m87xx.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/err.h>
18#include <linux/slab.h>
19#include <linux/i2c.h>
20#include <linux/interrupt.h>
21#include <linux/pm_runtime.h>
22#include <linux/mutex.h>
23#include <linux/mfd/core.h>
24#include <linux/mfd/s5m87xx/s5m-core.h>
25#include <linux/mfd/s5m87xx/s5m-pmic.h>
26#include <linux/mfd/s5m87xx/s5m-rtc.h>
27#include <linux/regmap.h>
28
29static struct mfd_cell s5m8751_devs[] = {
30 {
31 .name = "s5m8751-pmic",
32 }, {
33 .name = "s5m-charger",
34 }, {
35 .name = "s5m8751-codec",
36 },
37};
38
39static struct mfd_cell s5m8763_devs[] = {
40 {
41 .name = "s5m8763-pmic",
42 }, {
43 .name = "s5m-rtc",
44 }, {
45 .name = "s5m-charger",
46 },
47};
48
49static struct mfd_cell s5m8767_devs[] = {
50 {
51 .name = "s5m8767-pmic",
52 }, {
53 .name = "s5m-rtc",
54 },
55};
56
57int s5m_reg_read(struct s5m87xx_dev *s5m87xx, u8 reg, void *dest)
58{
59 return regmap_read(s5m87xx->regmap, reg, dest);
60}
61EXPORT_SYMBOL_GPL(s5m_reg_read);
62
63int s5m_bulk_read(struct s5m87xx_dev *s5m87xx, u8 reg, int count, u8 *buf)
64{
65 return regmap_bulk_read(s5m87xx->regmap, reg, buf, count);
66}
67EXPORT_SYMBOL_GPL(s5m_bulk_read);
68
69int s5m_reg_write(struct s5m87xx_dev *s5m87xx, u8 reg, u8 value)
70{
71 return regmap_write(s5m87xx->regmap, reg, value);
72}
73EXPORT_SYMBOL_GPL(s5m_reg_write);
74
75int s5m_bulk_write(struct s5m87xx_dev *s5m87xx, u8 reg, int count, u8 *buf)
76{
77 return regmap_raw_write(s5m87xx->regmap, reg, buf, count);
78}
79EXPORT_SYMBOL_GPL(s5m_bulk_write);
80
81int s5m_reg_update(struct s5m87xx_dev *s5m87xx, u8 reg, u8 val, u8 mask)
82{
83 return regmap_update_bits(s5m87xx->regmap, reg, mask, val);
84}
85EXPORT_SYMBOL_GPL(s5m_reg_update);
86
87static struct regmap_config s5m_regmap_config = {
88 .reg_bits = 8,
89 .val_bits = 8,
90};
91
92static int s5m87xx_i2c_probe(struct i2c_client *i2c,
93 const struct i2c_device_id *id)
94{
95 struct s5m_platform_data *pdata = i2c->dev.platform_data;
96 struct s5m87xx_dev *s5m87xx;
97 int ret;
98
99 s5m87xx = devm_kzalloc(&i2c->dev, sizeof(struct s5m87xx_dev),
100 GFP_KERNEL);
101 if (s5m87xx == NULL)
102 return -ENOMEM;
103
104 i2c_set_clientdata(i2c, s5m87xx);
105 s5m87xx->dev = &i2c->dev;
106 s5m87xx->i2c = i2c;
107 s5m87xx->irq = i2c->irq;
108 s5m87xx->type = id->driver_data;
109
110 if (pdata) {
111 s5m87xx->device_type = pdata->device_type;
112 s5m87xx->ono = pdata->ono;
113 s5m87xx->irq_base = pdata->irq_base;
114 s5m87xx->wakeup = pdata->wakeup;
115 }
116
117 s5m87xx->regmap = devm_regmap_init_i2c(i2c, &s5m_regmap_config);
118 if (IS_ERR(s5m87xx->regmap)) {
119 ret = PTR_ERR(s5m87xx->regmap);
120 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
121 ret);
122 return ret;
123 }
124
125 s5m87xx->rtc = i2c_new_dummy(i2c->adapter, RTC_I2C_ADDR);
126 i2c_set_clientdata(s5m87xx->rtc, s5m87xx);
127
128 if (pdata && pdata->cfg_pmic_irq)
129 pdata->cfg_pmic_irq();
130
131 s5m_irq_init(s5m87xx);
132
133 pm_runtime_set_active(s5m87xx->dev);
134
135 switch (s5m87xx->device_type) {
136 case S5M8751X:
137 ret = mfd_add_devices(s5m87xx->dev, -1, s5m8751_devs,
138 ARRAY_SIZE(s5m8751_devs), NULL, 0);
139 break;
140 case S5M8763X:
141 ret = mfd_add_devices(s5m87xx->dev, -1, s5m8763_devs,
142 ARRAY_SIZE(s5m8763_devs), NULL, 0);
143 break;
144 case S5M8767X:
145 ret = mfd_add_devices(s5m87xx->dev, -1, s5m8767_devs,
146 ARRAY_SIZE(s5m8767_devs), NULL, 0);
147 break;
148 default:
149 /* If this happens the probe function is problem */
150 BUG();
151 }
152
153 if (ret < 0)
154 goto err;
155
156 return ret;
157
158err:
159 mfd_remove_devices(s5m87xx->dev);
160 s5m_irq_exit(s5m87xx);
161 i2c_unregister_device(s5m87xx->rtc);
162 return ret;
163}
164
165static int s5m87xx_i2c_remove(struct i2c_client *i2c)
166{
167 struct s5m87xx_dev *s5m87xx = i2c_get_clientdata(i2c);
168
169 mfd_remove_devices(s5m87xx->dev);
170 s5m_irq_exit(s5m87xx);
171 i2c_unregister_device(s5m87xx->rtc);
172 return 0;
173}
174
175static const struct i2c_device_id s5m87xx_i2c_id[] = {
176 { "s5m87xx", 0 },
177 { }
178};
179MODULE_DEVICE_TABLE(i2c, s5m87xx_i2c_id);
180
181static struct i2c_driver s5m87xx_i2c_driver = {
182 .driver = {
183 .name = "s5m87xx",
184 .owner = THIS_MODULE,
185 },
186 .probe = s5m87xx_i2c_probe,
187 .remove = s5m87xx_i2c_remove,
188 .id_table = s5m87xx_i2c_id,
189};
190
191static int __init s5m87xx_i2c_init(void)
192{
193 return i2c_add_driver(&s5m87xx_i2c_driver);
194}
195
196subsys_initcall(s5m87xx_i2c_init);
197
198static void __exit s5m87xx_i2c_exit(void)
199{
200 i2c_del_driver(&s5m87xx_i2c_driver);
201}
202module_exit(s5m87xx_i2c_exit);
203
204MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
205MODULE_DESCRIPTION("Core support for the S5M MFD");
206MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/s5m-irq.c b/drivers/mfd/s5m-irq.c
deleted file mode 100644
index 0236676085cf..000000000000
--- a/drivers/mfd/s5m-irq.c
+++ /dev/null
@@ -1,495 +0,0 @@
1/*
2 * s5m-irq.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/mfd/s5m87xx/s5m-core.h>
18
19struct s5m_irq_data {
20 int reg;
21 int mask;
22};
23
24static struct s5m_irq_data s5m8767_irqs[] = {
25 [S5M8767_IRQ_PWRR] = {
26 .reg = 1,
27 .mask = S5M8767_IRQ_PWRR_MASK,
28 },
29 [S5M8767_IRQ_PWRF] = {
30 .reg = 1,
31 .mask = S5M8767_IRQ_PWRF_MASK,
32 },
33 [S5M8767_IRQ_PWR1S] = {
34 .reg = 1,
35 .mask = S5M8767_IRQ_PWR1S_MASK,
36 },
37 [S5M8767_IRQ_JIGR] = {
38 .reg = 1,
39 .mask = S5M8767_IRQ_JIGR_MASK,
40 },
41 [S5M8767_IRQ_JIGF] = {
42 .reg = 1,
43 .mask = S5M8767_IRQ_JIGF_MASK,
44 },
45 [S5M8767_IRQ_LOWBAT2] = {
46 .reg = 1,
47 .mask = S5M8767_IRQ_LOWBAT2_MASK,
48 },
49 [S5M8767_IRQ_LOWBAT1] = {
50 .reg = 1,
51 .mask = S5M8767_IRQ_LOWBAT1_MASK,
52 },
53 [S5M8767_IRQ_MRB] = {
54 .reg = 2,
55 .mask = S5M8767_IRQ_MRB_MASK,
56 },
57 [S5M8767_IRQ_DVSOK2] = {
58 .reg = 2,
59 .mask = S5M8767_IRQ_DVSOK2_MASK,
60 },
61 [S5M8767_IRQ_DVSOK3] = {
62 .reg = 2,
63 .mask = S5M8767_IRQ_DVSOK3_MASK,
64 },
65 [S5M8767_IRQ_DVSOK4] = {
66 .reg = 2,
67 .mask = S5M8767_IRQ_DVSOK4_MASK,
68 },
69 [S5M8767_IRQ_RTC60S] = {
70 .reg = 3,
71 .mask = S5M8767_IRQ_RTC60S_MASK,
72 },
73 [S5M8767_IRQ_RTCA1] = {
74 .reg = 3,
75 .mask = S5M8767_IRQ_RTCA1_MASK,
76 },
77 [S5M8767_IRQ_RTCA2] = {
78 .reg = 3,
79 .mask = S5M8767_IRQ_RTCA2_MASK,
80 },
81 [S5M8767_IRQ_SMPL] = {
82 .reg = 3,
83 .mask = S5M8767_IRQ_SMPL_MASK,
84 },
85 [S5M8767_IRQ_RTC1S] = {
86 .reg = 3,
87 .mask = S5M8767_IRQ_RTC1S_MASK,
88 },
89 [S5M8767_IRQ_WTSR] = {
90 .reg = 3,
91 .mask = S5M8767_IRQ_WTSR_MASK,
92 },
93};
94
95static struct s5m_irq_data s5m8763_irqs[] = {
96 [S5M8763_IRQ_DCINF] = {
97 .reg = 1,
98 .mask = S5M8763_IRQ_DCINF_MASK,
99 },
100 [S5M8763_IRQ_DCINR] = {
101 .reg = 1,
102 .mask = S5M8763_IRQ_DCINR_MASK,
103 },
104 [S5M8763_IRQ_JIGF] = {
105 .reg = 1,
106 .mask = S5M8763_IRQ_JIGF_MASK,
107 },
108 [S5M8763_IRQ_JIGR] = {
109 .reg = 1,
110 .mask = S5M8763_IRQ_JIGR_MASK,
111 },
112 [S5M8763_IRQ_PWRONF] = {
113 .reg = 1,
114 .mask = S5M8763_IRQ_PWRONF_MASK,
115 },
116 [S5M8763_IRQ_PWRONR] = {
117 .reg = 1,
118 .mask = S5M8763_IRQ_PWRONR_MASK,
119 },
120 [S5M8763_IRQ_WTSREVNT] = {
121 .reg = 2,
122 .mask = S5M8763_IRQ_WTSREVNT_MASK,
123 },
124 [S5M8763_IRQ_SMPLEVNT] = {
125 .reg = 2,
126 .mask = S5M8763_IRQ_SMPLEVNT_MASK,
127 },
128 [S5M8763_IRQ_ALARM1] = {
129 .reg = 2,
130 .mask = S5M8763_IRQ_ALARM1_MASK,
131 },
132 [S5M8763_IRQ_ALARM0] = {
133 .reg = 2,
134 .mask = S5M8763_IRQ_ALARM0_MASK,
135 },
136 [S5M8763_IRQ_ONKEY1S] = {
137 .reg = 3,
138 .mask = S5M8763_IRQ_ONKEY1S_MASK,
139 },
140 [S5M8763_IRQ_TOPOFFR] = {
141 .reg = 3,
142 .mask = S5M8763_IRQ_TOPOFFR_MASK,
143 },
144 [S5M8763_IRQ_DCINOVPR] = {
145 .reg = 3,
146 .mask = S5M8763_IRQ_DCINOVPR_MASK,
147 },
148 [S5M8763_IRQ_CHGRSTF] = {
149 .reg = 3,
150 .mask = S5M8763_IRQ_CHGRSTF_MASK,
151 },
152 [S5M8763_IRQ_DONER] = {
153 .reg = 3,
154 .mask = S5M8763_IRQ_DONER_MASK,
155 },
156 [S5M8763_IRQ_CHGFAULT] = {
157 .reg = 3,
158 .mask = S5M8763_IRQ_CHGFAULT_MASK,
159 },
160 [S5M8763_IRQ_LOBAT1] = {
161 .reg = 4,
162 .mask = S5M8763_IRQ_LOBAT1_MASK,
163 },
164 [S5M8763_IRQ_LOBAT2] = {
165 .reg = 4,
166 .mask = S5M8763_IRQ_LOBAT2_MASK,
167 },
168};
169
170static inline struct s5m_irq_data *
171irq_to_s5m8767_irq(struct s5m87xx_dev *s5m87xx, int irq)
172{
173 return &s5m8767_irqs[irq - s5m87xx->irq_base];
174}
175
176static void s5m8767_irq_lock(struct irq_data *data)
177{
178 struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
179
180 mutex_lock(&s5m87xx->irqlock);
181}
182
183static void s5m8767_irq_sync_unlock(struct irq_data *data)
184{
185 struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
186 int i;
187
188 for (i = 0; i < ARRAY_SIZE(s5m87xx->irq_masks_cur); i++) {
189 if (s5m87xx->irq_masks_cur[i] != s5m87xx->irq_masks_cache[i]) {
190 s5m87xx->irq_masks_cache[i] = s5m87xx->irq_masks_cur[i];
191 s5m_reg_write(s5m87xx, S5M8767_REG_INT1M + i,
192 s5m87xx->irq_masks_cur[i]);
193 }
194 }
195
196 mutex_unlock(&s5m87xx->irqlock);
197}
198
199static void s5m8767_irq_unmask(struct irq_data *data)
200{
201 struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
202 struct s5m_irq_data *irq_data = irq_to_s5m8767_irq(s5m87xx,
203 data->irq);
204
205 s5m87xx->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
206}
207
208static void s5m8767_irq_mask(struct irq_data *data)
209{
210 struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
211 struct s5m_irq_data *irq_data = irq_to_s5m8767_irq(s5m87xx,
212 data->irq);
213
214 s5m87xx->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
215}
216
217static struct irq_chip s5m8767_irq_chip = {
218 .name = "s5m8767",
219 .irq_bus_lock = s5m8767_irq_lock,
220 .irq_bus_sync_unlock = s5m8767_irq_sync_unlock,
221 .irq_mask = s5m8767_irq_mask,
222 .irq_unmask = s5m8767_irq_unmask,
223};
224
225static inline struct s5m_irq_data *
226irq_to_s5m8763_irq(struct s5m87xx_dev *s5m87xx, int irq)
227{
228 return &s5m8763_irqs[irq - s5m87xx->irq_base];
229}
230
231static void s5m8763_irq_lock(struct irq_data *data)
232{
233 struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
234
235 mutex_lock(&s5m87xx->irqlock);
236}
237
238static void s5m8763_irq_sync_unlock(struct irq_data *data)
239{
240 struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
241 int i;
242
243 for (i = 0; i < ARRAY_SIZE(s5m87xx->irq_masks_cur); i++) {
244 if (s5m87xx->irq_masks_cur[i] != s5m87xx->irq_masks_cache[i]) {
245 s5m87xx->irq_masks_cache[i] = s5m87xx->irq_masks_cur[i];
246 s5m_reg_write(s5m87xx, S5M8763_REG_IRQM1 + i,
247 s5m87xx->irq_masks_cur[i]);
248 }
249 }
250
251 mutex_unlock(&s5m87xx->irqlock);
252}
253
254static void s5m8763_irq_unmask(struct irq_data *data)
255{
256 struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
257 struct s5m_irq_data *irq_data = irq_to_s5m8763_irq(s5m87xx,
258 data->irq);
259
260 s5m87xx->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
261}
262
263static void s5m8763_irq_mask(struct irq_data *data)
264{
265 struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data);
266 struct s5m_irq_data *irq_data = irq_to_s5m8763_irq(s5m87xx,
267 data->irq);
268
269 s5m87xx->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
270}
271
272static struct irq_chip s5m8763_irq_chip = {
273 .name = "s5m8763",
274 .irq_bus_lock = s5m8763_irq_lock,
275 .irq_bus_sync_unlock = s5m8763_irq_sync_unlock,
276 .irq_mask = s5m8763_irq_mask,
277 .irq_unmask = s5m8763_irq_unmask,
278};
279
280
281static irqreturn_t s5m8767_irq_thread(int irq, void *data)
282{
283 struct s5m87xx_dev *s5m87xx = data;
284 u8 irq_reg[NUM_IRQ_REGS-1];
285 int ret;
286 int i;
287
288
289 ret = s5m_bulk_read(s5m87xx, S5M8767_REG_INT1,
290 NUM_IRQ_REGS - 1, irq_reg);
291 if (ret < 0) {
292 dev_err(s5m87xx->dev, "Failed to read interrupt register: %d\n",
293 ret);
294 return IRQ_NONE;
295 }
296
297 for (i = 0; i < NUM_IRQ_REGS - 1; i++)
298 irq_reg[i] &= ~s5m87xx->irq_masks_cur[i];
299
300 for (i = 0; i < S5M8767_IRQ_NR; i++) {
301 if (irq_reg[s5m8767_irqs[i].reg - 1] & s5m8767_irqs[i].mask)
302 handle_nested_irq(s5m87xx->irq_base + i);
303 }
304
305 return IRQ_HANDLED;
306}
307
308static irqreturn_t s5m8763_irq_thread(int irq, void *data)
309{
310 struct s5m87xx_dev *s5m87xx = data;
311 u8 irq_reg[NUM_IRQ_REGS];
312 int ret;
313 int i;
314
315 ret = s5m_bulk_read(s5m87xx, S5M8763_REG_IRQ1,
316 NUM_IRQ_REGS, irq_reg);
317 if (ret < 0) {
318 dev_err(s5m87xx->dev, "Failed to read interrupt register: %d\n",
319 ret);
320 return IRQ_NONE;
321 }
322
323 for (i = 0; i < NUM_IRQ_REGS; i++)
324 irq_reg[i] &= ~s5m87xx->irq_masks_cur[i];
325
326 for (i = 0; i < S5M8763_IRQ_NR; i++) {
327 if (irq_reg[s5m8763_irqs[i].reg - 1] & s5m8763_irqs[i].mask)
328 handle_nested_irq(s5m87xx->irq_base + i);
329 }
330
331 return IRQ_HANDLED;
332}
333
334int s5m_irq_resume(struct s5m87xx_dev *s5m87xx)
335{
336 if (s5m87xx->irq && s5m87xx->irq_base){
337 switch (s5m87xx->device_type) {
338 case S5M8763X:
339 s5m8763_irq_thread(s5m87xx->irq_base, s5m87xx);
340 break;
341 case S5M8767X:
342 s5m8767_irq_thread(s5m87xx->irq_base, s5m87xx);
343 break;
344 default:
345 dev_err(s5m87xx->dev,
346 "Unknown device type %d\n",
347 s5m87xx->device_type);
348 return -EINVAL;
349
350 }
351 }
352 return 0;
353}
354
355int s5m_irq_init(struct s5m87xx_dev *s5m87xx)
356{
357 int i;
358 int cur_irq;
359 int ret = 0;
360 int type = s5m87xx->device_type;
361
362 if (!s5m87xx->irq) {
363 dev_warn(s5m87xx->dev,
364 "No interrupt specified, no interrupts\n");
365 s5m87xx->irq_base = 0;
366 return 0;
367 }
368
369 if (!s5m87xx->irq_base) {
370 dev_err(s5m87xx->dev,
371 "No interrupt base specified, no interrupts\n");
372 return 0;
373 }
374
375 mutex_init(&s5m87xx->irqlock);
376
377 switch (type) {
378 case S5M8763X:
379 for (i = 0; i < NUM_IRQ_REGS; i++) {
380 s5m87xx->irq_masks_cur[i] = 0xff;
381 s5m87xx->irq_masks_cache[i] = 0xff;
382 s5m_reg_write(s5m87xx, S5M8763_REG_IRQM1 + i,
383 0xff);
384 }
385
386 s5m_reg_write(s5m87xx, S5M8763_REG_STATUSM1, 0xff);
387 s5m_reg_write(s5m87xx, S5M8763_REG_STATUSM2, 0xff);
388
389 for (i = 0; i < S5M8763_IRQ_NR; i++) {
390 cur_irq = i + s5m87xx->irq_base;
391 irq_set_chip_data(cur_irq, s5m87xx);
392 irq_set_chip_and_handler(cur_irq, &s5m8763_irq_chip,
393 handle_edge_irq);
394 irq_set_nested_thread(cur_irq, 1);
395#ifdef CONFIG_ARM
396 set_irq_flags(cur_irq, IRQF_VALID);
397#else
398 irq_set_noprobe(cur_irq);
399#endif
400 }
401
402 ret = request_threaded_irq(s5m87xx->irq, NULL,
403 s5m8763_irq_thread,
404 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
405 "s5m87xx-irq", s5m87xx);
406 if (ret) {
407 dev_err(s5m87xx->dev, "Failed to request IRQ %d: %d\n",
408 s5m87xx->irq, ret);
409 return ret;
410 }
411 break;
412 case S5M8767X:
413 for (i = 0; i < NUM_IRQ_REGS - 1; i++) {
414 s5m87xx->irq_masks_cur[i] = 0xff;
415 s5m87xx->irq_masks_cache[i] = 0xff;
416 s5m_reg_write(s5m87xx, S5M8767_REG_INT1M + i,
417 0xff);
418 }
419 for (i = 0; i < S5M8767_IRQ_NR; i++) {
420 cur_irq = i + s5m87xx->irq_base;
421 irq_set_chip_data(cur_irq, s5m87xx);
422 if (ret) {
423 dev_err(s5m87xx->dev,
424 "Failed to irq_set_chip_data %d: %d\n",
425 s5m87xx->irq, ret);
426 return ret;
427 }
428
429 irq_set_chip_and_handler(cur_irq, &s5m8767_irq_chip,
430 handle_edge_irq);
431 irq_set_nested_thread(cur_irq, 1);
432#ifdef CONFIG_ARM
433 set_irq_flags(cur_irq, IRQF_VALID);
434#else
435 irq_set_noprobe(cur_irq);
436#endif
437 }
438
439 ret = request_threaded_irq(s5m87xx->irq, NULL,
440 s5m8767_irq_thread,
441 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
442 "s5m87xx-irq", s5m87xx);
443 if (ret) {
444 dev_err(s5m87xx->dev, "Failed to request IRQ %d: %d\n",
445 s5m87xx->irq, ret);
446 return ret;
447 }
448 break;
449 default:
450 dev_err(s5m87xx->dev,
451 "Unknown device type %d\n", s5m87xx->device_type);
452 return -EINVAL;
453 }
454
455 if (!s5m87xx->ono)
456 return 0;
457
458 switch (type) {
459 case S5M8763X:
460 ret = request_threaded_irq(s5m87xx->ono, NULL,
461 s5m8763_irq_thread,
462 IRQF_TRIGGER_FALLING |
463 IRQF_TRIGGER_RISING |
464 IRQF_ONESHOT, "s5m87xx-ono",
465 s5m87xx);
466 break;
467 case S5M8767X:
468 ret = request_threaded_irq(s5m87xx->ono, NULL,
469 s5m8767_irq_thread,
470 IRQF_TRIGGER_FALLING |
471 IRQF_TRIGGER_RISING |
472 IRQF_ONESHOT, "s5m87xx-ono", s5m87xx);
473 break;
474 default:
475 ret = -EINVAL;
476 break;
477 }
478
479 if (ret) {
480 dev_err(s5m87xx->dev, "Failed to request IRQ %d: %d\n",
481 s5m87xx->ono, ret);
482 return ret;
483 }
484
485 return 0;
486}
487
488void s5m_irq_exit(struct s5m87xx_dev *s5m87xx)
489{
490 if (s5m87xx->ono)
491 free_irq(s5m87xx->ono, s5m87xx);
492
493 if (s5m87xx->irq)
494 free_irq(s5m87xx->irq, s5m87xx);
495}
diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c
new file mode 100644
index 000000000000..2988efde11eb
--- /dev/null
+++ b/drivers/mfd/sec-core.c
@@ -0,0 +1,216 @@
1/*
2 * sec-core.c
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/err.h>
18#include <linux/slab.h>
19#include <linux/i2c.h>
20#include <linux/interrupt.h>
21#include <linux/pm_runtime.h>
22#include <linux/mutex.h>
23#include <linux/mfd/core.h>
24#include <linux/mfd/samsung/core.h>
25#include <linux/mfd/samsung/irq.h>
26#include <linux/mfd/samsung/rtc.h>
27#include <linux/regmap.h>
28
29static struct mfd_cell s5m8751_devs[] = {
30 {
31 .name = "s5m8751-pmic",
32 }, {
33 .name = "s5m-charger",
34 }, {
35 .name = "s5m8751-codec",
36 },
37};
38
39static struct mfd_cell s5m8763_devs[] = {
40 {
41 .name = "s5m8763-pmic",
42 }, {
43 .name = "s5m-rtc",
44 }, {
45 .name = "s5m-charger",
46 },
47};
48
49static struct mfd_cell s5m8767_devs[] = {
50 {
51 .name = "s5m8767-pmic",
52 }, {
53 .name = "s5m-rtc",
54 },
55};
56
57static struct mfd_cell s2mps11_devs[] = {
58 {
59 .name = "s2mps11-pmic",
60 },
61};
62
63int sec_reg_read(struct sec_pmic_dev *sec_pmic, u8 reg, void *dest)
64{
65 return regmap_read(sec_pmic->regmap, reg, dest);
66}
67EXPORT_SYMBOL_GPL(sec_reg_read);
68
69int sec_bulk_read(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf)
70{
71 return regmap_bulk_read(sec_pmic->regmap, reg, buf, count);
72}
73EXPORT_SYMBOL_GPL(sec_bulk_read);
74
75int sec_reg_write(struct sec_pmic_dev *sec_pmic, u8 reg, u8 value)
76{
77 return regmap_write(sec_pmic->regmap, reg, value);
78}
79EXPORT_SYMBOL_GPL(sec_reg_write);
80
81int sec_bulk_write(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf)
82{
83 return regmap_raw_write(sec_pmic->regmap, reg, buf, count);
84}
85EXPORT_SYMBOL_GPL(sec_bulk_write);
86
87int sec_reg_update(struct sec_pmic_dev *sec_pmic, u8 reg, u8 val, u8 mask)
88{
89 return regmap_update_bits(sec_pmic->regmap, reg, mask, val);
90}
91EXPORT_SYMBOL_GPL(sec_reg_update);
92
93static struct regmap_config sec_regmap_config = {
94 .reg_bits = 8,
95 .val_bits = 8,
96};
97
98static int sec_pmic_probe(struct i2c_client *i2c,
99 const struct i2c_device_id *id)
100{
101 struct sec_platform_data *pdata = i2c->dev.platform_data;
102 struct sec_pmic_dev *sec_pmic;
103 int ret;
104
105 sec_pmic = devm_kzalloc(&i2c->dev, sizeof(struct sec_pmic_dev),
106 GFP_KERNEL);
107 if (sec_pmic == NULL)
108 return -ENOMEM;
109
110 i2c_set_clientdata(i2c, sec_pmic);
111 sec_pmic->dev = &i2c->dev;
112 sec_pmic->i2c = i2c;
113 sec_pmic->irq = i2c->irq;
114 sec_pmic->type = id->driver_data;
115
116 if (pdata) {
117 sec_pmic->device_type = pdata->device_type;
118 sec_pmic->ono = pdata->ono;
119 sec_pmic->irq_base = pdata->irq_base;
120 sec_pmic->wakeup = pdata->wakeup;
121 }
122
123 sec_pmic->regmap = devm_regmap_init_i2c(i2c, &sec_regmap_config);
124 if (IS_ERR(sec_pmic->regmap)) {
125 ret = PTR_ERR(sec_pmic->regmap);
126 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
127 ret);
128 return ret;
129 }
130
131 sec_pmic->rtc = i2c_new_dummy(i2c->adapter, RTC_I2C_ADDR);
132 i2c_set_clientdata(sec_pmic->rtc, sec_pmic);
133
134 if (pdata && pdata->cfg_pmic_irq)
135 pdata->cfg_pmic_irq();
136
137 sec_irq_init(sec_pmic);
138
139 pm_runtime_set_active(sec_pmic->dev);
140
141 switch (sec_pmic->device_type) {
142 case S5M8751X:
143 ret = mfd_add_devices(sec_pmic->dev, -1, s5m8751_devs,
144 ARRAY_SIZE(s5m8751_devs), NULL, 0);
145 break;
146 case S5M8763X:
147 ret = mfd_add_devices(sec_pmic->dev, -1, s5m8763_devs,
148 ARRAY_SIZE(s5m8763_devs), NULL, 0);
149 break;
150 case S5M8767X:
151 ret = mfd_add_devices(sec_pmic->dev, -1, s5m8767_devs,
152 ARRAY_SIZE(s5m8767_devs), NULL, 0);
153 break;
154 case S2MPS11X:
155 ret = mfd_add_devices(sec_pmic->dev, -1, s2mps11_devs,
156 ARRAY_SIZE(s2mps11_devs), NULL, 0);
157 break;
158 default:
159 /* If this happens the probe function is problem */
160 BUG();
161 }
162
163 if (ret < 0)
164 goto err;
165
166 return ret;
167
168err:
169 mfd_remove_devices(sec_pmic->dev);
170 sec_irq_exit(sec_pmic);
171 i2c_unregister_device(sec_pmic->rtc);
172 return ret;
173}
174
175static int sec_pmic_remove(struct i2c_client *i2c)
176{
177 struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c);
178
179 mfd_remove_devices(sec_pmic->dev);
180 sec_irq_exit(sec_pmic);
181 i2c_unregister_device(sec_pmic->rtc);
182 return 0;
183}
184
185static const struct i2c_device_id sec_pmic_id[] = {
186 { "sec_pmic", 0 },
187 { }
188};
189MODULE_DEVICE_TABLE(i2c, sec_pmic_id);
190
191static struct i2c_driver sec_pmic_driver = {
192 .driver = {
193 .name = "sec_pmic",
194 .owner = THIS_MODULE,
195 },
196 .probe = sec_pmic_probe,
197 .remove = sec_pmic_remove,
198 .id_table = sec_pmic_id,
199};
200
201static int __init sec_pmic_init(void)
202{
203 return i2c_add_driver(&sec_pmic_driver);
204}
205
206subsys_initcall(sec_pmic_init);
207
208static void __exit sec_pmic_exit(void)
209{
210 i2c_del_driver(&sec_pmic_driver);
211}
212module_exit(sec_pmic_exit);
213
214MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
215MODULE_DESCRIPTION("Core support for the S5M MFD");
216MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c
new file mode 100644
index 000000000000..c901fa50fea1
--- /dev/null
+++ b/drivers/mfd/sec-irq.c
@@ -0,0 +1,317 @@
1/*
2 * sec-irq.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/regmap.h>
18
19#include <linux/mfd/samsung/core.h>
20#include <linux/mfd/samsung/irq.h>
21#include <linux/mfd/samsung/s2mps11.h>
22#include <linux/mfd/samsung/s5m8763.h>
23#include <linux/mfd/samsung/s5m8767.h>
24
25static struct regmap_irq s2mps11_irqs[] = {
26 [S2MPS11_IRQ_PWRONF] = {
27 .reg_offset = 1,
28 .mask = S2MPS11_IRQ_PWRONF_MASK,
29 },
30 [S2MPS11_IRQ_PWRONR] = {
31 .reg_offset = 1,
32 .mask = S2MPS11_IRQ_PWRONR_MASK,
33 },
34 [S2MPS11_IRQ_JIGONBF] = {
35 .reg_offset = 1,
36 .mask = S2MPS11_IRQ_JIGONBF_MASK,
37 },
38 [S2MPS11_IRQ_JIGONBR] = {
39 .reg_offset = 1,
40 .mask = S2MPS11_IRQ_JIGONBR_MASK,
41 },
42 [S2MPS11_IRQ_ACOKBF] = {
43 .reg_offset = 1,
44 .mask = S2MPS11_IRQ_ACOKBF_MASK,
45 },
46 [S2MPS11_IRQ_ACOKBR] = {
47 .reg_offset = 1,
48 .mask = S2MPS11_IRQ_ACOKBR_MASK,
49 },
50 [S2MPS11_IRQ_PWRON1S] = {
51 .reg_offset = 1,
52 .mask = S2MPS11_IRQ_PWRON1S_MASK,
53 },
54 [S2MPS11_IRQ_MRB] = {
55 .reg_offset = 1,
56 .mask = S2MPS11_IRQ_MRB_MASK,
57 },
58 [S2MPS11_IRQ_RTC60S] = {
59 .reg_offset = 2,
60 .mask = S2MPS11_IRQ_RTC60S_MASK,
61 },
62 [S2MPS11_IRQ_RTCA1] = {
63 .reg_offset = 2,
64 .mask = S2MPS11_IRQ_RTCA1_MASK,
65 },
66 [S2MPS11_IRQ_RTCA2] = {
67 .reg_offset = 2,
68 .mask = S2MPS11_IRQ_RTCA2_MASK,
69 },
70 [S2MPS11_IRQ_SMPL] = {
71 .reg_offset = 2,
72 .mask = S2MPS11_IRQ_SMPL_MASK,
73 },
74 [S2MPS11_IRQ_RTC1S] = {
75 .reg_offset = 2,
76 .mask = S2MPS11_IRQ_RTC1S_MASK,
77 },
78 [S2MPS11_IRQ_WTSR] = {
79 .reg_offset = 2,
80 .mask = S2MPS11_IRQ_WTSR_MASK,
81 },
82 [S2MPS11_IRQ_INT120C] = {
83 .reg_offset = 3,
84 .mask = S2MPS11_IRQ_INT120C_MASK,
85 },
86 [S2MPS11_IRQ_INT140C] = {
87 .reg_offset = 3,
88 .mask = S2MPS11_IRQ_INT140C_MASK,
89 },
90};
91
92
93static struct regmap_irq s5m8767_irqs[] = {
94 [S5M8767_IRQ_PWRR] = {
95 .reg_offset = 1,
96 .mask = S5M8767_IRQ_PWRR_MASK,
97 },
98 [S5M8767_IRQ_PWRF] = {
99 .reg_offset = 1,
100 .mask = S5M8767_IRQ_PWRF_MASK,
101 },
102 [S5M8767_IRQ_PWR1S] = {
103 .reg_offset = 1,
104 .mask = S5M8767_IRQ_PWR1S_MASK,
105 },
106 [S5M8767_IRQ_JIGR] = {
107 .reg_offset = 1,
108 .mask = S5M8767_IRQ_JIGR_MASK,
109 },
110 [S5M8767_IRQ_JIGF] = {
111 .reg_offset = 1,
112 .mask = S5M8767_IRQ_JIGF_MASK,
113 },
114 [S5M8767_IRQ_LOWBAT2] = {
115 .reg_offset = 1,
116 .mask = S5M8767_IRQ_LOWBAT2_MASK,
117 },
118 [S5M8767_IRQ_LOWBAT1] = {
119 .reg_offset = 1,
120 .mask = S5M8767_IRQ_LOWBAT1_MASK,
121 },
122 [S5M8767_IRQ_MRB] = {
123 .reg_offset = 2,
124 .mask = S5M8767_IRQ_MRB_MASK,
125 },
126 [S5M8767_IRQ_DVSOK2] = {
127 .reg_offset = 2,
128 .mask = S5M8767_IRQ_DVSOK2_MASK,
129 },
130 [S5M8767_IRQ_DVSOK3] = {
131 .reg_offset = 2,
132 .mask = S5M8767_IRQ_DVSOK3_MASK,
133 },
134 [S5M8767_IRQ_DVSOK4] = {
135 .reg_offset = 2,
136 .mask = S5M8767_IRQ_DVSOK4_MASK,
137 },
138 [S5M8767_IRQ_RTC60S] = {
139 .reg_offset = 3,
140 .mask = S5M8767_IRQ_RTC60S_MASK,
141 },
142 [S5M8767_IRQ_RTCA1] = {
143 .reg_offset = 3,
144 .mask = S5M8767_IRQ_RTCA1_MASK,
145 },
146 [S5M8767_IRQ_RTCA2] = {
147 .reg_offset = 3,
148 .mask = S5M8767_IRQ_RTCA2_MASK,
149 },
150 [S5M8767_IRQ_SMPL] = {
151 .reg_offset = 3,
152 .mask = S5M8767_IRQ_SMPL_MASK,
153 },
154 [S5M8767_IRQ_RTC1S] = {
155 .reg_offset = 3,
156 .mask = S5M8767_IRQ_RTC1S_MASK,
157 },
158 [S5M8767_IRQ_WTSR] = {
159 .reg_offset = 3,
160 .mask = S5M8767_IRQ_WTSR_MASK,
161 },
162};
163
164static struct regmap_irq s5m8763_irqs[] = {
165 [S5M8763_IRQ_DCINF] = {
166 .reg_offset = 1,
167 .mask = S5M8763_IRQ_DCINF_MASK,
168 },
169 [S5M8763_IRQ_DCINR] = {
170 .reg_offset = 1,
171 .mask = S5M8763_IRQ_DCINR_MASK,
172 },
173 [S5M8763_IRQ_JIGF] = {
174 .reg_offset = 1,
175 .mask = S5M8763_IRQ_JIGF_MASK,
176 },
177 [S5M8763_IRQ_JIGR] = {
178 .reg_offset = 1,
179 .mask = S5M8763_IRQ_JIGR_MASK,
180 },
181 [S5M8763_IRQ_PWRONF] = {
182 .reg_offset = 1,
183 .mask = S5M8763_IRQ_PWRONF_MASK,
184 },
185 [S5M8763_IRQ_PWRONR] = {
186 .reg_offset = 1,
187 .mask = S5M8763_IRQ_PWRONR_MASK,
188 },
189 [S5M8763_IRQ_WTSREVNT] = {
190 .reg_offset = 2,
191 .mask = S5M8763_IRQ_WTSREVNT_MASK,
192 },
193 [S5M8763_IRQ_SMPLEVNT] = {
194 .reg_offset = 2,
195 .mask = S5M8763_IRQ_SMPLEVNT_MASK,
196 },
197 [S5M8763_IRQ_ALARM1] = {
198 .reg_offset = 2,
199 .mask = S5M8763_IRQ_ALARM1_MASK,
200 },
201 [S5M8763_IRQ_ALARM0] = {
202 .reg_offset = 2,
203 .mask = S5M8763_IRQ_ALARM0_MASK,
204 },
205 [S5M8763_IRQ_ONKEY1S] = {
206 .reg_offset = 3,
207 .mask = S5M8763_IRQ_ONKEY1S_MASK,
208 },
209 [S5M8763_IRQ_TOPOFFR] = {
210 .reg_offset = 3,
211 .mask = S5M8763_IRQ_TOPOFFR_MASK,
212 },
213 [S5M8763_IRQ_DCINOVPR] = {
214 .reg_offset = 3,
215 .mask = S5M8763_IRQ_DCINOVPR_MASK,
216 },
217 [S5M8763_IRQ_CHGRSTF] = {
218 .reg_offset = 3,
219 .mask = S5M8763_IRQ_CHGRSTF_MASK,
220 },
221 [S5M8763_IRQ_DONER] = {
222 .reg_offset = 3,
223 .mask = S5M8763_IRQ_DONER_MASK,
224 },
225 [S5M8763_IRQ_CHGFAULT] = {
226 .reg_offset = 3,
227 .mask = S5M8763_IRQ_CHGFAULT_MASK,
228 },
229 [S5M8763_IRQ_LOBAT1] = {
230 .reg_offset = 4,
231 .mask = S5M8763_IRQ_LOBAT1_MASK,
232 },
233 [S5M8763_IRQ_LOBAT2] = {
234 .reg_offset = 4,
235 .mask = S5M8763_IRQ_LOBAT2_MASK,
236 },
237};
238
239static struct regmap_irq_chip s2mps11_irq_chip = {
240 .name = "s2mps11",
241 .irqs = s2mps11_irqs,
242 .num_irqs = ARRAY_SIZE(s2mps11_irqs),
243 .num_regs = 3,
244 .status_base = S2MPS11_REG_INT1,
245 .mask_base = S2MPS11_REG_INT1M,
246 .ack_base = S2MPS11_REG_INT1,
247};
248
249static struct regmap_irq_chip s5m8767_irq_chip = {
250 .name = "s5m8767",
251 .irqs = s5m8767_irqs,
252 .num_irqs = ARRAY_SIZE(s5m8767_irqs),
253 .num_regs = 3,
254 .status_base = S5M8767_REG_INT1,
255 .mask_base = S5M8767_REG_INT1M,
256 .ack_base = S5M8767_REG_INT1,
257};
258
259static struct regmap_irq_chip s5m8763_irq_chip = {
260 .name = "s5m8763",
261 .irqs = s5m8763_irqs,
262 .num_irqs = ARRAY_SIZE(s5m8763_irqs),
263 .num_regs = 4,
264 .status_base = S5M8763_REG_IRQ1,
265 .mask_base = S5M8763_REG_IRQM1,
266 .ack_base = S5M8763_REG_IRQ1,
267};
268
269int sec_irq_init(struct sec_pmic_dev *sec_pmic)
270{
271 int ret = 0;
272 int type = sec_pmic->device_type;
273
274 if (!sec_pmic->irq) {
275 dev_warn(sec_pmic->dev,
276 "No interrupt specified, no interrupts\n");
277 sec_pmic->irq_base = 0;
278 return 0;
279 }
280
281 switch (type) {
282 case S5M8763X:
283 ret = regmap_add_irq_chip(sec_pmic->regmap, sec_pmic->irq,
284 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
285 sec_pmic->irq_base, &s5m8763_irq_chip,
286 &sec_pmic->irq_data);
287 break;
288 case S5M8767X:
289 ret = regmap_add_irq_chip(sec_pmic->regmap, sec_pmic->irq,
290 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
291 sec_pmic->irq_base, &s5m8767_irq_chip,
292 &sec_pmic->irq_data);
293 break;
294 case S2MPS11X:
295 ret = regmap_add_irq_chip(sec_pmic->regmap, sec_pmic->irq,
296 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
297 sec_pmic->irq_base, &s2mps11_irq_chip,
298 &sec_pmic->irq_data);
299 break;
300 default:
301 dev_err(sec_pmic->dev, "Unknown device type %d\n",
302 sec_pmic->device_type);
303 return -EINVAL;
304 }
305
306 if (ret != 0) {
307 dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
308 return ret;
309 }
310
311 return 0;
312}
313
314void sec_irq_exit(struct sec_pmic_dev *sec_pmic)
315{
316 regmap_del_irq_chip(sec_pmic->irq, sec_pmic->irq_data);
317}
diff --git a/drivers/mfd/tc3589x.c b/drivers/mfd/tc3589x.c
index de979742c6fc..048bf0532a09 100644
--- a/drivers/mfd/tc3589x.c
+++ b/drivers/mfd/tc3589x.c
@@ -357,7 +357,7 @@ static int __devexit tc3589x_remove(struct i2c_client *client)
357 return 0; 357 return 0;
358} 358}
359 359
360#ifdef CONFIG_PM 360#ifdef CONFIG_PM_SLEEP
361static int tc3589x_suspend(struct device *dev) 361static int tc3589x_suspend(struct device *dev)
362{ 362{
363 struct tc3589x *tc3589x = dev_get_drvdata(dev); 363 struct tc3589x *tc3589x = dev_get_drvdata(dev);
@@ -385,11 +385,10 @@ static int tc3589x_resume(struct device *dev)
385 385
386 return ret; 386 return ret;
387} 387}
388
389static const SIMPLE_DEV_PM_OPS(tc3589x_dev_pm_ops, tc3589x_suspend,
390 tc3589x_resume);
391#endif 388#endif
392 389
390static SIMPLE_DEV_PM_OPS(tc3589x_dev_pm_ops, tc3589x_suspend, tc3589x_resume);
391
393static const struct i2c_device_id tc3589x_id[] = { 392static const struct i2c_device_id tc3589x_id[] = {
394 { "tc3589x", 24 }, 393 { "tc3589x", 24 },
395 { } 394 { }
@@ -399,9 +398,7 @@ MODULE_DEVICE_TABLE(i2c, tc3589x_id);
399static struct i2c_driver tc3589x_driver = { 398static struct i2c_driver tc3589x_driver = {
400 .driver.name = "tc3589x", 399 .driver.name = "tc3589x",
401 .driver.owner = THIS_MODULE, 400 .driver.owner = THIS_MODULE,
402#ifdef CONFIG_PM
403 .driver.pm = &tc3589x_dev_pm_ops, 401 .driver.pm = &tc3589x_dev_pm_ops,
404#endif
405 .probe = tc3589x_probe, 402 .probe = tc3589x_probe,
406 .remove = __devexit_p(tc3589x_remove), 403 .remove = __devexit_p(tc3589x_remove),
407 .id_table = tc3589x_id, 404 .id_table = tc3589x_id,
diff --git a/drivers/mfd/tps65090.c b/drivers/mfd/tps65090.c
index 396b9d1b6bd6..80e24f4b47bf 100644
--- a/drivers/mfd/tps65090.c
+++ b/drivers/mfd/tps65090.c
@@ -71,10 +71,10 @@ static const struct tps65090_irq_data tps65090_irqs[] = {
71 71
72static struct mfd_cell tps65090s[] = { 72static struct mfd_cell tps65090s[] = {
73 { 73 {
74 .name = "tps65910-pmic", 74 .name = "tps65090-pmic",
75 }, 75 },
76 { 76 {
77 .name = "tps65910-regulator", 77 .name = "tps65090-regulator",
78 }, 78 },
79}; 79};
80 80
diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index c84b5506d5fb..353c34812120 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -21,17 +21,14 @@
21#include <linux/module.h> 21#include <linux/module.h>
22#include <linux/mutex.h> 22#include <linux/mutex.h>
23#include <linux/slab.h> 23#include <linux/slab.h>
24#include <linux/gpio.h> 24#include <linux/err.h>
25#include <linux/i2c.h> 25#include <linux/i2c.h>
26#include <linux/regmap.h>
26#include <linux/regulator/of_regulator.h> 27#include <linux/regulator/of_regulator.h>
27 28
28#include <linux/mfd/core.h> 29#include <linux/mfd/core.h>
29#include <linux/mfd/tps6586x.h> 30#include <linux/mfd/tps6586x.h>
30 31
31/* GPIO control registers */
32#define TPS6586X_GPIOSET1 0x5d
33#define TPS6586X_GPIOSET2 0x5e
34
35/* interrupt control registers */ 32/* interrupt control registers */
36#define TPS6586X_INT_ACK1 0xb5 33#define TPS6586X_INT_ACK1 0xb5
37#define TPS6586X_INT_ACK2 0xb6 34#define TPS6586X_INT_ACK2 0xb6
@@ -48,6 +45,9 @@
48/* device id */ 45/* device id */
49#define TPS6586X_VERSIONCRC 0xcd 46#define TPS6586X_VERSIONCRC 0xcd
50 47
48/* Maximum register */
49#define TPS6586X_MAX_REGISTER (TPS6586X_VERSIONCRC + 1)
50
51struct tps6586x_irq_data { 51struct tps6586x_irq_data {
52 u8 mask_reg; 52 u8 mask_reg;
53 u8 mask_mask; 53 u8 mask_mask;
@@ -89,226 +89,96 @@ static const struct tps6586x_irq_data tps6586x_irqs[] = {
89 [TPS6586X_INT_RTC_ALM2] = TPS6586X_IRQ(TPS6586X_INT_MASK4, 1 << 1), 89 [TPS6586X_INT_RTC_ALM2] = TPS6586X_IRQ(TPS6586X_INT_MASK4, 1 << 1),
90}; 90};
91 91
92static struct mfd_cell tps6586x_cell[] = {
93 {
94 .name = "tps6586x-gpio",
95 },
96 {
97 .name = "tps6586x-rtc",
98 },
99 {
100 .name = "tps6586x-onkey",
101 },
102};
103
92struct tps6586x { 104struct tps6586x {
93 struct mutex lock;
94 struct device *dev; 105 struct device *dev;
95 struct i2c_client *client; 106 struct i2c_client *client;
107 struct regmap *regmap;
96 108
97 struct gpio_chip gpio;
98 struct irq_chip irq_chip; 109 struct irq_chip irq_chip;
99 struct mutex irq_lock; 110 struct mutex irq_lock;
100 int irq_base; 111 int irq_base;
101 u32 irq_en; 112 u32 irq_en;
102 u8 mask_cache[5];
103 u8 mask_reg[5]; 113 u8 mask_reg[5];
104}; 114};
105 115
106static inline int __tps6586x_read(struct i2c_client *client, 116static inline struct tps6586x *dev_to_tps6586x(struct device *dev)
107 int reg, uint8_t *val)
108{
109 int ret;
110
111 ret = i2c_smbus_read_byte_data(client, reg);
112 if (ret < 0) {
113 dev_err(&client->dev, "failed reading at 0x%02x\n", reg);
114 return ret;
115 }
116
117 *val = (uint8_t)ret;
118
119 return 0;
120}
121
122static inline int __tps6586x_reads(struct i2c_client *client, int reg,
123 int len, uint8_t *val)
124{
125 int ret;
126
127 ret = i2c_smbus_read_i2c_block_data(client, reg, len, val);
128 if (ret < 0) {
129 dev_err(&client->dev, "failed reading from 0x%02x\n", reg);
130 return ret;
131 }
132
133 return 0;
134}
135
136static inline int __tps6586x_write(struct i2c_client *client,
137 int reg, uint8_t val)
138{ 117{
139 int ret; 118 return i2c_get_clientdata(to_i2c_client(dev));
140
141 ret = i2c_smbus_write_byte_data(client, reg, val);
142 if (ret < 0) {
143 dev_err(&client->dev, "failed writing 0x%02x to 0x%02x\n",
144 val, reg);
145 return ret;
146 }
147
148 return 0;
149}
150
151static inline int __tps6586x_writes(struct i2c_client *client, int reg,
152 int len, uint8_t *val)
153{
154 int ret, i;
155
156 for (i = 0; i < len; i++) {
157 ret = __tps6586x_write(client, reg + i, *(val + i));
158 if (ret < 0)
159 return ret;
160 }
161
162 return 0;
163} 119}
164 120
165int tps6586x_write(struct device *dev, int reg, uint8_t val) 121int tps6586x_write(struct device *dev, int reg, uint8_t val)
166{ 122{
167 return __tps6586x_write(to_i2c_client(dev), reg, val); 123 struct tps6586x *tps6586x = dev_to_tps6586x(dev);
124
125 return regmap_write(tps6586x->regmap, reg, val);
168} 126}
169EXPORT_SYMBOL_GPL(tps6586x_write); 127EXPORT_SYMBOL_GPL(tps6586x_write);
170 128
171int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val) 129int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val)
172{ 130{
173 return __tps6586x_writes(to_i2c_client(dev), reg, len, val); 131 struct tps6586x *tps6586x = dev_to_tps6586x(dev);
132
133 return regmap_bulk_write(tps6586x->regmap, reg, val, len);
174} 134}
175EXPORT_SYMBOL_GPL(tps6586x_writes); 135EXPORT_SYMBOL_GPL(tps6586x_writes);
176 136
177int tps6586x_read(struct device *dev, int reg, uint8_t *val) 137int tps6586x_read(struct device *dev, int reg, uint8_t *val)
178{ 138{
179 return __tps6586x_read(to_i2c_client(dev), reg, val); 139 struct tps6586x *tps6586x = dev_to_tps6586x(dev);
140 unsigned int rval;
141 int ret;
142
143 ret = regmap_read(tps6586x->regmap, reg, &rval);
144 if (!ret)
145 *val = rval;
146 return ret;
180} 147}
181EXPORT_SYMBOL_GPL(tps6586x_read); 148EXPORT_SYMBOL_GPL(tps6586x_read);
182 149
183int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val) 150int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val)
184{ 151{
185 return __tps6586x_reads(to_i2c_client(dev), reg, len, val); 152 struct tps6586x *tps6586x = dev_to_tps6586x(dev);
153
154 return regmap_bulk_read(tps6586x->regmap, reg, val, len);
186} 155}
187EXPORT_SYMBOL_GPL(tps6586x_reads); 156EXPORT_SYMBOL_GPL(tps6586x_reads);
188 157
189int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask) 158int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask)
190{ 159{
191 struct tps6586x *tps6586x = dev_get_drvdata(dev); 160 struct tps6586x *tps6586x = dev_to_tps6586x(dev);
192 uint8_t reg_val;
193 int ret = 0;
194
195 mutex_lock(&tps6586x->lock);
196 161
197 ret = __tps6586x_read(to_i2c_client(dev), reg, &reg_val); 162 return regmap_update_bits(tps6586x->regmap, reg, bit_mask, bit_mask);
198 if (ret)
199 goto out;
200
201 if ((reg_val & bit_mask) != bit_mask) {
202 reg_val |= bit_mask;
203 ret = __tps6586x_write(to_i2c_client(dev), reg, reg_val);
204 }
205out:
206 mutex_unlock(&tps6586x->lock);
207 return ret;
208} 163}
209EXPORT_SYMBOL_GPL(tps6586x_set_bits); 164EXPORT_SYMBOL_GPL(tps6586x_set_bits);
210 165
211int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask) 166int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask)
212{ 167{
213 struct tps6586x *tps6586x = dev_get_drvdata(dev); 168 struct tps6586x *tps6586x = dev_to_tps6586x(dev);
214 uint8_t reg_val;
215 int ret = 0;
216
217 mutex_lock(&tps6586x->lock);
218 169
219 ret = __tps6586x_read(to_i2c_client(dev), reg, &reg_val); 170 return regmap_update_bits(tps6586x->regmap, reg, bit_mask, 0);
220 if (ret)
221 goto out;
222
223 if (reg_val & bit_mask) {
224 reg_val &= ~bit_mask;
225 ret = __tps6586x_write(to_i2c_client(dev), reg, reg_val);
226 }
227out:
228 mutex_unlock(&tps6586x->lock);
229 return ret;
230} 171}
231EXPORT_SYMBOL_GPL(tps6586x_clr_bits); 172EXPORT_SYMBOL_GPL(tps6586x_clr_bits);
232 173
233int tps6586x_update(struct device *dev, int reg, uint8_t val, uint8_t mask) 174int tps6586x_update(struct device *dev, int reg, uint8_t val, uint8_t mask)
234{ 175{
235 struct tps6586x *tps6586x = dev_get_drvdata(dev); 176 struct tps6586x *tps6586x = dev_to_tps6586x(dev);
236 uint8_t reg_val;
237 int ret = 0;
238
239 mutex_lock(&tps6586x->lock);
240 177
241 ret = __tps6586x_read(tps6586x->client, reg, &reg_val); 178 return regmap_update_bits(tps6586x->regmap, reg, mask, val);
242 if (ret)
243 goto out;
244
245 if ((reg_val & mask) != val) {
246 reg_val = (reg_val & ~mask) | val;
247 ret = __tps6586x_write(tps6586x->client, reg, reg_val);
248 }
249out:
250 mutex_unlock(&tps6586x->lock);
251 return ret;
252} 179}
253EXPORT_SYMBOL_GPL(tps6586x_update); 180EXPORT_SYMBOL_GPL(tps6586x_update);
254 181
255static int tps6586x_gpio_get(struct gpio_chip *gc, unsigned offset)
256{
257 struct tps6586x *tps6586x = container_of(gc, struct tps6586x, gpio);
258 uint8_t val;
259 int ret;
260
261 ret = __tps6586x_read(tps6586x->client, TPS6586X_GPIOSET2, &val);
262 if (ret)
263 return ret;
264
265 return !!(val & (1 << offset));
266}
267
268
269static void tps6586x_gpio_set(struct gpio_chip *chip, unsigned offset,
270 int value)
271{
272 struct tps6586x *tps6586x = container_of(chip, struct tps6586x, gpio);
273
274 tps6586x_update(tps6586x->dev, TPS6586X_GPIOSET2,
275 value << offset, 1 << offset);
276}
277
278static int tps6586x_gpio_output(struct gpio_chip *gc, unsigned offset,
279 int value)
280{
281 struct tps6586x *tps6586x = container_of(gc, struct tps6586x, gpio);
282 uint8_t val, mask;
283
284 tps6586x_gpio_set(gc, offset, value);
285
286 val = 0x1 << (offset * 2);
287 mask = 0x3 << (offset * 2);
288
289 return tps6586x_update(tps6586x->dev, TPS6586X_GPIOSET1, val, mask);
290}
291
292static int tps6586x_gpio_init(struct tps6586x *tps6586x, int gpio_base)
293{
294 if (!gpio_base)
295 return 0;
296
297 tps6586x->gpio.owner = THIS_MODULE;
298 tps6586x->gpio.label = tps6586x->client->name;
299 tps6586x->gpio.dev = tps6586x->dev;
300 tps6586x->gpio.base = gpio_base;
301 tps6586x->gpio.ngpio = 4;
302 tps6586x->gpio.can_sleep = 1;
303
304 /* FIXME: add handling of GPIOs as dedicated inputs */
305 tps6586x->gpio.direction_output = tps6586x_gpio_output;
306 tps6586x->gpio.set = tps6586x_gpio_set;
307 tps6586x->gpio.get = tps6586x_gpio_get;
308
309 return gpiochip_add(&tps6586x->gpio);
310}
311
312static int __remove_subdev(struct device *dev, void *unused) 182static int __remove_subdev(struct device *dev, void *unused)
313{ 183{
314 platform_device_unregister(to_platform_device(dev)); 184 platform_device_unregister(to_platform_device(dev));
@@ -354,12 +224,11 @@ static void tps6586x_irq_sync_unlock(struct irq_data *data)
354 int i; 224 int i;
355 225
356 for (i = 0; i < ARRAY_SIZE(tps6586x->mask_reg); i++) { 226 for (i = 0; i < ARRAY_SIZE(tps6586x->mask_reg); i++) {
357 if (tps6586x->mask_reg[i] != tps6586x->mask_cache[i]) { 227 int ret;
358 if (!WARN_ON(tps6586x_write(tps6586x->dev, 228 ret = tps6586x_write(tps6586x->dev,
359 TPS6586X_INT_MASK1 + i, 229 TPS6586X_INT_MASK1 + i,
360 tps6586x->mask_reg[i]))) 230 tps6586x->mask_reg[i]);
361 tps6586x->mask_cache[i] = tps6586x->mask_reg[i]; 231 WARN_ON(ret);
362 }
363 } 232 }
364 233
365 mutex_unlock(&tps6586x->irq_lock); 234 mutex_unlock(&tps6586x->irq_lock);
@@ -406,7 +275,6 @@ static int __devinit tps6586x_irq_init(struct tps6586x *tps6586x, int irq,
406 275
407 mutex_init(&tps6586x->irq_lock); 276 mutex_init(&tps6586x->irq_lock);
408 for (i = 0; i < 5; i++) { 277 for (i = 0; i < 5; i++) {
409 tps6586x->mask_cache[i] = 0xff;
410 tps6586x->mask_reg[i] = 0xff; 278 tps6586x->mask_reg[i] = 0xff;
411 tps6586x_write(tps6586x->dev, TPS6586X_INT_MASK1 + i, 0xff); 279 tps6586x_write(tps6586x->dev, TPS6586X_INT_MASK1 + i, 0xff);
412 } 280 }
@@ -556,6 +424,23 @@ static struct tps6586x_platform_data *tps6586x_parse_dt(struct i2c_client *clien
556} 424}
557#endif 425#endif
558 426
427static bool is_volatile_reg(struct device *dev, unsigned int reg)
428{
429 /* Cache all interrupt mask register */
430 if ((reg >= TPS6586X_INT_MASK1) && (reg <= TPS6586X_INT_MASK5))
431 return false;
432
433 return true;
434}
435
436static const struct regmap_config tps6586x_regmap_config = {
437 .reg_bits = 8,
438 .val_bits = 8,
439 .max_register = TPS6586X_MAX_REGISTER - 1,
440 .volatile_reg = is_volatile_reg,
441 .cache_type = REGCACHE_RBTREE,
442};
443
559static int __devinit tps6586x_i2c_probe(struct i2c_client *client, 444static int __devinit tps6586x_i2c_probe(struct i2c_client *client,
560 const struct i2c_device_id *id) 445 const struct i2c_device_id *id)
561{ 446{
@@ -579,29 +464,39 @@ static int __devinit tps6586x_i2c_probe(struct i2c_client *client,
579 464
580 dev_info(&client->dev, "VERSIONCRC is %02x\n", ret); 465 dev_info(&client->dev, "VERSIONCRC is %02x\n", ret);
581 466
582 tps6586x = kzalloc(sizeof(struct tps6586x), GFP_KERNEL); 467 tps6586x = devm_kzalloc(&client->dev, sizeof(*tps6586x), GFP_KERNEL);
583 if (tps6586x == NULL) 468 if (tps6586x == NULL) {
469 dev_err(&client->dev, "memory for tps6586x alloc failed\n");
584 return -ENOMEM; 470 return -ENOMEM;
471 }
585 472
586 tps6586x->client = client; 473 tps6586x->client = client;
587 tps6586x->dev = &client->dev; 474 tps6586x->dev = &client->dev;
588 i2c_set_clientdata(client, tps6586x); 475 i2c_set_clientdata(client, tps6586x);
589 476
590 mutex_init(&tps6586x->lock); 477 tps6586x->regmap = devm_regmap_init_i2c(client,
478 &tps6586x_regmap_config);
479 if (IS_ERR(tps6586x->regmap)) {
480 ret = PTR_ERR(tps6586x->regmap);
481 dev_err(&client->dev, "regmap init failed: %d\n", ret);
482 return ret;
483 }
484
591 485
592 if (client->irq) { 486 if (client->irq) {
593 ret = tps6586x_irq_init(tps6586x, client->irq, 487 ret = tps6586x_irq_init(tps6586x, client->irq,
594 pdata->irq_base); 488 pdata->irq_base);
595 if (ret) { 489 if (ret) {
596 dev_err(&client->dev, "IRQ init failed: %d\n", ret); 490 dev_err(&client->dev, "IRQ init failed: %d\n", ret);
597 goto err_irq_init; 491 return ret;
598 } 492 }
599 } 493 }
600 494
601 ret = tps6586x_gpio_init(tps6586x, pdata->gpio_base); 495 ret = mfd_add_devices(tps6586x->dev, -1,
602 if (ret) { 496 tps6586x_cell, ARRAY_SIZE(tps6586x_cell), NULL, 0);
603 dev_err(&client->dev, "GPIO registration failed: %d\n", ret); 497 if (ret < 0) {
604 goto err_gpio_init; 498 dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret);
499 goto err_mfd_add;
605 } 500 }
606 501
607 ret = tps6586x_add_subdevs(tps6586x, pdata); 502 ret = tps6586x_add_subdevs(tps6586x, pdata);
@@ -613,38 +508,21 @@ static int __devinit tps6586x_i2c_probe(struct i2c_client *client,
613 return 0; 508 return 0;
614 509
615err_add_devs: 510err_add_devs:
616 if (pdata->gpio_base) { 511 mfd_remove_devices(tps6586x->dev);
617 ret = gpiochip_remove(&tps6586x->gpio); 512err_mfd_add:
618 if (ret)
619 dev_err(&client->dev, "Can't remove gpio chip: %d\n",
620 ret);
621 }
622err_gpio_init:
623 if (client->irq) 513 if (client->irq)
624 free_irq(client->irq, tps6586x); 514 free_irq(client->irq, tps6586x);
625err_irq_init:
626 kfree(tps6586x);
627 return ret; 515 return ret;
628} 516}
629 517
630static int __devexit tps6586x_i2c_remove(struct i2c_client *client) 518static int __devexit tps6586x_i2c_remove(struct i2c_client *client)
631{ 519{
632 struct tps6586x *tps6586x = i2c_get_clientdata(client); 520 struct tps6586x *tps6586x = i2c_get_clientdata(client);
633 struct tps6586x_platform_data *pdata = client->dev.platform_data;
634 int ret;
635 521
522 tps6586x_remove_subdevs(tps6586x);
523 mfd_remove_devices(tps6586x->dev);
636 if (client->irq) 524 if (client->irq)
637 free_irq(client->irq, tps6586x); 525 free_irq(client->irq, tps6586x);
638
639 if (pdata->gpio_base) {
640 ret = gpiochip_remove(&tps6586x->gpio);
641 if (ret)
642 dev_err(&client->dev, "Can't remove gpio chip: %d\n",
643 ret);
644 }
645
646 tps6586x_remove_subdevs(tps6586x);
647 kfree(tps6586x);
648 return 0; 526 return 0;
649} 527}
650 528
diff --git a/drivers/mfd/tps65910.c b/drivers/mfd/tps65910.c
index be9e07b77325..1c563792c777 100644
--- a/drivers/mfd/tps65910.c
+++ b/drivers/mfd/tps65910.c
@@ -68,6 +68,24 @@ static const struct regmap_config tps65910_regmap_config = {
68 .cache_type = REGCACHE_RBTREE, 68 .cache_type = REGCACHE_RBTREE,
69}; 69};
70 70
71static int __devinit tps65910_ck32k_init(struct tps65910 *tps65910,
72 struct tps65910_board *pmic_pdata)
73{
74 int ret;
75
76 if (!pmic_pdata->en_ck32k_xtal)
77 return 0;
78
79 ret = tps65910_reg_clear_bits(tps65910, TPS65910_DEVCTRL,
80 DEVCTRL_CK32K_CTRL_MASK);
81 if (ret < 0) {
82 dev_err(tps65910->dev, "clear ck32k_ctrl failed: %d\n", ret);
83 return ret;
84 }
85
86 return 0;
87}
88
71static int __devinit tps65910_sleepinit(struct tps65910 *tps65910, 89static int __devinit tps65910_sleepinit(struct tps65910 *tps65910,
72 struct tps65910_board *pmic_pdata) 90 struct tps65910_board *pmic_pdata)
73{ 91{
@@ -175,6 +193,9 @@ static struct tps65910_board *tps65910_parse_dt(struct i2c_client *client,
175 else if (*chip_id == TPS65911) 193 else if (*chip_id == TPS65911)
176 dev_warn(&client->dev, "VMBCH2-Threshold not specified"); 194 dev_warn(&client->dev, "VMBCH2-Threshold not specified");
177 195
196 prop = of_property_read_bool(np, "ti,en-ck32k-xtal");
197 board_info->en_ck32k_xtal = prop;
198
178 board_info->irq = client->irq; 199 board_info->irq = client->irq;
179 board_info->irq_base = -1; 200 board_info->irq_base = -1;
180 201
@@ -243,7 +264,7 @@ static __devinit int tps65910_i2c_probe(struct i2c_client *i2c,
243 init_data->irq_base = pmic_plat_data->irq_base; 264 init_data->irq_base = pmic_plat_data->irq_base;
244 265
245 tps65910_irq_init(tps65910, init_data->irq, init_data); 266 tps65910_irq_init(tps65910, init_data->irq, init_data);
246 267 tps65910_ck32k_init(tps65910, pmic_plat_data);
247 tps65910_sleepinit(tps65910, pmic_plat_data); 268 tps65910_sleepinit(tps65910, pmic_plat_data);
248 269
249 return ret; 270 return ret;
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 6fc90befa79e..b012efd29e01 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -568,7 +568,6 @@ add_numbered_child(unsigned chip, const char *name, int num,
568 goto err; 568 goto err;
569 } 569 }
570 570
571 device_init_wakeup(&pdev->dev, can_wakeup);
572 pdev->dev.parent = &twl->client->dev; 571 pdev->dev.parent = &twl->client->dev;
573 572
574 if (pdata) { 573 if (pdata) {
@@ -593,6 +592,8 @@ add_numbered_child(unsigned chip, const char *name, int num,
593 } 592 }
594 593
595 status = platform_device_add(pdev); 594 status = platform_device_add(pdev);
595 if (status == 0)
596 device_init_wakeup(&pdev->dev, can_wakeup);
596 597
597err: 598err:
598 if (status < 0) { 599 if (status < 0) {
diff --git a/drivers/mfd/twl6040-core.c b/drivers/mfd/twl6040-core.c
index 4ded9e7aa246..b0fad0ffca56 100644
--- a/drivers/mfd/twl6040-core.c
+++ b/drivers/mfd/twl6040-core.c
@@ -64,19 +64,15 @@ int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg)
64 int ret; 64 int ret;
65 unsigned int val; 65 unsigned int val;
66 66
67 mutex_lock(&twl6040->io_mutex);
68 /* Vibra control registers from cache */ 67 /* Vibra control registers from cache */
69 if (unlikely(reg == TWL6040_REG_VIBCTLL || 68 if (unlikely(reg == TWL6040_REG_VIBCTLL ||
70 reg == TWL6040_REG_VIBCTLR)) { 69 reg == TWL6040_REG_VIBCTLR)) {
71 val = twl6040->vibra_ctrl_cache[VIBRACTRL_MEMBER(reg)]; 70 val = twl6040->vibra_ctrl_cache[VIBRACTRL_MEMBER(reg)];
72 } else { 71 } else {
73 ret = regmap_read(twl6040->regmap, reg, &val); 72 ret = regmap_read(twl6040->regmap, reg, &val);
74 if (ret < 0) { 73 if (ret < 0)
75 mutex_unlock(&twl6040->io_mutex);
76 return ret; 74 return ret;
77 }
78 } 75 }
79 mutex_unlock(&twl6040->io_mutex);
80 76
81 return val; 77 return val;
82} 78}
@@ -86,12 +82,10 @@ int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val)
86{ 82{
87 int ret; 83 int ret;
88 84
89 mutex_lock(&twl6040->io_mutex);
90 ret = regmap_write(twl6040->regmap, reg, val); 85 ret = regmap_write(twl6040->regmap, reg, val);
91 /* Cache the vibra control registers */ 86 /* Cache the vibra control registers */
92 if (reg == TWL6040_REG_VIBCTLL || reg == TWL6040_REG_VIBCTLR) 87 if (reg == TWL6040_REG_VIBCTLL || reg == TWL6040_REG_VIBCTLR)
93 twl6040->vibra_ctrl_cache[VIBRACTRL_MEMBER(reg)] = val; 88 twl6040->vibra_ctrl_cache[VIBRACTRL_MEMBER(reg)] = val;
94 mutex_unlock(&twl6040->io_mutex);
95 89
96 return ret; 90 return ret;
97} 91}
@@ -99,23 +93,13 @@ EXPORT_SYMBOL(twl6040_reg_write);
99 93
100int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask) 94int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
101{ 95{
102 int ret; 96 return regmap_update_bits(twl6040->regmap, reg, mask, mask);
103
104 mutex_lock(&twl6040->io_mutex);
105 ret = regmap_update_bits(twl6040->regmap, reg, mask, mask);
106 mutex_unlock(&twl6040->io_mutex);
107 return ret;
108} 97}
109EXPORT_SYMBOL(twl6040_set_bits); 98EXPORT_SYMBOL(twl6040_set_bits);
110 99
111int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask) 100int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
112{ 101{
113 int ret; 102 return regmap_update_bits(twl6040->regmap, reg, mask, 0);
114
115 mutex_lock(&twl6040->io_mutex);
116 ret = regmap_update_bits(twl6040->regmap, reg, mask, 0);
117 mutex_unlock(&twl6040->io_mutex);
118 return ret;
119} 103}
120EXPORT_SYMBOL(twl6040_clear_bits); 104EXPORT_SYMBOL(twl6040_clear_bits);
121 105
@@ -573,7 +557,6 @@ static int __devinit twl6040_probe(struct i2c_client *client,
573 twl6040->irq = client->irq; 557 twl6040->irq = client->irq;
574 558
575 mutex_init(&twl6040->mutex); 559 mutex_init(&twl6040->mutex);
576 mutex_init(&twl6040->io_mutex);
577 init_completion(&twl6040->ready); 560 init_completion(&twl6040->ready);
578 561
579 twl6040->rev = twl6040_reg_read(twl6040, TWL6040_REG_ASICREV); 562 twl6040->rev = twl6040_reg_read(twl6040, TWL6040_REG_ASICREV);
@@ -696,6 +679,7 @@ static int __devexit twl6040_remove(struct i2c_client *client)
696 679
697static const struct i2c_device_id twl6040_i2c_id[] = { 680static const struct i2c_device_id twl6040_i2c_id[] = {
698 { "twl6040", 0, }, 681 { "twl6040", 0, },
682 { "twl6041", 0, },
699 { }, 683 { },
700}; 684};
701MODULE_DEVICE_TABLE(i2c, twl6040_i2c_id); 685MODULE_DEVICE_TABLE(i2c, twl6040_i2c_id);
diff --git a/drivers/mfd/wm5102-tables.c b/drivers/mfd/wm5102-tables.c
new file mode 100644
index 000000000000..01b9255ed631
--- /dev/null
+++ b/drivers/mfd/wm5102-tables.c
@@ -0,0 +1,2399 @@
1/*
2 * wm5102-tables.c -- WM5102 data tables
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14
15#include <linux/mfd/arizona/core.h>
16#include <linux/mfd/arizona/registers.h>
17
18#include "arizona.h"
19
20#define WM5102_NUM_AOD_ISR 2
21#define WM5102_NUM_ISR 5
22
23static const struct reg_default wm5102_reva_patch[] = {
24 { 0x80, 0x0003 },
25 { 0x221, 0x0090 },
26 { 0x211, 0x0014 },
27 { 0x212, 0x0000 },
28 { 0x214, 0x000C },
29 { 0x171, 0x0002 },
30 { 0x171, 0x0000 },
31 { 0x461, 0x8000 },
32 { 0x463, 0x50F0 },
33 { 0x465, 0x4820 },
34 { 0x467, 0x4040 },
35 { 0x469, 0x3940 },
36 { 0x46B, 0x3310 },
37 { 0x46D, 0x2D80 },
38 { 0x46F, 0x2890 },
39 { 0x471, 0x1990 },
40 { 0x473, 0x1450 },
41 { 0x475, 0x1020 },
42 { 0x477, 0x0CD0 },
43 { 0x479, 0x0A30 },
44 { 0x47B, 0x0810 },
45 { 0x47D, 0x0510 },
46 { 0x500, 0x000D },
47 { 0x507, 0x1820 },
48 { 0x508, 0x1820 },
49 { 0x540, 0x000D },
50 { 0x547, 0x1820 },
51 { 0x548, 0x1820 },
52 { 0x580, 0x000D },
53 { 0x587, 0x1820 },
54 { 0x588, 0x1820 },
55 { 0x101, 0x8140 },
56 { 0x3000, 0x2225 },
57 { 0x3001, 0x3a03 },
58 { 0x3002, 0x0225 },
59 { 0x3003, 0x0801 },
60 { 0x3004, 0x6249 },
61 { 0x3005, 0x0c04 },
62 { 0x3006, 0x0225 },
63 { 0x3007, 0x5901 },
64 { 0x3008, 0xe249 },
65 { 0x3009, 0x030d },
66 { 0x300a, 0x0249 },
67 { 0x300b, 0x2c01 },
68 { 0x300c, 0xe249 },
69 { 0x300d, 0x4342 },
70 { 0x300e, 0xe249 },
71 { 0x300f, 0x73c0 },
72 { 0x3010, 0x4249 },
73 { 0x3011, 0x0c00 },
74 { 0x3012, 0x0225 },
75 { 0x3013, 0x1f01 },
76 { 0x3014, 0x0225 },
77 { 0x3015, 0x1e01 },
78 { 0x3016, 0x0225 },
79 { 0x3017, 0xfa00 },
80 { 0x3018, 0x0000 },
81 { 0x3019, 0xf000 },
82 { 0x301a, 0x0000 },
83 { 0x301b, 0xf000 },
84 { 0x301c, 0x0000 },
85 { 0x301d, 0xf000 },
86 { 0x301e, 0x0000 },
87 { 0x301f, 0xf000 },
88 { 0x3020, 0x0000 },
89 { 0x3021, 0xf000 },
90 { 0x3022, 0x0000 },
91 { 0x3023, 0xf000 },
92 { 0x3024, 0x0000 },
93 { 0x3025, 0xf000 },
94 { 0x3026, 0x0000 },
95 { 0x3027, 0xf000 },
96 { 0x3028, 0x0000 },
97 { 0x3029, 0xf000 },
98 { 0x302a, 0x0000 },
99 { 0x302b, 0xf000 },
100 { 0x302c, 0x0000 },
101 { 0x302d, 0xf000 },
102 { 0x302e, 0x0000 },
103 { 0x302f, 0xf000 },
104 { 0x3030, 0x0225 },
105 { 0x3031, 0x1a01 },
106 { 0x3032, 0x0225 },
107 { 0x3033, 0x1e00 },
108 { 0x3034, 0x0225 },
109 { 0x3035, 0x1f00 },
110 { 0x3036, 0x6225 },
111 { 0x3037, 0xf800 },
112 { 0x3038, 0x0000 },
113 { 0x3039, 0xf000 },
114 { 0x303a, 0x0000 },
115 { 0x303b, 0xf000 },
116 { 0x303c, 0x0000 },
117 { 0x303d, 0xf000 },
118 { 0x303e, 0x0000 },
119 { 0x303f, 0xf000 },
120 { 0x3040, 0x2226 },
121 { 0x3041, 0x3a03 },
122 { 0x3042, 0x0226 },
123 { 0x3043, 0x0801 },
124 { 0x3044, 0x6249 },
125 { 0x3045, 0x0c06 },
126 { 0x3046, 0x0226 },
127 { 0x3047, 0x5901 },
128 { 0x3048, 0xe249 },
129 { 0x3049, 0x030d },
130 { 0x304a, 0x0249 },
131 { 0x304b, 0x2c01 },
132 { 0x304c, 0xe249 },
133 { 0x304d, 0x4342 },
134 { 0x304e, 0xe249 },
135 { 0x304f, 0x73c0 },
136 { 0x3050, 0x4249 },
137 { 0x3051, 0x0c00 },
138 { 0x3052, 0x0226 },
139 { 0x3053, 0x1f01 },
140 { 0x3054, 0x0226 },
141 { 0x3055, 0x1e01 },
142 { 0x3056, 0x0226 },
143 { 0x3057, 0xfa00 },
144 { 0x3058, 0x0000 },
145 { 0x3059, 0xf000 },
146 { 0x305a, 0x0000 },
147 { 0x305b, 0xf000 },
148 { 0x305c, 0x0000 },
149 { 0x305d, 0xf000 },
150 { 0x305e, 0x0000 },
151 { 0x305f, 0xf000 },
152 { 0x3060, 0x0000 },
153 { 0x3061, 0xf000 },
154 { 0x3062, 0x0000 },
155 { 0x3063, 0xf000 },
156 { 0x3064, 0x0000 },
157 { 0x3065, 0xf000 },
158 { 0x3066, 0x0000 },
159 { 0x3067, 0xf000 },
160 { 0x3068, 0x0000 },
161 { 0x3069, 0xf000 },
162 { 0x306a, 0x0000 },
163 { 0x306b, 0xf000 },
164 { 0x306c, 0x0000 },
165 { 0x306d, 0xf000 },
166 { 0x306e, 0x0000 },
167 { 0x306f, 0xf000 },
168 { 0x3070, 0x0226 },
169 { 0x3071, 0x1a01 },
170 { 0x3072, 0x0226 },
171 { 0x3073, 0x1e00 },
172 { 0x3074, 0x0226 },
173 { 0x3075, 0x1f00 },
174 { 0x3076, 0x6226 },
175 { 0x3077, 0xf800 },
176 { 0x3078, 0x0000 },
177 { 0x3079, 0xf000 },
178 { 0x307a, 0x0000 },
179 { 0x307b, 0xf000 },
180 { 0x307c, 0x0000 },
181 { 0x307d, 0xf000 },
182 { 0x307e, 0x0000 },
183 { 0x307f, 0xf000 },
184 { 0x3080, 0x2227 },
185 { 0x3081, 0x3a03 },
186 { 0x3082, 0x0227 },
187 { 0x3083, 0x0801 },
188 { 0x3084, 0x6255 },
189 { 0x3085, 0x0c04 },
190 { 0x3086, 0x0227 },
191 { 0x3087, 0x5901 },
192 { 0x3088, 0xe255 },
193 { 0x3089, 0x030d },
194 { 0x308a, 0x0255 },
195 { 0x308b, 0x2c01 },
196 { 0x308c, 0xe255 },
197 { 0x308d, 0x4342 },
198 { 0x308e, 0xe255 },
199 { 0x308f, 0x73c0 },
200 { 0x3090, 0x4255 },
201 { 0x3091, 0x0c00 },
202 { 0x3092, 0x0227 },
203 { 0x3093, 0x1f01 },
204 { 0x3094, 0x0227 },
205 { 0x3095, 0x1e01 },
206 { 0x3096, 0x0227 },
207 { 0x3097, 0xfa00 },
208 { 0x3098, 0x0000 },
209 { 0x3099, 0xf000 },
210 { 0x309a, 0x0000 },
211 { 0x309b, 0xf000 },
212 { 0x309c, 0x0000 },
213 { 0x309d, 0xf000 },
214 { 0x309e, 0x0000 },
215 { 0x309f, 0xf000 },
216 { 0x30a0, 0x0000 },
217 { 0x30a1, 0xf000 },
218 { 0x30a2, 0x0000 },
219 { 0x30a3, 0xf000 },
220 { 0x30a4, 0x0000 },
221 { 0x30a5, 0xf000 },
222 { 0x30a6, 0x0000 },
223 { 0x30a7, 0xf000 },
224 { 0x30a8, 0x0000 },
225 { 0x30a9, 0xf000 },
226 { 0x30aa, 0x0000 },
227 { 0x30ab, 0xf000 },
228 { 0x30ac, 0x0000 },
229 { 0x30ad, 0xf000 },
230 { 0x30ae, 0x0000 },
231 { 0x30af, 0xf000 },
232 { 0x30b0, 0x0227 },
233 { 0x30b1, 0x1a01 },
234 { 0x30b2, 0x0227 },
235 { 0x30b3, 0x1e00 },
236 { 0x30b4, 0x0227 },
237 { 0x30b5, 0x1f00 },
238 { 0x30b6, 0x6227 },
239 { 0x30b7, 0xf800 },
240 { 0x30b8, 0x0000 },
241 { 0x30b9, 0xf000 },
242 { 0x30ba, 0x0000 },
243 { 0x30bb, 0xf000 },
244 { 0x30bc, 0x0000 },
245 { 0x30bd, 0xf000 },
246 { 0x30be, 0x0000 },
247 { 0x30bf, 0xf000 },
248 { 0x30c0, 0x2228 },
249 { 0x30c1, 0x3a03 },
250 { 0x30c2, 0x0228 },
251 { 0x30c3, 0x0801 },
252 { 0x30c4, 0x6255 },
253 { 0x30c5, 0x0c06 },
254 { 0x30c6, 0x0228 },
255 { 0x30c7, 0x5901 },
256 { 0x30c8, 0xe255 },
257 { 0x30c9, 0x030d },
258 { 0x30ca, 0x0255 },
259 { 0x30cb, 0x2c01 },
260 { 0x30cc, 0xe255 },
261 { 0x30cd, 0x4342 },
262 { 0x30ce, 0xe255 },
263 { 0x30cf, 0x73c0 },
264 { 0x30d0, 0x4255 },
265 { 0x30d1, 0x0c00 },
266 { 0x30d2, 0x0228 },
267 { 0x30d3, 0x1f01 },
268 { 0x30d4, 0x0228 },
269 { 0x30d5, 0x1e01 },
270 { 0x30d6, 0x0228 },
271 { 0x30d7, 0xfa00 },
272 { 0x30d8, 0x0000 },
273 { 0x30d9, 0xf000 },
274 { 0x30da, 0x0000 },
275 { 0x30db, 0xf000 },
276 { 0x30dc, 0x0000 },
277 { 0x30dd, 0xf000 },
278 { 0x30de, 0x0000 },
279 { 0x30df, 0xf000 },
280 { 0x30e0, 0x0000 },
281 { 0x30e1, 0xf000 },
282 { 0x30e2, 0x0000 },
283 { 0x30e3, 0xf000 },
284 { 0x30e4, 0x0000 },
285 { 0x30e5, 0xf000 },
286 { 0x30e6, 0x0000 },
287 { 0x30e7, 0xf000 },
288 { 0x30e8, 0x0000 },
289 { 0x30e9, 0xf000 },
290 { 0x30ea, 0x0000 },
291 { 0x30eb, 0xf000 },
292 { 0x30ec, 0x0000 },
293 { 0x30ed, 0xf000 },
294 { 0x30ee, 0x0000 },
295 { 0x30ef, 0xf000 },
296 { 0x30f0, 0x0228 },
297 { 0x30f1, 0x1a01 },
298 { 0x30f2, 0x0228 },
299 { 0x30f3, 0x1e00 },
300 { 0x30f4, 0x0228 },
301 { 0x30f5, 0x1f00 },
302 { 0x30f6, 0x6228 },
303 { 0x30f7, 0xf800 },
304 { 0x30f8, 0x0000 },
305 { 0x30f9, 0xf000 },
306 { 0x30fa, 0x0000 },
307 { 0x30fb, 0xf000 },
308 { 0x30fc, 0x0000 },
309 { 0x30fd, 0xf000 },
310 { 0x30fe, 0x0000 },
311 { 0x30ff, 0xf000 },
312 { 0x3100, 0x222b },
313 { 0x3101, 0x3a03 },
314 { 0x3102, 0x222b },
315 { 0x3103, 0x5803 },
316 { 0x3104, 0xe26f },
317 { 0x3105, 0x030d },
318 { 0x3106, 0x626f },
319 { 0x3107, 0x2c01 },
320 { 0x3108, 0xe26f },
321 { 0x3109, 0x4342 },
322 { 0x310a, 0xe26f },
323 { 0x310b, 0x73c0 },
324 { 0x310c, 0x026f },
325 { 0x310d, 0x0c00 },
326 { 0x310e, 0x022b },
327 { 0x310f, 0x1f01 },
328 { 0x3110, 0x022b },
329 { 0x3111, 0x1e01 },
330 { 0x3112, 0x022b },
331 { 0x3113, 0xfa00 },
332 { 0x3114, 0x0000 },
333 { 0x3115, 0xf000 },
334 { 0x3116, 0x0000 },
335 { 0x3117, 0xf000 },
336 { 0x3118, 0x0000 },
337 { 0x3119, 0xf000 },
338 { 0x311a, 0x0000 },
339 { 0x311b, 0xf000 },
340 { 0x311c, 0x0000 },
341 { 0x311d, 0xf000 },
342 { 0x311e, 0x0000 },
343 { 0x311f, 0xf000 },
344 { 0x3120, 0x022b },
345 { 0x3121, 0x0a01 },
346 { 0x3122, 0x022b },
347 { 0x3123, 0x1e00 },
348 { 0x3124, 0x022b },
349 { 0x3125, 0x1f00 },
350 { 0x3126, 0x622b },
351 { 0x3127, 0xf800 },
352 { 0x3128, 0x0000 },
353 { 0x3129, 0xf000 },
354 { 0x312a, 0x0000 },
355 { 0x312b, 0xf000 },
356 { 0x312c, 0x0000 },
357 { 0x312d, 0xf000 },
358 { 0x312e, 0x0000 },
359 { 0x312f, 0xf000 },
360 { 0x3130, 0x0000 },
361 { 0x3131, 0xf000 },
362 { 0x3132, 0x0000 },
363 { 0x3133, 0xf000 },
364 { 0x3134, 0x0000 },
365 { 0x3135, 0xf000 },
366 { 0x3136, 0x0000 },
367 { 0x3137, 0xf000 },
368 { 0x3138, 0x0000 },
369 { 0x3139, 0xf000 },
370 { 0x313a, 0x0000 },
371 { 0x313b, 0xf000 },
372 { 0x313c, 0x0000 },
373 { 0x313d, 0xf000 },
374 { 0x313e, 0x0000 },
375 { 0x313f, 0xf000 },
376 { 0x3140, 0x0000 },
377 { 0x3141, 0xf000 },
378 { 0x3142, 0x0000 },
379 { 0x3143, 0xf000 },
380 { 0x3144, 0x0000 },
381 { 0x3145, 0xf000 },
382 { 0x3146, 0x0000 },
383 { 0x3147, 0xf000 },
384 { 0x3148, 0x0000 },
385 { 0x3149, 0xf000 },
386 { 0x314a, 0x0000 },
387 { 0x314b, 0xf000 },
388 { 0x314c, 0x0000 },
389 { 0x314d, 0xf000 },
390 { 0x314e, 0x0000 },
391 { 0x314f, 0xf000 },
392 { 0x3150, 0x0000 },
393 { 0x3151, 0xf000 },
394 { 0x3152, 0x0000 },
395 { 0x3153, 0xf000 },
396 { 0x3154, 0x0000 },
397 { 0x3155, 0xf000 },
398 { 0x3156, 0x0000 },
399 { 0x3157, 0xf000 },
400 { 0x3158, 0x0000 },
401 { 0x3159, 0xf000 },
402 { 0x315a, 0x0000 },
403 { 0x315b, 0xf000 },
404 { 0x315c, 0x0000 },
405 { 0x315d, 0xf000 },
406 { 0x315e, 0x0000 },
407 { 0x315f, 0xf000 },
408 { 0x3160, 0x0000 },
409 { 0x3161, 0xf000 },
410 { 0x3162, 0x0000 },
411 { 0x3163, 0xf000 },
412 { 0x3164, 0x0000 },
413 { 0x3165, 0xf000 },
414 { 0x3166, 0x0000 },
415 { 0x3167, 0xf000 },
416 { 0x3168, 0x0000 },
417 { 0x3169, 0xf000 },
418 { 0x316a, 0x0000 },
419 { 0x316b, 0xf000 },
420 { 0x316c, 0x0000 },
421 { 0x316d, 0xf000 },
422 { 0x316e, 0x0000 },
423 { 0x316f, 0xf000 },
424 { 0x3170, 0x0000 },
425 { 0x3171, 0xf000 },
426 { 0x3172, 0x0000 },
427 { 0x3173, 0xf000 },
428 { 0x3174, 0x0000 },
429 { 0x3175, 0xf000 },
430 { 0x3176, 0x0000 },
431 { 0x3177, 0xf000 },
432 { 0x3178, 0x0000 },
433 { 0x3179, 0xf000 },
434 { 0x317a, 0x0000 },
435 { 0x317b, 0xf000 },
436 { 0x317c, 0x0000 },
437 { 0x317d, 0xf000 },
438 { 0x317e, 0x0000 },
439 { 0x317f, 0xf000 },
440 { 0x3180, 0x2001 },
441 { 0x3181, 0xf101 },
442 { 0x3182, 0x0000 },
443 { 0x3183, 0xf000 },
444 { 0x3184, 0x0000 },
445 { 0x3185, 0xf000 },
446 { 0x3186, 0x0000 },
447 { 0x3187, 0xf000 },
448 { 0x3188, 0x0000 },
449 { 0x3189, 0xf000 },
450 { 0x318a, 0x0000 },
451 { 0x318b, 0xf000 },
452 { 0x318c, 0x0000 },
453 { 0x318d, 0xf000 },
454 { 0x318e, 0x0000 },
455 { 0x318f, 0xf000 },
456 { 0x3190, 0x0000 },
457 { 0x3191, 0xf000 },
458 { 0x3192, 0x0000 },
459 { 0x3193, 0xf000 },
460 { 0x3194, 0x0000 },
461 { 0x3195, 0xf000 },
462 { 0x3196, 0x0000 },
463 { 0x3197, 0xf000 },
464 { 0x3198, 0x0000 },
465 { 0x3199, 0xf000 },
466 { 0x319a, 0x0000 },
467 { 0x319b, 0xf000 },
468 { 0x319c, 0x0000 },
469 { 0x319d, 0xf000 },
470 { 0x319e, 0x0000 },
471 { 0x319f, 0xf000 },
472 { 0x31a0, 0x0000 },
473 { 0x31a1, 0xf000 },
474 { 0x31a2, 0x0000 },
475 { 0x31a3, 0xf000 },
476 { 0x31a4, 0x0000 },
477 { 0x31a5, 0xf000 },
478 { 0x31a6, 0x0000 },
479 { 0x31a7, 0xf000 },
480 { 0x31a8, 0x0000 },
481 { 0x31a9, 0xf000 },
482 { 0x31aa, 0x0000 },
483 { 0x31ab, 0xf000 },
484 { 0x31ac, 0x0000 },
485 { 0x31ad, 0xf000 },
486 { 0x31ae, 0x0000 },
487 { 0x31af, 0xf000 },
488 { 0x31b0, 0x0000 },
489 { 0x31b1, 0xf000 },
490 { 0x31b2, 0x0000 },
491 { 0x31b3, 0xf000 },
492 { 0x31b4, 0x0000 },
493 { 0x31b5, 0xf000 },
494 { 0x31b6, 0x0000 },
495 { 0x31b7, 0xf000 },
496 { 0x31b8, 0x0000 },
497 { 0x31b9, 0xf000 },
498 { 0x31ba, 0x0000 },
499 { 0x31bb, 0xf000 },
500 { 0x31bc, 0x0000 },
501 { 0x31bd, 0xf000 },
502 { 0x31be, 0x0000 },
503 { 0x31bf, 0xf000 },
504 { 0x31c0, 0x0000 },
505 { 0x31c1, 0xf000 },
506 { 0x31c2, 0x0000 },
507 { 0x31c3, 0xf000 },
508 { 0x31c4, 0x0000 },
509 { 0x31c5, 0xf000 },
510 { 0x31c6, 0x0000 },
511 { 0x31c7, 0xf000 },
512 { 0x31c8, 0x0000 },
513 { 0x31c9, 0xf000 },
514 { 0x31ca, 0x0000 },
515 { 0x31cb, 0xf000 },
516 { 0x31cc, 0x0000 },
517 { 0x31cd, 0xf000 },
518 { 0x31ce, 0x0000 },
519 { 0x31cf, 0xf000 },
520 { 0x31d0, 0x0000 },
521 { 0x31d1, 0xf000 },
522 { 0x31d2, 0x0000 },
523 { 0x31d3, 0xf000 },
524 { 0x31d4, 0x0000 },
525 { 0x31d5, 0xf000 },
526 { 0x31d6, 0x0000 },
527 { 0x31d7, 0xf000 },
528 { 0x31d8, 0x0000 },
529 { 0x31d9, 0xf000 },
530 { 0x31da, 0x0000 },
531 { 0x31db, 0xf000 },
532 { 0x31dc, 0x0000 },
533 { 0x31dd, 0xf000 },
534 { 0x31de, 0x0000 },
535 { 0x31df, 0xf000 },
536 { 0x31e0, 0x0000 },
537 { 0x31e1, 0xf000 },
538 { 0x31e2, 0x0000 },
539 { 0x31e3, 0xf000 },
540 { 0x31e4, 0x0000 },
541 { 0x31e5, 0xf000 },
542 { 0x31e6, 0x0000 },
543 { 0x31e7, 0xf000 },
544 { 0x31e8, 0x0000 },
545 { 0x31e9, 0xf000 },
546 { 0x31ea, 0x0000 },
547 { 0x31eb, 0xf000 },
548 { 0x31ec, 0x0000 },
549 { 0x31ed, 0xf000 },
550 { 0x31ee, 0x0000 },
551 { 0x31ef, 0xf000 },
552 { 0x31f0, 0x0000 },
553 { 0x31f1, 0xf000 },
554 { 0x31f2, 0x0000 },
555 { 0x31f3, 0xf000 },
556 { 0x31f4, 0x0000 },
557 { 0x31f5, 0xf000 },
558 { 0x31f6, 0x0000 },
559 { 0x31f7, 0xf000 },
560 { 0x31f8, 0x0000 },
561 { 0x31f9, 0xf000 },
562 { 0x31fa, 0x0000 },
563 { 0x31fb, 0xf000 },
564 { 0x31fc, 0x0000 },
565 { 0x31fd, 0xf000 },
566 { 0x31fe, 0x0000 },
567 { 0x31ff, 0xf000 },
568 { 0x024d, 0xff50 },
569 { 0x0252, 0xff50 },
570 { 0x0259, 0x0112 },
571 { 0x025e, 0x0112 },
572 { 0x101, 0x0304 },
573 { 0x80, 0x0000 },
574};
575
576/* We use a function so we can use ARRAY_SIZE() */
577int wm5102_patch(struct arizona *arizona)
578{
579 switch (arizona->rev) {
580 case 0:
581 return regmap_register_patch(arizona->regmap,
582 wm5102_reva_patch,
583 ARRAY_SIZE(wm5102_reva_patch));
584 default:
585 return 0;
586 }
587}
588
589static const struct regmap_irq wm5102_aod_irqs[ARIZONA_NUM_IRQ] = {
590 [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
591 [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
592 [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
593 [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
594};
595
596const struct regmap_irq_chip wm5102_aod = {
597 .name = "wm5102 AOD",
598 .status_base = ARIZONA_AOD_IRQ1,
599 .mask_base = ARIZONA_AOD_IRQ_MASK_IRQ1,
600 .ack_base = ARIZONA_AOD_IRQ1,
601 .wake_base = ARIZONA_WAKE_CONTROL,
602 .num_regs = 1,
603 .irqs = wm5102_aod_irqs,
604 .num_irqs = ARRAY_SIZE(wm5102_aod_irqs),
605};
606
607static const struct regmap_irq wm5102_irqs[ARIZONA_NUM_IRQ] = {
608 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
609 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
610 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
611 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
612
613 [ARIZONA_IRQ_DSP1_RAM_RDY] = {
614 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
615 },
616 [ARIZONA_IRQ_DSP_IRQ2] = {
617 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
618 },
619 [ARIZONA_IRQ_DSP_IRQ1] = {
620 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
621 },
622
623 [ARIZONA_IRQ_SPK_SHUTDOWN_WARN] = {
624 .reg_offset = 2, .mask = ARIZONA_SPK_SHUTDOWN_WARN_EINT1
625 },
626 [ARIZONA_IRQ_SPK_SHUTDOWN] = {
627 .reg_offset = 2, .mask = ARIZONA_SPK_SHUTDOWN_EINT1
628 },
629 [ARIZONA_IRQ_HPDET] = {
630 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
631 },
632 [ARIZONA_IRQ_MICDET] = {
633 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
634 },
635 [ARIZONA_IRQ_WSEQ_DONE] = {
636 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
637 },
638 [ARIZONA_IRQ_DRC2_SIG_DET] = {
639 .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1
640 },
641 [ARIZONA_IRQ_DRC1_SIG_DET] = {
642 .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
643 },
644 [ARIZONA_IRQ_ASRC2_LOCK] = {
645 .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
646 },
647 [ARIZONA_IRQ_ASRC1_LOCK] = {
648 .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
649 },
650 [ARIZONA_IRQ_UNDERCLOCKED] = {
651 .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1
652 },
653 [ARIZONA_IRQ_OVERCLOCKED] = {
654 .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
655 },
656 [ARIZONA_IRQ_FLL2_LOCK] = {
657 .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
658 },
659 [ARIZONA_IRQ_FLL1_LOCK] = {
660 .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
661 },
662 [ARIZONA_IRQ_CLKGEN_ERR] = {
663 .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
664 },
665 [ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = {
666 .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1
667 },
668
669 [ARIZONA_IRQ_ASRC_CFG_ERR] = {
670 .reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1
671 },
672 [ARIZONA_IRQ_AIF3_ERR] = {
673 .reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1
674 },
675 [ARIZONA_IRQ_AIF2_ERR] = {
676 .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1
677 },
678 [ARIZONA_IRQ_AIF1_ERR] = {
679 .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1
680 },
681 [ARIZONA_IRQ_CTRLIF_ERR] = {
682 .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1
683 },
684 [ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = {
685 .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1
686 },
687 [ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = {
688 .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1
689 },
690 [ARIZONA_IRQ_SYSCLK_ENA_LOW] = {
691 .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1
692 },
693 [ARIZONA_IRQ_ISRC1_CFG_ERR] = {
694 .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1
695 },
696 [ARIZONA_IRQ_ISRC2_CFG_ERR] = {
697 .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1
698 },
699
700 [ARIZONA_IRQ_BOOT_DONE] = {
701 .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1
702 },
703 [ARIZONA_IRQ_DCS_DAC_DONE] = {
704 .reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1
705 },
706 [ARIZONA_IRQ_DCS_HP_DONE] = {
707 .reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1
708 },
709 [ARIZONA_IRQ_FLL2_CLOCK_OK] = {
710 .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1
711 },
712 [ARIZONA_IRQ_FLL1_CLOCK_OK] = {
713 .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1
714 },
715};
716
717const struct regmap_irq_chip wm5102_irq = {
718 .name = "wm5102 IRQ",
719 .status_base = ARIZONA_INTERRUPT_STATUS_1,
720 .mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK,
721 .ack_base = ARIZONA_INTERRUPT_STATUS_1,
722 .num_regs = 5,
723 .irqs = wm5102_irqs,
724 .num_irqs = ARRAY_SIZE(wm5102_irqs),
725};
726
727static const struct reg_default wm5102_reg_default[] = {
728 { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
729 { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
730 { 0x0000000D, 0x0000 }, /* R13 - Ctrl IF Status 1 */
731 { 0x00000016, 0x0000 }, /* R22 - Write Sequencer Ctrl 0 */
732 { 0x00000017, 0x0000 }, /* R23 - Write Sequencer Ctrl 1 */
733 { 0x00000018, 0x0000 }, /* R24 - Write Sequencer Ctrl 2 */
734 { 0x0000001A, 0x0000 }, /* R26 - Write Sequencer PROM */
735 { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
736 { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
737 { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
738 { 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */
739 { 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */
740 { 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */
741 { 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */
742 { 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */
743 { 0x00000040, 0x0000 }, /* R64 - Wake control */
744 { 0x00000041, 0x0000 }, /* R65 - Sequence control */
745 { 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */
746 { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */
747 { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */
748 { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */
749 { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 1 */
750 { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 2 */
751 { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 3 */
752 { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 4 */
753 { 0x0000006C, 0x01FF }, /* R108 - Always On Triggers Sequence Select 5 */
754 { 0x0000006D, 0x01FF }, /* R109 - Always On Triggers Sequence Select 6 */
755 { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */
756 { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */
757 { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */
758 { 0x00000092, 0x0000 }, /* R146 - Haptics phase 1 intensity */
759 { 0x00000093, 0x0000 }, /* R147 - Haptics phase 1 duration */
760 { 0x00000094, 0x0000 }, /* R148 - Haptics phase 2 intensity */
761 { 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */
762 { 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */
763 { 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */
764 { 0x00000100, 0x0001 }, /* R256 - Clock 32k 1 */
765 { 0x00000101, 0x0304 }, /* R257 - System Clock 1 */
766 { 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */
767 { 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */
768 { 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */
769 { 0x00000112, 0x0305 }, /* R274 - Async clock 1 */
770 { 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */
771 { 0x00000149, 0x0000 }, /* R329 - Output system clock */
772 { 0x0000014A, 0x0000 }, /* R330 - Output async clock */
773 { 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */
774 { 0x00000153, 0x0000 }, /* R339 - Rate Estimator 2 */
775 { 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */
776 { 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */
777 { 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */
778 { 0x00000171, 0x0000 }, /* R369 - FLL1 Control 1 */
779 { 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */
780 { 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */
781 { 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */
782 { 0x00000175, 0x0004 }, /* R373 - FLL1 Control 5 */
783 { 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */
784 { 0x00000177, 0x0181 }, /* R375 - FLL1 Loop Filter Test 1 */
785 { 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */
786 { 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */
787 { 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */
788 { 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */
789 { 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */
790 { 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */
791 { 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */
792 { 0x0000018A, 0x0004 }, /* R394 - FLL1 GPIO Clock */
793 { 0x00000191, 0x0000 }, /* R401 - FLL2 Control 1 */
794 { 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */
795 { 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */
796 { 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */
797 { 0x00000195, 0x0004 }, /* R405 - FLL2 Control 5 */
798 { 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */
799 { 0x00000197, 0x0000 }, /* R407 - FLL2 Loop Filter Test 1 */
800 { 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */
801 { 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */
802 { 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */
803 { 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */
804 { 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */
805 { 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */
806 { 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */
807 { 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */
808 { 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */
809 { 0x00000210, 0x00D4 }, /* R528 - LDO1 Control 1 */
810 { 0x00000213, 0x0344 }, /* R531 - LDO2 Control 1 */
811 { 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */
812 { 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */
813 { 0x0000021A, 0x01A6 }, /* R538 - Mic Bias Ctrl 3 */
814 { 0x00000293, 0x0000 }, /* R659 - Accessory Detect Mode 1 */
815 { 0x0000029B, 0x0020 }, /* R667 - Headphone Detect 1 */
816 { 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */
817 { 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */
818 { 0x000002A5, 0x0000 }, /* R677 - Mic Detect 3 */
819 { 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */
820 { 0x000002CB, 0x0000 }, /* R715 - Isolation control */
821 { 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */
822 { 0x00000300, 0x0000 }, /* R768 - Input Enables */
823 { 0x00000308, 0x0000 }, /* R776 - Input Rate */
824 { 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */
825 { 0x00000310, 0x2080 }, /* R784 - IN1L Control */
826 { 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */
827 { 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */
828 { 0x00000314, 0x0080 }, /* R788 - IN1R Control */
829 { 0x00000315, 0x0180 }, /* R789 - ADC Digital Volume 1R */
830 { 0x00000316, 0x0000 }, /* R790 - DMIC1R Control */
831 { 0x00000318, 0x2080 }, /* R792 - IN2L Control */
832 { 0x00000319, 0x0180 }, /* R793 - ADC Digital Volume 2L */
833 { 0x0000031A, 0x0000 }, /* R794 - DMIC2L Control */
834 { 0x0000031C, 0x0080 }, /* R796 - IN2R Control */
835 { 0x0000031D, 0x0180 }, /* R797 - ADC Digital Volume 2R */
836 { 0x0000031E, 0x0000 }, /* R798 - DMIC2R Control */
837 { 0x00000320, 0x2080 }, /* R800 - IN3L Control */
838 { 0x00000321, 0x0180 }, /* R801 - ADC Digital Volume 3L */
839 { 0x00000322, 0x0000 }, /* R802 - DMIC3L Control */
840 { 0x00000324, 0x0080 }, /* R804 - IN3R Control */
841 { 0x00000325, 0x0180 }, /* R805 - ADC Digital Volume 3R */
842 { 0x00000326, 0x0000 }, /* R806 - DMIC3R Control */
843 { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */
844 { 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */
845 { 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */
846 { 0x00000410, 0x0080 }, /* R1040 - Output Path Config 1L */
847 { 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */
848 { 0x00000412, 0x0080 }, /* R1042 - DAC Volume Limit 1L */
849 { 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */
850 { 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */
851 { 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */
852 { 0x00000416, 0x0080 }, /* R1046 - DAC Volume Limit 1R */
853 { 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */
854 { 0x00000418, 0x0080 }, /* R1048 - Output Path Config 2L */
855 { 0x00000419, 0x0180 }, /* R1049 - DAC Digital Volume 2L */
856 { 0x0000041A, 0x0080 }, /* R1050 - DAC Volume Limit 2L */
857 { 0x0000041B, 0x0004 }, /* R1051 - Noise Gate Select 2L */
858 { 0x0000041C, 0x0080 }, /* R1052 - Output Path Config 2R */
859 { 0x0000041D, 0x0180 }, /* R1053 - DAC Digital Volume 2R */
860 { 0x0000041E, 0x0080 }, /* R1054 - DAC Volume Limit 2R */
861 { 0x0000041F, 0x0008 }, /* R1055 - Noise Gate Select 2R */
862 { 0x00000420, 0x0080 }, /* R1056 - Output Path Config 3L */
863 { 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */
864 { 0x00000422, 0x0080 }, /* R1058 - DAC Volume Limit 3L */
865 { 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */
866 { 0x00000424, 0x0080 }, /* R1060 - Output Path Config 3R */
867 { 0x00000425, 0x0180 }, /* R1061 - DAC Digital Volume 3R */
868 { 0x00000426, 0x0080 }, /* R1062 - DAC Volume Limit 3R */
869 { 0x00000428, 0x0000 }, /* R1064 - Output Path Config 4L */
870 { 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */
871 { 0x0000042A, 0x0080 }, /* R1066 - Out Volume 4L */
872 { 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */
873 { 0x0000042C, 0x0000 }, /* R1068 - Output Path Config 4R */
874 { 0x0000042D, 0x0180 }, /* R1069 - DAC Digital Volume 4R */
875 { 0x0000042E, 0x0080 }, /* R1070 - Out Volume 4R */
876 { 0x0000042F, 0x0080 }, /* R1071 - Noise Gate Select 4R */
877 { 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */
878 { 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */
879 { 0x00000432, 0x0080 }, /* R1074 - DAC Volume Limit 5L */
880 { 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */
881 { 0x00000434, 0x0000 }, /* R1076 - Output Path Config 5R */
882 { 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */
883 { 0x00000436, 0x0080 }, /* R1078 - DAC Volume Limit 5R */
884 { 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */
885 { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
886 { 0x00000458, 0x0001 }, /* R1112 - Noise Gate Control */
887 { 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */
888 { 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */
889 { 0x000004DC, 0x0000 }, /* R1244 - DAC comp 1 */
890 { 0x000004DD, 0x0000 }, /* R1245 - DAC comp 2 */
891 { 0x000004DE, 0x0000 }, /* R1246 - DAC comp 3 */
892 { 0x000004DF, 0x0000 }, /* R1247 - DAC comp 4 */
893 { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */
894 { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */
895 { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */
896 { 0x00000503, 0x0000 }, /* R1283 - AIF1 Rate Ctrl */
897 { 0x00000504, 0x0000 }, /* R1284 - AIF1 Format */
898 { 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */
899 { 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */
900 { 0x00000507, 0x1818 }, /* R1287 - AIF1 Frame Ctrl 1 */
901 { 0x00000508, 0x1818 }, /* R1288 - AIF1 Frame Ctrl 2 */
902 { 0x00000509, 0x0000 }, /* R1289 - AIF1 Frame Ctrl 3 */
903 { 0x0000050A, 0x0001 }, /* R1290 - AIF1 Frame Ctrl 4 */
904 { 0x0000050B, 0x0002 }, /* R1291 - AIF1 Frame Ctrl 5 */
905 { 0x0000050C, 0x0003 }, /* R1292 - AIF1 Frame Ctrl 6 */
906 { 0x0000050D, 0x0004 }, /* R1293 - AIF1 Frame Ctrl 7 */
907 { 0x0000050E, 0x0005 }, /* R1294 - AIF1 Frame Ctrl 8 */
908 { 0x0000050F, 0x0006 }, /* R1295 - AIF1 Frame Ctrl 9 */
909 { 0x00000510, 0x0007 }, /* R1296 - AIF1 Frame Ctrl 10 */
910 { 0x00000511, 0x0000 }, /* R1297 - AIF1 Frame Ctrl 11 */
911 { 0x00000512, 0x0001 }, /* R1298 - AIF1 Frame Ctrl 12 */
912 { 0x00000513, 0x0002 }, /* R1299 - AIF1 Frame Ctrl 13 */
913 { 0x00000514, 0x0003 }, /* R1300 - AIF1 Frame Ctrl 14 */
914 { 0x00000515, 0x0004 }, /* R1301 - AIF1 Frame Ctrl 15 */
915 { 0x00000516, 0x0005 }, /* R1302 - AIF1 Frame Ctrl 16 */
916 { 0x00000517, 0x0006 }, /* R1303 - AIF1 Frame Ctrl 17 */
917 { 0x00000518, 0x0007 }, /* R1304 - AIF1 Frame Ctrl 18 */
918 { 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */
919 { 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */
920 { 0x0000051B, 0x0000 }, /* R1307 - AIF1 Force Write */
921 { 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */
922 { 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */
923 { 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */
924 { 0x00000543, 0x0000 }, /* R1347 - AIF2 Rate Ctrl */
925 { 0x00000544, 0x0000 }, /* R1348 - AIF2 Format */
926 { 0x00000545, 0x0040 }, /* R1349 - AIF2 Tx BCLK Rate */
927 { 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */
928 { 0x00000547, 0x1818 }, /* R1351 - AIF2 Frame Ctrl 1 */
929 { 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */
930 { 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */
931 { 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */
932 { 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */
933 { 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */
934 { 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */
935 { 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */
936 { 0x0000055B, 0x0000 }, /* R1371 - AIF2 Force Write */
937 { 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */
938 { 0x00000581, 0x0008 }, /* R1409 - AIF3 Tx Pin Ctrl */
939 { 0x00000582, 0x0000 }, /* R1410 - AIF3 Rx Pin Ctrl */
940 { 0x00000583, 0x0000 }, /* R1411 - AIF3 Rate Ctrl */
941 { 0x00000584, 0x0000 }, /* R1412 - AIF3 Format */
942 { 0x00000585, 0x0040 }, /* R1413 - AIF3 Tx BCLK Rate */
943 { 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */
944 { 0x00000587, 0x1818 }, /* R1415 - AIF3 Frame Ctrl 1 */
945 { 0x00000588, 0x1818 }, /* R1416 - AIF3 Frame Ctrl 2 */
946 { 0x00000589, 0x0000 }, /* R1417 - AIF3 Frame Ctrl 3 */
947 { 0x0000058A, 0x0001 }, /* R1418 - AIF3 Frame Ctrl 4 */
948 { 0x00000591, 0x0000 }, /* R1425 - AIF3 Frame Ctrl 11 */
949 { 0x00000592, 0x0001 }, /* R1426 - AIF3 Frame Ctrl 12 */
950 { 0x00000599, 0x0000 }, /* R1433 - AIF3 Tx Enables */
951 { 0x0000059A, 0x0000 }, /* R1434 - AIF3 Rx Enables */
952 { 0x0000059B, 0x0000 }, /* R1435 - AIF3 Force Write */
953 { 0x000005E3, 0x0004 }, /* R1507 - SLIMbus Framer Ref Gear */
954 { 0x000005E5, 0x0000 }, /* R1509 - SLIMbus Rates 1 */
955 { 0x000005E6, 0x0000 }, /* R1510 - SLIMbus Rates 2 */
956 { 0x000005E7, 0x0000 }, /* R1511 - SLIMbus Rates 3 */
957 { 0x000005E8, 0x0000 }, /* R1512 - SLIMbus Rates 4 */
958 { 0x000005E9, 0x0000 }, /* R1513 - SLIMbus Rates 5 */
959 { 0x000005EA, 0x0000 }, /* R1514 - SLIMbus Rates 6 */
960 { 0x000005EB, 0x0000 }, /* R1515 - SLIMbus Rates 7 */
961 { 0x000005EC, 0x0000 }, /* R1516 - SLIMbus Rates 8 */
962 { 0x000005F5, 0x0000 }, /* R1525 - SLIMbus RX Channel Enable */
963 { 0x000005F6, 0x0000 }, /* R1526 - SLIMbus TX Channel Enable */
964 { 0x00000640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */
965 { 0x00000641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */
966 { 0x00000642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */
967 { 0x00000643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */
968 { 0x00000644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */
969 { 0x00000645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */
970 { 0x00000646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */
971 { 0x00000647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */
972 { 0x00000648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */
973 { 0x00000649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */
974 { 0x0000064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */
975 { 0x0000064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */
976 { 0x0000064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */
977 { 0x0000064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */
978 { 0x0000064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */
979 { 0x0000064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */
980 { 0x00000660, 0x0000 }, /* R1632 - MICMIX Input 1 Source */
981 { 0x00000661, 0x0080 }, /* R1633 - MICMIX Input 1 Volume */
982 { 0x00000662, 0x0000 }, /* R1634 - MICMIX Input 2 Source */
983 { 0x00000663, 0x0080 }, /* R1635 - MICMIX Input 2 Volume */
984 { 0x00000664, 0x0000 }, /* R1636 - MICMIX Input 3 Source */
985 { 0x00000665, 0x0080 }, /* R1637 - MICMIX Input 3 Volume */
986 { 0x00000666, 0x0000 }, /* R1638 - MICMIX Input 4 Source */
987 { 0x00000667, 0x0080 }, /* R1639 - MICMIX Input 4 Volume */
988 { 0x00000668, 0x0000 }, /* R1640 - NOISEMIX Input 1 Source */
989 { 0x00000669, 0x0080 }, /* R1641 - NOISEMIX Input 1 Volume */
990 { 0x0000066A, 0x0000 }, /* R1642 - NOISEMIX Input 2 Source */
991 { 0x0000066B, 0x0080 }, /* R1643 - NOISEMIX Input 2 Volume */
992 { 0x0000066C, 0x0000 }, /* R1644 - NOISEMIX Input 3 Source */
993 { 0x0000066D, 0x0080 }, /* R1645 - NOISEMIX Input 3 Volume */
994 { 0x0000066E, 0x0000 }, /* R1646 - NOISEMIX Input 4 Source */
995 { 0x0000066F, 0x0080 }, /* R1647 - NOISEMIX Input 4 Volume */
996 { 0x00000680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */
997 { 0x00000681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */
998 { 0x00000682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */
999 { 0x00000683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */
1000 { 0x00000684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */
1001 { 0x00000685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */
1002 { 0x00000686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */
1003 { 0x00000687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */
1004 { 0x00000688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */
1005 { 0x00000689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */
1006 { 0x0000068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */
1007 { 0x0000068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */
1008 { 0x0000068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */
1009 { 0x0000068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */
1010 { 0x0000068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */
1011 { 0x0000068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */
1012 { 0x00000690, 0x0000 }, /* R1680 - OUT2LMIX Input 1 Source */
1013 { 0x00000691, 0x0080 }, /* R1681 - OUT2LMIX Input 1 Volume */
1014 { 0x00000692, 0x0000 }, /* R1682 - OUT2LMIX Input 2 Source */
1015 { 0x00000693, 0x0080 }, /* R1683 - OUT2LMIX Input 2 Volume */
1016 { 0x00000694, 0x0000 }, /* R1684 - OUT2LMIX Input 3 Source */
1017 { 0x00000695, 0x0080 }, /* R1685 - OUT2LMIX Input 3 Volume */
1018 { 0x00000696, 0x0000 }, /* R1686 - OUT2LMIX Input 4 Source */
1019 { 0x00000697, 0x0080 }, /* R1687 - OUT2LMIX Input 4 Volume */
1020 { 0x00000698, 0x0000 }, /* R1688 - OUT2RMIX Input 1 Source */
1021 { 0x00000699, 0x0080 }, /* R1689 - OUT2RMIX Input 1 Volume */
1022 { 0x0000069A, 0x0000 }, /* R1690 - OUT2RMIX Input 2 Source */
1023 { 0x0000069B, 0x0080 }, /* R1691 - OUT2RMIX Input 2 Volume */
1024 { 0x0000069C, 0x0000 }, /* R1692 - OUT2RMIX Input 3 Source */
1025 { 0x0000069D, 0x0080 }, /* R1693 - OUT2RMIX Input 3 Volume */
1026 { 0x0000069E, 0x0000 }, /* R1694 - OUT2RMIX Input 4 Source */
1027 { 0x0000069F, 0x0080 }, /* R1695 - OUT2RMIX Input 4 Volume */
1028 { 0x000006A0, 0x0000 }, /* R1696 - OUT3LMIX Input 1 Source */
1029 { 0x000006A1, 0x0080 }, /* R1697 - OUT3LMIX Input 1 Volume */
1030 { 0x000006A2, 0x0000 }, /* R1698 - OUT3LMIX Input 2 Source */
1031 { 0x000006A3, 0x0080 }, /* R1699 - OUT3LMIX Input 2 Volume */
1032 { 0x000006A4, 0x0000 }, /* R1700 - OUT3LMIX Input 3 Source */
1033 { 0x000006A5, 0x0080 }, /* R1701 - OUT3LMIX Input 3 Volume */
1034 { 0x000006A6, 0x0000 }, /* R1702 - OUT3LMIX Input 4 Source */
1035 { 0x000006A7, 0x0080 }, /* R1703 - OUT3LMIX Input 4 Volume */
1036 { 0x000006B0, 0x0000 }, /* R1712 - OUT4LMIX Input 1 Source */
1037 { 0x000006B1, 0x0080 }, /* R1713 - OUT4LMIX Input 1 Volume */
1038 { 0x000006B2, 0x0000 }, /* R1714 - OUT4LMIX Input 2 Source */
1039 { 0x000006B3, 0x0080 }, /* R1715 - OUT4LMIX Input 2 Volume */
1040 { 0x000006B4, 0x0000 }, /* R1716 - OUT4LMIX Input 3 Source */
1041 { 0x000006B5, 0x0080 }, /* R1717 - OUT4LMIX Input 3 Volume */
1042 { 0x000006B6, 0x0000 }, /* R1718 - OUT4LMIX Input 4 Source */
1043 { 0x000006B7, 0x0080 }, /* R1719 - OUT4LMIX Input 4 Volume */
1044 { 0x000006B8, 0x0000 }, /* R1720 - OUT4RMIX Input 1 Source */
1045 { 0x000006B9, 0x0080 }, /* R1721 - OUT4RMIX Input 1 Volume */
1046 { 0x000006BA, 0x0000 }, /* R1722 - OUT4RMIX Input 2 Source */
1047 { 0x000006BB, 0x0080 }, /* R1723 - OUT4RMIX Input 2 Volume */
1048 { 0x000006BC, 0x0000 }, /* R1724 - OUT4RMIX Input 3 Source */
1049 { 0x000006BD, 0x0080 }, /* R1725 - OUT4RMIX Input 3 Volume */
1050 { 0x000006BE, 0x0000 }, /* R1726 - OUT4RMIX Input 4 Source */
1051 { 0x000006BF, 0x0080 }, /* R1727 - OUT4RMIX Input 4 Volume */
1052 { 0x000006C0, 0x0000 }, /* R1728 - OUT5LMIX Input 1 Source */
1053 { 0x000006C1, 0x0080 }, /* R1729 - OUT5LMIX Input 1 Volume */
1054 { 0x000006C2, 0x0000 }, /* R1730 - OUT5LMIX Input 2 Source */
1055 { 0x000006C3, 0x0080 }, /* R1731 - OUT5LMIX Input 2 Volume */
1056 { 0x000006C4, 0x0000 }, /* R1732 - OUT5LMIX Input 3 Source */
1057 { 0x000006C5, 0x0080 }, /* R1733 - OUT5LMIX Input 3 Volume */
1058 { 0x000006C6, 0x0000 }, /* R1734 - OUT5LMIX Input 4 Source */
1059 { 0x000006C7, 0x0080 }, /* R1735 - OUT5LMIX Input 4 Volume */
1060 { 0x000006C8, 0x0000 }, /* R1736 - OUT5RMIX Input 1 Source */
1061 { 0x000006C9, 0x0080 }, /* R1737 - OUT5RMIX Input 1 Volume */
1062 { 0x000006CA, 0x0000 }, /* R1738 - OUT5RMIX Input 2 Source */
1063 { 0x000006CB, 0x0080 }, /* R1739 - OUT5RMIX Input 2 Volume */
1064 { 0x000006CC, 0x0000 }, /* R1740 - OUT5RMIX Input 3 Source */
1065 { 0x000006CD, 0x0080 }, /* R1741 - OUT5RMIX Input 3 Volume */
1066 { 0x000006CE, 0x0000 }, /* R1742 - OUT5RMIX Input 4 Source */
1067 { 0x000006CF, 0x0080 }, /* R1743 - OUT5RMIX Input 4 Volume */
1068 { 0x00000700, 0x0000 }, /* R1792 - AIF1TX1MIX Input 1 Source */
1069 { 0x00000701, 0x0080 }, /* R1793 - AIF1TX1MIX Input 1 Volume */
1070 { 0x00000702, 0x0000 }, /* R1794 - AIF1TX1MIX Input 2 Source */
1071 { 0x00000703, 0x0080 }, /* R1795 - AIF1TX1MIX Input 2 Volume */
1072 { 0x00000704, 0x0000 }, /* R1796 - AIF1TX1MIX Input 3 Source */
1073 { 0x00000705, 0x0080 }, /* R1797 - AIF1TX1MIX Input 3 Volume */
1074 { 0x00000706, 0x0000 }, /* R1798 - AIF1TX1MIX Input 4 Source */
1075 { 0x00000707, 0x0080 }, /* R1799 - AIF1TX1MIX Input 4 Volume */
1076 { 0x00000708, 0x0000 }, /* R1800 - AIF1TX2MIX Input 1 Source */
1077 { 0x00000709, 0x0080 }, /* R1801 - AIF1TX2MIX Input 1 Volume */
1078 { 0x0000070A, 0x0000 }, /* R1802 - AIF1TX2MIX Input 2 Source */
1079 { 0x0000070B, 0x0080 }, /* R1803 - AIF1TX2MIX Input 2 Volume */
1080 { 0x0000070C, 0x0000 }, /* R1804 - AIF1TX2MIX Input 3 Source */
1081 { 0x0000070D, 0x0080 }, /* R1805 - AIF1TX2MIX Input 3 Volume */
1082 { 0x0000070E, 0x0000 }, /* R1806 - AIF1TX2MIX Input 4 Source */
1083 { 0x0000070F, 0x0080 }, /* R1807 - AIF1TX2MIX Input 4 Volume */
1084 { 0x00000710, 0x0000 }, /* R1808 - AIF1TX3MIX Input 1 Source */
1085 { 0x00000711, 0x0080 }, /* R1809 - AIF1TX3MIX Input 1 Volume */
1086 { 0x00000712, 0x0000 }, /* R1810 - AIF1TX3MIX Input 2 Source */
1087 { 0x00000713, 0x0080 }, /* R1811 - AIF1TX3MIX Input 2 Volume */
1088 { 0x00000714, 0x0000 }, /* R1812 - AIF1TX3MIX Input 3 Source */
1089 { 0x00000715, 0x0080 }, /* R1813 - AIF1TX3MIX Input 3 Volume */
1090 { 0x00000716, 0x0000 }, /* R1814 - AIF1TX3MIX Input 4 Source */
1091 { 0x00000717, 0x0080 }, /* R1815 - AIF1TX3MIX Input 4 Volume */
1092 { 0x00000718, 0x0000 }, /* R1816 - AIF1TX4MIX Input 1 Source */
1093 { 0x00000719, 0x0080 }, /* R1817 - AIF1TX4MIX Input 1 Volume */
1094 { 0x0000071A, 0x0000 }, /* R1818 - AIF1TX4MIX Input 2 Source */
1095 { 0x0000071B, 0x0080 }, /* R1819 - AIF1TX4MIX Input 2 Volume */
1096 { 0x0000071C, 0x0000 }, /* R1820 - AIF1TX4MIX Input 3 Source */
1097 { 0x0000071D, 0x0080 }, /* R1821 - AIF1TX4MIX Input 3 Volume */
1098 { 0x0000071E, 0x0000 }, /* R1822 - AIF1TX4MIX Input 4 Source */
1099 { 0x0000071F, 0x0080 }, /* R1823 - AIF1TX4MIX Input 4 Volume */
1100 { 0x00000720, 0x0000 }, /* R1824 - AIF1TX5MIX Input 1 Source */
1101 { 0x00000721, 0x0080 }, /* R1825 - AIF1TX5MIX Input 1 Volume */
1102 { 0x00000722, 0x0000 }, /* R1826 - AIF1TX5MIX Input 2 Source */
1103 { 0x00000723, 0x0080 }, /* R1827 - AIF1TX5MIX Input 2 Volume */
1104 { 0x00000724, 0x0000 }, /* R1828 - AIF1TX5MIX Input 3 Source */
1105 { 0x00000725, 0x0080 }, /* R1829 - AIF1TX5MIX Input 3 Volume */
1106 { 0x00000726, 0x0000 }, /* R1830 - AIF1TX5MIX Input 4 Source */
1107 { 0x00000727, 0x0080 }, /* R1831 - AIF1TX5MIX Input 4 Volume */
1108 { 0x00000728, 0x0000 }, /* R1832 - AIF1TX6MIX Input 1 Source */
1109 { 0x00000729, 0x0080 }, /* R1833 - AIF1TX6MIX Input 1 Volume */
1110 { 0x0000072A, 0x0000 }, /* R1834 - AIF1TX6MIX Input 2 Source */
1111 { 0x0000072B, 0x0080 }, /* R1835 - AIF1TX6MIX Input 2 Volume */
1112 { 0x0000072C, 0x0000 }, /* R1836 - AIF1TX6MIX Input 3 Source */
1113 { 0x0000072D, 0x0080 }, /* R1837 - AIF1TX6MIX Input 3 Volume */
1114 { 0x0000072E, 0x0000 }, /* R1838 - AIF1TX6MIX Input 4 Source */
1115 { 0x0000072F, 0x0080 }, /* R1839 - AIF1TX6MIX Input 4 Volume */
1116 { 0x00000730, 0x0000 }, /* R1840 - AIF1TX7MIX Input 1 Source */
1117 { 0x00000731, 0x0080 }, /* R1841 - AIF1TX7MIX Input 1 Volume */
1118 { 0x00000732, 0x0000 }, /* R1842 - AIF1TX7MIX Input 2 Source */
1119 { 0x00000733, 0x0080 }, /* R1843 - AIF1TX7MIX Input 2 Volume */
1120 { 0x00000734, 0x0000 }, /* R1844 - AIF1TX7MIX Input 3 Source */
1121 { 0x00000735, 0x0080 }, /* R1845 - AIF1TX7MIX Input 3 Volume */
1122 { 0x00000736, 0x0000 }, /* R1846 - AIF1TX7MIX Input 4 Source */
1123 { 0x00000737, 0x0080 }, /* R1847 - AIF1TX7MIX Input 4 Volume */
1124 { 0x00000738, 0x0000 }, /* R1848 - AIF1TX8MIX Input 1 Source */
1125 { 0x00000739, 0x0080 }, /* R1849 - AIF1TX8MIX Input 1 Volume */
1126 { 0x0000073A, 0x0000 }, /* R1850 - AIF1TX8MIX Input 2 Source */
1127 { 0x0000073B, 0x0080 }, /* R1851 - AIF1TX8MIX Input 2 Volume */
1128 { 0x0000073C, 0x0000 }, /* R1852 - AIF1TX8MIX Input 3 Source */
1129 { 0x0000073D, 0x0080 }, /* R1853 - AIF1TX8MIX Input 3 Volume */
1130 { 0x0000073E, 0x0000 }, /* R1854 - AIF1TX8MIX Input 4 Source */
1131 { 0x0000073F, 0x0080 }, /* R1855 - AIF1TX8MIX Input 4 Volume */
1132 { 0x00000740, 0x0000 }, /* R1856 - AIF2TX1MIX Input 1 Source */
1133 { 0x00000741, 0x0080 }, /* R1857 - AIF2TX1MIX Input 1 Volume */
1134 { 0x00000742, 0x0000 }, /* R1858 - AIF2TX1MIX Input 2 Source */
1135 { 0x00000743, 0x0080 }, /* R1859 - AIF2TX1MIX Input 2 Volume */
1136 { 0x00000744, 0x0000 }, /* R1860 - AIF2TX1MIX Input 3 Source */
1137 { 0x00000745, 0x0080 }, /* R1861 - AIF2TX1MIX Input 3 Volume */
1138 { 0x00000746, 0x0000 }, /* R1862 - AIF2TX1MIX Input 4 Source */
1139 { 0x00000747, 0x0080 }, /* R1863 - AIF2TX1MIX Input 4 Volume */
1140 { 0x00000748, 0x0000 }, /* R1864 - AIF2TX2MIX Input 1 Source */
1141 { 0x00000749, 0x0080 }, /* R1865 - AIF2TX2MIX Input 1 Volume */
1142 { 0x0000074A, 0x0000 }, /* R1866 - AIF2TX2MIX Input 2 Source */
1143 { 0x0000074B, 0x0080 }, /* R1867 - AIF2TX2MIX Input 2 Volume */
1144 { 0x0000074C, 0x0000 }, /* R1868 - AIF2TX2MIX Input 3 Source */
1145 { 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */
1146 { 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */
1147 { 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */
1148 { 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */
1149 { 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */
1150 { 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */
1151 { 0x00000783, 0x0080 }, /* R1923 - AIF3TX1MIX Input 2 Volume */
1152 { 0x00000784, 0x0000 }, /* R1924 - AIF3TX1MIX Input 3 Source */
1153 { 0x00000785, 0x0080 }, /* R1925 - AIF3TX1MIX Input 3 Volume */
1154 { 0x00000786, 0x0000 }, /* R1926 - AIF3TX1MIX Input 4 Source */
1155 { 0x00000787, 0x0080 }, /* R1927 - AIF3TX1MIX Input 4 Volume */
1156 { 0x00000788, 0x0000 }, /* R1928 - AIF3TX2MIX Input 1 Source */
1157 { 0x00000789, 0x0080 }, /* R1929 - AIF3TX2MIX Input 1 Volume */
1158 { 0x0000078A, 0x0000 }, /* R1930 - AIF3TX2MIX Input 2 Source */
1159 { 0x0000078B, 0x0080 }, /* R1931 - AIF3TX2MIX Input 2 Volume */
1160 { 0x0000078C, 0x0000 }, /* R1932 - AIF3TX2MIX Input 3 Source */
1161 { 0x0000078D, 0x0080 }, /* R1933 - AIF3TX2MIX Input 3 Volume */
1162 { 0x0000078E, 0x0000 }, /* R1934 - AIF3TX2MIX Input 4 Source */
1163 { 0x0000078F, 0x0080 }, /* R1935 - AIF3TX2MIX Input 4 Volume */
1164 { 0x000007C0, 0x0000 }, /* R1984 - SLIMTX1MIX Input 1 Source */
1165 { 0x000007C1, 0x0080 }, /* R1985 - SLIMTX1MIX Input 1 Volume */
1166 { 0x000007C2, 0x0000 }, /* R1986 - SLIMTX1MIX Input 2 Source */
1167 { 0x000007C3, 0x0080 }, /* R1987 - SLIMTX1MIX Input 2 Volume */
1168 { 0x000007C4, 0x0000 }, /* R1988 - SLIMTX1MIX Input 3 Source */
1169 { 0x000007C5, 0x0080 }, /* R1989 - SLIMTX1MIX Input 3 Volume */
1170 { 0x000007C6, 0x0000 }, /* R1990 - SLIMTX1MIX Input 4 Source */
1171 { 0x000007C7, 0x0080 }, /* R1991 - SLIMTX1MIX Input 4 Volume */
1172 { 0x000007C8, 0x0000 }, /* R1992 - SLIMTX2MIX Input 1 Source */
1173 { 0x000007C9, 0x0080 }, /* R1993 - SLIMTX2MIX Input 1 Volume */
1174 { 0x000007CA, 0x0000 }, /* R1994 - SLIMTX2MIX Input 2 Source */
1175 { 0x000007CB, 0x0080 }, /* R1995 - SLIMTX2MIX Input 2 Volume */
1176 { 0x000007CC, 0x0000 }, /* R1996 - SLIMTX2MIX Input 3 Source */
1177 { 0x000007CD, 0x0080 }, /* R1997 - SLIMTX2MIX Input 3 Volume */
1178 { 0x000007CE, 0x0000 }, /* R1998 - SLIMTX2MIX Input 4 Source */
1179 { 0x000007CF, 0x0080 }, /* R1999 - SLIMTX2MIX Input 4 Volume */
1180 { 0x000007D0, 0x0000 }, /* R2000 - SLIMTX3MIX Input 1 Source */
1181 { 0x000007D1, 0x0080 }, /* R2001 - SLIMTX3MIX Input 1 Volume */
1182 { 0x000007D2, 0x0000 }, /* R2002 - SLIMTX3MIX Input 2 Source */
1183 { 0x000007D3, 0x0080 }, /* R2003 - SLIMTX3MIX Input 2 Volume */
1184 { 0x000007D4, 0x0000 }, /* R2004 - SLIMTX3MIX Input 3 Source */
1185 { 0x000007D5, 0x0080 }, /* R2005 - SLIMTX3MIX Input 3 Volume */
1186 { 0x000007D6, 0x0000 }, /* R2006 - SLIMTX3MIX Input 4 Source */
1187 { 0x000007D7, 0x0080 }, /* R2007 - SLIMTX3MIX Input 4 Volume */
1188 { 0x000007D8, 0x0000 }, /* R2008 - SLIMTX4MIX Input 1 Source */
1189 { 0x000007D9, 0x0080 }, /* R2009 - SLIMTX4MIX Input 1 Volume */
1190 { 0x000007DA, 0x0000 }, /* R2010 - SLIMTX4MIX Input 2 Source */
1191 { 0x000007DB, 0x0080 }, /* R2011 - SLIMTX4MIX Input 2 Volume */
1192 { 0x000007DC, 0x0000 }, /* R2012 - SLIMTX4MIX Input 3 Source */
1193 { 0x000007DD, 0x0080 }, /* R2013 - SLIMTX4MIX Input 3 Volume */
1194 { 0x000007DE, 0x0000 }, /* R2014 - SLIMTX4MIX Input 4 Source */
1195 { 0x000007DF, 0x0080 }, /* R2015 - SLIMTX4MIX Input 4 Volume */
1196 { 0x000007E0, 0x0000 }, /* R2016 - SLIMTX5MIX Input 1 Source */
1197 { 0x000007E1, 0x0080 }, /* R2017 - SLIMTX5MIX Input 1 Volume */
1198 { 0x000007E2, 0x0000 }, /* R2018 - SLIMTX5MIX Input 2 Source */
1199 { 0x000007E3, 0x0080 }, /* R2019 - SLIMTX5MIX Input 2 Volume */
1200 { 0x000007E4, 0x0000 }, /* R2020 - SLIMTX5MIX Input 3 Source */
1201 { 0x000007E5, 0x0080 }, /* R2021 - SLIMTX5MIX Input 3 Volume */
1202 { 0x000007E6, 0x0000 }, /* R2022 - SLIMTX5MIX Input 4 Source */
1203 { 0x000007E7, 0x0080 }, /* R2023 - SLIMTX5MIX Input 4 Volume */
1204 { 0x000007E8, 0x0000 }, /* R2024 - SLIMTX6MIX Input 1 Source */
1205 { 0x000007E9, 0x0080 }, /* R2025 - SLIMTX6MIX Input 1 Volume */
1206 { 0x000007EA, 0x0000 }, /* R2026 - SLIMTX6MIX Input 2 Source */
1207 { 0x000007EB, 0x0080 }, /* R2027 - SLIMTX6MIX Input 2 Volume */
1208 { 0x000007EC, 0x0000 }, /* R2028 - SLIMTX6MIX Input 3 Source */
1209 { 0x000007ED, 0x0080 }, /* R2029 - SLIMTX6MIX Input 3 Volume */
1210 { 0x000007EE, 0x0000 }, /* R2030 - SLIMTX6MIX Input 4 Source */
1211 { 0x000007EF, 0x0080 }, /* R2031 - SLIMTX6MIX Input 4 Volume */
1212 { 0x000007F0, 0x0000 }, /* R2032 - SLIMTX7MIX Input 1 Source */
1213 { 0x000007F1, 0x0080 }, /* R2033 - SLIMTX7MIX Input 1 Volume */
1214 { 0x000007F2, 0x0000 }, /* R2034 - SLIMTX7MIX Input 2 Source */
1215 { 0x000007F3, 0x0080 }, /* R2035 - SLIMTX7MIX Input 2 Volume */
1216 { 0x000007F4, 0x0000 }, /* R2036 - SLIMTX7MIX Input 3 Source */
1217 { 0x000007F5, 0x0080 }, /* R2037 - SLIMTX7MIX Input 3 Volume */
1218 { 0x000007F6, 0x0000 }, /* R2038 - SLIMTX7MIX Input 4 Source */
1219 { 0x000007F7, 0x0080 }, /* R2039 - SLIMTX7MIX Input 4 Volume */
1220 { 0x000007F8, 0x0000 }, /* R2040 - SLIMTX8MIX Input 1 Source */
1221 { 0x000007F9, 0x0080 }, /* R2041 - SLIMTX8MIX Input 1 Volume */
1222 { 0x000007FA, 0x0000 }, /* R2042 - SLIMTX8MIX Input 2 Source */
1223 { 0x000007FB, 0x0080 }, /* R2043 - SLIMTX8MIX Input 2 Volume */
1224 { 0x000007FC, 0x0000 }, /* R2044 - SLIMTX8MIX Input 3 Source */
1225 { 0x000007FD, 0x0080 }, /* R2045 - SLIMTX8MIX Input 3 Volume */
1226 { 0x000007FE, 0x0000 }, /* R2046 - SLIMTX8MIX Input 4 Source */
1227 { 0x000007FF, 0x0080 }, /* R2047 - SLIMTX8MIX Input 4 Volume */
1228 { 0x00000880, 0x0000 }, /* R2176 - EQ1MIX Input 1 Source */
1229 { 0x00000881, 0x0080 }, /* R2177 - EQ1MIX Input 1 Volume */
1230 { 0x00000882, 0x0000 }, /* R2178 - EQ1MIX Input 2 Source */
1231 { 0x00000883, 0x0080 }, /* R2179 - EQ1MIX Input 2 Volume */
1232 { 0x00000884, 0x0000 }, /* R2180 - EQ1MIX Input 3 Source */
1233 { 0x00000885, 0x0080 }, /* R2181 - EQ1MIX Input 3 Volume */
1234 { 0x00000886, 0x0000 }, /* R2182 - EQ1MIX Input 4 Source */
1235 { 0x00000887, 0x0080 }, /* R2183 - EQ1MIX Input 4 Volume */
1236 { 0x00000888, 0x0000 }, /* R2184 - EQ2MIX Input 1 Source */
1237 { 0x00000889, 0x0080 }, /* R2185 - EQ2MIX Input 1 Volume */
1238 { 0x0000088A, 0x0000 }, /* R2186 - EQ2MIX Input 2 Source */
1239 { 0x0000088B, 0x0080 }, /* R2187 - EQ2MIX Input 2 Volume */
1240 { 0x0000088C, 0x0000 }, /* R2188 - EQ2MIX Input 3 Source */
1241 { 0x0000088D, 0x0080 }, /* R2189 - EQ2MIX Input 3 Volume */
1242 { 0x0000088E, 0x0000 }, /* R2190 - EQ2MIX Input 4 Source */
1243 { 0x0000088F, 0x0080 }, /* R2191 - EQ2MIX Input 4 Volume */
1244 { 0x00000890, 0x0000 }, /* R2192 - EQ3MIX Input 1 Source */
1245 { 0x00000891, 0x0080 }, /* R2193 - EQ3MIX Input 1 Volume */
1246 { 0x00000892, 0x0000 }, /* R2194 - EQ3MIX Input 2 Source */
1247 { 0x00000893, 0x0080 }, /* R2195 - EQ3MIX Input 2 Volume */
1248 { 0x00000894, 0x0000 }, /* R2196 - EQ3MIX Input 3 Source */
1249 { 0x00000895, 0x0080 }, /* R2197 - EQ3MIX Input 3 Volume */
1250 { 0x00000896, 0x0000 }, /* R2198 - EQ3MIX Input 4 Source */
1251 { 0x00000897, 0x0080 }, /* R2199 - EQ3MIX Input 4 Volume */
1252 { 0x00000898, 0x0000 }, /* R2200 - EQ4MIX Input 1 Source */
1253 { 0x00000899, 0x0080 }, /* R2201 - EQ4MIX Input 1 Volume */
1254 { 0x0000089A, 0x0000 }, /* R2202 - EQ4MIX Input 2 Source */
1255 { 0x0000089B, 0x0080 }, /* R2203 - EQ4MIX Input 2 Volume */
1256 { 0x0000089C, 0x0000 }, /* R2204 - EQ4MIX Input 3 Source */
1257 { 0x0000089D, 0x0080 }, /* R2205 - EQ4MIX Input 3 Volume */
1258 { 0x0000089E, 0x0000 }, /* R2206 - EQ4MIX Input 4 Source */
1259 { 0x0000089F, 0x0080 }, /* R2207 - EQ4MIX Input 4 Volume */
1260 { 0x000008C0, 0x0000 }, /* R2240 - DRC1LMIX Input 1 Source */
1261 { 0x000008C1, 0x0080 }, /* R2241 - DRC1LMIX Input 1 Volume */
1262 { 0x000008C2, 0x0000 }, /* R2242 - DRC1LMIX Input 2 Source */
1263 { 0x000008C3, 0x0080 }, /* R2243 - DRC1LMIX Input 2 Volume */
1264 { 0x000008C4, 0x0000 }, /* R2244 - DRC1LMIX Input 3 Source */
1265 { 0x000008C5, 0x0080 }, /* R2245 - DRC1LMIX Input 3 Volume */
1266 { 0x000008C6, 0x0000 }, /* R2246 - DRC1LMIX Input 4 Source */
1267 { 0x000008C7, 0x0080 }, /* R2247 - DRC1LMIX Input 4 Volume */
1268 { 0x000008C8, 0x0000 }, /* R2248 - DRC1RMIX Input 1 Source */
1269 { 0x000008C9, 0x0080 }, /* R2249 - DRC1RMIX Input 1 Volume */
1270 { 0x000008CA, 0x0000 }, /* R2250 - DRC1RMIX Input 2 Source */
1271 { 0x000008CB, 0x0080 }, /* R2251 - DRC1RMIX Input 2 Volume */
1272 { 0x000008CC, 0x0000 }, /* R2252 - DRC1RMIX Input 3 Source */
1273 { 0x000008CD, 0x0080 }, /* R2253 - DRC1RMIX Input 3 Volume */
1274 { 0x000008CE, 0x0000 }, /* R2254 - DRC1RMIX Input 4 Source */
1275 { 0x000008CF, 0x0080 }, /* R2255 - DRC1RMIX Input 4 Volume */
1276 { 0x000008D0, 0x0000 }, /* R2256 - DRC2LMIX Input 1 Source */
1277 { 0x000008D1, 0x0080 }, /* R2257 - DRC2LMIX Input 1 Volume */
1278 { 0x000008D2, 0x0000 }, /* R2258 - DRC2LMIX Input 2 Source */
1279 { 0x000008D3, 0x0080 }, /* R2259 - DRC2LMIX Input 2 Volume */
1280 { 0x000008D4, 0x0000 }, /* R2260 - DRC2LMIX Input 3 Source */
1281 { 0x000008D5, 0x0080 }, /* R2261 - DRC2LMIX Input 3 Volume */
1282 { 0x000008D6, 0x0000 }, /* R2262 - DRC2LMIX Input 4 Source */
1283 { 0x000008D7, 0x0080 }, /* R2263 - DRC2LMIX Input 4 Volume */
1284 { 0x000008D8, 0x0000 }, /* R2264 - DRC2RMIX Input 1 Source */
1285 { 0x000008D9, 0x0080 }, /* R2265 - DRC2RMIX Input 1 Volume */
1286 { 0x000008DA, 0x0000 }, /* R2266 - DRC2RMIX Input 2 Source */
1287 { 0x000008DB, 0x0080 }, /* R2267 - DRC2RMIX Input 2 Volume */
1288 { 0x000008DC, 0x0000 }, /* R2268 - DRC2RMIX Input 3 Source */
1289 { 0x000008DD, 0x0080 }, /* R2269 - DRC2RMIX Input 3 Volume */
1290 { 0x000008DE, 0x0000 }, /* R2270 - DRC2RMIX Input 4 Source */
1291 { 0x000008DF, 0x0080 }, /* R2271 - DRC2RMIX Input 4 Volume */
1292 { 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */
1293 { 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */
1294 { 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */
1295 { 0x00000903, 0x0080 }, /* R2307 - HPLP1MIX Input 2 Volume */
1296 { 0x00000904, 0x0000 }, /* R2308 - HPLP1MIX Input 3 Source */
1297 { 0x00000905, 0x0080 }, /* R2309 - HPLP1MIX Input 3 Volume */
1298 { 0x00000906, 0x0000 }, /* R2310 - HPLP1MIX Input 4 Source */
1299 { 0x00000907, 0x0080 }, /* R2311 - HPLP1MIX Input 4 Volume */
1300 { 0x00000908, 0x0000 }, /* R2312 - HPLP2MIX Input 1 Source */
1301 { 0x00000909, 0x0080 }, /* R2313 - HPLP2MIX Input 1 Volume */
1302 { 0x0000090A, 0x0000 }, /* R2314 - HPLP2MIX Input 2 Source */
1303 { 0x0000090B, 0x0080 }, /* R2315 - HPLP2MIX Input 2 Volume */
1304 { 0x0000090C, 0x0000 }, /* R2316 - HPLP2MIX Input 3 Source */
1305 { 0x0000090D, 0x0080 }, /* R2317 - HPLP2MIX Input 3 Volume */
1306 { 0x0000090E, 0x0000 }, /* R2318 - HPLP2MIX Input 4 Source */
1307 { 0x0000090F, 0x0080 }, /* R2319 - HPLP2MIX Input 4 Volume */
1308 { 0x00000910, 0x0000 }, /* R2320 - HPLP3MIX Input 1 Source */
1309 { 0x00000911, 0x0080 }, /* R2321 - HPLP3MIX Input 1 Volume */
1310 { 0x00000912, 0x0000 }, /* R2322 - HPLP3MIX Input 2 Source */
1311 { 0x00000913, 0x0080 }, /* R2323 - HPLP3MIX Input 2 Volume */
1312 { 0x00000914, 0x0000 }, /* R2324 - HPLP3MIX Input 3 Source */
1313 { 0x00000915, 0x0080 }, /* R2325 - HPLP3MIX Input 3 Volume */
1314 { 0x00000916, 0x0000 }, /* R2326 - HPLP3MIX Input 4 Source */
1315 { 0x00000917, 0x0080 }, /* R2327 - HPLP3MIX Input 4 Volume */
1316 { 0x00000918, 0x0000 }, /* R2328 - HPLP4MIX Input 1 Source */
1317 { 0x00000919, 0x0080 }, /* R2329 - HPLP4MIX Input 1 Volume */
1318 { 0x0000091A, 0x0000 }, /* R2330 - HPLP4MIX Input 2 Source */
1319 { 0x0000091B, 0x0080 }, /* R2331 - HPLP4MIX Input 2 Volume */
1320 { 0x0000091C, 0x0000 }, /* R2332 - HPLP4MIX Input 3 Source */
1321 { 0x0000091D, 0x0080 }, /* R2333 - HPLP4MIX Input 3 Volume */
1322 { 0x0000091E, 0x0000 }, /* R2334 - HPLP4MIX Input 4 Source */
1323 { 0x0000091F, 0x0080 }, /* R2335 - HPLP4MIX Input 4 Volume */
1324 { 0x00000940, 0x0000 }, /* R2368 - DSP1LMIX Input 1 Source */
1325 { 0x00000941, 0x0080 }, /* R2369 - DSP1LMIX Input 1 Volume */
1326 { 0x00000942, 0x0000 }, /* R2370 - DSP1LMIX Input 2 Source */
1327 { 0x00000943, 0x0080 }, /* R2371 - DSP1LMIX Input 2 Volume */
1328 { 0x00000944, 0x0000 }, /* R2372 - DSP1LMIX Input 3 Source */
1329 { 0x00000945, 0x0080 }, /* R2373 - DSP1LMIX Input 3 Volume */
1330 { 0x00000946, 0x0000 }, /* R2374 - DSP1LMIX Input 4 Source */
1331 { 0x00000947, 0x0080 }, /* R2375 - DSP1LMIX Input 4 Volume */
1332 { 0x00000948, 0x0000 }, /* R2376 - DSP1RMIX Input 1 Source */
1333 { 0x00000949, 0x0080 }, /* R2377 - DSP1RMIX Input 1 Volume */
1334 { 0x0000094A, 0x0000 }, /* R2378 - DSP1RMIX Input 2 Source */
1335 { 0x0000094B, 0x0080 }, /* R2379 - DSP1RMIX Input 2 Volume */
1336 { 0x0000094C, 0x0000 }, /* R2380 - DSP1RMIX Input 3 Source */
1337 { 0x0000094D, 0x0080 }, /* R2381 - DSP1RMIX Input 3 Volume */
1338 { 0x0000094E, 0x0000 }, /* R2382 - DSP1RMIX Input 4 Source */
1339 { 0x0000094F, 0x0080 }, /* R2383 - DSP1RMIX Input 4 Volume */
1340 { 0x00000950, 0x0000 }, /* R2384 - DSP1AUX1MIX Input 1 Source */
1341 { 0x00000958, 0x0000 }, /* R2392 - DSP1AUX2MIX Input 1 Source */
1342 { 0x00000960, 0x0000 }, /* R2400 - DSP1AUX3MIX Input 1 Source */
1343 { 0x00000968, 0x0000 }, /* R2408 - DSP1AUX4MIX Input 1 Source */
1344 { 0x00000970, 0x0000 }, /* R2416 - DSP1AUX5MIX Input 1 Source */
1345 { 0x00000978, 0x0000 }, /* R2424 - DSP1AUX6MIX Input 1 Source */
1346 { 0x00000A80, 0x0000 }, /* R2688 - ASRC1LMIX Input 1 Source */
1347 { 0x00000A88, 0x0000 }, /* R2696 - ASRC1RMIX Input 1 Source */
1348 { 0x00000A90, 0x0000 }, /* R2704 - ASRC2LMIX Input 1 Source */
1349 { 0x00000A98, 0x0000 }, /* R2712 - ASRC2RMIX Input 1 Source */
1350 { 0x00000B00, 0x0000 }, /* R2816 - ISRC1DEC1MIX Input 1 Source */
1351 { 0x00000B08, 0x0000 }, /* R2824 - ISRC1DEC2MIX Input 1 Source */
1352 { 0x00000B20, 0x0000 }, /* R2848 - ISRC1INT1MIX Input 1 Source */
1353 { 0x00000B28, 0x0000 }, /* R2856 - ISRC1INT2MIX Input 1 Source */
1354 { 0x00000B40, 0x0000 }, /* R2880 - ISRC2DEC1MIX Input 1 Source */
1355 { 0x00000B48, 0x0000 }, /* R2888 - ISRC2DEC2MIX Input 1 Source */
1356 { 0x00000B60, 0x0000 }, /* R2912 - ISRC2INT1MIX Input 1 Source */
1357 { 0x00000B68, 0x0000 }, /* R2920 - ISRC2INT2MIX Input 1 Source */
1358 { 0x00000C00, 0xA101 }, /* R3072 - GPIO1 CTRL */
1359 { 0x00000C01, 0xA101 }, /* R3073 - GPIO2 CTRL */
1360 { 0x00000C02, 0xA101 }, /* R3074 - GPIO3 CTRL */
1361 { 0x00000C03, 0xA101 }, /* R3075 - GPIO4 CTRL */
1362 { 0x00000C04, 0xA101 }, /* R3076 - GPIO5 CTRL */
1363 { 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */
1364 { 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */
1365 { 0x00000C20, 0x8002 }, /* R3104 - Misc Pad Ctrl 1 */
1366 { 0x00000C21, 0x8001 }, /* R3105 - Misc Pad Ctrl 2 */
1367 { 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */
1368 { 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */
1369 { 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */
1370 { 0x00000C25, 0x0000 }, /* R3109 - Misc Pad Ctrl 6 */
1371 { 0x00000D08, 0xFFFF }, /* R3336 - Interrupt Status 1 Mask */
1372 { 0x00000D09, 0xFFFF }, /* R3337 - Interrupt Status 2 Mask */
1373 { 0x00000D0A, 0xFFFF }, /* R3338 - Interrupt Status 3 Mask */
1374 { 0x00000D0B, 0xFFFF }, /* R3339 - Interrupt Status 4 Mask */
1375 { 0x00000D0C, 0xFEFF }, /* R3340 - Interrupt Status 5 Mask */
1376 { 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */
1377 { 0x00000D18, 0xFFFF }, /* R3352 - IRQ2 Status 1 Mask */
1378 { 0x00000D19, 0xFFFF }, /* R3353 - IRQ2 Status 2 Mask */
1379 { 0x00000D1A, 0xFFFF }, /* R3354 - IRQ2 Status 3 Mask */
1380 { 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */
1381 { 0x00000D1C, 0xFFFF }, /* R3356 - IRQ2 Status 5 Mask */
1382 { 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */
1383 { 0x00000D41, 0x0000 }, /* R3393 - ADSP2 IRQ0 */
1384 { 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */
1385 { 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */
1386 { 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */
1387 { 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */
1388 { 0x00000E01, 0x0000 }, /* R3585 - FX_Ctrl2 */
1389 { 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */
1390 { 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */
1391 { 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */
1392 { 0x00000E13, 0x03FE }, /* R3603 - EQ1_4 */
1393 { 0x00000E14, 0x00E0 }, /* R3604 - EQ1_5 */
1394 { 0x00000E15, 0x1EC4 }, /* R3605 - EQ1_6 */
1395 { 0x00000E16, 0xF136 }, /* R3606 - EQ1_7 */
1396 { 0x00000E17, 0x0409 }, /* R3607 - EQ1_8 */
1397 { 0x00000E18, 0x04CC }, /* R3608 - EQ1_9 */
1398 { 0x00000E19, 0x1C9B }, /* R3609 - EQ1_10 */
1399 { 0x00000E1A, 0xF337 }, /* R3610 - EQ1_11 */
1400 { 0x00000E1B, 0x040B }, /* R3611 - EQ1_12 */
1401 { 0x00000E1C, 0x0CBB }, /* R3612 - EQ1_13 */
1402 { 0x00000E1D, 0x16F8 }, /* R3613 - EQ1_14 */
1403 { 0x00000E1E, 0xF7D9 }, /* R3614 - EQ1_15 */
1404 { 0x00000E1F, 0x040A }, /* R3615 - EQ1_16 */
1405 { 0x00000E20, 0x1F14 }, /* R3616 - EQ1_17 */
1406 { 0x00000E21, 0x058C }, /* R3617 - EQ1_18 */
1407 { 0x00000E22, 0x0563 }, /* R3618 - EQ1_19 */
1408 { 0x00000E23, 0x4000 }, /* R3619 - EQ1_20 */
1409 { 0x00000E24, 0x0B75 }, /* R3620 - EQ1_21 */
1410 { 0x00000E26, 0x6318 }, /* R3622 - EQ2_1 */
1411 { 0x00000E27, 0x6300 }, /* R3623 - EQ2_2 */
1412 { 0x00000E28, 0x0FC8 }, /* R3624 - EQ2_3 */
1413 { 0x00000E29, 0x03FE }, /* R3625 - EQ2_4 */
1414 { 0x00000E2A, 0x00E0 }, /* R3626 - EQ2_5 */
1415 { 0x00000E2B, 0x1EC4 }, /* R3627 - EQ2_6 */
1416 { 0x00000E2C, 0xF136 }, /* R3628 - EQ2_7 */
1417 { 0x00000E2D, 0x0409 }, /* R3629 - EQ2_8 */
1418 { 0x00000E2E, 0x04CC }, /* R3630 - EQ2_9 */
1419 { 0x00000E2F, 0x1C9B }, /* R3631 - EQ2_10 */
1420 { 0x00000E30, 0xF337 }, /* R3632 - EQ2_11 */
1421 { 0x00000E31, 0x040B }, /* R3633 - EQ2_12 */
1422 { 0x00000E32, 0x0CBB }, /* R3634 - EQ2_13 */
1423 { 0x00000E33, 0x16F8 }, /* R3635 - EQ2_14 */
1424 { 0x00000E34, 0xF7D9 }, /* R3636 - EQ2_15 */
1425 { 0x00000E35, 0x040A }, /* R3637 - EQ2_16 */
1426 { 0x00000E36, 0x1F14 }, /* R3638 - EQ2_17 */
1427 { 0x00000E37, 0x058C }, /* R3639 - EQ2_18 */
1428 { 0x00000E38, 0x0563 }, /* R3640 - EQ2_19 */
1429 { 0x00000E39, 0x4000 }, /* R3641 - EQ2_20 */
1430 { 0x00000E3A, 0x0B75 }, /* R3642 - EQ2_21 */
1431 { 0x00000E3C, 0x6318 }, /* R3644 - EQ3_1 */
1432 { 0x00000E3D, 0x6300 }, /* R3645 - EQ3_2 */
1433 { 0x00000E3E, 0x0FC8 }, /* R3646 - EQ3_3 */
1434 { 0x00000E3F, 0x03FE }, /* R3647 - EQ3_4 */
1435 { 0x00000E40, 0x00E0 }, /* R3648 - EQ3_5 */
1436 { 0x00000E41, 0x1EC4 }, /* R3649 - EQ3_6 */
1437 { 0x00000E42, 0xF136 }, /* R3650 - EQ3_7 */
1438 { 0x00000E43, 0x0409 }, /* R3651 - EQ3_8 */
1439 { 0x00000E44, 0x04CC }, /* R3652 - EQ3_9 */
1440 { 0x00000E45, 0x1C9B }, /* R3653 - EQ3_10 */
1441 { 0x00000E46, 0xF337 }, /* R3654 - EQ3_11 */
1442 { 0x00000E47, 0x040B }, /* R3655 - EQ3_12 */
1443 { 0x00000E48, 0x0CBB }, /* R3656 - EQ3_13 */
1444 { 0x00000E49, 0x16F8 }, /* R3657 - EQ3_14 */
1445 { 0x00000E4A, 0xF7D9 }, /* R3658 - EQ3_15 */
1446 { 0x00000E4B, 0x040A }, /* R3659 - EQ3_16 */
1447 { 0x00000E4C, 0x1F14 }, /* R3660 - EQ3_17 */
1448 { 0x00000E4D, 0x058C }, /* R3661 - EQ3_18 */
1449 { 0x00000E4E, 0x0563 }, /* R3662 - EQ3_19 */
1450 { 0x00000E4F, 0x4000 }, /* R3663 - EQ3_20 */
1451 { 0x00000E50, 0x0B75 }, /* R3664 - EQ3_21 */
1452 { 0x00000E52, 0x6318 }, /* R3666 - EQ4_1 */
1453 { 0x00000E53, 0x6300 }, /* R3667 - EQ4_2 */
1454 { 0x00000E54, 0x0FC8 }, /* R3668 - EQ4_3 */
1455 { 0x00000E55, 0x03FE }, /* R3669 - EQ4_4 */
1456 { 0x00000E56, 0x00E0 }, /* R3670 - EQ4_5 */
1457 { 0x00000E57, 0x1EC4 }, /* R3671 - EQ4_6 */
1458 { 0x00000E58, 0xF136 }, /* R3672 - EQ4_7 */
1459 { 0x00000E59, 0x0409 }, /* R3673 - EQ4_8 */
1460 { 0x00000E5A, 0x04CC }, /* R3674 - EQ4_9 */
1461 { 0x00000E5B, 0x1C9B }, /* R3675 - EQ4_10 */
1462 { 0x00000E5C, 0xF337 }, /* R3676 - EQ4_11 */
1463 { 0x00000E5D, 0x040B }, /* R3677 - EQ4_12 */
1464 { 0x00000E5E, 0x0CBB }, /* R3678 - EQ4_13 */
1465 { 0x00000E5F, 0x16F8 }, /* R3679 - EQ4_14 */
1466 { 0x00000E60, 0xF7D9 }, /* R3680 - EQ4_15 */
1467 { 0x00000E61, 0x040A }, /* R3681 - EQ4_16 */
1468 { 0x00000E62, 0x1F14 }, /* R3682 - EQ4_17 */
1469 { 0x00000E63, 0x058C }, /* R3683 - EQ4_18 */
1470 { 0x00000E64, 0x0563 }, /* R3684 - EQ4_19 */
1471 { 0x00000E65, 0x4000 }, /* R3685 - EQ4_20 */
1472 { 0x00000E66, 0x0B75 }, /* R3686 - EQ4_21 */
1473 { 0x00000E80, 0x0018 }, /* R3712 - DRC1 ctrl1 */
1474 { 0x00000E81, 0x0933 }, /* R3713 - DRC1 ctrl2 */
1475 { 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */
1476 { 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */
1477 { 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */
1478 { 0x00000E89, 0x0018 }, /* R3721 - DRC2 ctrl1 */
1479 { 0x00000E8A, 0x0933 }, /* R3722 - DRC2 ctrl2 */
1480 { 0x00000E8B, 0x0018 }, /* R3723 - DRC2 ctrl3 */
1481 { 0x00000E8C, 0x0000 }, /* R3724 - DRC2 ctrl4 */
1482 { 0x00000E8D, 0x0000 }, /* R3725 - DRC2 ctrl5 */
1483 { 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */
1484 { 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */
1485 { 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */
1486 { 0x00000EC5, 0x0000 }, /* R3781 - HPLPF2_2 */
1487 { 0x00000EC8, 0x0000 }, /* R3784 - HPLPF3_1 */
1488 { 0x00000EC9, 0x0000 }, /* R3785 - HPLPF3_2 */
1489 { 0x00000ECC, 0x0000 }, /* R3788 - HPLPF4_1 */
1490 { 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
1491 { 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */
1492 { 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */
1493 { 0x00000EE3, 0x4000 }, /* R3811 - ASRC_RATE2 */
1494 { 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */
1495 { 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */
1496 { 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */
1497 { 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */
1498 { 0x00000EF4, 0x0000 }, /* R3828 - ISRC 2 CTRL 2 */
1499 { 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */
1500 { 0x00000EF6, 0x0000 }, /* R3830 - ISRC 3 CTRL 1 */
1501 { 0x00000EF7, 0x0000 }, /* R3831 - ISRC 3 CTRL 2 */
1502 { 0x00000EF8, 0x0000 }, /* R3832 - ISRC 3 CTRL 3 */
1503 { 0x00001100, 0x0010 }, /* R4352 - DSP1 Control 1 */
1504 { 0x00001101, 0x0000 }, /* R4353 - DSP1 Clocking 1 */
1505};
1506
1507static bool wm5102_readable_register(struct device *dev, unsigned int reg)
1508{
1509 switch (reg) {
1510 case ARIZONA_SOFTWARE_RESET:
1511 case ARIZONA_DEVICE_REVISION:
1512 case ARIZONA_CTRL_IF_SPI_CFG_1:
1513 case ARIZONA_CTRL_IF_I2C1_CFG_1:
1514 case ARIZONA_CTRL_IF_STATUS_1:
1515 case ARIZONA_WRITE_SEQUENCER_CTRL_0:
1516 case ARIZONA_WRITE_SEQUENCER_CTRL_1:
1517 case ARIZONA_WRITE_SEQUENCER_CTRL_2:
1518 case ARIZONA_WRITE_SEQUENCER_PROM:
1519 case ARIZONA_TONE_GENERATOR_1:
1520 case ARIZONA_TONE_GENERATOR_2:
1521 case ARIZONA_TONE_GENERATOR_3:
1522 case ARIZONA_TONE_GENERATOR_4:
1523 case ARIZONA_TONE_GENERATOR_5:
1524 case ARIZONA_PWM_DRIVE_1:
1525 case ARIZONA_PWM_DRIVE_2:
1526 case ARIZONA_PWM_DRIVE_3:
1527 case ARIZONA_WAKE_CONTROL:
1528 case ARIZONA_SEQUENCE_CONTROL:
1529 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1:
1530 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2:
1531 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3:
1532 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4:
1533 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1:
1534 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2:
1535 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3:
1536 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4:
1537 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5:
1538 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6:
1539 case ARIZONA_COMFORT_NOISE_GENERATOR:
1540 case ARIZONA_HAPTICS_CONTROL_1:
1541 case ARIZONA_HAPTICS_CONTROL_2:
1542 case ARIZONA_HAPTICS_PHASE_1_INTENSITY:
1543 case ARIZONA_HAPTICS_PHASE_1_DURATION:
1544 case ARIZONA_HAPTICS_PHASE_2_INTENSITY:
1545 case ARIZONA_HAPTICS_PHASE_2_DURATION:
1546 case ARIZONA_HAPTICS_PHASE_3_INTENSITY:
1547 case ARIZONA_HAPTICS_PHASE_3_DURATION:
1548 case ARIZONA_HAPTICS_STATUS:
1549 case ARIZONA_CLOCK_32K_1:
1550 case ARIZONA_SYSTEM_CLOCK_1:
1551 case ARIZONA_SAMPLE_RATE_1:
1552 case ARIZONA_SAMPLE_RATE_2:
1553 case ARIZONA_SAMPLE_RATE_3:
1554 case ARIZONA_SAMPLE_RATE_1_STATUS:
1555 case ARIZONA_SAMPLE_RATE_2_STATUS:
1556 case ARIZONA_SAMPLE_RATE_3_STATUS:
1557 case ARIZONA_ASYNC_CLOCK_1:
1558 case ARIZONA_ASYNC_SAMPLE_RATE_1:
1559 case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
1560 case ARIZONA_OUTPUT_SYSTEM_CLOCK:
1561 case ARIZONA_OUTPUT_ASYNC_CLOCK:
1562 case ARIZONA_RATE_ESTIMATOR_1:
1563 case ARIZONA_RATE_ESTIMATOR_2:
1564 case ARIZONA_RATE_ESTIMATOR_3:
1565 case ARIZONA_RATE_ESTIMATOR_4:
1566 case ARIZONA_RATE_ESTIMATOR_5:
1567 case ARIZONA_FLL1_CONTROL_1:
1568 case ARIZONA_FLL1_CONTROL_2:
1569 case ARIZONA_FLL1_CONTROL_3:
1570 case ARIZONA_FLL1_CONTROL_4:
1571 case ARIZONA_FLL1_CONTROL_5:
1572 case ARIZONA_FLL1_CONTROL_6:
1573 case ARIZONA_FLL1_LOOP_FILTER_TEST_1:
1574 case ARIZONA_FLL1_SYNCHRONISER_1:
1575 case ARIZONA_FLL1_SYNCHRONISER_2:
1576 case ARIZONA_FLL1_SYNCHRONISER_3:
1577 case ARIZONA_FLL1_SYNCHRONISER_4:
1578 case ARIZONA_FLL1_SYNCHRONISER_5:
1579 case ARIZONA_FLL1_SYNCHRONISER_6:
1580 case ARIZONA_FLL1_SPREAD_SPECTRUM:
1581 case ARIZONA_FLL1_GPIO_CLOCK:
1582 case ARIZONA_FLL2_CONTROL_1:
1583 case ARIZONA_FLL2_CONTROL_2:
1584 case ARIZONA_FLL2_CONTROL_3:
1585 case ARIZONA_FLL2_CONTROL_4:
1586 case ARIZONA_FLL2_CONTROL_5:
1587 case ARIZONA_FLL2_CONTROL_6:
1588 case ARIZONA_FLL2_LOOP_FILTER_TEST_1:
1589 case ARIZONA_FLL2_SYNCHRONISER_1:
1590 case ARIZONA_FLL2_SYNCHRONISER_2:
1591 case ARIZONA_FLL2_SYNCHRONISER_3:
1592 case ARIZONA_FLL2_SYNCHRONISER_4:
1593 case ARIZONA_FLL2_SYNCHRONISER_5:
1594 case ARIZONA_FLL2_SYNCHRONISER_6:
1595 case ARIZONA_FLL2_SPREAD_SPECTRUM:
1596 case ARIZONA_FLL2_GPIO_CLOCK:
1597 case ARIZONA_MIC_CHARGE_PUMP_1:
1598 case ARIZONA_LDO1_CONTROL_1:
1599 case ARIZONA_LDO2_CONTROL_1:
1600 case ARIZONA_MIC_BIAS_CTRL_1:
1601 case ARIZONA_MIC_BIAS_CTRL_2:
1602 case ARIZONA_MIC_BIAS_CTRL_3:
1603 case ARIZONA_ACCESSORY_DETECT_MODE_1:
1604 case ARIZONA_HEADPHONE_DETECT_1:
1605 case ARIZONA_HEADPHONE_DETECT_2:
1606 case ARIZONA_MIC_DETECT_1:
1607 case ARIZONA_MIC_DETECT_2:
1608 case ARIZONA_MIC_DETECT_3:
1609 case ARIZONA_MIC_NOISE_MIX_CONTROL_1:
1610 case ARIZONA_ISOLATION_CONTROL:
1611 case ARIZONA_JACK_DETECT_ANALOGUE:
1612 case ARIZONA_INPUT_ENABLES:
1613 case ARIZONA_INPUT_RATE:
1614 case ARIZONA_INPUT_VOLUME_RAMP:
1615 case ARIZONA_IN1L_CONTROL:
1616 case ARIZONA_ADC_DIGITAL_VOLUME_1L:
1617 case ARIZONA_DMIC1L_CONTROL:
1618 case ARIZONA_IN1R_CONTROL:
1619 case ARIZONA_ADC_DIGITAL_VOLUME_1R:
1620 case ARIZONA_DMIC1R_CONTROL:
1621 case ARIZONA_IN2L_CONTROL:
1622 case ARIZONA_ADC_DIGITAL_VOLUME_2L:
1623 case ARIZONA_DMIC2L_CONTROL:
1624 case ARIZONA_IN2R_CONTROL:
1625 case ARIZONA_ADC_DIGITAL_VOLUME_2R:
1626 case ARIZONA_DMIC2R_CONTROL:
1627 case ARIZONA_IN3L_CONTROL:
1628 case ARIZONA_ADC_DIGITAL_VOLUME_3L:
1629 case ARIZONA_DMIC3L_CONTROL:
1630 case ARIZONA_IN3R_CONTROL:
1631 case ARIZONA_ADC_DIGITAL_VOLUME_3R:
1632 case ARIZONA_DMIC3R_CONTROL:
1633 case ARIZONA_OUTPUT_ENABLES_1:
1634 case ARIZONA_OUTPUT_STATUS_1:
1635 case ARIZONA_OUTPUT_RATE_1:
1636 case ARIZONA_OUTPUT_VOLUME_RAMP:
1637 case ARIZONA_OUTPUT_PATH_CONFIG_1L:
1638 case ARIZONA_DAC_DIGITAL_VOLUME_1L:
1639 case ARIZONA_DAC_VOLUME_LIMIT_1L:
1640 case ARIZONA_NOISE_GATE_SELECT_1L:
1641 case ARIZONA_OUTPUT_PATH_CONFIG_1R:
1642 case ARIZONA_DAC_DIGITAL_VOLUME_1R:
1643 case ARIZONA_DAC_VOLUME_LIMIT_1R:
1644 case ARIZONA_NOISE_GATE_SELECT_1R:
1645 case ARIZONA_OUTPUT_PATH_CONFIG_2L:
1646 case ARIZONA_DAC_DIGITAL_VOLUME_2L:
1647 case ARIZONA_DAC_VOLUME_LIMIT_2L:
1648 case ARIZONA_NOISE_GATE_SELECT_2L:
1649 case ARIZONA_OUTPUT_PATH_CONFIG_2R:
1650 case ARIZONA_DAC_DIGITAL_VOLUME_2R:
1651 case ARIZONA_DAC_VOLUME_LIMIT_2R:
1652 case ARIZONA_NOISE_GATE_SELECT_2R:
1653 case ARIZONA_OUTPUT_PATH_CONFIG_3L:
1654 case ARIZONA_DAC_DIGITAL_VOLUME_3L:
1655 case ARIZONA_DAC_VOLUME_LIMIT_3L:
1656 case ARIZONA_NOISE_GATE_SELECT_3L:
1657 case ARIZONA_OUTPUT_PATH_CONFIG_3R:
1658 case ARIZONA_DAC_DIGITAL_VOLUME_3R:
1659 case ARIZONA_DAC_VOLUME_LIMIT_3R:
1660 case ARIZONA_OUTPUT_PATH_CONFIG_4L:
1661 case ARIZONA_DAC_DIGITAL_VOLUME_4L:
1662 case ARIZONA_OUT_VOLUME_4L:
1663 case ARIZONA_NOISE_GATE_SELECT_4L:
1664 case ARIZONA_OUTPUT_PATH_CONFIG_4R:
1665 case ARIZONA_DAC_DIGITAL_VOLUME_4R:
1666 case ARIZONA_OUT_VOLUME_4R:
1667 case ARIZONA_NOISE_GATE_SELECT_4R:
1668 case ARIZONA_OUTPUT_PATH_CONFIG_5L:
1669 case ARIZONA_DAC_DIGITAL_VOLUME_5L:
1670 case ARIZONA_DAC_VOLUME_LIMIT_5L:
1671 case ARIZONA_NOISE_GATE_SELECT_5L:
1672 case ARIZONA_OUTPUT_PATH_CONFIG_5R:
1673 case ARIZONA_DAC_DIGITAL_VOLUME_5R:
1674 case ARIZONA_DAC_VOLUME_LIMIT_5R:
1675 case ARIZONA_NOISE_GATE_SELECT_5R:
1676 case ARIZONA_DAC_AEC_CONTROL_1:
1677 case ARIZONA_NOISE_GATE_CONTROL:
1678 case ARIZONA_PDM_SPK1_CTRL_1:
1679 case ARIZONA_PDM_SPK1_CTRL_2:
1680 case ARIZONA_DAC_COMP_1:
1681 case ARIZONA_DAC_COMP_2:
1682 case ARIZONA_DAC_COMP_3:
1683 case ARIZONA_DAC_COMP_4:
1684 case ARIZONA_AIF1_BCLK_CTRL:
1685 case ARIZONA_AIF1_TX_PIN_CTRL:
1686 case ARIZONA_AIF1_RX_PIN_CTRL:
1687 case ARIZONA_AIF1_RATE_CTRL:
1688 case ARIZONA_AIF1_FORMAT:
1689 case ARIZONA_AIF1_TX_BCLK_RATE:
1690 case ARIZONA_AIF1_RX_BCLK_RATE:
1691 case ARIZONA_AIF1_FRAME_CTRL_1:
1692 case ARIZONA_AIF1_FRAME_CTRL_2:
1693 case ARIZONA_AIF1_FRAME_CTRL_3:
1694 case ARIZONA_AIF1_FRAME_CTRL_4:
1695 case ARIZONA_AIF1_FRAME_CTRL_5:
1696 case ARIZONA_AIF1_FRAME_CTRL_6:
1697 case ARIZONA_AIF1_FRAME_CTRL_7:
1698 case ARIZONA_AIF1_FRAME_CTRL_8:
1699 case ARIZONA_AIF1_FRAME_CTRL_9:
1700 case ARIZONA_AIF1_FRAME_CTRL_10:
1701 case ARIZONA_AIF1_FRAME_CTRL_11:
1702 case ARIZONA_AIF1_FRAME_CTRL_12:
1703 case ARIZONA_AIF1_FRAME_CTRL_13:
1704 case ARIZONA_AIF1_FRAME_CTRL_14:
1705 case ARIZONA_AIF1_FRAME_CTRL_15:
1706 case ARIZONA_AIF1_FRAME_CTRL_16:
1707 case ARIZONA_AIF1_FRAME_CTRL_17:
1708 case ARIZONA_AIF1_FRAME_CTRL_18:
1709 case ARIZONA_AIF1_TX_ENABLES:
1710 case ARIZONA_AIF1_RX_ENABLES:
1711 case ARIZONA_AIF1_FORCE_WRITE:
1712 case ARIZONA_AIF2_BCLK_CTRL:
1713 case ARIZONA_AIF2_TX_PIN_CTRL:
1714 case ARIZONA_AIF2_RX_PIN_CTRL:
1715 case ARIZONA_AIF2_RATE_CTRL:
1716 case ARIZONA_AIF2_FORMAT:
1717 case ARIZONA_AIF2_TX_BCLK_RATE:
1718 case ARIZONA_AIF2_RX_BCLK_RATE:
1719 case ARIZONA_AIF2_FRAME_CTRL_1:
1720 case ARIZONA_AIF2_FRAME_CTRL_2:
1721 case ARIZONA_AIF2_FRAME_CTRL_3:
1722 case ARIZONA_AIF2_FRAME_CTRL_4:
1723 case ARIZONA_AIF2_FRAME_CTRL_11:
1724 case ARIZONA_AIF2_FRAME_CTRL_12:
1725 case ARIZONA_AIF2_TX_ENABLES:
1726 case ARIZONA_AIF2_RX_ENABLES:
1727 case ARIZONA_AIF2_FORCE_WRITE:
1728 case ARIZONA_AIF3_BCLK_CTRL:
1729 case ARIZONA_AIF3_TX_PIN_CTRL:
1730 case ARIZONA_AIF3_RX_PIN_CTRL:
1731 case ARIZONA_AIF3_RATE_CTRL:
1732 case ARIZONA_AIF3_FORMAT:
1733 case ARIZONA_AIF3_TX_BCLK_RATE:
1734 case ARIZONA_AIF3_RX_BCLK_RATE:
1735 case ARIZONA_AIF3_FRAME_CTRL_1:
1736 case ARIZONA_AIF3_FRAME_CTRL_2:
1737 case ARIZONA_AIF3_FRAME_CTRL_3:
1738 case ARIZONA_AIF3_FRAME_CTRL_4:
1739 case ARIZONA_AIF3_FRAME_CTRL_11:
1740 case ARIZONA_AIF3_FRAME_CTRL_12:
1741 case ARIZONA_AIF3_TX_ENABLES:
1742 case ARIZONA_AIF3_RX_ENABLES:
1743 case ARIZONA_AIF3_FORCE_WRITE:
1744 case ARIZONA_SLIMBUS_FRAMER_REF_GEAR:
1745 case ARIZONA_SLIMBUS_RATES_1:
1746 case ARIZONA_SLIMBUS_RATES_2:
1747 case ARIZONA_SLIMBUS_RATES_3:
1748 case ARIZONA_SLIMBUS_RATES_4:
1749 case ARIZONA_SLIMBUS_RATES_5:
1750 case ARIZONA_SLIMBUS_RATES_6:
1751 case ARIZONA_SLIMBUS_RATES_7:
1752 case ARIZONA_SLIMBUS_RATES_8:
1753 case ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE:
1754 case ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE:
1755 case ARIZONA_SLIMBUS_RX_PORT_STATUS:
1756 case ARIZONA_SLIMBUS_TX_PORT_STATUS:
1757 case ARIZONA_PWM1MIX_INPUT_1_SOURCE:
1758 case ARIZONA_PWM1MIX_INPUT_1_VOLUME:
1759 case ARIZONA_PWM1MIX_INPUT_2_SOURCE:
1760 case ARIZONA_PWM1MIX_INPUT_2_VOLUME:
1761 case ARIZONA_PWM1MIX_INPUT_3_SOURCE:
1762 case ARIZONA_PWM1MIX_INPUT_3_VOLUME:
1763 case ARIZONA_PWM1MIX_INPUT_4_SOURCE:
1764 case ARIZONA_PWM1MIX_INPUT_4_VOLUME:
1765 case ARIZONA_PWM2MIX_INPUT_1_SOURCE:
1766 case ARIZONA_PWM2MIX_INPUT_1_VOLUME:
1767 case ARIZONA_PWM2MIX_INPUT_2_SOURCE:
1768 case ARIZONA_PWM2MIX_INPUT_2_VOLUME:
1769 case ARIZONA_PWM2MIX_INPUT_3_SOURCE:
1770 case ARIZONA_PWM2MIX_INPUT_3_VOLUME:
1771 case ARIZONA_PWM2MIX_INPUT_4_SOURCE:
1772 case ARIZONA_PWM2MIX_INPUT_4_VOLUME:
1773 case ARIZONA_MICMIX_INPUT_1_SOURCE:
1774 case ARIZONA_MICMIX_INPUT_1_VOLUME:
1775 case ARIZONA_MICMIX_INPUT_2_SOURCE:
1776 case ARIZONA_MICMIX_INPUT_2_VOLUME:
1777 case ARIZONA_MICMIX_INPUT_3_SOURCE:
1778 case ARIZONA_MICMIX_INPUT_3_VOLUME:
1779 case ARIZONA_MICMIX_INPUT_4_SOURCE:
1780 case ARIZONA_MICMIX_INPUT_4_VOLUME:
1781 case ARIZONA_NOISEMIX_INPUT_1_SOURCE:
1782 case ARIZONA_NOISEMIX_INPUT_1_VOLUME:
1783 case ARIZONA_NOISEMIX_INPUT_2_SOURCE:
1784 case ARIZONA_NOISEMIX_INPUT_2_VOLUME:
1785 case ARIZONA_NOISEMIX_INPUT_3_SOURCE:
1786 case ARIZONA_NOISEMIX_INPUT_3_VOLUME:
1787 case ARIZONA_NOISEMIX_INPUT_4_SOURCE:
1788 case ARIZONA_NOISEMIX_INPUT_4_VOLUME:
1789 case ARIZONA_OUT1LMIX_INPUT_1_SOURCE:
1790 case ARIZONA_OUT1LMIX_INPUT_1_VOLUME:
1791 case ARIZONA_OUT1LMIX_INPUT_2_SOURCE:
1792 case ARIZONA_OUT1LMIX_INPUT_2_VOLUME:
1793 case ARIZONA_OUT1LMIX_INPUT_3_SOURCE:
1794 case ARIZONA_OUT1LMIX_INPUT_3_VOLUME:
1795 case ARIZONA_OUT1LMIX_INPUT_4_SOURCE:
1796 case ARIZONA_OUT1LMIX_INPUT_4_VOLUME:
1797 case ARIZONA_OUT1RMIX_INPUT_1_SOURCE:
1798 case ARIZONA_OUT1RMIX_INPUT_1_VOLUME:
1799 case ARIZONA_OUT1RMIX_INPUT_2_SOURCE:
1800 case ARIZONA_OUT1RMIX_INPUT_2_VOLUME:
1801 case ARIZONA_OUT1RMIX_INPUT_3_SOURCE:
1802 case ARIZONA_OUT1RMIX_INPUT_3_VOLUME:
1803 case ARIZONA_OUT1RMIX_INPUT_4_SOURCE:
1804 case ARIZONA_OUT1RMIX_INPUT_4_VOLUME:
1805 case ARIZONA_OUT2LMIX_INPUT_1_SOURCE:
1806 case ARIZONA_OUT2LMIX_INPUT_1_VOLUME:
1807 case ARIZONA_OUT2LMIX_INPUT_2_SOURCE:
1808 case ARIZONA_OUT2LMIX_INPUT_2_VOLUME:
1809 case ARIZONA_OUT2LMIX_INPUT_3_SOURCE:
1810 case ARIZONA_OUT2LMIX_INPUT_3_VOLUME:
1811 case ARIZONA_OUT2LMIX_INPUT_4_SOURCE:
1812 case ARIZONA_OUT2LMIX_INPUT_4_VOLUME:
1813 case ARIZONA_OUT2RMIX_INPUT_1_SOURCE:
1814 case ARIZONA_OUT2RMIX_INPUT_1_VOLUME:
1815 case ARIZONA_OUT2RMIX_INPUT_2_SOURCE:
1816 case ARIZONA_OUT2RMIX_INPUT_2_VOLUME:
1817 case ARIZONA_OUT2RMIX_INPUT_3_SOURCE:
1818 case ARIZONA_OUT2RMIX_INPUT_3_VOLUME:
1819 case ARIZONA_OUT2RMIX_INPUT_4_SOURCE:
1820 case ARIZONA_OUT2RMIX_INPUT_4_VOLUME:
1821 case ARIZONA_OUT3LMIX_INPUT_1_SOURCE:
1822 case ARIZONA_OUT3LMIX_INPUT_1_VOLUME:
1823 case ARIZONA_OUT3LMIX_INPUT_2_SOURCE:
1824 case ARIZONA_OUT3LMIX_INPUT_2_VOLUME:
1825 case ARIZONA_OUT3LMIX_INPUT_3_SOURCE:
1826 case ARIZONA_OUT3LMIX_INPUT_3_VOLUME:
1827 case ARIZONA_OUT3LMIX_INPUT_4_SOURCE:
1828 case ARIZONA_OUT3LMIX_INPUT_4_VOLUME:
1829 case ARIZONA_OUT4LMIX_INPUT_1_SOURCE:
1830 case ARIZONA_OUT4LMIX_INPUT_1_VOLUME:
1831 case ARIZONA_OUT4LMIX_INPUT_2_SOURCE:
1832 case ARIZONA_OUT4LMIX_INPUT_2_VOLUME:
1833 case ARIZONA_OUT4LMIX_INPUT_3_SOURCE:
1834 case ARIZONA_OUT4LMIX_INPUT_3_VOLUME:
1835 case ARIZONA_OUT4LMIX_INPUT_4_SOURCE:
1836 case ARIZONA_OUT4LMIX_INPUT_4_VOLUME:
1837 case ARIZONA_OUT4RMIX_INPUT_1_SOURCE:
1838 case ARIZONA_OUT4RMIX_INPUT_1_VOLUME:
1839 case ARIZONA_OUT4RMIX_INPUT_2_SOURCE:
1840 case ARIZONA_OUT4RMIX_INPUT_2_VOLUME:
1841 case ARIZONA_OUT4RMIX_INPUT_3_SOURCE:
1842 case ARIZONA_OUT4RMIX_INPUT_3_VOLUME:
1843 case ARIZONA_OUT4RMIX_INPUT_4_SOURCE:
1844 case ARIZONA_OUT4RMIX_INPUT_4_VOLUME:
1845 case ARIZONA_OUT5LMIX_INPUT_1_SOURCE:
1846 case ARIZONA_OUT5LMIX_INPUT_1_VOLUME:
1847 case ARIZONA_OUT5LMIX_INPUT_2_SOURCE:
1848 case ARIZONA_OUT5LMIX_INPUT_2_VOLUME:
1849 case ARIZONA_OUT5LMIX_INPUT_3_SOURCE:
1850 case ARIZONA_OUT5LMIX_INPUT_3_VOLUME:
1851 case ARIZONA_OUT5LMIX_INPUT_4_SOURCE:
1852 case ARIZONA_OUT5LMIX_INPUT_4_VOLUME:
1853 case ARIZONA_OUT5RMIX_INPUT_1_SOURCE:
1854 case ARIZONA_OUT5RMIX_INPUT_1_VOLUME:
1855 case ARIZONA_OUT5RMIX_INPUT_2_SOURCE:
1856 case ARIZONA_OUT5RMIX_INPUT_2_VOLUME:
1857 case ARIZONA_OUT5RMIX_INPUT_3_SOURCE:
1858 case ARIZONA_OUT5RMIX_INPUT_3_VOLUME:
1859 case ARIZONA_OUT5RMIX_INPUT_4_SOURCE:
1860 case ARIZONA_OUT5RMIX_INPUT_4_VOLUME:
1861 case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE:
1862 case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME:
1863 case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE:
1864 case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME:
1865 case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE:
1866 case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME:
1867 case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE:
1868 case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME:
1869 case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE:
1870 case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME:
1871 case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE:
1872 case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME:
1873 case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE:
1874 case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME:
1875 case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE:
1876 case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME:
1877 case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE:
1878 case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME:
1879 case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE:
1880 case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME:
1881 case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE:
1882 case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME:
1883 case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE:
1884 case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME:
1885 case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE:
1886 case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME:
1887 case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE:
1888 case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME:
1889 case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE:
1890 case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME:
1891 case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE:
1892 case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME:
1893 case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE:
1894 case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME:
1895 case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE:
1896 case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME:
1897 case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE:
1898 case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME:
1899 case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE:
1900 case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME:
1901 case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE:
1902 case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME:
1903 case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE:
1904 case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME:
1905 case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE:
1906 case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME:
1907 case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE:
1908 case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME:
1909 case ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE:
1910 case ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME:
1911 case ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE:
1912 case ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME:
1913 case ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE:
1914 case ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME:
1915 case ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE:
1916 case ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME:
1917 case ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE:
1918 case ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME:
1919 case ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE:
1920 case ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME:
1921 case ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE:
1922 case ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME:
1923 case ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE:
1924 case ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME:
1925 case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE:
1926 case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME:
1927 case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE:
1928 case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME:
1929 case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE:
1930 case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME:
1931 case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE:
1932 case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME:
1933 case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE:
1934 case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME:
1935 case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE:
1936 case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME:
1937 case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE:
1938 case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME:
1939 case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE:
1940 case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME:
1941 case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE:
1942 case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME:
1943 case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE:
1944 case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME:
1945 case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE:
1946 case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME:
1947 case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE:
1948 case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME:
1949 case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE:
1950 case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME:
1951 case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE:
1952 case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME:
1953 case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE:
1954 case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME:
1955 case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE:
1956 case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME:
1957 case ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE:
1958 case ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME:
1959 case ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE:
1960 case ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME:
1961 case ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE:
1962 case ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME:
1963 case ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE:
1964 case ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME:
1965 case ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE:
1966 case ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME:
1967 case ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE:
1968 case ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME:
1969 case ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE:
1970 case ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME:
1971 case ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE:
1972 case ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME:
1973 case ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE:
1974 case ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME:
1975 case ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE:
1976 case ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME:
1977 case ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE:
1978 case ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME:
1979 case ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE:
1980 case ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME:
1981 case ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE:
1982 case ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME:
1983 case ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE:
1984 case ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME:
1985 case ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE:
1986 case ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME:
1987 case ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE:
1988 case ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME:
1989 case ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE:
1990 case ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME:
1991 case ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE:
1992 case ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME:
1993 case ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE:
1994 case ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME:
1995 case ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE:
1996 case ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME:
1997 case ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE:
1998 case ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME:
1999 case ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE:
2000 case ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME:
2001 case ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE:
2002 case ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME:
2003 case ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE:
2004 case ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME:
2005 case ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE:
2006 case ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME:
2007 case ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE:
2008 case ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME:
2009 case ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE:
2010 case ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME:
2011 case ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE:
2012 case ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME:
2013 case ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE:
2014 case ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME:
2015 case ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE:
2016 case ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME:
2017 case ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE:
2018 case ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME:
2019 case ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE:
2020 case ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME:
2021 case ARIZONA_EQ1MIX_INPUT_1_SOURCE:
2022 case ARIZONA_EQ1MIX_INPUT_1_VOLUME:
2023 case ARIZONA_EQ1MIX_INPUT_2_SOURCE:
2024 case ARIZONA_EQ1MIX_INPUT_2_VOLUME:
2025 case ARIZONA_EQ1MIX_INPUT_3_SOURCE:
2026 case ARIZONA_EQ1MIX_INPUT_3_VOLUME:
2027 case ARIZONA_EQ1MIX_INPUT_4_SOURCE:
2028 case ARIZONA_EQ1MIX_INPUT_4_VOLUME:
2029 case ARIZONA_EQ2MIX_INPUT_1_SOURCE:
2030 case ARIZONA_EQ2MIX_INPUT_1_VOLUME:
2031 case ARIZONA_EQ2MIX_INPUT_2_SOURCE:
2032 case ARIZONA_EQ2MIX_INPUT_2_VOLUME:
2033 case ARIZONA_EQ2MIX_INPUT_3_SOURCE:
2034 case ARIZONA_EQ2MIX_INPUT_3_VOLUME:
2035 case ARIZONA_EQ2MIX_INPUT_4_SOURCE:
2036 case ARIZONA_EQ2MIX_INPUT_4_VOLUME:
2037 case ARIZONA_EQ3MIX_INPUT_1_SOURCE:
2038 case ARIZONA_EQ3MIX_INPUT_1_VOLUME:
2039 case ARIZONA_EQ3MIX_INPUT_2_SOURCE:
2040 case ARIZONA_EQ3MIX_INPUT_2_VOLUME:
2041 case ARIZONA_EQ3MIX_INPUT_3_SOURCE:
2042 case ARIZONA_EQ3MIX_INPUT_3_VOLUME:
2043 case ARIZONA_EQ3MIX_INPUT_4_SOURCE:
2044 case ARIZONA_EQ3MIX_INPUT_4_VOLUME:
2045 case ARIZONA_EQ4MIX_INPUT_1_SOURCE:
2046 case ARIZONA_EQ4MIX_INPUT_1_VOLUME:
2047 case ARIZONA_EQ4MIX_INPUT_2_SOURCE:
2048 case ARIZONA_EQ4MIX_INPUT_2_VOLUME:
2049 case ARIZONA_EQ4MIX_INPUT_3_SOURCE:
2050 case ARIZONA_EQ4MIX_INPUT_3_VOLUME:
2051 case ARIZONA_EQ4MIX_INPUT_4_SOURCE:
2052 case ARIZONA_EQ4MIX_INPUT_4_VOLUME:
2053 case ARIZONA_DRC1LMIX_INPUT_1_SOURCE:
2054 case ARIZONA_DRC1LMIX_INPUT_1_VOLUME:
2055 case ARIZONA_DRC1LMIX_INPUT_2_SOURCE:
2056 case ARIZONA_DRC1LMIX_INPUT_2_VOLUME:
2057 case ARIZONA_DRC1LMIX_INPUT_3_SOURCE:
2058 case ARIZONA_DRC1LMIX_INPUT_3_VOLUME:
2059 case ARIZONA_DRC1LMIX_INPUT_4_SOURCE:
2060 case ARIZONA_DRC1LMIX_INPUT_4_VOLUME:
2061 case ARIZONA_DRC1RMIX_INPUT_1_SOURCE:
2062 case ARIZONA_DRC1RMIX_INPUT_1_VOLUME:
2063 case ARIZONA_DRC1RMIX_INPUT_2_SOURCE:
2064 case ARIZONA_DRC1RMIX_INPUT_2_VOLUME:
2065 case ARIZONA_DRC1RMIX_INPUT_3_SOURCE:
2066 case ARIZONA_DRC1RMIX_INPUT_3_VOLUME:
2067 case ARIZONA_DRC1RMIX_INPUT_4_SOURCE:
2068 case ARIZONA_DRC1RMIX_INPUT_4_VOLUME:
2069 case ARIZONA_DRC2LMIX_INPUT_1_SOURCE:
2070 case ARIZONA_DRC2LMIX_INPUT_1_VOLUME:
2071 case ARIZONA_DRC2LMIX_INPUT_2_SOURCE:
2072 case ARIZONA_DRC2LMIX_INPUT_2_VOLUME:
2073 case ARIZONA_DRC2LMIX_INPUT_3_SOURCE:
2074 case ARIZONA_DRC2LMIX_INPUT_3_VOLUME:
2075 case ARIZONA_DRC2LMIX_INPUT_4_SOURCE:
2076 case ARIZONA_DRC2LMIX_INPUT_4_VOLUME:
2077 case ARIZONA_DRC2RMIX_INPUT_1_SOURCE:
2078 case ARIZONA_DRC2RMIX_INPUT_1_VOLUME:
2079 case ARIZONA_DRC2RMIX_INPUT_2_SOURCE:
2080 case ARIZONA_DRC2RMIX_INPUT_2_VOLUME:
2081 case ARIZONA_DRC2RMIX_INPUT_3_SOURCE:
2082 case ARIZONA_DRC2RMIX_INPUT_3_VOLUME:
2083 case ARIZONA_DRC2RMIX_INPUT_4_SOURCE:
2084 case ARIZONA_DRC2RMIX_INPUT_4_VOLUME:
2085 case ARIZONA_HPLP1MIX_INPUT_1_SOURCE:
2086 case ARIZONA_HPLP1MIX_INPUT_1_VOLUME:
2087 case ARIZONA_HPLP1MIX_INPUT_2_SOURCE:
2088 case ARIZONA_HPLP1MIX_INPUT_2_VOLUME:
2089 case ARIZONA_HPLP1MIX_INPUT_3_SOURCE:
2090 case ARIZONA_HPLP1MIX_INPUT_3_VOLUME:
2091 case ARIZONA_HPLP1MIX_INPUT_4_SOURCE:
2092 case ARIZONA_HPLP1MIX_INPUT_4_VOLUME:
2093 case ARIZONA_HPLP2MIX_INPUT_1_SOURCE:
2094 case ARIZONA_HPLP2MIX_INPUT_1_VOLUME:
2095 case ARIZONA_HPLP2MIX_INPUT_2_SOURCE:
2096 case ARIZONA_HPLP2MIX_INPUT_2_VOLUME:
2097 case ARIZONA_HPLP2MIX_INPUT_3_SOURCE:
2098 case ARIZONA_HPLP2MIX_INPUT_3_VOLUME:
2099 case ARIZONA_HPLP2MIX_INPUT_4_SOURCE:
2100 case ARIZONA_HPLP2MIX_INPUT_4_VOLUME:
2101 case ARIZONA_HPLP3MIX_INPUT_1_SOURCE:
2102 case ARIZONA_HPLP3MIX_INPUT_1_VOLUME:
2103 case ARIZONA_HPLP3MIX_INPUT_2_SOURCE:
2104 case ARIZONA_HPLP3MIX_INPUT_2_VOLUME:
2105 case ARIZONA_HPLP3MIX_INPUT_3_SOURCE:
2106 case ARIZONA_HPLP3MIX_INPUT_3_VOLUME:
2107 case ARIZONA_HPLP3MIX_INPUT_4_SOURCE:
2108 case ARIZONA_HPLP3MIX_INPUT_4_VOLUME:
2109 case ARIZONA_HPLP4MIX_INPUT_1_SOURCE:
2110 case ARIZONA_HPLP4MIX_INPUT_1_VOLUME:
2111 case ARIZONA_HPLP4MIX_INPUT_2_SOURCE:
2112 case ARIZONA_HPLP4MIX_INPUT_2_VOLUME:
2113 case ARIZONA_HPLP4MIX_INPUT_3_SOURCE:
2114 case ARIZONA_HPLP4MIX_INPUT_3_VOLUME:
2115 case ARIZONA_HPLP4MIX_INPUT_4_SOURCE:
2116 case ARIZONA_HPLP4MIX_INPUT_4_VOLUME:
2117 case ARIZONA_DSP1LMIX_INPUT_1_SOURCE:
2118 case ARIZONA_DSP1LMIX_INPUT_1_VOLUME:
2119 case ARIZONA_DSP1LMIX_INPUT_2_SOURCE:
2120 case ARIZONA_DSP1LMIX_INPUT_2_VOLUME:
2121 case ARIZONA_DSP1LMIX_INPUT_3_SOURCE:
2122 case ARIZONA_DSP1LMIX_INPUT_3_VOLUME:
2123 case ARIZONA_DSP1LMIX_INPUT_4_SOURCE:
2124 case ARIZONA_DSP1LMIX_INPUT_4_VOLUME:
2125 case ARIZONA_DSP1RMIX_INPUT_1_SOURCE:
2126 case ARIZONA_DSP1RMIX_INPUT_1_VOLUME:
2127 case ARIZONA_DSP1RMIX_INPUT_2_SOURCE:
2128 case ARIZONA_DSP1RMIX_INPUT_2_VOLUME:
2129 case ARIZONA_DSP1RMIX_INPUT_3_SOURCE:
2130 case ARIZONA_DSP1RMIX_INPUT_3_VOLUME:
2131 case ARIZONA_DSP1RMIX_INPUT_4_SOURCE:
2132 case ARIZONA_DSP1RMIX_INPUT_4_VOLUME:
2133 case ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE:
2134 case ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE:
2135 case ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE:
2136 case ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE:
2137 case ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE:
2138 case ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE:
2139 case ARIZONA_ASRC1LMIX_INPUT_1_SOURCE:
2140 case ARIZONA_ASRC1RMIX_INPUT_1_SOURCE:
2141 case ARIZONA_ASRC2LMIX_INPUT_1_SOURCE:
2142 case ARIZONA_ASRC2RMIX_INPUT_1_SOURCE:
2143 case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE:
2144 case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE:
2145 case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE:
2146 case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE:
2147 case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE:
2148 case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE:
2149 case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE:
2150 case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE:
2151 case ARIZONA_GPIO1_CTRL:
2152 case ARIZONA_GPIO2_CTRL:
2153 case ARIZONA_GPIO3_CTRL:
2154 case ARIZONA_GPIO4_CTRL:
2155 case ARIZONA_GPIO5_CTRL:
2156 case ARIZONA_IRQ_CTRL_1:
2157 case ARIZONA_GPIO_DEBOUNCE_CONFIG:
2158 case ARIZONA_MISC_PAD_CTRL_1:
2159 case ARIZONA_MISC_PAD_CTRL_2:
2160 case ARIZONA_MISC_PAD_CTRL_3:
2161 case ARIZONA_MISC_PAD_CTRL_4:
2162 case ARIZONA_MISC_PAD_CTRL_5:
2163 case ARIZONA_MISC_PAD_CTRL_6:
2164 case ARIZONA_INTERRUPT_STATUS_1:
2165 case ARIZONA_INTERRUPT_STATUS_2:
2166 case ARIZONA_INTERRUPT_STATUS_3:
2167 case ARIZONA_INTERRUPT_STATUS_4:
2168 case ARIZONA_INTERRUPT_STATUS_5:
2169 case ARIZONA_INTERRUPT_STATUS_1_MASK:
2170 case ARIZONA_INTERRUPT_STATUS_2_MASK:
2171 case ARIZONA_INTERRUPT_STATUS_3_MASK:
2172 case ARIZONA_INTERRUPT_STATUS_4_MASK:
2173 case ARIZONA_INTERRUPT_STATUS_5_MASK:
2174 case ARIZONA_INTERRUPT_CONTROL:
2175 case ARIZONA_IRQ2_STATUS_1:
2176 case ARIZONA_IRQ2_STATUS_2:
2177 case ARIZONA_IRQ2_STATUS_3:
2178 case ARIZONA_IRQ2_STATUS_4:
2179 case ARIZONA_IRQ2_STATUS_5:
2180 case ARIZONA_IRQ2_STATUS_1_MASK:
2181 case ARIZONA_IRQ2_STATUS_2_MASK:
2182 case ARIZONA_IRQ2_STATUS_3_MASK:
2183 case ARIZONA_IRQ2_STATUS_4_MASK:
2184 case ARIZONA_IRQ2_STATUS_5_MASK:
2185 case ARIZONA_IRQ2_CONTROL:
2186 case ARIZONA_INTERRUPT_RAW_STATUS_2:
2187 case ARIZONA_INTERRUPT_RAW_STATUS_3:
2188 case ARIZONA_INTERRUPT_RAW_STATUS_4:
2189 case ARIZONA_INTERRUPT_RAW_STATUS_5:
2190 case ARIZONA_INTERRUPT_RAW_STATUS_6:
2191 case ARIZONA_INTERRUPT_RAW_STATUS_7:
2192 case ARIZONA_INTERRUPT_RAW_STATUS_8:
2193 case ARIZONA_IRQ_PIN_STATUS:
2194 case ARIZONA_ADSP2_IRQ0:
2195 case ARIZONA_AOD_WKUP_AND_TRIG:
2196 case ARIZONA_AOD_IRQ1:
2197 case ARIZONA_AOD_IRQ2:
2198 case ARIZONA_AOD_IRQ_MASK_IRQ1:
2199 case ARIZONA_AOD_IRQ_MASK_IRQ2:
2200 case ARIZONA_AOD_IRQ_RAW_STATUS:
2201 case ARIZONA_JACK_DETECT_DEBOUNCE:
2202 case ARIZONA_FX_CTRL1:
2203 case ARIZONA_FX_CTRL2:
2204 case ARIZONA_EQ1_1:
2205 case ARIZONA_EQ1_2:
2206 case ARIZONA_EQ1_3:
2207 case ARIZONA_EQ1_4:
2208 case ARIZONA_EQ1_5:
2209 case ARIZONA_EQ1_6:
2210 case ARIZONA_EQ1_7:
2211 case ARIZONA_EQ1_8:
2212 case ARIZONA_EQ1_9:
2213 case ARIZONA_EQ1_10:
2214 case ARIZONA_EQ1_11:
2215 case ARIZONA_EQ1_12:
2216 case ARIZONA_EQ1_13:
2217 case ARIZONA_EQ1_14:
2218 case ARIZONA_EQ1_15:
2219 case ARIZONA_EQ1_16:
2220 case ARIZONA_EQ1_17:
2221 case ARIZONA_EQ1_18:
2222 case ARIZONA_EQ1_19:
2223 case ARIZONA_EQ1_20:
2224 case ARIZONA_EQ1_21:
2225 case ARIZONA_EQ2_1:
2226 case ARIZONA_EQ2_2:
2227 case ARIZONA_EQ2_3:
2228 case ARIZONA_EQ2_4:
2229 case ARIZONA_EQ2_5:
2230 case ARIZONA_EQ2_6:
2231 case ARIZONA_EQ2_7:
2232 case ARIZONA_EQ2_8:
2233 case ARIZONA_EQ2_9:
2234 case ARIZONA_EQ2_10:
2235 case ARIZONA_EQ2_11:
2236 case ARIZONA_EQ2_12:
2237 case ARIZONA_EQ2_13:
2238 case ARIZONA_EQ2_14:
2239 case ARIZONA_EQ2_15:
2240 case ARIZONA_EQ2_16:
2241 case ARIZONA_EQ2_17:
2242 case ARIZONA_EQ2_18:
2243 case ARIZONA_EQ2_19:
2244 case ARIZONA_EQ2_20:
2245 case ARIZONA_EQ2_21:
2246 case ARIZONA_EQ3_1:
2247 case ARIZONA_EQ3_2:
2248 case ARIZONA_EQ3_3:
2249 case ARIZONA_EQ3_4:
2250 case ARIZONA_EQ3_5:
2251 case ARIZONA_EQ3_6:
2252 case ARIZONA_EQ3_7:
2253 case ARIZONA_EQ3_8:
2254 case ARIZONA_EQ3_9:
2255 case ARIZONA_EQ3_10:
2256 case ARIZONA_EQ3_11:
2257 case ARIZONA_EQ3_12:
2258 case ARIZONA_EQ3_13:
2259 case ARIZONA_EQ3_14:
2260 case ARIZONA_EQ3_15:
2261 case ARIZONA_EQ3_16:
2262 case ARIZONA_EQ3_17:
2263 case ARIZONA_EQ3_18:
2264 case ARIZONA_EQ3_19:
2265 case ARIZONA_EQ3_20:
2266 case ARIZONA_EQ3_21:
2267 case ARIZONA_EQ4_1:
2268 case ARIZONA_EQ4_2:
2269 case ARIZONA_EQ4_3:
2270 case ARIZONA_EQ4_4:
2271 case ARIZONA_EQ4_5:
2272 case ARIZONA_EQ4_6:
2273 case ARIZONA_EQ4_7:
2274 case ARIZONA_EQ4_8:
2275 case ARIZONA_EQ4_9:
2276 case ARIZONA_EQ4_10:
2277 case ARIZONA_EQ4_11:
2278 case ARIZONA_EQ4_12:
2279 case ARIZONA_EQ4_13:
2280 case ARIZONA_EQ4_14:
2281 case ARIZONA_EQ4_15:
2282 case ARIZONA_EQ4_16:
2283 case ARIZONA_EQ4_17:
2284 case ARIZONA_EQ4_18:
2285 case ARIZONA_EQ4_19:
2286 case ARIZONA_EQ4_20:
2287 case ARIZONA_EQ4_21:
2288 case ARIZONA_DRC1_CTRL1:
2289 case ARIZONA_DRC1_CTRL2:
2290 case ARIZONA_DRC1_CTRL3:
2291 case ARIZONA_DRC1_CTRL4:
2292 case ARIZONA_DRC1_CTRL5:
2293 case ARIZONA_DRC2_CTRL1:
2294 case ARIZONA_DRC2_CTRL2:
2295 case ARIZONA_DRC2_CTRL3:
2296 case ARIZONA_DRC2_CTRL4:
2297 case ARIZONA_DRC2_CTRL5:
2298 case ARIZONA_HPLPF1_1:
2299 case ARIZONA_HPLPF1_2:
2300 case ARIZONA_HPLPF2_1:
2301 case ARIZONA_HPLPF2_2:
2302 case ARIZONA_HPLPF3_1:
2303 case ARIZONA_HPLPF3_2:
2304 case ARIZONA_HPLPF4_1:
2305 case ARIZONA_HPLPF4_2:
2306 case ARIZONA_ASRC_ENABLE:
2307 case ARIZONA_ASRC_RATE1:
2308 case ARIZONA_ASRC_RATE2:
2309 case ARIZONA_ISRC_1_CTRL_1:
2310 case ARIZONA_ISRC_1_CTRL_2:
2311 case ARIZONA_ISRC_1_CTRL_3:
2312 case ARIZONA_ISRC_2_CTRL_1:
2313 case ARIZONA_ISRC_2_CTRL_2:
2314 case ARIZONA_ISRC_2_CTRL_3:
2315 case ARIZONA_ISRC_3_CTRL_1:
2316 case ARIZONA_ISRC_3_CTRL_2:
2317 case ARIZONA_ISRC_3_CTRL_3:
2318 case ARIZONA_DSP1_CONTROL_1:
2319 case ARIZONA_DSP1_CLOCKING_1:
2320 case ARIZONA_DSP1_STATUS_1:
2321 case ARIZONA_DSP1_STATUS_2:
2322 return true;
2323 default:
2324 return false;
2325 }
2326}
2327
2328static bool wm5102_volatile_register(struct device *dev, unsigned int reg)
2329{
2330 switch (reg) {
2331 case ARIZONA_SOFTWARE_RESET:
2332 case ARIZONA_DEVICE_REVISION:
2333 case ARIZONA_OUTPUT_STATUS_1:
2334 case ARIZONA_SAMPLE_RATE_1_STATUS:
2335 case ARIZONA_SAMPLE_RATE_2_STATUS:
2336 case ARIZONA_SAMPLE_RATE_3_STATUS:
2337 case ARIZONA_HAPTICS_STATUS:
2338 case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
2339 case ARIZONA_FX_CTRL2:
2340 case ARIZONA_INTERRUPT_STATUS_1:
2341 case ARIZONA_INTERRUPT_STATUS_2:
2342 case ARIZONA_INTERRUPT_STATUS_3:
2343 case ARIZONA_INTERRUPT_STATUS_4:
2344 case ARIZONA_INTERRUPT_STATUS_5:
2345 case ARIZONA_IRQ2_STATUS_1:
2346 case ARIZONA_IRQ2_STATUS_2:
2347 case ARIZONA_IRQ2_STATUS_3:
2348 case ARIZONA_IRQ2_STATUS_4:
2349 case ARIZONA_IRQ2_STATUS_5:
2350 case ARIZONA_INTERRUPT_RAW_STATUS_2:
2351 case ARIZONA_INTERRUPT_RAW_STATUS_3:
2352 case ARIZONA_INTERRUPT_RAW_STATUS_4:
2353 case ARIZONA_INTERRUPT_RAW_STATUS_5:
2354 case ARIZONA_INTERRUPT_RAW_STATUS_6:
2355 case ARIZONA_INTERRUPT_RAW_STATUS_7:
2356 case ARIZONA_INTERRUPT_RAW_STATUS_8:
2357 case ARIZONA_IRQ_PIN_STATUS:
2358 case ARIZONA_AOD_WKUP_AND_TRIG:
2359 case ARIZONA_AOD_IRQ1:
2360 case ARIZONA_AOD_IRQ2:
2361 case ARIZONA_AOD_IRQ_RAW_STATUS:
2362 case ARIZONA_DSP1_STATUS_1:
2363 case ARIZONA_DSP1_STATUS_2:
2364 case ARIZONA_HEADPHONE_DETECT_2:
2365 case ARIZONA_MIC_DETECT_3:
2366 return true;
2367 default:
2368 return false;
2369 }
2370}
2371
2372const struct regmap_config wm5102_spi_regmap = {
2373 .reg_bits = 32,
2374 .pad_bits = 16,
2375 .val_bits = 16,
2376
2377 .max_register = ARIZONA_DSP1_STATUS_2,
2378 .readable_reg = wm5102_readable_register,
2379 .volatile_reg = wm5102_volatile_register,
2380
2381 .cache_type = REGCACHE_RBTREE,
2382 .reg_defaults = wm5102_reg_default,
2383 .num_reg_defaults = ARRAY_SIZE(wm5102_reg_default),
2384};
2385EXPORT_SYMBOL_GPL(wm5102_spi_regmap);
2386
2387const struct regmap_config wm5102_i2c_regmap = {
2388 .reg_bits = 32,
2389 .val_bits = 16,
2390
2391 .max_register = ARIZONA_DSP1_STATUS_2,
2392 .readable_reg = wm5102_readable_register,
2393 .volatile_reg = wm5102_volatile_register,
2394
2395 .cache_type = REGCACHE_RBTREE,
2396 .reg_defaults = wm5102_reg_default,
2397 .num_reg_defaults = ARRAY_SIZE(wm5102_reg_default),
2398};
2399EXPORT_SYMBOL_GPL(wm5102_i2c_regmap);
diff --git a/drivers/mfd/wm5110-tables.c b/drivers/mfd/wm5110-tables.c
new file mode 100644
index 000000000000..bd8782c8896b
--- /dev/null
+++ b/drivers/mfd/wm5110-tables.c
@@ -0,0 +1,2281 @@
1/*
2 * wm5110-tables.c -- WM5110 data tables
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14
15#include <linux/mfd/arizona/core.h>
16#include <linux/mfd/arizona/registers.h>
17
18#include "arizona.h"
19
20#define WM5110_NUM_AOD_ISR 2
21#define WM5110_NUM_ISR 5
22
23static const struct reg_default wm5110_reva_patch[] = {
24 { 0x80, 0x3 },
25 { 0x44, 0x20 },
26 { 0x45, 0x40 },
27 { 0x46, 0x60 },
28 { 0x47, 0x80 },
29 { 0x48, 0xa0 },
30 { 0x51, 0x13 },
31 { 0x52, 0x33 },
32 { 0x53, 0x53 },
33 { 0x54, 0x73 },
34 { 0x55, 0x75 },
35 { 0x56, 0xb3 },
36 { 0x2ef, 0x124 },
37 { 0x2ef, 0x124 },
38 { 0x2f0, 0x124 },
39 { 0x2f0, 0x124 },
40 { 0x2f1, 0x124 },
41 { 0x2f1, 0x124 },
42 { 0x2f2, 0x124 },
43 { 0x2f2, 0x124 },
44 { 0x2f3, 0x124 },
45 { 0x2f3, 0x124 },
46 { 0x2f4, 0x124 },
47 { 0x2f4, 0x124 },
48 { 0x2eb, 0x60 },
49 { 0x2ec, 0x60 },
50 { 0x2ed, 0x60 },
51 { 0xc30, 0x3e3e },
52 { 0xc30, 0x3e3e },
53 { 0xc31, 0x3e },
54 { 0xc32, 0x3e3e },
55 { 0xc32, 0x3e3e },
56 { 0xc33, 0x3e3e },
57 { 0xc33, 0x3e3e },
58 { 0xc34, 0x3e3e },
59 { 0xc34, 0x3e3e },
60 { 0xc35, 0x3e3e },
61 { 0xc35, 0x3e3e },
62 { 0xc36, 0x3e3e },
63 { 0xc36, 0x3e3e },
64 { 0xc37, 0x3e3e },
65 { 0xc37, 0x3e3e },
66 { 0xc38, 0x3e3e },
67 { 0xc38, 0x3e3e },
68 { 0xc30, 0x3e3e },
69 { 0xc30, 0x3e3e },
70 { 0xc39, 0x3e3e },
71 { 0xc39, 0x3e3e },
72 { 0xc3a, 0x3e3e },
73 { 0xc3a, 0x3e3e },
74 { 0xc3b, 0x3e3e },
75 { 0xc3b, 0x3e3e },
76 { 0xc3c, 0x3e },
77 { 0x201, 0x18a5 },
78 { 0x201, 0x18a5 },
79 { 0x201, 0x18a5 },
80 { 0x202, 0x4100 },
81 { 0x460, 0xc00 },
82 { 0x461, 0x8000 },
83 { 0x462, 0xc01 },
84 { 0x463, 0x50f0 },
85 { 0x464, 0xc01 },
86 { 0x465, 0x4820 },
87 { 0x466, 0xc01 },
88 { 0x466, 0xc01 },
89 { 0x467, 0x4040 },
90 { 0x468, 0xc01 },
91 { 0x468, 0xc01 },
92 { 0x469, 0x3940 },
93 { 0x46a, 0xc01 },
94 { 0x46a, 0xc01 },
95 { 0x46a, 0xc01 },
96 { 0x46b, 0x3310 },
97 { 0x46c, 0x801 },
98 { 0x46c, 0x801 },
99 { 0x46d, 0x2d80 },
100 { 0x46e, 0x801 },
101 { 0x46e, 0x801 },
102 { 0x46f, 0x2890 },
103 { 0x470, 0x801 },
104 { 0x470, 0x801 },
105 { 0x471, 0x1990 },
106 { 0x472, 0x801 },
107 { 0x472, 0x801 },
108 { 0x473, 0x1450 },
109 { 0x474, 0x801 },
110 { 0x474, 0x801 },
111 { 0x474, 0x801 },
112 { 0x475, 0x1020 },
113 { 0x476, 0x801 },
114 { 0x476, 0x801 },
115 { 0x476, 0x801 },
116 { 0x477, 0xcd0 },
117 { 0x478, 0x806 },
118 { 0x478, 0x806 },
119 { 0x479, 0xa30 },
120 { 0x47a, 0x806 },
121 { 0x47a, 0x806 },
122 { 0x47b, 0x810 },
123 { 0x47c, 0x80e },
124 { 0x47c, 0x80e },
125 { 0x47d, 0x510 },
126 { 0x47e, 0x81f },
127 { 0x47e, 0x81f },
128 { 0x2DB, 0x0A00 },
129 { 0x2DD, 0x0023 },
130 { 0x2DF, 0x0102 },
131 { 0x80, 0x0 },
132 { 0xC20, 0x0002 },
133 { 0x209, 0x002A },
134};
135
136/* We use a function so we can use ARRAY_SIZE() */
137int wm5110_patch(struct arizona *arizona)
138{
139 switch (arizona->rev) {
140 case 0:
141 case 1:
142 return regmap_register_patch(arizona->regmap,
143 wm5110_reva_patch,
144 ARRAY_SIZE(wm5110_reva_patch));
145 default:
146 return 0;
147 }
148}
149EXPORT_SYMBOL_GPL(wm5110_patch);
150
151static const struct regmap_irq wm5110_aod_irqs[ARIZONA_NUM_IRQ] = {
152 [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
153 [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
154 [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
155 [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
156};
157
158const struct regmap_irq_chip wm5110_aod = {
159 .name = "wm5110 AOD",
160 .status_base = ARIZONA_AOD_IRQ1,
161 .mask_base = ARIZONA_AOD_IRQ_MASK_IRQ1,
162 .ack_base = ARIZONA_AOD_IRQ1,
163 .wake_base = ARIZONA_WAKE_CONTROL,
164 .num_regs = 1,
165 .irqs = wm5110_aod_irqs,
166 .num_irqs = ARRAY_SIZE(wm5110_aod_irqs),
167};
168EXPORT_SYMBOL_GPL(wm5110_aod);
169
170static const struct regmap_irq wm5110_irqs[ARIZONA_NUM_IRQ] = {
171 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
172 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
173 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
174 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
175
176 [ARIZONA_IRQ_DSP4_RAM_RDY] = {
177 .reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1
178 },
179 [ARIZONA_IRQ_DSP3_RAM_RDY] = {
180 .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
181 },
182 [ARIZONA_IRQ_DSP2_RAM_RDY] = {
183 .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
184 },
185 [ARIZONA_IRQ_DSP1_RAM_RDY] = {
186 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
187 },
188 [ARIZONA_IRQ_DSP_IRQ8] = {
189 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
190 },
191 [ARIZONA_IRQ_DSP_IRQ7] = {
192 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
193 },
194 [ARIZONA_IRQ_DSP_IRQ6] = {
195 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
196 },
197 [ARIZONA_IRQ_DSP_IRQ5] = {
198 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
199 },
200 [ARIZONA_IRQ_DSP_IRQ4] = {
201 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
202 },
203 [ARIZONA_IRQ_DSP_IRQ3] = {
204 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
205 },
206 [ARIZONA_IRQ_DSP_IRQ2] = {
207 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
208 },
209 [ARIZONA_IRQ_DSP_IRQ1] = {
210 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
211 },
212
213 [ARIZONA_IRQ_SPK_SHUTDOWN_WARN] = {
214 .reg_offset = 2, .mask = ARIZONA_SPK_SHUTDOWN_WARN_EINT1
215 },
216 [ARIZONA_IRQ_SPK_SHUTDOWN] = {
217 .reg_offset = 2, .mask = ARIZONA_SPK_SHUTDOWN_EINT1
218 },
219 [ARIZONA_IRQ_HPDET] = {
220 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
221 },
222 [ARIZONA_IRQ_MICDET] = {
223 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
224 },
225 [ARIZONA_IRQ_WSEQ_DONE] = {
226 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
227 },
228 [ARIZONA_IRQ_DRC2_SIG_DET] = {
229 .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1
230 },
231 [ARIZONA_IRQ_DRC1_SIG_DET] = {
232 .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
233 },
234 [ARIZONA_IRQ_ASRC2_LOCK] = {
235 .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
236 },
237 [ARIZONA_IRQ_ASRC1_LOCK] = {
238 .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
239 },
240 [ARIZONA_IRQ_UNDERCLOCKED] = {
241 .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1
242 },
243 [ARIZONA_IRQ_OVERCLOCKED] = {
244 .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
245 },
246 [ARIZONA_IRQ_FLL2_LOCK] = {
247 .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
248 },
249 [ARIZONA_IRQ_FLL1_LOCK] = {
250 .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
251 },
252 [ARIZONA_IRQ_CLKGEN_ERR] = {
253 .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
254 },
255 [ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = {
256 .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1
257 },
258
259 [ARIZONA_IRQ_ASRC_CFG_ERR] = {
260 .reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1
261 },
262 [ARIZONA_IRQ_AIF3_ERR] = {
263 .reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1
264 },
265 [ARIZONA_IRQ_AIF2_ERR] = {
266 .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1
267 },
268 [ARIZONA_IRQ_AIF1_ERR] = {
269 .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1
270 },
271 [ARIZONA_IRQ_CTRLIF_ERR] = {
272 .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1
273 },
274 [ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = {
275 .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1
276 },
277 [ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = {
278 .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1
279 },
280 [ARIZONA_IRQ_SYSCLK_ENA_LOW] = {
281 .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1
282 },
283 [ARIZONA_IRQ_ISRC1_CFG_ERR] = {
284 .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1
285 },
286 [ARIZONA_IRQ_ISRC2_CFG_ERR] = {
287 .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1
288 },
289
290 [ARIZONA_IRQ_BOOT_DONE] = {
291 .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1
292 },
293 [ARIZONA_IRQ_DCS_DAC_DONE] = {
294 .reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1
295 },
296 [ARIZONA_IRQ_DCS_HP_DONE] = {
297 .reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1
298 },
299 [ARIZONA_IRQ_FLL2_CLOCK_OK] = {
300 .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1
301 },
302 [ARIZONA_IRQ_FLL1_CLOCK_OK] = {
303 .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1
304 },
305};
306
307const struct regmap_irq_chip wm5110_irq = {
308 .name = "wm5110 IRQ",
309 .status_base = ARIZONA_INTERRUPT_STATUS_1,
310 .mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK,
311 .ack_base = ARIZONA_INTERRUPT_STATUS_1,
312 .num_regs = 5,
313 .irqs = wm5110_irqs,
314 .num_irqs = ARRAY_SIZE(wm5110_irqs),
315};
316EXPORT_SYMBOL_GPL(wm5110_irq);
317
318static const struct reg_default wm5110_reg_default[] = {
319 { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
320 { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
321 { 0x0000000A, 0x0001 }, /* R10 - Ctrl IF I2C2 CFG 1 */
322 { 0x0000000B, 0x0036 }, /* R11 - Ctrl IF I2C1 CFG 2 */
323 { 0x0000000C, 0x0036 }, /* R12 - Ctrl IF I2C2 CFG 2 */
324 { 0x00000016, 0x0000 }, /* R22 - Write Sequencer Ctrl 0 */
325 { 0x00000017, 0x0000 }, /* R23 - Write Sequencer Ctrl 1 */
326 { 0x00000018, 0x0000 }, /* R24 - Write Sequencer Ctrl 2 */
327 { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
328 { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
329 { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
330 { 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */
331 { 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */
332 { 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */
333 { 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */
334 { 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */
335 { 0x00000040, 0x0000 }, /* R64 - Wake control */
336 { 0x00000041, 0x0000 }, /* R65 - Sequence control */
337 { 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */
338 { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */
339 { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */
340 { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */
341 { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 1 */
342 { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 2 */
343 { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 3 */
344 { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 4 */
345 { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */
346 { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */
347 { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */
348 { 0x00000092, 0x0000 }, /* R146 - Haptics phase 1 intensity */
349 { 0x00000093, 0x0000 }, /* R147 - Haptics phase 1 duration */
350 { 0x00000094, 0x0000 }, /* R148 - Haptics phase 2 intensity */
351 { 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */
352 { 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */
353 { 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */
354 { 0x00000100, 0x0001 }, /* R256 - Clock 32k 1 */
355 { 0x00000101, 0x0504 }, /* R257 - System Clock 1 */
356 { 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */
357 { 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */
358 { 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */
359 { 0x00000112, 0x0305 }, /* R274 - Async clock 1 */
360 { 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */
361 { 0x00000149, 0x0000 }, /* R329 - Output system clock */
362 { 0x0000014A, 0x0000 }, /* R330 - Output async clock */
363 { 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */
364 { 0x00000153, 0x0000 }, /* R339 - Rate Estimator 2 */
365 { 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */
366 { 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */
367 { 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */
368 { 0x00000171, 0x0000 }, /* R369 - FLL1 Control 1 */
369 { 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */
370 { 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */
371 { 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */
372 { 0x00000175, 0x0006 }, /* R373 - FLL1 Control 5 */
373 { 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */
374 { 0x00000177, 0x0281 }, /* R375 - FLL1 Loop Filter Test 1 */
375 { 0x00000178, 0x0000 }, /* R376 - FLL1 NCO Test 0 */
376 { 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */
377 { 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */
378 { 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */
379 { 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */
380 { 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */
381 { 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */
382 { 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */
383 { 0x0000018A, 0x0004 }, /* R394 - FLL1 GPIO Clock */
384 { 0x00000191, 0x0000 }, /* R401 - FLL2 Control 1 */
385 { 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */
386 { 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */
387 { 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */
388 { 0x00000195, 0x000C }, /* R405 - FLL2 Control 5 */
389 { 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */
390 { 0x00000197, 0x0000 }, /* R407 - FLL2 Loop Filter Test 1 */
391 { 0x00000198, 0x0000 }, /* R408 - FLL2 NCO Test 0 */
392 { 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */
393 { 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */
394 { 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */
395 { 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */
396 { 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */
397 { 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */
398 { 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */
399 { 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */
400 { 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */
401 { 0x00000210, 0x0184 }, /* R528 - LDO1 Control 1 */
402 { 0x00000213, 0x0344 }, /* R531 - LDO2 Control 1 */
403 { 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */
404 { 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */
405 { 0x0000021A, 0x01A6 }, /* R538 - Mic Bias Ctrl 3 */
406 { 0x00000293, 0x0000 }, /* R659 - Accessory Detect Mode 1 */
407 { 0x0000029B, 0x0020 }, /* R667 - Headphone Detect 1 */
408 { 0x0000029C, 0x0000 }, /* R668 - Headphone Detect 2 */
409 { 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */
410 { 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */
411 { 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */
412 { 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */
413 { 0x00000300, 0x0000 }, /* R768 - Input Enables */
414 { 0x00000308, 0x0000 }, /* R776 - Input Rate */
415 { 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */
416 { 0x00000310, 0x2080 }, /* R784 - IN1L Control */
417 { 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */
418 { 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */
419 { 0x00000314, 0x0080 }, /* R788 - IN1R Control */
420 { 0x00000315, 0x0180 }, /* R789 - ADC Digital Volume 1R */
421 { 0x00000316, 0x0000 }, /* R790 - DMIC1R Control */
422 { 0x00000318, 0x2080 }, /* R792 - IN2L Control */
423 { 0x00000319, 0x0180 }, /* R793 - ADC Digital Volume 2L */
424 { 0x0000031A, 0x0000 }, /* R794 - DMIC2L Control */
425 { 0x0000031C, 0x0080 }, /* R796 - IN2R Control */
426 { 0x0000031D, 0x0180 }, /* R797 - ADC Digital Volume 2R */
427 { 0x0000031E, 0x0000 }, /* R798 - DMIC2R Control */
428 { 0x00000320, 0x2080 }, /* R800 - IN3L Control */
429 { 0x00000321, 0x0180 }, /* R801 - ADC Digital Volume 3L */
430 { 0x00000322, 0x0000 }, /* R802 - DMIC3L Control */
431 { 0x00000324, 0x0080 }, /* R804 - IN3R Control */
432 { 0x00000325, 0x0180 }, /* R805 - ADC Digital Volume 3R */
433 { 0x00000326, 0x0000 }, /* R806 - DMIC3R Control */
434 { 0x00000328, 0x2000 }, /* R808 - IN4L Control */
435 { 0x00000329, 0x0180 }, /* R809 - ADC Digital Volume 4L */
436 { 0x0000032A, 0x0000 }, /* R810 - DMIC4L Control */
437 { 0x0000032D, 0x0180 }, /* R813 - ADC Digital Volume 4R */
438 { 0x0000032E, 0x0000 }, /* R814 - DMIC4R Control */
439 { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */
440 { 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */
441 { 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */
442 { 0x00000410, 0x0080 }, /* R1040 - Output Path Config 1L */
443 { 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */
444 { 0x00000412, 0x0080 }, /* R1042 - DAC Volume Limit 1L */
445 { 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */
446 { 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */
447 { 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */
448 { 0x00000416, 0x0080 }, /* R1046 - DAC Volume Limit 1R */
449 { 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */
450 { 0x00000418, 0x0080 }, /* R1048 - Output Path Config 2L */
451 { 0x00000419, 0x0180 }, /* R1049 - DAC Digital Volume 2L */
452 { 0x0000041A, 0x0080 }, /* R1050 - DAC Volume Limit 2L */
453 { 0x0000041B, 0x0004 }, /* R1051 - Noise Gate Select 2L */
454 { 0x0000041C, 0x0080 }, /* R1052 - Output Path Config 2R */
455 { 0x0000041D, 0x0180 }, /* R1053 - DAC Digital Volume 2R */
456 { 0x0000041E, 0x0080 }, /* R1054 - DAC Volume Limit 2R */
457 { 0x0000041F, 0x0008 }, /* R1055 - Noise Gate Select 2R */
458 { 0x00000420, 0x0080 }, /* R1056 - Output Path Config 3L */
459 { 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */
460 { 0x00000422, 0x0080 }, /* R1058 - DAC Volume Limit 3L */
461 { 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */
462 { 0x00000424, 0x0080 }, /* R1060 - Output Path Config 3R */
463 { 0x00000425, 0x0180 }, /* R1061 - DAC Digital Volume 3R */
464 { 0x00000426, 0x0080 }, /* R1062 - DAC Volume Limit 3R */
465 { 0x00000427, 0x0020 }, /* R1063 - Noise Gate Select 3R */
466 { 0x00000428, 0x0000 }, /* R1064 - Output Path Config 4L */
467 { 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */
468 { 0x0000042A, 0x0080 }, /* R1066 - Out Volume 4L */
469 { 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */
470 { 0x0000042C, 0x0000 }, /* R1068 - Output Path Config 4R */
471 { 0x0000042D, 0x0180 }, /* R1069 - DAC Digital Volume 4R */
472 { 0x0000042E, 0x0080 }, /* R1070 - Out Volume 4R */
473 { 0x0000042F, 0x0080 }, /* R1071 - Noise Gate Select 4R */
474 { 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */
475 { 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */
476 { 0x00000432, 0x0080 }, /* R1074 - DAC Volume Limit 5L */
477 { 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */
478 { 0x00000434, 0x0000 }, /* R1076 - Output Path Config 5R */
479 { 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */
480 { 0x00000436, 0x0080 }, /* R1078 - DAC Volume Limit 5R */
481 { 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */
482 { 0x00000438, 0x0000 }, /* R1080 - Output Path Config 6L */
483 { 0x00000439, 0x0180 }, /* R1081 - DAC Digital Volume 6L */
484 { 0x0000043A, 0x0080 }, /* R1082 - DAC Volume Limit 6L */
485 { 0x0000043B, 0x0400 }, /* R1083 - Noise Gate Select 6L */
486 { 0x0000043C, 0x0000 }, /* R1084 - Output Path Config 6R */
487 { 0x0000043D, 0x0180 }, /* R1085 - DAC Digital Volume 6R */
488 { 0x0000043E, 0x0080 }, /* R1086 - DAC Volume Limit 6R */
489 { 0x0000043F, 0x0800 }, /* R1087 - Noise Gate Select 6R */
490 { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
491 { 0x00000458, 0x0001 }, /* R1112 - Noise Gate Control */
492 { 0x00000480, 0x0040 }, /* R1152 - Class W ANC Threshold 1 */
493 { 0x00000481, 0x0040 }, /* R1153 - Class W ANC Threshold 2 */
494 { 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */
495 { 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */
496 { 0x00000492, 0x0069 }, /* R1170 - PDM SPK2 CTRL 1 */
497 { 0x00000493, 0x0000 }, /* R1171 - PDM SPK2 CTRL 2 */
498 { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */
499 { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */
500 { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */
501 { 0x00000503, 0x0000 }, /* R1283 - AIF1 Rate Ctrl */
502 { 0x00000504, 0x0000 }, /* R1284 - AIF1 Format */
503 { 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */
504 { 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */
505 { 0x00000507, 0x1818 }, /* R1287 - AIF1 Frame Ctrl 1 */
506 { 0x00000508, 0x1818 }, /* R1288 - AIF1 Frame Ctrl 2 */
507 { 0x00000509, 0x0000 }, /* R1289 - AIF1 Frame Ctrl 3 */
508 { 0x0000050A, 0x0001 }, /* R1290 - AIF1 Frame Ctrl 4 */
509 { 0x0000050B, 0x0002 }, /* R1291 - AIF1 Frame Ctrl 5 */
510 { 0x0000050C, 0x0003 }, /* R1292 - AIF1 Frame Ctrl 6 */
511 { 0x0000050D, 0x0004 }, /* R1293 - AIF1 Frame Ctrl 7 */
512 { 0x0000050E, 0x0005 }, /* R1294 - AIF1 Frame Ctrl 8 */
513 { 0x0000050F, 0x0006 }, /* R1295 - AIF1 Frame Ctrl 9 */
514 { 0x00000510, 0x0007 }, /* R1296 - AIF1 Frame Ctrl 10 */
515 { 0x00000511, 0x0000 }, /* R1297 - AIF1 Frame Ctrl 11 */
516 { 0x00000512, 0x0001 }, /* R1298 - AIF1 Frame Ctrl 12 */
517 { 0x00000513, 0x0002 }, /* R1299 - AIF1 Frame Ctrl 13 */
518 { 0x00000514, 0x0003 }, /* R1300 - AIF1 Frame Ctrl 14 */
519 { 0x00000515, 0x0004 }, /* R1301 - AIF1 Frame Ctrl 15 */
520 { 0x00000516, 0x0005 }, /* R1302 - AIF1 Frame Ctrl 16 */
521 { 0x00000517, 0x0006 }, /* R1303 - AIF1 Frame Ctrl 17 */
522 { 0x00000518, 0x0007 }, /* R1304 - AIF1 Frame Ctrl 18 */
523 { 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */
524 { 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */
525 { 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */
526 { 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */
527 { 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */
528 { 0x00000543, 0x0000 }, /* R1347 - AIF2 Rate Ctrl */
529 { 0x00000544, 0x0000 }, /* R1348 - AIF2 Format */
530 { 0x00000545, 0x0040 }, /* R1349 - AIF2 Tx BCLK Rate */
531 { 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */
532 { 0x00000547, 0x1818 }, /* R1351 - AIF2 Frame Ctrl 1 */
533 { 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */
534 { 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */
535 { 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */
536 { 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */
537 { 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */
538 { 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */
539 { 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */
540 { 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */
541 { 0x00000581, 0x0008 }, /* R1409 - AIF3 Tx Pin Ctrl */
542 { 0x00000582, 0x0000 }, /* R1410 - AIF3 Rx Pin Ctrl */
543 { 0x00000583, 0x0000 }, /* R1411 - AIF3 Rate Ctrl */
544 { 0x00000584, 0x0000 }, /* R1412 - AIF3 Format */
545 { 0x00000585, 0x0040 }, /* R1413 - AIF3 Tx BCLK Rate */
546 { 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */
547 { 0x00000587, 0x1818 }, /* R1415 - AIF3 Frame Ctrl 1 */
548 { 0x00000588, 0x1818 }, /* R1416 - AIF3 Frame Ctrl 2 */
549 { 0x00000589, 0x0000 }, /* R1417 - AIF3 Frame Ctrl 3 */
550 { 0x0000058A, 0x0001 }, /* R1418 - AIF3 Frame Ctrl 4 */
551 { 0x00000591, 0x0000 }, /* R1425 - AIF3 Frame Ctrl 11 */
552 { 0x00000592, 0x0001 }, /* R1426 - AIF3 Frame Ctrl 12 */
553 { 0x00000599, 0x0000 }, /* R1433 - AIF3 Tx Enables */
554 { 0x0000059A, 0x0000 }, /* R1434 - AIF3 Rx Enables */
555 { 0x000005E3, 0x0004 }, /* R1507 - SLIMbus Framer Ref Gear */
556 { 0x000005E5, 0x0000 }, /* R1509 - SLIMbus Rates 1 */
557 { 0x000005E6, 0x0000 }, /* R1510 - SLIMbus Rates 2 */
558 { 0x000005E7, 0x0000 }, /* R1511 - SLIMbus Rates 3 */
559 { 0x000005E8, 0x0000 }, /* R1512 - SLIMbus Rates 4 */
560 { 0x000005E9, 0x0000 }, /* R1513 - SLIMbus Rates 5 */
561 { 0x000005EA, 0x0000 }, /* R1514 - SLIMbus Rates 6 */
562 { 0x000005EB, 0x0000 }, /* R1515 - SLIMbus Rates 7 */
563 { 0x000005EC, 0x0000 }, /* R1516 - SLIMbus Rates 8 */
564 { 0x000005F5, 0x0000 }, /* R1525 - SLIMbus RX Channel Enable */
565 { 0x000005F6, 0x0000 }, /* R1526 - SLIMbus TX Channel Enable */
566 { 0x00000640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */
567 { 0x00000641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */
568 { 0x00000642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */
569 { 0x00000643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */
570 { 0x00000644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */
571 { 0x00000645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */
572 { 0x00000646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */
573 { 0x00000647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */
574 { 0x00000648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */
575 { 0x00000649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */
576 { 0x0000064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */
577 { 0x0000064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */
578 { 0x0000064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */
579 { 0x0000064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */
580 { 0x0000064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */
581 { 0x0000064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */
582 { 0x00000660, 0x0000 }, /* R1632 - MICMIX Input 1 Source */
583 { 0x00000661, 0x0080 }, /* R1633 - MICMIX Input 1 Volume */
584 { 0x00000662, 0x0000 }, /* R1634 - MICMIX Input 2 Source */
585 { 0x00000663, 0x0080 }, /* R1635 - MICMIX Input 2 Volume */
586 { 0x00000664, 0x0000 }, /* R1636 - MICMIX Input 3 Source */
587 { 0x00000665, 0x0080 }, /* R1637 - MICMIX Input 3 Volume */
588 { 0x00000666, 0x0000 }, /* R1638 - MICMIX Input 4 Source */
589 { 0x00000667, 0x0080 }, /* R1639 - MICMIX Input 4 Volume */
590 { 0x00000668, 0x0000 }, /* R1640 - NOISEMIX Input 1 Source */
591 { 0x00000669, 0x0080 }, /* R1641 - NOISEMIX Input 1 Volume */
592 { 0x0000066A, 0x0000 }, /* R1642 - NOISEMIX Input 2 Source */
593 { 0x0000066B, 0x0080 }, /* R1643 - NOISEMIX Input 2 Volume */
594 { 0x0000066C, 0x0000 }, /* R1644 - NOISEMIX Input 3 Source */
595 { 0x0000066D, 0x0080 }, /* R1645 - NOISEMIX Input 3 Volume */
596 { 0x0000066E, 0x0000 }, /* R1646 - NOISEMIX Input 4 Source */
597 { 0x0000066F, 0x0080 }, /* R1647 - NOISEMIX Input 4 Volume */
598 { 0x00000680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */
599 { 0x00000681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */
600 { 0x00000682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */
601 { 0x00000683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */
602 { 0x00000684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */
603 { 0x00000685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */
604 { 0x00000686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */
605 { 0x00000687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */
606 { 0x00000688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */
607 { 0x00000689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */
608 { 0x0000068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */
609 { 0x0000068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */
610 { 0x0000068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */
611 { 0x0000068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */
612 { 0x0000068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */
613 { 0x0000068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */
614 { 0x00000690, 0x0000 }, /* R1680 - OUT2LMIX Input 1 Source */
615 { 0x00000691, 0x0080 }, /* R1681 - OUT2LMIX Input 1 Volume */
616 { 0x00000692, 0x0000 }, /* R1682 - OUT2LMIX Input 2 Source */
617 { 0x00000693, 0x0080 }, /* R1683 - OUT2LMIX Input 2 Volume */
618 { 0x00000694, 0x0000 }, /* R1684 - OUT2LMIX Input 3 Source */
619 { 0x00000695, 0x0080 }, /* R1685 - OUT2LMIX Input 3 Volume */
620 { 0x00000696, 0x0000 }, /* R1686 - OUT2LMIX Input 4 Source */
621 { 0x00000697, 0x0080 }, /* R1687 - OUT2LMIX Input 4 Volume */
622 { 0x00000698, 0x0000 }, /* R1688 - OUT2RMIX Input 1 Source */
623 { 0x00000699, 0x0080 }, /* R1689 - OUT2RMIX Input 1 Volume */
624 { 0x0000069A, 0x0000 }, /* R1690 - OUT2RMIX Input 2 Source */
625 { 0x0000069B, 0x0080 }, /* R1691 - OUT2RMIX Input 2 Volume */
626 { 0x0000069C, 0x0000 }, /* R1692 - OUT2RMIX Input 3 Source */
627 { 0x0000069D, 0x0080 }, /* R1693 - OUT2RMIX Input 3 Volume */
628 { 0x0000069E, 0x0000 }, /* R1694 - OUT2RMIX Input 4 Source */
629 { 0x0000069F, 0x0080 }, /* R1695 - OUT2RMIX Input 4 Volume */
630 { 0x000006A0, 0x0000 }, /* R1696 - OUT3LMIX Input 1 Source */
631 { 0x000006A1, 0x0080 }, /* R1697 - OUT3LMIX Input 1 Volume */
632 { 0x000006A2, 0x0000 }, /* R1698 - OUT3LMIX Input 2 Source */
633 { 0x000006A3, 0x0080 }, /* R1699 - OUT3LMIX Input 2 Volume */
634 { 0x000006A4, 0x0000 }, /* R1700 - OUT3LMIX Input 3 Source */
635 { 0x000006A5, 0x0080 }, /* R1701 - OUT3LMIX Input 3 Volume */
636 { 0x000006A6, 0x0000 }, /* R1702 - OUT3LMIX Input 4 Source */
637 { 0x000006A7, 0x0080 }, /* R1703 - OUT3LMIX Input 4 Volume */
638 { 0x000006A8, 0x0000 }, /* R1704 - OUT3RMIX Input 1 Source */
639 { 0x000006A9, 0x0080 }, /* R1705 - OUT3RMIX Input 1 Volume */
640 { 0x000006AA, 0x0000 }, /* R1706 - OUT3RMIX Input 2 Source */
641 { 0x000006AB, 0x0080 }, /* R1707 - OUT3RMIX Input 2 Volume */
642 { 0x000006AC, 0x0000 }, /* R1708 - OUT3RMIX Input 3 Source */
643 { 0x000006AD, 0x0080 }, /* R1709 - OUT3RMIX Input 3 Volume */
644 { 0x000006AE, 0x0000 }, /* R1710 - OUT3RMIX Input 4 Source */
645 { 0x000006AF, 0x0080 }, /* R1711 - OUT3RMIX Input 4 Volume */
646 { 0x000006B0, 0x0000 }, /* R1712 - OUT4LMIX Input 1 Source */
647 { 0x000006B1, 0x0080 }, /* R1713 - OUT4LMIX Input 1 Volume */
648 { 0x000006B2, 0x0000 }, /* R1714 - OUT4LMIX Input 2 Source */
649 { 0x000006B3, 0x0080 }, /* R1715 - OUT4LMIX Input 2 Volume */
650 { 0x000006B4, 0x0000 }, /* R1716 - OUT4LMIX Input 3 Source */
651 { 0x000006B5, 0x0080 }, /* R1717 - OUT4LMIX Input 3 Volume */
652 { 0x000006B6, 0x0000 }, /* R1718 - OUT4LMIX Input 4 Source */
653 { 0x000006B7, 0x0080 }, /* R1719 - OUT4LMIX Input 4 Volume */
654 { 0x000006B8, 0x0000 }, /* R1720 - OUT4RMIX Input 1 Source */
655 { 0x000006B9, 0x0080 }, /* R1721 - OUT4RMIX Input 1 Volume */
656 { 0x000006BA, 0x0000 }, /* R1722 - OUT4RMIX Input 2 Source */
657 { 0x000006BB, 0x0080 }, /* R1723 - OUT4RMIX Input 2 Volume */
658 { 0x000006BC, 0x0000 }, /* R1724 - OUT4RMIX Input 3 Source */
659 { 0x000006BD, 0x0080 }, /* R1725 - OUT4RMIX Input 3 Volume */
660 { 0x000006BE, 0x0000 }, /* R1726 - OUT4RMIX Input 4 Source */
661 { 0x000006BF, 0x0080 }, /* R1727 - OUT4RMIX Input 4 Volume */
662 { 0x000006C0, 0x0000 }, /* R1728 - OUT5LMIX Input 1 Source */
663 { 0x000006C1, 0x0080 }, /* R1729 - OUT5LMIX Input 1 Volume */
664 { 0x000006C2, 0x0000 }, /* R1730 - OUT5LMIX Input 2 Source */
665 { 0x000006C3, 0x0080 }, /* R1731 - OUT5LMIX Input 2 Volume */
666 { 0x000006C4, 0x0000 }, /* R1732 - OUT5LMIX Input 3 Source */
667 { 0x000006C5, 0x0080 }, /* R1733 - OUT5LMIX Input 3 Volume */
668 { 0x000006C6, 0x0000 }, /* R1734 - OUT5LMIX Input 4 Source */
669 { 0x000006C7, 0x0080 }, /* R1735 - OUT5LMIX Input 4 Volume */
670 { 0x000006C8, 0x0000 }, /* R1736 - OUT5RMIX Input 1 Source */
671 { 0x000006C9, 0x0080 }, /* R1737 - OUT5RMIX Input 1 Volume */
672 { 0x000006CA, 0x0000 }, /* R1738 - OUT5RMIX Input 2 Source */
673 { 0x000006CB, 0x0080 }, /* R1739 - OUT5RMIX Input 2 Volume */
674 { 0x000006CC, 0x0000 }, /* R1740 - OUT5RMIX Input 3 Source */
675 { 0x000006CD, 0x0080 }, /* R1741 - OUT5RMIX Input 3 Volume */
676 { 0x000006CE, 0x0000 }, /* R1742 - OUT5RMIX Input 4 Source */
677 { 0x000006CF, 0x0080 }, /* R1743 - OUT5RMIX Input 4 Volume */
678 { 0x000006D0, 0x0000 }, /* R1744 - OUT6LMIX Input 1 Source */
679 { 0x000006D1, 0x0080 }, /* R1745 - OUT6LMIX Input 1 Volume */
680 { 0x000006D2, 0x0000 }, /* R1746 - OUT6LMIX Input 2 Source */
681 { 0x000006D3, 0x0080 }, /* R1747 - OUT6LMIX Input 2 Volume */
682 { 0x000006D4, 0x0000 }, /* R1748 - OUT6LMIX Input 3 Source */
683 { 0x000006D5, 0x0080 }, /* R1749 - OUT6LMIX Input 3 Volume */
684 { 0x000006D6, 0x0000 }, /* R1750 - OUT6LMIX Input 4 Source */
685 { 0x000006D7, 0x0080 }, /* R1751 - OUT6LMIX Input 4 Volume */
686 { 0x000006D8, 0x0000 }, /* R1752 - OUT6RMIX Input 1 Source */
687 { 0x000006D9, 0x0080 }, /* R1753 - OUT6RMIX Input 1 Volume */
688 { 0x000006DA, 0x0000 }, /* R1754 - OUT6RMIX Input 2 Source */
689 { 0x000006DB, 0x0080 }, /* R1755 - OUT6RMIX Input 2 Volume */
690 { 0x000006DC, 0x0000 }, /* R1756 - OUT6RMIX Input 3 Source */
691 { 0x000006DD, 0x0080 }, /* R1757 - OUT6RMIX Input 3 Volume */
692 { 0x000006DE, 0x0000 }, /* R1758 - OUT6RMIX Input 4 Source */
693 { 0x000006DF, 0x0080 }, /* R1759 - OUT6RMIX Input 4 Volume */
694 { 0x00000700, 0x0000 }, /* R1792 - AIF1TX1MIX Input 1 Source */
695 { 0x00000701, 0x0080 }, /* R1793 - AIF1TX1MIX Input 1 Volume */
696 { 0x00000702, 0x0000 }, /* R1794 - AIF1TX1MIX Input 2 Source */
697 { 0x00000703, 0x0080 }, /* R1795 - AIF1TX1MIX Input 2 Volume */
698 { 0x00000704, 0x0000 }, /* R1796 - AIF1TX1MIX Input 3 Source */
699 { 0x00000705, 0x0080 }, /* R1797 - AIF1TX1MIX Input 3 Volume */
700 { 0x00000706, 0x0000 }, /* R1798 - AIF1TX1MIX Input 4 Source */
701 { 0x00000707, 0x0080 }, /* R1799 - AIF1TX1MIX Input 4 Volume */
702 { 0x00000708, 0x0000 }, /* R1800 - AIF1TX2MIX Input 1 Source */
703 { 0x00000709, 0x0080 }, /* R1801 - AIF1TX2MIX Input 1 Volume */
704 { 0x0000070A, 0x0000 }, /* R1802 - AIF1TX2MIX Input 2 Source */
705 { 0x0000070B, 0x0080 }, /* R1803 - AIF1TX2MIX Input 2 Volume */
706 { 0x0000070C, 0x0000 }, /* R1804 - AIF1TX2MIX Input 3 Source */
707 { 0x0000070D, 0x0080 }, /* R1805 - AIF1TX2MIX Input 3 Volume */
708 { 0x0000070E, 0x0000 }, /* R1806 - AIF1TX2MIX Input 4 Source */
709 { 0x0000070F, 0x0080 }, /* R1807 - AIF1TX2MIX Input 4 Volume */
710 { 0x00000710, 0x0000 }, /* R1808 - AIF1TX3MIX Input 1 Source */
711 { 0x00000711, 0x0080 }, /* R1809 - AIF1TX3MIX Input 1 Volume */
712 { 0x00000712, 0x0000 }, /* R1810 - AIF1TX3MIX Input 2 Source */
713 { 0x00000713, 0x0080 }, /* R1811 - AIF1TX3MIX Input 2 Volume */
714 { 0x00000714, 0x0000 }, /* R1812 - AIF1TX3MIX Input 3 Source */
715 { 0x00000715, 0x0080 }, /* R1813 - AIF1TX3MIX Input 3 Volume */
716 { 0x00000716, 0x0000 }, /* R1814 - AIF1TX3MIX Input 4 Source */
717 { 0x00000717, 0x0080 }, /* R1815 - AIF1TX3MIX Input 4 Volume */
718 { 0x00000718, 0x0000 }, /* R1816 - AIF1TX4MIX Input 1 Source */
719 { 0x00000719, 0x0080 }, /* R1817 - AIF1TX4MIX Input 1 Volume */
720 { 0x0000071A, 0x0000 }, /* R1818 - AIF1TX4MIX Input 2 Source */
721 { 0x0000071B, 0x0080 }, /* R1819 - AIF1TX4MIX Input 2 Volume */
722 { 0x0000071C, 0x0000 }, /* R1820 - AIF1TX4MIX Input 3 Source */
723 { 0x0000071D, 0x0080 }, /* R1821 - AIF1TX4MIX Input 3 Volume */
724 { 0x0000071E, 0x0000 }, /* R1822 - AIF1TX4MIX Input 4 Source */
725 { 0x0000071F, 0x0080 }, /* R1823 - AIF1TX4MIX Input 4 Volume */
726 { 0x00000720, 0x0000 }, /* R1824 - AIF1TX5MIX Input 1 Source */
727 { 0x00000721, 0x0080 }, /* R1825 - AIF1TX5MIX Input 1 Volume */
728 { 0x00000722, 0x0000 }, /* R1826 - AIF1TX5MIX Input 2 Source */
729 { 0x00000723, 0x0080 }, /* R1827 - AIF1TX5MIX Input 2 Volume */
730 { 0x00000724, 0x0000 }, /* R1828 - AIF1TX5MIX Input 3 Source */
731 { 0x00000725, 0x0080 }, /* R1829 - AIF1TX5MIX Input 3 Volume */
732 { 0x00000726, 0x0000 }, /* R1830 - AIF1TX5MIX Input 4 Source */
733 { 0x00000727, 0x0080 }, /* R1831 - AIF1TX5MIX Input 4 Volume */
734 { 0x00000728, 0x0000 }, /* R1832 - AIF1TX6MIX Input 1 Source */
735 { 0x00000729, 0x0080 }, /* R1833 - AIF1TX6MIX Input 1 Volume */
736 { 0x0000072A, 0x0000 }, /* R1834 - AIF1TX6MIX Input 2 Source */
737 { 0x0000072B, 0x0080 }, /* R1835 - AIF1TX6MIX Input 2 Volume */
738 { 0x0000072C, 0x0000 }, /* R1836 - AIF1TX6MIX Input 3 Source */
739 { 0x0000072D, 0x0080 }, /* R1837 - AIF1TX6MIX Input 3 Volume */
740 { 0x0000072E, 0x0000 }, /* R1838 - AIF1TX6MIX Input 4 Source */
741 { 0x0000072F, 0x0080 }, /* R1839 - AIF1TX6MIX Input 4 Volume */
742 { 0x00000730, 0x0000 }, /* R1840 - AIF1TX7MIX Input 1 Source */
743 { 0x00000731, 0x0080 }, /* R1841 - AIF1TX7MIX Input 1 Volume */
744 { 0x00000732, 0x0000 }, /* R1842 - AIF1TX7MIX Input 2 Source */
745 { 0x00000733, 0x0080 }, /* R1843 - AIF1TX7MIX Input 2 Volume */
746 { 0x00000734, 0x0000 }, /* R1844 - AIF1TX7MIX Input 3 Source */
747 { 0x00000735, 0x0080 }, /* R1845 - AIF1TX7MIX Input 3 Volume */
748 { 0x00000736, 0x0000 }, /* R1846 - AIF1TX7MIX Input 4 Source */
749 { 0x00000737, 0x0080 }, /* R1847 - AIF1TX7MIX Input 4 Volume */
750 { 0x00000738, 0x0000 }, /* R1848 - AIF1TX8MIX Input 1 Source */
751 { 0x00000739, 0x0080 }, /* R1849 - AIF1TX8MIX Input 1 Volume */
752 { 0x0000073A, 0x0000 }, /* R1850 - AIF1TX8MIX Input 2 Source */
753 { 0x0000073B, 0x0080 }, /* R1851 - AIF1TX8MIX Input 2 Volume */
754 { 0x0000073C, 0x0000 }, /* R1852 - AIF1TX8MIX Input 3 Source */
755 { 0x0000073D, 0x0080 }, /* R1853 - AIF1TX8MIX Input 3 Volume */
756 { 0x0000073E, 0x0000 }, /* R1854 - AIF1TX8MIX Input 4 Source */
757 { 0x0000073F, 0x0080 }, /* R1855 - AIF1TX8MIX Input 4 Volume */
758 { 0x00000740, 0x0000 }, /* R1856 - AIF2TX1MIX Input 1 Source */
759 { 0x00000741, 0x0080 }, /* R1857 - AIF2TX1MIX Input 1 Volume */
760 { 0x00000742, 0x0000 }, /* R1858 - AIF2TX1MIX Input 2 Source */
761 { 0x00000743, 0x0080 }, /* R1859 - AIF2TX1MIX Input 2 Volume */
762 { 0x00000744, 0x0000 }, /* R1860 - AIF2TX1MIX Input 3 Source */
763 { 0x00000745, 0x0080 }, /* R1861 - AIF2TX1MIX Input 3 Volume */
764 { 0x00000746, 0x0000 }, /* R1862 - AIF2TX1MIX Input 4 Source */
765 { 0x00000747, 0x0080 }, /* R1863 - AIF2TX1MIX Input 4 Volume */
766 { 0x00000748, 0x0000 }, /* R1864 - AIF2TX2MIX Input 1 Source */
767 { 0x00000749, 0x0080 }, /* R1865 - AIF2TX2MIX Input 1 Volume */
768 { 0x0000074A, 0x0000 }, /* R1866 - AIF2TX2MIX Input 2 Source */
769 { 0x0000074B, 0x0080 }, /* R1867 - AIF2TX2MIX Input 2 Volume */
770 { 0x0000074C, 0x0000 }, /* R1868 - AIF2TX2MIX Input 3 Source */
771 { 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */
772 { 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */
773 { 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */
774 { 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */
775 { 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */
776 { 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */
777 { 0x00000783, 0x0080 }, /* R1923 - AIF3TX1MIX Input 2 Volume */
778 { 0x00000784, 0x0000 }, /* R1924 - AIF3TX1MIX Input 3 Source */
779 { 0x00000785, 0x0080 }, /* R1925 - AIF3TX1MIX Input 3 Volume */
780 { 0x00000786, 0x0000 }, /* R1926 - AIF3TX1MIX Input 4 Source */
781 { 0x00000787, 0x0080 }, /* R1927 - AIF3TX1MIX Input 4 Volume */
782 { 0x00000788, 0x0000 }, /* R1928 - AIF3TX2MIX Input 1 Source */
783 { 0x00000789, 0x0080 }, /* R1929 - AIF3TX2MIX Input 1 Volume */
784 { 0x0000078A, 0x0000 }, /* R1930 - AIF3TX2MIX Input 2 Source */
785 { 0x0000078B, 0x0080 }, /* R1931 - AIF3TX2MIX Input 2 Volume */
786 { 0x0000078C, 0x0000 }, /* R1932 - AIF3TX2MIX Input 3 Source */
787 { 0x0000078D, 0x0080 }, /* R1933 - AIF3TX2MIX Input 3 Volume */
788 { 0x0000078E, 0x0000 }, /* R1934 - AIF3TX2MIX Input 4 Source */
789 { 0x0000078F, 0x0080 }, /* R1935 - AIF3TX2MIX Input 4 Volume */
790 { 0x000007C0, 0x0000 }, /* R1984 - SLIMTX1MIX Input 1 Source */
791 { 0x000007C1, 0x0080 }, /* R1985 - SLIMTX1MIX Input 1 Volume */
792 { 0x000007C2, 0x0000 }, /* R1986 - SLIMTX1MIX Input 2 Source */
793 { 0x000007C3, 0x0080 }, /* R1987 - SLIMTX1MIX Input 2 Volume */
794 { 0x000007C4, 0x0000 }, /* R1988 - SLIMTX1MIX Input 3 Source */
795 { 0x000007C5, 0x0080 }, /* R1989 - SLIMTX1MIX Input 3 Volume */
796 { 0x000007C6, 0x0000 }, /* R1990 - SLIMTX1MIX Input 4 Source */
797 { 0x000007C7, 0x0080 }, /* R1991 - SLIMTX1MIX Input 4 Volume */
798 { 0x000007C8, 0x0000 }, /* R1992 - SLIMTX2MIX Input 1 Source */
799 { 0x000007C9, 0x0080 }, /* R1993 - SLIMTX2MIX Input 1 Volume */
800 { 0x000007CA, 0x0000 }, /* R1994 - SLIMTX2MIX Input 2 Source */
801 { 0x000007CB, 0x0080 }, /* R1995 - SLIMTX2MIX Input 2 Volume */
802 { 0x000007CC, 0x0000 }, /* R1996 - SLIMTX2MIX Input 3 Source */
803 { 0x000007CD, 0x0080 }, /* R1997 - SLIMTX2MIX Input 3 Volume */
804 { 0x000007CE, 0x0000 }, /* R1998 - SLIMTX2MIX Input 4 Source */
805 { 0x000007CF, 0x0080 }, /* R1999 - SLIMTX2MIX Input 4 Volume */
806 { 0x000007D0, 0x0000 }, /* R2000 - SLIMTX3MIX Input 1 Source */
807 { 0x000007D1, 0x0080 }, /* R2001 - SLIMTX3MIX Input 1 Volume */
808 { 0x000007D2, 0x0000 }, /* R2002 - SLIMTX3MIX Input 2 Source */
809 { 0x000007D3, 0x0080 }, /* R2003 - SLIMTX3MIX Input 2 Volume */
810 { 0x000007D4, 0x0000 }, /* R2004 - SLIMTX3MIX Input 3 Source */
811 { 0x000007D5, 0x0080 }, /* R2005 - SLIMTX3MIX Input 3 Volume */
812 { 0x000007D6, 0x0000 }, /* R2006 - SLIMTX3MIX Input 4 Source */
813 { 0x000007D7, 0x0080 }, /* R2007 - SLIMTX3MIX Input 4 Volume */
814 { 0x000007D8, 0x0000 }, /* R2008 - SLIMTX4MIX Input 1 Source */
815 { 0x000007D9, 0x0080 }, /* R2009 - SLIMTX4MIX Input 1 Volume */
816 { 0x000007DA, 0x0000 }, /* R2010 - SLIMTX4MIX Input 2 Source */
817 { 0x000007DB, 0x0080 }, /* R2011 - SLIMTX4MIX Input 2 Volume */
818 { 0x000007DC, 0x0000 }, /* R2012 - SLIMTX4MIX Input 3 Source */
819 { 0x000007DD, 0x0080 }, /* R2013 - SLIMTX4MIX Input 3 Volume */
820 { 0x000007DE, 0x0000 }, /* R2014 - SLIMTX4MIX Input 4 Source */
821 { 0x000007DF, 0x0080 }, /* R2015 - SLIMTX4MIX Input 4 Volume */
822 { 0x000007E0, 0x0000 }, /* R2016 - SLIMTX5MIX Input 1 Source */
823 { 0x000007E1, 0x0080 }, /* R2017 - SLIMTX5MIX Input 1 Volume */
824 { 0x000007E2, 0x0000 }, /* R2018 - SLIMTX5MIX Input 2 Source */
825 { 0x000007E3, 0x0080 }, /* R2019 - SLIMTX5MIX Input 2 Volume */
826 { 0x000007E4, 0x0000 }, /* R2020 - SLIMTX5MIX Input 3 Source */
827 { 0x000007E5, 0x0080 }, /* R2021 - SLIMTX5MIX Input 3 Volume */
828 { 0x000007E6, 0x0000 }, /* R2022 - SLIMTX5MIX Input 4 Source */
829 { 0x000007E7, 0x0080 }, /* R2023 - SLIMTX5MIX Input 4 Volume */
830 { 0x000007E8, 0x0000 }, /* R2024 - SLIMTX6MIX Input 1 Source */
831 { 0x000007E9, 0x0080 }, /* R2025 - SLIMTX6MIX Input 1 Volume */
832 { 0x000007EA, 0x0000 }, /* R2026 - SLIMTX6MIX Input 2 Source */
833 { 0x000007EB, 0x0080 }, /* R2027 - SLIMTX6MIX Input 2 Volume */
834 { 0x000007EC, 0x0000 }, /* R2028 - SLIMTX6MIX Input 3 Source */
835 { 0x000007ED, 0x0080 }, /* R2029 - SLIMTX6MIX Input 3 Volume */
836 { 0x000007EE, 0x0000 }, /* R2030 - SLIMTX6MIX Input 4 Source */
837 { 0x000007EF, 0x0080 }, /* R2031 - SLIMTX6MIX Input 4 Volume */
838 { 0x000007F0, 0x0000 }, /* R2032 - SLIMTX7MIX Input 1 Source */
839 { 0x000007F1, 0x0080 }, /* R2033 - SLIMTX7MIX Input 1 Volume */
840 { 0x000007F2, 0x0000 }, /* R2034 - SLIMTX7MIX Input 2 Source */
841 { 0x000007F3, 0x0080 }, /* R2035 - SLIMTX7MIX Input 2 Volume */
842 { 0x000007F4, 0x0000 }, /* R2036 - SLIMTX7MIX Input 3 Source */
843 { 0x000007F5, 0x0080 }, /* R2037 - SLIMTX7MIX Input 3 Volume */
844 { 0x000007F6, 0x0000 }, /* R2038 - SLIMTX7MIX Input 4 Source */
845 { 0x000007F7, 0x0080 }, /* R2039 - SLIMTX7MIX Input 4 Volume */
846 { 0x000007F8, 0x0000 }, /* R2040 - SLIMTX8MIX Input 1 Source */
847 { 0x000007F9, 0x0080 }, /* R2041 - SLIMTX8MIX Input 1 Volume */
848 { 0x000007FA, 0x0000 }, /* R2042 - SLIMTX8MIX Input 2 Source */
849 { 0x000007FB, 0x0080 }, /* R2043 - SLIMTX8MIX Input 2 Volume */
850 { 0x000007FC, 0x0000 }, /* R2044 - SLIMTX8MIX Input 3 Source */
851 { 0x000007FD, 0x0080 }, /* R2045 - SLIMTX8MIX Input 3 Volume */
852 { 0x000007FE, 0x0000 }, /* R2046 - SLIMTX8MIX Input 4 Source */
853 { 0x000007FF, 0x0080 }, /* R2047 - SLIMTX8MIX Input 4 Volume */
854 { 0x00000880, 0x0000 }, /* R2176 - EQ1MIX Input 1 Source */
855 { 0x00000881, 0x0080 }, /* R2177 - EQ1MIX Input 1 Volume */
856 { 0x00000882, 0x0000 }, /* R2178 - EQ1MIX Input 2 Source */
857 { 0x00000883, 0x0080 }, /* R2179 - EQ1MIX Input 2 Volume */
858 { 0x00000884, 0x0000 }, /* R2180 - EQ1MIX Input 3 Source */
859 { 0x00000885, 0x0080 }, /* R2181 - EQ1MIX Input 3 Volume */
860 { 0x00000886, 0x0000 }, /* R2182 - EQ1MIX Input 4 Source */
861 { 0x00000887, 0x0080 }, /* R2183 - EQ1MIX Input 4 Volume */
862 { 0x00000888, 0x0000 }, /* R2184 - EQ2MIX Input 1 Source */
863 { 0x00000889, 0x0080 }, /* R2185 - EQ2MIX Input 1 Volume */
864 { 0x0000088A, 0x0000 }, /* R2186 - EQ2MIX Input 2 Source */
865 { 0x0000088B, 0x0080 }, /* R2187 - EQ2MIX Input 2 Volume */
866 { 0x0000088C, 0x0000 }, /* R2188 - EQ2MIX Input 3 Source */
867 { 0x0000088D, 0x0080 }, /* R2189 - EQ2MIX Input 3 Volume */
868 { 0x0000088E, 0x0000 }, /* R2190 - EQ2MIX Input 4 Source */
869 { 0x0000088F, 0x0080 }, /* R2191 - EQ2MIX Input 4 Volume */
870 { 0x00000890, 0x0000 }, /* R2192 - EQ3MIX Input 1 Source */
871 { 0x00000891, 0x0080 }, /* R2193 - EQ3MIX Input 1 Volume */
872 { 0x00000892, 0x0000 }, /* R2194 - EQ3MIX Input 2 Source */
873 { 0x00000893, 0x0080 }, /* R2195 - EQ3MIX Input 2 Volume */
874 { 0x00000894, 0x0000 }, /* R2196 - EQ3MIX Input 3 Source */
875 { 0x00000895, 0x0080 }, /* R2197 - EQ3MIX Input 3 Volume */
876 { 0x00000896, 0x0000 }, /* R2198 - EQ3MIX Input 4 Source */
877 { 0x00000897, 0x0080 }, /* R2199 - EQ3MIX Input 4 Volume */
878 { 0x00000898, 0x0000 }, /* R2200 - EQ4MIX Input 1 Source */
879 { 0x00000899, 0x0080 }, /* R2201 - EQ4MIX Input 1 Volume */
880 { 0x0000089A, 0x0000 }, /* R2202 - EQ4MIX Input 2 Source */
881 { 0x0000089B, 0x0080 }, /* R2203 - EQ4MIX Input 2 Volume */
882 { 0x0000089C, 0x0000 }, /* R2204 - EQ4MIX Input 3 Source */
883 { 0x0000089D, 0x0080 }, /* R2205 - EQ4MIX Input 3 Volume */
884 { 0x0000089E, 0x0000 }, /* R2206 - EQ4MIX Input 4 Source */
885 { 0x0000089F, 0x0080 }, /* R2207 - EQ4MIX Input 4 Volume */
886 { 0x000008C0, 0x0000 }, /* R2240 - DRC1LMIX Input 1 Source */
887 { 0x000008C1, 0x0080 }, /* R2241 - DRC1LMIX Input 1 Volume */
888 { 0x000008C2, 0x0000 }, /* R2242 - DRC1LMIX Input 2 Source */
889 { 0x000008C3, 0x0080 }, /* R2243 - DRC1LMIX Input 2 Volume */
890 { 0x000008C4, 0x0000 }, /* R2244 - DRC1LMIX Input 3 Source */
891 { 0x000008C5, 0x0080 }, /* R2245 - DRC1LMIX Input 3 Volume */
892 { 0x000008C6, 0x0000 }, /* R2246 - DRC1LMIX Input 4 Source */
893 { 0x000008C7, 0x0080 }, /* R2247 - DRC1LMIX Input 4 Volume */
894 { 0x000008C8, 0x0000 }, /* R2248 - DRC1RMIX Input 1 Source */
895 { 0x000008C9, 0x0080 }, /* R2249 - DRC1RMIX Input 1 Volume */
896 { 0x000008CA, 0x0000 }, /* R2250 - DRC1RMIX Input 2 Source */
897 { 0x000008CB, 0x0080 }, /* R2251 - DRC1RMIX Input 2 Volume */
898 { 0x000008CC, 0x0000 }, /* R2252 - DRC1RMIX Input 3 Source */
899 { 0x000008CD, 0x0080 }, /* R2253 - DRC1RMIX Input 3 Volume */
900 { 0x000008CE, 0x0000 }, /* R2254 - DRC1RMIX Input 4 Source */
901 { 0x000008CF, 0x0080 }, /* R2255 - DRC1RMIX Input 4 Volume */
902 { 0x000008D0, 0x0000 }, /* R2256 - DRC2LMIX Input 1 Source */
903 { 0x000008D1, 0x0080 }, /* R2257 - DRC2LMIX Input 1 Volume */
904 { 0x000008D2, 0x0000 }, /* R2258 - DRC2LMIX Input 2 Source */
905 { 0x000008D3, 0x0080 }, /* R2259 - DRC2LMIX Input 2 Volume */
906 { 0x000008D4, 0x0000 }, /* R2260 - DRC2LMIX Input 3 Source */
907 { 0x000008D5, 0x0080 }, /* R2261 - DRC2LMIX Input 3 Volume */
908 { 0x000008D6, 0x0000 }, /* R2262 - DRC2LMIX Input 4 Source */
909 { 0x000008D7, 0x0080 }, /* R2263 - DRC2LMIX Input 4 Volume */
910 { 0x000008D8, 0x0000 }, /* R2264 - DRC2RMIX Input 1 Source */
911 { 0x000008D9, 0x0080 }, /* R2265 - DRC2RMIX Input 1 Volume */
912 { 0x000008DA, 0x0000 }, /* R2266 - DRC2RMIX Input 2 Source */
913 { 0x000008DB, 0x0080 }, /* R2267 - DRC2RMIX Input 2 Volume */
914 { 0x000008DC, 0x0000 }, /* R2268 - DRC2RMIX Input 3 Source */
915 { 0x000008DD, 0x0080 }, /* R2269 - DRC2RMIX Input 3 Volume */
916 { 0x000008DE, 0x0000 }, /* R2270 - DRC2RMIX Input 4 Source */
917 { 0x000008DF, 0x0080 }, /* R2271 - DRC2RMIX Input 4 Volume */
918 { 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */
919 { 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */
920 { 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */
921 { 0x00000903, 0x0080 }, /* R2307 - HPLP1MIX Input 2 Volume */
922 { 0x00000904, 0x0000 }, /* R2308 - HPLP1MIX Input 3 Source */
923 { 0x00000905, 0x0080 }, /* R2309 - HPLP1MIX Input 3 Volume */
924 { 0x00000906, 0x0000 }, /* R2310 - HPLP1MIX Input 4 Source */
925 { 0x00000907, 0x0080 }, /* R2311 - HPLP1MIX Input 4 Volume */
926 { 0x00000908, 0x0000 }, /* R2312 - HPLP2MIX Input 1 Source */
927 { 0x00000909, 0x0080 }, /* R2313 - HPLP2MIX Input 1 Volume */
928 { 0x0000090A, 0x0000 }, /* R2314 - HPLP2MIX Input 2 Source */
929 { 0x0000090B, 0x0080 }, /* R2315 - HPLP2MIX Input 2 Volume */
930 { 0x0000090C, 0x0000 }, /* R2316 - HPLP2MIX Input 3 Source */
931 { 0x0000090D, 0x0080 }, /* R2317 - HPLP2MIX Input 3 Volume */
932 { 0x0000090E, 0x0000 }, /* R2318 - HPLP2MIX Input 4 Source */
933 { 0x0000090F, 0x0080 }, /* R2319 - HPLP2MIX Input 4 Volume */
934 { 0x00000910, 0x0000 }, /* R2320 - HPLP3MIX Input 1 Source */
935 { 0x00000911, 0x0080 }, /* R2321 - HPLP3MIX Input 1 Volume */
936 { 0x00000912, 0x0000 }, /* R2322 - HPLP3MIX Input 2 Source */
937 { 0x00000913, 0x0080 }, /* R2323 - HPLP3MIX Input 2 Volume */
938 { 0x00000914, 0x0000 }, /* R2324 - HPLP3MIX Input 3 Source */
939 { 0x00000915, 0x0080 }, /* R2325 - HPLP3MIX Input 3 Volume */
940 { 0x00000916, 0x0000 }, /* R2326 - HPLP3MIX Input 4 Source */
941 { 0x00000917, 0x0080 }, /* R2327 - HPLP3MIX Input 4 Volume */
942 { 0x00000918, 0x0000 }, /* R2328 - HPLP4MIX Input 1 Source */
943 { 0x00000919, 0x0080 }, /* R2329 - HPLP4MIX Input 1 Volume */
944 { 0x0000091A, 0x0000 }, /* R2330 - HPLP4MIX Input 2 Source */
945 { 0x0000091B, 0x0080 }, /* R2331 - HPLP4MIX Input 2 Volume */
946 { 0x0000091C, 0x0000 }, /* R2332 - HPLP4MIX Input 3 Source */
947 { 0x0000091D, 0x0080 }, /* R2333 - HPLP4MIX Input 3 Volume */
948 { 0x0000091E, 0x0000 }, /* R2334 - HPLP4MIX Input 4 Source */
949 { 0x0000091F, 0x0080 }, /* R2335 - HPLP4MIX Input 4 Volume */
950 { 0x00000940, 0x0000 }, /* R2368 - DSP1LMIX Input 1 Source */
951 { 0x00000941, 0x0080 }, /* R2369 - DSP1LMIX Input 1 Volume */
952 { 0x00000942, 0x0000 }, /* R2370 - DSP1LMIX Input 2 Source */
953 { 0x00000943, 0x0080 }, /* R2371 - DSP1LMIX Input 2 Volume */
954 { 0x00000944, 0x0000 }, /* R2372 - DSP1LMIX Input 3 Source */
955 { 0x00000945, 0x0080 }, /* R2373 - DSP1LMIX Input 3 Volume */
956 { 0x00000946, 0x0000 }, /* R2374 - DSP1LMIX Input 4 Source */
957 { 0x00000947, 0x0080 }, /* R2375 - DSP1LMIX Input 4 Volume */
958 { 0x00000948, 0x0000 }, /* R2376 - DSP1RMIX Input 1 Source */
959 { 0x00000949, 0x0080 }, /* R2377 - DSP1RMIX Input 1 Volume */
960 { 0x0000094A, 0x0000 }, /* R2378 - DSP1RMIX Input 2 Source */
961 { 0x0000094B, 0x0080 }, /* R2379 - DSP1RMIX Input 2 Volume */
962 { 0x0000094C, 0x0000 }, /* R2380 - DSP1RMIX Input 3 Source */
963 { 0x0000094D, 0x0080 }, /* R2381 - DSP1RMIX Input 3 Volume */
964 { 0x0000094E, 0x0000 }, /* R2382 - DSP1RMIX Input 4 Source */
965 { 0x0000094F, 0x0080 }, /* R2383 - DSP1RMIX Input 4 Volume */
966 { 0x00000950, 0x0000 }, /* R2384 - DSP1AUX1MIX Input 1 Source */
967 { 0x00000958, 0x0000 }, /* R2392 - DSP1AUX2MIX Input 1 Source */
968 { 0x00000960, 0x0000 }, /* R2400 - DSP1AUX3MIX Input 1 Source */
969 { 0x00000968, 0x0000 }, /* R2408 - DSP1AUX4MIX Input 1 Source */
970 { 0x00000970, 0x0000 }, /* R2416 - DSP1AUX5MIX Input 1 Source */
971 { 0x00000978, 0x0000 }, /* R2424 - DSP1AUX6MIX Input 1 Source */
972 { 0x00000980, 0x0000 }, /* R2432 - DSP2LMIX Input 1 Source */
973 { 0x00000981, 0x0080 }, /* R2433 - DSP2LMIX Input 1 Volume */
974 { 0x00000982, 0x0000 }, /* R2434 - DSP2LMIX Input 2 Source */
975 { 0x00000983, 0x0080 }, /* R2435 - DSP2LMIX Input 2 Volume */
976 { 0x00000984, 0x0000 }, /* R2436 - DSP2LMIX Input 3 Source */
977 { 0x00000985, 0x0080 }, /* R2437 - DSP2LMIX Input 3 Volume */
978 { 0x00000986, 0x0000 }, /* R2438 - DSP2LMIX Input 4 Source */
979 { 0x00000987, 0x0080 }, /* R2439 - DSP2LMIX Input 4 Volume */
980 { 0x00000988, 0x0000 }, /* R2440 - DSP2RMIX Input 1 Source */
981 { 0x00000989, 0x0080 }, /* R2441 - DSP2RMIX Input 1 Volume */
982 { 0x0000098A, 0x0000 }, /* R2442 - DSP2RMIX Input 2 Source */
983 { 0x0000098B, 0x0080 }, /* R2443 - DSP2RMIX Input 2 Volume */
984 { 0x0000098C, 0x0000 }, /* R2444 - DSP2RMIX Input 3 Source */
985 { 0x0000098D, 0x0080 }, /* R2445 - DSP2RMIX Input 3 Volume */
986 { 0x0000098E, 0x0000 }, /* R2446 - DSP2RMIX Input 4 Source */
987 { 0x0000098F, 0x0080 }, /* R2447 - DSP2RMIX Input 4 Volume */
988 { 0x00000990, 0x0000 }, /* R2448 - DSP2AUX1MIX Input 1 Source */
989 { 0x00000998, 0x0000 }, /* R2456 - DSP2AUX2MIX Input 1 Source */
990 { 0x000009A0, 0x0000 }, /* R2464 - DSP2AUX3MIX Input 1 Source */
991 { 0x000009A8, 0x0000 }, /* R2472 - DSP2AUX4MIX Input 1 Source */
992 { 0x000009B0, 0x0000 }, /* R2480 - DSP2AUX5MIX Input 1 Source */
993 { 0x000009B8, 0x0000 }, /* R2488 - DSP2AUX6MIX Input 1 Source */
994 { 0x000009C0, 0x0000 }, /* R2496 - DSP3LMIX Input 1 Source */
995 { 0x000009C1, 0x0080 }, /* R2497 - DSP3LMIX Input 1 Volume */
996 { 0x000009C2, 0x0000 }, /* R2498 - DSP3LMIX Input 2 Source */
997 { 0x000009C3, 0x0080 }, /* R2499 - DSP3LMIX Input 2 Volume */
998 { 0x000009C4, 0x0000 }, /* R2500 - DSP3LMIX Input 3 Source */
999 { 0x000009C5, 0x0080 }, /* R2501 - DSP3LMIX Input 3 Volume */
1000 { 0x000009C6, 0x0000 }, /* R2502 - DSP3LMIX Input 4 Source */
1001 { 0x000009C7, 0x0080 }, /* R2503 - DSP3LMIX Input 4 Volume */
1002 { 0x000009C8, 0x0000 }, /* R2504 - DSP3RMIX Input 1 Source */
1003 { 0x000009C9, 0x0080 }, /* R2505 - DSP3RMIX Input 1 Volume */
1004 { 0x000009CA, 0x0000 }, /* R2506 - DSP3RMIX Input 2 Source */
1005 { 0x000009CB, 0x0080 }, /* R2507 - DSP3RMIX Input 2 Volume */
1006 { 0x000009CC, 0x0000 }, /* R2508 - DSP3RMIX Input 3 Source */
1007 { 0x000009CD, 0x0080 }, /* R2509 - DSP3RMIX Input 3 Volume */
1008 { 0x000009CE, 0x0000 }, /* R2510 - DSP3RMIX Input 4 Source */
1009 { 0x000009CF, 0x0080 }, /* R2511 - DSP3RMIX Input 4 Volume */
1010 { 0x000009D0, 0x0000 }, /* R2512 - DSP3AUX1MIX Input 1 Source */
1011 { 0x000009D8, 0x0000 }, /* R2520 - DSP3AUX2MIX Input 1 Source */
1012 { 0x000009E0, 0x0000 }, /* R2528 - DSP3AUX3MIX Input 1 Source */
1013 { 0x000009E8, 0x0000 }, /* R2536 - DSP3AUX4MIX Input 1 Source */
1014 { 0x000009F0, 0x0000 }, /* R2544 - DSP3AUX5MIX Input 1 Source */
1015 { 0x000009F8, 0x0000 }, /* R2552 - DSP3AUX6MIX Input 1 Source */
1016 { 0x00000A00, 0x0000 }, /* R2560 - DSP4LMIX Input 1 Source */
1017 { 0x00000A01, 0x0080 }, /* R2561 - DSP4LMIX Input 1 Volume */
1018 { 0x00000A02, 0x0000 }, /* R2562 - DSP4LMIX Input 2 Source */
1019 { 0x00000A03, 0x0080 }, /* R2563 - DSP4LMIX Input 2 Volume */
1020 { 0x00000A04, 0x0000 }, /* R2564 - DSP4LMIX Input 3 Source */
1021 { 0x00000A05, 0x0080 }, /* R2565 - DSP4LMIX Input 3 Volume */
1022 { 0x00000A06, 0x0000 }, /* R2566 - DSP4LMIX Input 4 Source */
1023 { 0x00000A07, 0x0080 }, /* R2567 - DSP4LMIX Input 4 Volume */
1024 { 0x00000A08, 0x0000 }, /* R2568 - DSP4RMIX Input 1 Source */
1025 { 0x00000A09, 0x0080 }, /* R2569 - DSP4RMIX Input 1 Volume */
1026 { 0x00000A0A, 0x0000 }, /* R2570 - DSP4RMIX Input 2 Source */
1027 { 0x00000A0B, 0x0080 }, /* R2571 - DSP4RMIX Input 2 Volume */
1028 { 0x00000A0C, 0x0000 }, /* R2572 - DSP4RMIX Input 3 Source */
1029 { 0x00000A0D, 0x0080 }, /* R2573 - DSP4RMIX Input 3 Volume */
1030 { 0x00000A0E, 0x0000 }, /* R2574 - DSP4RMIX Input 4 Source */
1031 { 0x00000A0F, 0x0080 }, /* R2575 - DSP4RMIX Input 4 Volume */
1032 { 0x00000A10, 0x0000 }, /* R2576 - DSP4AUX1MIX Input 1 Source */
1033 { 0x00000A18, 0x0000 }, /* R2584 - DSP4AUX2MIX Input 1 Source */
1034 { 0x00000A20, 0x0000 }, /* R2592 - DSP4AUX3MIX Input 1 Source */
1035 { 0x00000A28, 0x0000 }, /* R2600 - DSP4AUX4MIX Input 1 Source */
1036 { 0x00000A30, 0x0000 }, /* R2608 - DSP4AUX5MIX Input 1 Source */
1037 { 0x00000A38, 0x0000 }, /* R2616 - DSP4AUX6MIX Input 1 Source */
1038 { 0x00000A80, 0x0000 }, /* R2688 - ASRC1LMIX Input 1 Source */
1039 { 0x00000A88, 0x0000 }, /* R2696 - ASRC1RMIX Input 1 Source */
1040 { 0x00000A90, 0x0000 }, /* R2704 - ASRC2LMIX Input 1 Source */
1041 { 0x00000A98, 0x0000 }, /* R2712 - ASRC2RMIX Input 1 Source */
1042 { 0x00000B00, 0x0000 }, /* R2816 - ISRC1DEC1MIX Input 1 Source */
1043 { 0x00000B08, 0x0000 }, /* R2824 - ISRC1DEC2MIX Input 1 Source */
1044 { 0x00000B10, 0x0000 }, /* R2832 - ISRC1DEC3MIX Input 1 Source */
1045 { 0x00000B18, 0x0000 }, /* R2840 - ISRC1DEC4MIX Input 1 Source */
1046 { 0x00000B20, 0x0000 }, /* R2848 - ISRC1INT1MIX Input 1 Source */
1047 { 0x00000B28, 0x0000 }, /* R2856 - ISRC1INT2MIX Input 1 Source */
1048 { 0x00000B30, 0x0000 }, /* R2864 - ISRC1INT3MIX Input 1 Source */
1049 { 0x00000B38, 0x0000 }, /* R2872 - ISRC1INT4MIX Input 1 Source */
1050 { 0x00000B40, 0x0000 }, /* R2880 - ISRC2DEC1MIX Input 1 Source */
1051 { 0x00000B48, 0x0000 }, /* R2888 - ISRC2DEC2MIX Input 1 Source */
1052 { 0x00000B50, 0x0000 }, /* R2896 - ISRC2DEC3MIX Input 1 Source */
1053 { 0x00000B58, 0x0000 }, /* R2904 - ISRC2DEC4MIX Input 1 Source */
1054 { 0x00000B60, 0x0000 }, /* R2912 - ISRC2INT1MIX Input 1 Source */
1055 { 0x00000B68, 0x0000 }, /* R2920 - ISRC2INT2MIX Input 1 Source */
1056 { 0x00000B70, 0x0000 }, /* R2928 - ISRC2INT3MIX Input 1 Source */
1057 { 0x00000B78, 0x0000 }, /* R2936 - ISRC2INT4MIX Input 1 Source */
1058 { 0x00000B80, 0x0000 }, /* R2944 - ISRC3DEC1MIX Input 1 Source */
1059 { 0x00000B88, 0x0000 }, /* R2952 - ISRC3DEC2MIX Input 1 Source */
1060 { 0x00000B90, 0x0000 }, /* R2960 - ISRC3DEC3MIX Input 1 Source */
1061 { 0x00000B98, 0x0000 }, /* R2968 - ISRC3DEC4MIX Input 1 Source */
1062 { 0x00000BA0, 0x0000 }, /* R2976 - ISRC3INT1MIX Input 1 Source */
1063 { 0x00000BA8, 0x0000 }, /* R2984 - ISRC3INT2MIX Input 1 Source */
1064 { 0x00000BB0, 0x0000 }, /* R2992 - ISRC3INT3MIX Input 1 Source */
1065 { 0x00000BB8, 0x0000 }, /* R3000 - ISRC3INT4MIX Input 1 Source */
1066 { 0x00000C00, 0xA101 }, /* R3072 - GPIO1 CTRL */
1067 { 0x00000C01, 0xA101 }, /* R3073 - GPIO2 CTRL */
1068 { 0x00000C02, 0xA101 }, /* R3074 - GPIO3 CTRL */
1069 { 0x00000C03, 0xA101 }, /* R3075 - GPIO4 CTRL */
1070 { 0x00000C04, 0xA101 }, /* R3076 - GPIO5 CTRL */
1071 { 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */
1072 { 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */
1073 { 0x00000C20, 0x8002 }, /* R3104 - Misc Pad Ctrl 1 */
1074 { 0x00000C21, 0x8001 }, /* R3105 - Misc Pad Ctrl 2 */
1075 { 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */
1076 { 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */
1077 { 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */
1078 { 0x00000C25, 0x0000 }, /* R3109 - Misc Pad Ctrl 6 */
1079 { 0x00000C30, 0x8282 }, /* R3120 - Misc Pad Ctrl 7 */
1080 { 0x00000C31, 0x0082 }, /* R3121 - Misc Pad Ctrl 8 */
1081 { 0x00000C32, 0x8282 }, /* R3122 - Misc Pad Ctrl 9 */
1082 { 0x00000C33, 0x8282 }, /* R3123 - Misc Pad Ctrl 10 */
1083 { 0x00000C34, 0x8282 }, /* R3124 - Misc Pad Ctrl 11 */
1084 { 0x00000C35, 0x8282 }, /* R3125 - Misc Pad Ctrl 12 */
1085 { 0x00000C36, 0x8282 }, /* R3126 - Misc Pad Ctrl 13 */
1086 { 0x00000C37, 0x8282 }, /* R3127 - Misc Pad Ctrl 14 */
1087 { 0x00000C38, 0x8282 }, /* R3128 - Misc Pad Ctrl 15 */
1088 { 0x00000C39, 0x8282 }, /* R3129 - Misc Pad Ctrl 16 */
1089 { 0x00000C3A, 0x8282 }, /* R3130 - Misc Pad Ctrl 17 */
1090 { 0x00000C3B, 0x8282 }, /* R3131 - Misc Pad Ctrl 18 */
1091 { 0x00000D08, 0xFFFF }, /* R3336 - Interrupt Status 1 Mask */
1092 { 0x00000D09, 0xFFFF }, /* R3337 - Interrupt Status 2 Mask */
1093 { 0x00000D0A, 0xFFFF }, /* R3338 - Interrupt Status 3 Mask */
1094 { 0x00000D0B, 0xFFFF }, /* R3339 - Interrupt Status 4 Mask */
1095 { 0x00000D0C, 0xFEFF }, /* R3340 - Interrupt Status 5 Mask */
1096 { 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */
1097 { 0x00000D18, 0xFFFF }, /* R3352 - IRQ2 Status 1 Mask */
1098 { 0x00000D19, 0xFFFF }, /* R3353 - IRQ2 Status 2 Mask */
1099 { 0x00000D1A, 0xFFFF }, /* R3354 - IRQ2 Status 3 Mask */
1100 { 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */
1101 { 0x00000D1C, 0xFFFF }, /* R3356 - IRQ2 Status 5 Mask */
1102 { 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */
1103 { 0x00000D50, 0x0000 }, /* R3408 - AOD wkup and trig */
1104 { 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */
1105 { 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */
1106 { 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */
1107 { 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */
1108 { 0x00000E01, 0x0000 }, /* R3585 - FX_Ctrl2 */
1109 { 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */
1110 { 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */
1111 { 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */
1112 { 0x00000E13, 0x03FE }, /* R3603 - EQ1_4 */
1113 { 0x00000E14, 0x00E0 }, /* R3604 - EQ1_5 */
1114 { 0x00000E15, 0x1EC4 }, /* R3605 - EQ1_6 */
1115 { 0x00000E16, 0xF136 }, /* R3606 - EQ1_7 */
1116 { 0x00000E17, 0x0409 }, /* R3607 - EQ1_8 */
1117 { 0x00000E18, 0x04CC }, /* R3608 - EQ1_9 */
1118 { 0x00000E19, 0x1C9B }, /* R3609 - EQ1_10 */
1119 { 0x00000E1A, 0xF337 }, /* R3610 - EQ1_11 */
1120 { 0x00000E1B, 0x040B }, /* R3611 - EQ1_12 */
1121 { 0x00000E1C, 0x0CBB }, /* R3612 - EQ1_13 */
1122 { 0x00000E1D, 0x16F8 }, /* R3613 - EQ1_14 */
1123 { 0x00000E1E, 0xF7D9 }, /* R3614 - EQ1_15 */
1124 { 0x00000E1F, 0x040A }, /* R3615 - EQ1_16 */
1125 { 0x00000E20, 0x1F14 }, /* R3616 - EQ1_17 */
1126 { 0x00000E21, 0x058C }, /* R3617 - EQ1_18 */
1127 { 0x00000E22, 0x0563 }, /* R3618 - EQ1_19 */
1128 { 0x00000E23, 0x4000 }, /* R3619 - EQ1_20 */
1129 { 0x00000E24, 0x0B75 }, /* R3620 - EQ1_21 */
1130 { 0x00000E26, 0x6318 }, /* R3622 - EQ2_1 */
1131 { 0x00000E27, 0x6300 }, /* R3623 - EQ2_2 */
1132 { 0x00000E28, 0x0FC8 }, /* R3624 - EQ2_3 */
1133 { 0x00000E29, 0x03FE }, /* R3625 - EQ2_4 */
1134 { 0x00000E2A, 0x00E0 }, /* R3626 - EQ2_5 */
1135 { 0x00000E2B, 0x1EC4 }, /* R3627 - EQ2_6 */
1136 { 0x00000E2C, 0xF136 }, /* R3628 - EQ2_7 */
1137 { 0x00000E2D, 0x0409 }, /* R3629 - EQ2_8 */
1138 { 0x00000E2E, 0x04CC }, /* R3630 - EQ2_9 */
1139 { 0x00000E2F, 0x1C9B }, /* R3631 - EQ2_10 */
1140 { 0x00000E30, 0xF337 }, /* R3632 - EQ2_11 */
1141 { 0x00000E31, 0x040B }, /* R3633 - EQ2_12 */
1142 { 0x00000E32, 0x0CBB }, /* R3634 - EQ2_13 */
1143 { 0x00000E33, 0x16F8 }, /* R3635 - EQ2_14 */
1144 { 0x00000E34, 0xF7D9 }, /* R3636 - EQ2_15 */
1145 { 0x00000E35, 0x040A }, /* R3637 - EQ2_16 */
1146 { 0x00000E36, 0x1F14 }, /* R3638 - EQ2_17 */
1147 { 0x00000E37, 0x058C }, /* R3639 - EQ2_18 */
1148 { 0x00000E38, 0x0563 }, /* R3640 - EQ2_19 */
1149 { 0x00000E39, 0x4000 }, /* R3641 - EQ2_20 */
1150 { 0x00000E3A, 0x0B75 }, /* R3642 - EQ2_21 */
1151 { 0x00000E3C, 0x6318 }, /* R3644 - EQ3_1 */
1152 { 0x00000E3D, 0x6300 }, /* R3645 - EQ3_2 */
1153 { 0x00000E3E, 0x0FC8 }, /* R3646 - EQ3_3 */
1154 { 0x00000E3F, 0x03FE }, /* R3647 - EQ3_4 */
1155 { 0x00000E40, 0x00E0 }, /* R3648 - EQ3_5 */
1156 { 0x00000E41, 0x1EC4 }, /* R3649 - EQ3_6 */
1157 { 0x00000E42, 0xF136 }, /* R3650 - EQ3_7 */
1158 { 0x00000E43, 0x0409 }, /* R3651 - EQ3_8 */
1159 { 0x00000E44, 0x04CC }, /* R3652 - EQ3_9 */
1160 { 0x00000E45, 0x1C9B }, /* R3653 - EQ3_10 */
1161 { 0x00000E46, 0xF337 }, /* R3654 - EQ3_11 */
1162 { 0x00000E47, 0x040B }, /* R3655 - EQ3_12 */
1163 { 0x00000E48, 0x0CBB }, /* R3656 - EQ3_13 */
1164 { 0x00000E49, 0x16F8 }, /* R3657 - EQ3_14 */
1165 { 0x00000E4A, 0xF7D9 }, /* R3658 - EQ3_15 */
1166 { 0x00000E4B, 0x040A }, /* R3659 - EQ3_16 */
1167 { 0x00000E4C, 0x1F14 }, /* R3660 - EQ3_17 */
1168 { 0x00000E4D, 0x058C }, /* R3661 - EQ3_18 */
1169 { 0x00000E4E, 0x0563 }, /* R3662 - EQ3_19 */
1170 { 0x00000E4F, 0x4000 }, /* R3663 - EQ3_20 */
1171 { 0x00000E50, 0x0B75 }, /* R3664 - EQ3_21 */
1172 { 0x00000E52, 0x6318 }, /* R3666 - EQ4_1 */
1173 { 0x00000E53, 0x6300 }, /* R3667 - EQ4_2 */
1174 { 0x00000E54, 0x0FC8 }, /* R3668 - EQ4_3 */
1175 { 0x00000E55, 0x03FE }, /* R3669 - EQ4_4 */
1176 { 0x00000E56, 0x00E0 }, /* R3670 - EQ4_5 */
1177 { 0x00000E57, 0x1EC4 }, /* R3671 - EQ4_6 */
1178 { 0x00000E58, 0xF136 }, /* R3672 - EQ4_7 */
1179 { 0x00000E59, 0x0409 }, /* R3673 - EQ4_8 */
1180 { 0x00000E5A, 0x04CC }, /* R3674 - EQ4_9 */
1181 { 0x00000E5B, 0x1C9B }, /* R3675 - EQ4_10 */
1182 { 0x00000E5C, 0xF337 }, /* R3676 - EQ4_11 */
1183 { 0x00000E5D, 0x040B }, /* R3677 - EQ4_12 */
1184 { 0x00000E5E, 0x0CBB }, /* R3678 - EQ4_13 */
1185 { 0x00000E5F, 0x16F8 }, /* R3679 - EQ4_14 */
1186 { 0x00000E60, 0xF7D9 }, /* R3680 - EQ4_15 */
1187 { 0x00000E61, 0x040A }, /* R3681 - EQ4_16 */
1188 { 0x00000E62, 0x1F14 }, /* R3682 - EQ4_17 */
1189 { 0x00000E63, 0x058C }, /* R3683 - EQ4_18 */
1190 { 0x00000E64, 0x0563 }, /* R3684 - EQ4_19 */
1191 { 0x00000E65, 0x4000 }, /* R3685 - EQ4_20 */
1192 { 0x00000E66, 0x0B75 }, /* R3686 - EQ4_21 */
1193 { 0x00000E80, 0x0018 }, /* R3712 - DRC1 ctrl1 */
1194 { 0x00000E81, 0x0933 }, /* R3713 - DRC1 ctrl2 */
1195 { 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */
1196 { 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */
1197 { 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */
1198 { 0x00000E89, 0x0018 }, /* R3721 - DRC2 ctrl1 */
1199 { 0x00000E8A, 0x0933 }, /* R3722 - DRC2 ctrl2 */
1200 { 0x00000E8B, 0x0018 }, /* R3723 - DRC2 ctrl3 */
1201 { 0x00000E8C, 0x0000 }, /* R3724 - DRC2 ctrl4 */
1202 { 0x00000E8D, 0x0000 }, /* R3725 - DRC2 ctrl5 */
1203 { 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */
1204 { 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */
1205 { 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */
1206 { 0x00000EC5, 0x0000 }, /* R3781 - HPLPF2_2 */
1207 { 0x00000EC8, 0x0000 }, /* R3784 - HPLPF3_1 */
1208 { 0x00000EC9, 0x0000 }, /* R3785 - HPLPF3_2 */
1209 { 0x00000ECC, 0x0000 }, /* R3788 - HPLPF4_1 */
1210 { 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
1211 { 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */
1212 { 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */
1213 { 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */
1214 { 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */
1215 { 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */
1216 { 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */
1217 { 0x00000EF4, 0x0000 }, /* R3828 - ISRC 2 CTRL 2 */
1218 { 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */
1219 { 0x00000EF6, 0x0000 }, /* R3830 - ISRC 3 CTRL 1 */
1220 { 0x00000EF7, 0x0000 }, /* R3831 - ISRC 3 CTRL 2 */
1221 { 0x00000EF8, 0x0000 }, /* R3832 - ISRC 3 CTRL 3 */
1222 { 0x00000F00, 0x0000 }, /* R3840 - Clock Control */
1223 { 0x00000F01, 0x0000 }, /* R3841 - ANC_SRC */
1224 { 0x00001100, 0x0010 }, /* R4352 - DSP1 Control 1 */
1225 { 0x00001101, 0x0000 }, /* R4353 - DSP1 Clocking 1 */
1226 { 0x00001200, 0x0010 }, /* R4608 - DSP2 Control 1 */
1227 { 0x00001201, 0x0000 }, /* R4609 - DSP2 Clocking 1 */
1228 { 0x00001300, 0x0010 }, /* R4864 - DSP3 Control 1 */
1229 { 0x00001301, 0x0000 }, /* R4865 - DSP3 Clocking 1 */
1230 { 0x00001400, 0x0010 }, /* R5120 - DSP4 Control 1 */
1231 { 0x00001401, 0x0000 }, /* R5121 - DSP4 Clocking 1 */
1232 { 0x00001404, 0x0000 }, /* R5124 - DSP4 Status 1 */
1233};
1234
1235static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1236{
1237 switch (reg) {
1238 case ARIZONA_SOFTWARE_RESET:
1239 case ARIZONA_DEVICE_REVISION:
1240 case ARIZONA_CTRL_IF_SPI_CFG_1:
1241 case ARIZONA_CTRL_IF_I2C1_CFG_1:
1242 case ARIZONA_CTRL_IF_I2C2_CFG_1:
1243 case ARIZONA_CTRL_IF_I2C1_CFG_2:
1244 case ARIZONA_CTRL_IF_I2C2_CFG_2:
1245 case ARIZONA_WRITE_SEQUENCER_CTRL_0:
1246 case ARIZONA_WRITE_SEQUENCER_CTRL_1:
1247 case ARIZONA_WRITE_SEQUENCER_CTRL_2:
1248 case ARIZONA_TONE_GENERATOR_1:
1249 case ARIZONA_TONE_GENERATOR_2:
1250 case ARIZONA_TONE_GENERATOR_3:
1251 case ARIZONA_TONE_GENERATOR_4:
1252 case ARIZONA_TONE_GENERATOR_5:
1253 case ARIZONA_PWM_DRIVE_1:
1254 case ARIZONA_PWM_DRIVE_2:
1255 case ARIZONA_PWM_DRIVE_3:
1256 case ARIZONA_WAKE_CONTROL:
1257 case ARIZONA_SEQUENCE_CONTROL:
1258 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1:
1259 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2:
1260 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3:
1261 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4:
1262 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1:
1263 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2:
1264 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3:
1265 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4:
1266 case ARIZONA_COMFORT_NOISE_GENERATOR:
1267 case ARIZONA_HAPTICS_CONTROL_1:
1268 case ARIZONA_HAPTICS_CONTROL_2:
1269 case ARIZONA_HAPTICS_PHASE_1_INTENSITY:
1270 case ARIZONA_HAPTICS_PHASE_1_DURATION:
1271 case ARIZONA_HAPTICS_PHASE_2_INTENSITY:
1272 case ARIZONA_HAPTICS_PHASE_2_DURATION:
1273 case ARIZONA_HAPTICS_PHASE_3_INTENSITY:
1274 case ARIZONA_HAPTICS_PHASE_3_DURATION:
1275 case ARIZONA_HAPTICS_STATUS:
1276 case ARIZONA_CLOCK_32K_1:
1277 case ARIZONA_SYSTEM_CLOCK_1:
1278 case ARIZONA_SAMPLE_RATE_1:
1279 case ARIZONA_SAMPLE_RATE_2:
1280 case ARIZONA_SAMPLE_RATE_3:
1281 case ARIZONA_SAMPLE_RATE_1_STATUS:
1282 case ARIZONA_SAMPLE_RATE_2_STATUS:
1283 case ARIZONA_SAMPLE_RATE_3_STATUS:
1284 case ARIZONA_ASYNC_CLOCK_1:
1285 case ARIZONA_ASYNC_SAMPLE_RATE_1:
1286 case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
1287 case ARIZONA_OUTPUT_SYSTEM_CLOCK:
1288 case ARIZONA_OUTPUT_ASYNC_CLOCK:
1289 case ARIZONA_RATE_ESTIMATOR_1:
1290 case ARIZONA_RATE_ESTIMATOR_2:
1291 case ARIZONA_RATE_ESTIMATOR_3:
1292 case ARIZONA_RATE_ESTIMATOR_4:
1293 case ARIZONA_RATE_ESTIMATOR_5:
1294 case ARIZONA_FLL1_CONTROL_1:
1295 case ARIZONA_FLL1_CONTROL_2:
1296 case ARIZONA_FLL1_CONTROL_3:
1297 case ARIZONA_FLL1_CONTROL_4:
1298 case ARIZONA_FLL1_CONTROL_5:
1299 case ARIZONA_FLL1_CONTROL_6:
1300 case ARIZONA_FLL1_LOOP_FILTER_TEST_1:
1301 case ARIZONA_FLL1_NCO_TEST_0:
1302 case ARIZONA_FLL1_SYNCHRONISER_1:
1303 case ARIZONA_FLL1_SYNCHRONISER_2:
1304 case ARIZONA_FLL1_SYNCHRONISER_3:
1305 case ARIZONA_FLL1_SYNCHRONISER_4:
1306 case ARIZONA_FLL1_SYNCHRONISER_5:
1307 case ARIZONA_FLL1_SYNCHRONISER_6:
1308 case ARIZONA_FLL1_SPREAD_SPECTRUM:
1309 case ARIZONA_FLL1_GPIO_CLOCK:
1310 case ARIZONA_FLL2_CONTROL_1:
1311 case ARIZONA_FLL2_CONTROL_2:
1312 case ARIZONA_FLL2_CONTROL_3:
1313 case ARIZONA_FLL2_CONTROL_4:
1314 case ARIZONA_FLL2_CONTROL_5:
1315 case ARIZONA_FLL2_CONTROL_6:
1316 case ARIZONA_FLL2_LOOP_FILTER_TEST_1:
1317 case ARIZONA_FLL2_NCO_TEST_0:
1318 case ARIZONA_FLL2_SYNCHRONISER_1:
1319 case ARIZONA_FLL2_SYNCHRONISER_2:
1320 case ARIZONA_FLL2_SYNCHRONISER_3:
1321 case ARIZONA_FLL2_SYNCHRONISER_4:
1322 case ARIZONA_FLL2_SYNCHRONISER_5:
1323 case ARIZONA_FLL2_SYNCHRONISER_6:
1324 case ARIZONA_FLL2_SPREAD_SPECTRUM:
1325 case ARIZONA_FLL2_GPIO_CLOCK:
1326 case ARIZONA_MIC_CHARGE_PUMP_1:
1327 case ARIZONA_LDO1_CONTROL_1:
1328 case ARIZONA_LDO2_CONTROL_1:
1329 case ARIZONA_MIC_BIAS_CTRL_1:
1330 case ARIZONA_MIC_BIAS_CTRL_2:
1331 case ARIZONA_MIC_BIAS_CTRL_3:
1332 case ARIZONA_ACCESSORY_DETECT_MODE_1:
1333 case ARIZONA_HEADPHONE_DETECT_1:
1334 case ARIZONA_HEADPHONE_DETECT_2:
1335 case ARIZONA_MIC_DETECT_1:
1336 case ARIZONA_MIC_DETECT_2:
1337 case ARIZONA_MIC_DETECT_3:
1338 case ARIZONA_MIC_NOISE_MIX_CONTROL_1:
1339 case ARIZONA_JACK_DETECT_ANALOGUE:
1340 case ARIZONA_INPUT_ENABLES:
1341 case ARIZONA_INPUT_ENABLES_STATUS:
1342 case ARIZONA_INPUT_RATE:
1343 case ARIZONA_INPUT_VOLUME_RAMP:
1344 case ARIZONA_IN1L_CONTROL:
1345 case ARIZONA_ADC_DIGITAL_VOLUME_1L:
1346 case ARIZONA_DMIC1L_CONTROL:
1347 case ARIZONA_IN1R_CONTROL:
1348 case ARIZONA_ADC_DIGITAL_VOLUME_1R:
1349 case ARIZONA_DMIC1R_CONTROL:
1350 case ARIZONA_IN2L_CONTROL:
1351 case ARIZONA_ADC_DIGITAL_VOLUME_2L:
1352 case ARIZONA_DMIC2L_CONTROL:
1353 case ARIZONA_IN2R_CONTROL:
1354 case ARIZONA_ADC_DIGITAL_VOLUME_2R:
1355 case ARIZONA_DMIC2R_CONTROL:
1356 case ARIZONA_IN3L_CONTROL:
1357 case ARIZONA_ADC_DIGITAL_VOLUME_3L:
1358 case ARIZONA_DMIC3L_CONTROL:
1359 case ARIZONA_IN3R_CONTROL:
1360 case ARIZONA_ADC_DIGITAL_VOLUME_3R:
1361 case ARIZONA_DMIC3R_CONTROL:
1362 case ARIZONA_IN4L_CONTROL:
1363 case ARIZONA_ADC_DIGITAL_VOLUME_4L:
1364 case ARIZONA_DMIC4L_CONTROL:
1365 case ARIZONA_ADC_DIGITAL_VOLUME_4R:
1366 case ARIZONA_DMIC4R_CONTROL:
1367 case ARIZONA_OUTPUT_ENABLES_1:
1368 case ARIZONA_OUTPUT_STATUS_1:
1369 case ARIZONA_RAW_OUTPUT_STATUS_1:
1370 case ARIZONA_OUTPUT_RATE_1:
1371 case ARIZONA_OUTPUT_VOLUME_RAMP:
1372 case ARIZONA_OUTPUT_PATH_CONFIG_1L:
1373 case ARIZONA_DAC_DIGITAL_VOLUME_1L:
1374 case ARIZONA_DAC_VOLUME_LIMIT_1L:
1375 case ARIZONA_NOISE_GATE_SELECT_1L:
1376 case ARIZONA_OUTPUT_PATH_CONFIG_1R:
1377 case ARIZONA_DAC_DIGITAL_VOLUME_1R:
1378 case ARIZONA_DAC_VOLUME_LIMIT_1R:
1379 case ARIZONA_NOISE_GATE_SELECT_1R:
1380 case ARIZONA_OUTPUT_PATH_CONFIG_2L:
1381 case ARIZONA_DAC_DIGITAL_VOLUME_2L:
1382 case ARIZONA_DAC_VOLUME_LIMIT_2L:
1383 case ARIZONA_NOISE_GATE_SELECT_2L:
1384 case ARIZONA_OUTPUT_PATH_CONFIG_2R:
1385 case ARIZONA_DAC_DIGITAL_VOLUME_2R:
1386 case ARIZONA_DAC_VOLUME_LIMIT_2R:
1387 case ARIZONA_NOISE_GATE_SELECT_2R:
1388 case ARIZONA_OUTPUT_PATH_CONFIG_3L:
1389 case ARIZONA_DAC_DIGITAL_VOLUME_3L:
1390 case ARIZONA_DAC_VOLUME_LIMIT_3L:
1391 case ARIZONA_NOISE_GATE_SELECT_3L:
1392 case ARIZONA_OUTPUT_PATH_CONFIG_3R:
1393 case ARIZONA_DAC_DIGITAL_VOLUME_3R:
1394 case ARIZONA_DAC_VOLUME_LIMIT_3R:
1395 case ARIZONA_NOISE_GATE_SELECT_3R:
1396 case ARIZONA_OUTPUT_PATH_CONFIG_4L:
1397 case ARIZONA_DAC_DIGITAL_VOLUME_4L:
1398 case ARIZONA_OUT_VOLUME_4L:
1399 case ARIZONA_NOISE_GATE_SELECT_4L:
1400 case ARIZONA_OUTPUT_PATH_CONFIG_4R:
1401 case ARIZONA_DAC_DIGITAL_VOLUME_4R:
1402 case ARIZONA_OUT_VOLUME_4R:
1403 case ARIZONA_NOISE_GATE_SELECT_4R:
1404 case ARIZONA_OUTPUT_PATH_CONFIG_5L:
1405 case ARIZONA_DAC_DIGITAL_VOLUME_5L:
1406 case ARIZONA_DAC_VOLUME_LIMIT_5L:
1407 case ARIZONA_NOISE_GATE_SELECT_5L:
1408 case ARIZONA_OUTPUT_PATH_CONFIG_5R:
1409 case ARIZONA_DAC_DIGITAL_VOLUME_5R:
1410 case ARIZONA_DAC_VOLUME_LIMIT_5R:
1411 case ARIZONA_NOISE_GATE_SELECT_5R:
1412 case ARIZONA_OUTPUT_PATH_CONFIG_6L:
1413 case ARIZONA_DAC_DIGITAL_VOLUME_6L:
1414 case ARIZONA_DAC_VOLUME_LIMIT_6L:
1415 case ARIZONA_NOISE_GATE_SELECT_6L:
1416 case ARIZONA_OUTPUT_PATH_CONFIG_6R:
1417 case ARIZONA_DAC_DIGITAL_VOLUME_6R:
1418 case ARIZONA_DAC_VOLUME_LIMIT_6R:
1419 case ARIZONA_NOISE_GATE_SELECT_6R:
1420 case ARIZONA_DAC_AEC_CONTROL_1:
1421 case ARIZONA_NOISE_GATE_CONTROL:
1422 case ARIZONA_PDM_SPK1_CTRL_1:
1423 case ARIZONA_PDM_SPK1_CTRL_2:
1424 case ARIZONA_PDM_SPK2_CTRL_1:
1425 case ARIZONA_PDM_SPK2_CTRL_2:
1426 case ARIZONA_AIF1_BCLK_CTRL:
1427 case ARIZONA_AIF1_TX_PIN_CTRL:
1428 case ARIZONA_AIF1_RX_PIN_CTRL:
1429 case ARIZONA_AIF1_RATE_CTRL:
1430 case ARIZONA_AIF1_FORMAT:
1431 case ARIZONA_AIF1_TX_BCLK_RATE:
1432 case ARIZONA_AIF1_RX_BCLK_RATE:
1433 case ARIZONA_AIF1_FRAME_CTRL_1:
1434 case ARIZONA_AIF1_FRAME_CTRL_2:
1435 case ARIZONA_AIF1_FRAME_CTRL_3:
1436 case ARIZONA_AIF1_FRAME_CTRL_4:
1437 case ARIZONA_AIF1_FRAME_CTRL_5:
1438 case ARIZONA_AIF1_FRAME_CTRL_6:
1439 case ARIZONA_AIF1_FRAME_CTRL_7:
1440 case ARIZONA_AIF1_FRAME_CTRL_8:
1441 case ARIZONA_AIF1_FRAME_CTRL_9:
1442 case ARIZONA_AIF1_FRAME_CTRL_10:
1443 case ARIZONA_AIF1_FRAME_CTRL_11:
1444 case ARIZONA_AIF1_FRAME_CTRL_12:
1445 case ARIZONA_AIF1_FRAME_CTRL_13:
1446 case ARIZONA_AIF1_FRAME_CTRL_14:
1447 case ARIZONA_AIF1_FRAME_CTRL_15:
1448 case ARIZONA_AIF1_FRAME_CTRL_16:
1449 case ARIZONA_AIF1_FRAME_CTRL_17:
1450 case ARIZONA_AIF1_FRAME_CTRL_18:
1451 case ARIZONA_AIF1_TX_ENABLES:
1452 case ARIZONA_AIF1_RX_ENABLES:
1453 case ARIZONA_AIF2_BCLK_CTRL:
1454 case ARIZONA_AIF2_TX_PIN_CTRL:
1455 case ARIZONA_AIF2_RX_PIN_CTRL:
1456 case ARIZONA_AIF2_RATE_CTRL:
1457 case ARIZONA_AIF2_FORMAT:
1458 case ARIZONA_AIF2_TX_BCLK_RATE:
1459 case ARIZONA_AIF2_RX_BCLK_RATE:
1460 case ARIZONA_AIF2_FRAME_CTRL_1:
1461 case ARIZONA_AIF2_FRAME_CTRL_2:
1462 case ARIZONA_AIF2_FRAME_CTRL_3:
1463 case ARIZONA_AIF2_FRAME_CTRL_4:
1464 case ARIZONA_AIF2_FRAME_CTRL_11:
1465 case ARIZONA_AIF2_FRAME_CTRL_12:
1466 case ARIZONA_AIF2_TX_ENABLES:
1467 case ARIZONA_AIF2_RX_ENABLES:
1468 case ARIZONA_AIF3_BCLK_CTRL:
1469 case ARIZONA_AIF3_TX_PIN_CTRL:
1470 case ARIZONA_AIF3_RX_PIN_CTRL:
1471 case ARIZONA_AIF3_RATE_CTRL:
1472 case ARIZONA_AIF3_FORMAT:
1473 case ARIZONA_AIF3_TX_BCLK_RATE:
1474 case ARIZONA_AIF3_RX_BCLK_RATE:
1475 case ARIZONA_AIF3_FRAME_CTRL_1:
1476 case ARIZONA_AIF3_FRAME_CTRL_2:
1477 case ARIZONA_AIF3_FRAME_CTRL_3:
1478 case ARIZONA_AIF3_FRAME_CTRL_4:
1479 case ARIZONA_AIF3_FRAME_CTRL_11:
1480 case ARIZONA_AIF3_FRAME_CTRL_12:
1481 case ARIZONA_AIF3_TX_ENABLES:
1482 case ARIZONA_AIF3_RX_ENABLES:
1483 case ARIZONA_SLIMBUS_FRAMER_REF_GEAR:
1484 case ARIZONA_SLIMBUS_RATES_1:
1485 case ARIZONA_SLIMBUS_RATES_2:
1486 case ARIZONA_SLIMBUS_RATES_3:
1487 case ARIZONA_SLIMBUS_RATES_4:
1488 case ARIZONA_SLIMBUS_RATES_5:
1489 case ARIZONA_SLIMBUS_RATES_6:
1490 case ARIZONA_SLIMBUS_RATES_7:
1491 case ARIZONA_SLIMBUS_RATES_8:
1492 case ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE:
1493 case ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE:
1494 case ARIZONA_SLIMBUS_RX_PORT_STATUS:
1495 case ARIZONA_SLIMBUS_TX_PORT_STATUS:
1496 case ARIZONA_PWM1MIX_INPUT_1_SOURCE:
1497 case ARIZONA_PWM1MIX_INPUT_1_VOLUME:
1498 case ARIZONA_PWM1MIX_INPUT_2_SOURCE:
1499 case ARIZONA_PWM1MIX_INPUT_2_VOLUME:
1500 case ARIZONA_PWM1MIX_INPUT_3_SOURCE:
1501 case ARIZONA_PWM1MIX_INPUT_3_VOLUME:
1502 case ARIZONA_PWM1MIX_INPUT_4_SOURCE:
1503 case ARIZONA_PWM1MIX_INPUT_4_VOLUME:
1504 case ARIZONA_PWM2MIX_INPUT_1_SOURCE:
1505 case ARIZONA_PWM2MIX_INPUT_1_VOLUME:
1506 case ARIZONA_PWM2MIX_INPUT_2_SOURCE:
1507 case ARIZONA_PWM2MIX_INPUT_2_VOLUME:
1508 case ARIZONA_PWM2MIX_INPUT_3_SOURCE:
1509 case ARIZONA_PWM2MIX_INPUT_3_VOLUME:
1510 case ARIZONA_PWM2MIX_INPUT_4_SOURCE:
1511 case ARIZONA_PWM2MIX_INPUT_4_VOLUME:
1512 case ARIZONA_MICMIX_INPUT_1_SOURCE:
1513 case ARIZONA_MICMIX_INPUT_1_VOLUME:
1514 case ARIZONA_MICMIX_INPUT_2_SOURCE:
1515 case ARIZONA_MICMIX_INPUT_2_VOLUME:
1516 case ARIZONA_MICMIX_INPUT_3_SOURCE:
1517 case ARIZONA_MICMIX_INPUT_3_VOLUME:
1518 case ARIZONA_MICMIX_INPUT_4_SOURCE:
1519 case ARIZONA_MICMIX_INPUT_4_VOLUME:
1520 case ARIZONA_NOISEMIX_INPUT_1_SOURCE:
1521 case ARIZONA_NOISEMIX_INPUT_1_VOLUME:
1522 case ARIZONA_NOISEMIX_INPUT_2_SOURCE:
1523 case ARIZONA_NOISEMIX_INPUT_2_VOLUME:
1524 case ARIZONA_NOISEMIX_INPUT_3_SOURCE:
1525 case ARIZONA_NOISEMIX_INPUT_3_VOLUME:
1526 case ARIZONA_NOISEMIX_INPUT_4_SOURCE:
1527 case ARIZONA_NOISEMIX_INPUT_4_VOLUME:
1528 case ARIZONA_OUT1LMIX_INPUT_1_SOURCE:
1529 case ARIZONA_OUT1LMIX_INPUT_1_VOLUME:
1530 case ARIZONA_OUT1LMIX_INPUT_2_SOURCE:
1531 case ARIZONA_OUT1LMIX_INPUT_2_VOLUME:
1532 case ARIZONA_OUT1LMIX_INPUT_3_SOURCE:
1533 case ARIZONA_OUT1LMIX_INPUT_3_VOLUME:
1534 case ARIZONA_OUT1LMIX_INPUT_4_SOURCE:
1535 case ARIZONA_OUT1LMIX_INPUT_4_VOLUME:
1536 case ARIZONA_OUT1RMIX_INPUT_1_SOURCE:
1537 case ARIZONA_OUT1RMIX_INPUT_1_VOLUME:
1538 case ARIZONA_OUT1RMIX_INPUT_2_SOURCE:
1539 case ARIZONA_OUT1RMIX_INPUT_2_VOLUME:
1540 case ARIZONA_OUT1RMIX_INPUT_3_SOURCE:
1541 case ARIZONA_OUT1RMIX_INPUT_3_VOLUME:
1542 case ARIZONA_OUT1RMIX_INPUT_4_SOURCE:
1543 case ARIZONA_OUT1RMIX_INPUT_4_VOLUME:
1544 case ARIZONA_OUT2LMIX_INPUT_1_SOURCE:
1545 case ARIZONA_OUT2LMIX_INPUT_1_VOLUME:
1546 case ARIZONA_OUT2LMIX_INPUT_2_SOURCE:
1547 case ARIZONA_OUT2LMIX_INPUT_2_VOLUME:
1548 case ARIZONA_OUT2LMIX_INPUT_3_SOURCE:
1549 case ARIZONA_OUT2LMIX_INPUT_3_VOLUME:
1550 case ARIZONA_OUT2LMIX_INPUT_4_SOURCE:
1551 case ARIZONA_OUT2LMIX_INPUT_4_VOLUME:
1552 case ARIZONA_OUT2RMIX_INPUT_1_SOURCE:
1553 case ARIZONA_OUT2RMIX_INPUT_1_VOLUME:
1554 case ARIZONA_OUT2RMIX_INPUT_2_SOURCE:
1555 case ARIZONA_OUT2RMIX_INPUT_2_VOLUME:
1556 case ARIZONA_OUT2RMIX_INPUT_3_SOURCE:
1557 case ARIZONA_OUT2RMIX_INPUT_3_VOLUME:
1558 case ARIZONA_OUT2RMIX_INPUT_4_SOURCE:
1559 case ARIZONA_OUT2RMIX_INPUT_4_VOLUME:
1560 case ARIZONA_OUT3LMIX_INPUT_1_SOURCE:
1561 case ARIZONA_OUT3LMIX_INPUT_1_VOLUME:
1562 case ARIZONA_OUT3LMIX_INPUT_2_SOURCE:
1563 case ARIZONA_OUT3LMIX_INPUT_2_VOLUME:
1564 case ARIZONA_OUT3LMIX_INPUT_3_SOURCE:
1565 case ARIZONA_OUT3LMIX_INPUT_3_VOLUME:
1566 case ARIZONA_OUT3LMIX_INPUT_4_SOURCE:
1567 case ARIZONA_OUT3LMIX_INPUT_4_VOLUME:
1568 case ARIZONA_OUT3RMIX_INPUT_1_SOURCE:
1569 case ARIZONA_OUT3RMIX_INPUT_1_VOLUME:
1570 case ARIZONA_OUT3RMIX_INPUT_2_SOURCE:
1571 case ARIZONA_OUT3RMIX_INPUT_2_VOLUME:
1572 case ARIZONA_OUT3RMIX_INPUT_3_SOURCE:
1573 case ARIZONA_OUT3RMIX_INPUT_3_VOLUME:
1574 case ARIZONA_OUT3RMIX_INPUT_4_SOURCE:
1575 case ARIZONA_OUT3RMIX_INPUT_4_VOLUME:
1576 case ARIZONA_OUT4LMIX_INPUT_1_SOURCE:
1577 case ARIZONA_OUT4LMIX_INPUT_1_VOLUME:
1578 case ARIZONA_OUT4LMIX_INPUT_2_SOURCE:
1579 case ARIZONA_OUT4LMIX_INPUT_2_VOLUME:
1580 case ARIZONA_OUT4LMIX_INPUT_3_SOURCE:
1581 case ARIZONA_OUT4LMIX_INPUT_3_VOLUME:
1582 case ARIZONA_OUT4LMIX_INPUT_4_SOURCE:
1583 case ARIZONA_OUT4LMIX_INPUT_4_VOLUME:
1584 case ARIZONA_OUT4RMIX_INPUT_1_SOURCE:
1585 case ARIZONA_OUT4RMIX_INPUT_1_VOLUME:
1586 case ARIZONA_OUT4RMIX_INPUT_2_SOURCE:
1587 case ARIZONA_OUT4RMIX_INPUT_2_VOLUME:
1588 case ARIZONA_OUT4RMIX_INPUT_3_SOURCE:
1589 case ARIZONA_OUT4RMIX_INPUT_3_VOLUME:
1590 case ARIZONA_OUT4RMIX_INPUT_4_SOURCE:
1591 case ARIZONA_OUT4RMIX_INPUT_4_VOLUME:
1592 case ARIZONA_OUT5LMIX_INPUT_1_SOURCE:
1593 case ARIZONA_OUT5LMIX_INPUT_1_VOLUME:
1594 case ARIZONA_OUT5LMIX_INPUT_2_SOURCE:
1595 case ARIZONA_OUT5LMIX_INPUT_2_VOLUME:
1596 case ARIZONA_OUT5LMIX_INPUT_3_SOURCE:
1597 case ARIZONA_OUT5LMIX_INPUT_3_VOLUME:
1598 case ARIZONA_OUT5LMIX_INPUT_4_SOURCE:
1599 case ARIZONA_OUT5LMIX_INPUT_4_VOLUME:
1600 case ARIZONA_OUT5RMIX_INPUT_1_SOURCE:
1601 case ARIZONA_OUT5RMIX_INPUT_1_VOLUME:
1602 case ARIZONA_OUT5RMIX_INPUT_2_SOURCE:
1603 case ARIZONA_OUT5RMIX_INPUT_2_VOLUME:
1604 case ARIZONA_OUT5RMIX_INPUT_3_SOURCE:
1605 case ARIZONA_OUT5RMIX_INPUT_3_VOLUME:
1606 case ARIZONA_OUT5RMIX_INPUT_4_SOURCE:
1607 case ARIZONA_OUT5RMIX_INPUT_4_VOLUME:
1608 case ARIZONA_OUT6LMIX_INPUT_1_SOURCE:
1609 case ARIZONA_OUT6LMIX_INPUT_1_VOLUME:
1610 case ARIZONA_OUT6LMIX_INPUT_2_SOURCE:
1611 case ARIZONA_OUT6LMIX_INPUT_2_VOLUME:
1612 case ARIZONA_OUT6LMIX_INPUT_3_SOURCE:
1613 case ARIZONA_OUT6LMIX_INPUT_3_VOLUME:
1614 case ARIZONA_OUT6LMIX_INPUT_4_SOURCE:
1615 case ARIZONA_OUT6LMIX_INPUT_4_VOLUME:
1616 case ARIZONA_OUT6RMIX_INPUT_1_SOURCE:
1617 case ARIZONA_OUT6RMIX_INPUT_1_VOLUME:
1618 case ARIZONA_OUT6RMIX_INPUT_2_SOURCE:
1619 case ARIZONA_OUT6RMIX_INPUT_2_VOLUME:
1620 case ARIZONA_OUT6RMIX_INPUT_3_SOURCE:
1621 case ARIZONA_OUT6RMIX_INPUT_3_VOLUME:
1622 case ARIZONA_OUT6RMIX_INPUT_4_SOURCE:
1623 case ARIZONA_OUT6RMIX_INPUT_4_VOLUME:
1624 case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE:
1625 case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME:
1626 case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE:
1627 case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME:
1628 case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE:
1629 case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME:
1630 case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE:
1631 case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME:
1632 case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE:
1633 case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME:
1634 case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE:
1635 case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME:
1636 case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE:
1637 case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME:
1638 case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE:
1639 case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME:
1640 case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE:
1641 case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME:
1642 case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE:
1643 case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME:
1644 case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE:
1645 case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME:
1646 case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE:
1647 case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME:
1648 case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE:
1649 case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME:
1650 case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE:
1651 case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME:
1652 case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE:
1653 case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME:
1654 case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE:
1655 case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME:
1656 case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE:
1657 case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME:
1658 case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE:
1659 case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME:
1660 case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE:
1661 case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME:
1662 case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE:
1663 case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME:
1664 case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE:
1665 case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME:
1666 case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE:
1667 case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME:
1668 case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE:
1669 case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME:
1670 case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE:
1671 case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME:
1672 case ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE:
1673 case ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME:
1674 case ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE:
1675 case ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME:
1676 case ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE:
1677 case ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME:
1678 case ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE:
1679 case ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME:
1680 case ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE:
1681 case ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME:
1682 case ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE:
1683 case ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME:
1684 case ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE:
1685 case ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME:
1686 case ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE:
1687 case ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME:
1688 case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE:
1689 case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME:
1690 case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE:
1691 case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME:
1692 case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE:
1693 case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME:
1694 case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE:
1695 case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME:
1696 case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE:
1697 case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME:
1698 case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE:
1699 case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME:
1700 case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE:
1701 case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME:
1702 case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE:
1703 case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME:
1704 case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE:
1705 case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME:
1706 case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE:
1707 case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME:
1708 case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE:
1709 case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME:
1710 case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE:
1711 case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME:
1712 case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE:
1713 case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME:
1714 case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE:
1715 case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME:
1716 case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE:
1717 case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME:
1718 case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE:
1719 case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME:
1720 case ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE:
1721 case ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME:
1722 case ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE:
1723 case ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME:
1724 case ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE:
1725 case ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME:
1726 case ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE:
1727 case ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME:
1728 case ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE:
1729 case ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME:
1730 case ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE:
1731 case ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME:
1732 case ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE:
1733 case ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME:
1734 case ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE:
1735 case ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME:
1736 case ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE:
1737 case ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME:
1738 case ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE:
1739 case ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME:
1740 case ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE:
1741 case ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME:
1742 case ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE:
1743 case ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME:
1744 case ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE:
1745 case ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME:
1746 case ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE:
1747 case ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME:
1748 case ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE:
1749 case ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME:
1750 case ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE:
1751 case ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME:
1752 case ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE:
1753 case ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME:
1754 case ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE:
1755 case ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME:
1756 case ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE:
1757 case ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME:
1758 case ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE:
1759 case ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME:
1760 case ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE:
1761 case ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME:
1762 case ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE:
1763 case ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME:
1764 case ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE:
1765 case ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME:
1766 case ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE:
1767 case ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME:
1768 case ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE:
1769 case ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME:
1770 case ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE:
1771 case ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME:
1772 case ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE:
1773 case ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME:
1774 case ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE:
1775 case ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME:
1776 case ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE:
1777 case ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME:
1778 case ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE:
1779 case ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME:
1780 case ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE:
1781 case ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME:
1782 case ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE:
1783 case ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME:
1784 case ARIZONA_EQ1MIX_INPUT_1_SOURCE:
1785 case ARIZONA_EQ1MIX_INPUT_1_VOLUME:
1786 case ARIZONA_EQ1MIX_INPUT_2_SOURCE:
1787 case ARIZONA_EQ1MIX_INPUT_2_VOLUME:
1788 case ARIZONA_EQ1MIX_INPUT_3_SOURCE:
1789 case ARIZONA_EQ1MIX_INPUT_3_VOLUME:
1790 case ARIZONA_EQ1MIX_INPUT_4_SOURCE:
1791 case ARIZONA_EQ1MIX_INPUT_4_VOLUME:
1792 case ARIZONA_EQ2MIX_INPUT_1_SOURCE:
1793 case ARIZONA_EQ2MIX_INPUT_1_VOLUME:
1794 case ARIZONA_EQ2MIX_INPUT_2_SOURCE:
1795 case ARIZONA_EQ2MIX_INPUT_2_VOLUME:
1796 case ARIZONA_EQ2MIX_INPUT_3_SOURCE:
1797 case ARIZONA_EQ2MIX_INPUT_3_VOLUME:
1798 case ARIZONA_EQ2MIX_INPUT_4_SOURCE:
1799 case ARIZONA_EQ2MIX_INPUT_4_VOLUME:
1800 case ARIZONA_EQ3MIX_INPUT_1_SOURCE:
1801 case ARIZONA_EQ3MIX_INPUT_1_VOLUME:
1802 case ARIZONA_EQ3MIX_INPUT_2_SOURCE:
1803 case ARIZONA_EQ3MIX_INPUT_2_VOLUME:
1804 case ARIZONA_EQ3MIX_INPUT_3_SOURCE:
1805 case ARIZONA_EQ3MIX_INPUT_3_VOLUME:
1806 case ARIZONA_EQ3MIX_INPUT_4_SOURCE:
1807 case ARIZONA_EQ3MIX_INPUT_4_VOLUME:
1808 case ARIZONA_EQ4MIX_INPUT_1_SOURCE:
1809 case ARIZONA_EQ4MIX_INPUT_1_VOLUME:
1810 case ARIZONA_EQ4MIX_INPUT_2_SOURCE:
1811 case ARIZONA_EQ4MIX_INPUT_2_VOLUME:
1812 case ARIZONA_EQ4MIX_INPUT_3_SOURCE:
1813 case ARIZONA_EQ4MIX_INPUT_3_VOLUME:
1814 case ARIZONA_EQ4MIX_INPUT_4_SOURCE:
1815 case ARIZONA_EQ4MIX_INPUT_4_VOLUME:
1816 case ARIZONA_DRC1LMIX_INPUT_1_SOURCE:
1817 case ARIZONA_DRC1LMIX_INPUT_1_VOLUME:
1818 case ARIZONA_DRC1LMIX_INPUT_2_SOURCE:
1819 case ARIZONA_DRC1LMIX_INPUT_2_VOLUME:
1820 case ARIZONA_DRC1LMIX_INPUT_3_SOURCE:
1821 case ARIZONA_DRC1LMIX_INPUT_3_VOLUME:
1822 case ARIZONA_DRC1LMIX_INPUT_4_SOURCE:
1823 case ARIZONA_DRC1LMIX_INPUT_4_VOLUME:
1824 case ARIZONA_DRC1RMIX_INPUT_1_SOURCE:
1825 case ARIZONA_DRC1RMIX_INPUT_1_VOLUME:
1826 case ARIZONA_DRC1RMIX_INPUT_2_SOURCE:
1827 case ARIZONA_DRC1RMIX_INPUT_2_VOLUME:
1828 case ARIZONA_DRC1RMIX_INPUT_3_SOURCE:
1829 case ARIZONA_DRC1RMIX_INPUT_3_VOLUME:
1830 case ARIZONA_DRC1RMIX_INPUT_4_SOURCE:
1831 case ARIZONA_DRC1RMIX_INPUT_4_VOLUME:
1832 case ARIZONA_DRC2LMIX_INPUT_1_SOURCE:
1833 case ARIZONA_DRC2LMIX_INPUT_1_VOLUME:
1834 case ARIZONA_DRC2LMIX_INPUT_2_SOURCE:
1835 case ARIZONA_DRC2LMIX_INPUT_2_VOLUME:
1836 case ARIZONA_DRC2LMIX_INPUT_3_SOURCE:
1837 case ARIZONA_DRC2LMIX_INPUT_3_VOLUME:
1838 case ARIZONA_DRC2LMIX_INPUT_4_SOURCE:
1839 case ARIZONA_DRC2LMIX_INPUT_4_VOLUME:
1840 case ARIZONA_DRC2RMIX_INPUT_1_SOURCE:
1841 case ARIZONA_DRC2RMIX_INPUT_1_VOLUME:
1842 case ARIZONA_DRC2RMIX_INPUT_2_SOURCE:
1843 case ARIZONA_DRC2RMIX_INPUT_2_VOLUME:
1844 case ARIZONA_DRC2RMIX_INPUT_3_SOURCE:
1845 case ARIZONA_DRC2RMIX_INPUT_3_VOLUME:
1846 case ARIZONA_DRC2RMIX_INPUT_4_SOURCE:
1847 case ARIZONA_DRC2RMIX_INPUT_4_VOLUME:
1848 case ARIZONA_HPLP1MIX_INPUT_1_SOURCE:
1849 case ARIZONA_HPLP1MIX_INPUT_1_VOLUME:
1850 case ARIZONA_HPLP1MIX_INPUT_2_SOURCE:
1851 case ARIZONA_HPLP1MIX_INPUT_2_VOLUME:
1852 case ARIZONA_HPLP1MIX_INPUT_3_SOURCE:
1853 case ARIZONA_HPLP1MIX_INPUT_3_VOLUME:
1854 case ARIZONA_HPLP1MIX_INPUT_4_SOURCE:
1855 case ARIZONA_HPLP1MIX_INPUT_4_VOLUME:
1856 case ARIZONA_HPLP2MIX_INPUT_1_SOURCE:
1857 case ARIZONA_HPLP2MIX_INPUT_1_VOLUME:
1858 case ARIZONA_HPLP2MIX_INPUT_2_SOURCE:
1859 case ARIZONA_HPLP2MIX_INPUT_2_VOLUME:
1860 case ARIZONA_HPLP2MIX_INPUT_3_SOURCE:
1861 case ARIZONA_HPLP2MIX_INPUT_3_VOLUME:
1862 case ARIZONA_HPLP2MIX_INPUT_4_SOURCE:
1863 case ARIZONA_HPLP2MIX_INPUT_4_VOLUME:
1864 case ARIZONA_HPLP3MIX_INPUT_1_SOURCE:
1865 case ARIZONA_HPLP3MIX_INPUT_1_VOLUME:
1866 case ARIZONA_HPLP3MIX_INPUT_2_SOURCE:
1867 case ARIZONA_HPLP3MIX_INPUT_2_VOLUME:
1868 case ARIZONA_HPLP3MIX_INPUT_3_SOURCE:
1869 case ARIZONA_HPLP3MIX_INPUT_3_VOLUME:
1870 case ARIZONA_HPLP3MIX_INPUT_4_SOURCE:
1871 case ARIZONA_HPLP3MIX_INPUT_4_VOLUME:
1872 case ARIZONA_HPLP4MIX_INPUT_1_SOURCE:
1873 case ARIZONA_HPLP4MIX_INPUT_1_VOLUME:
1874 case ARIZONA_HPLP4MIX_INPUT_2_SOURCE:
1875 case ARIZONA_HPLP4MIX_INPUT_2_VOLUME:
1876 case ARIZONA_HPLP4MIX_INPUT_3_SOURCE:
1877 case ARIZONA_HPLP4MIX_INPUT_3_VOLUME:
1878 case ARIZONA_HPLP4MIX_INPUT_4_SOURCE:
1879 case ARIZONA_HPLP4MIX_INPUT_4_VOLUME:
1880 case ARIZONA_DSP1LMIX_INPUT_1_SOURCE:
1881 case ARIZONA_DSP1LMIX_INPUT_1_VOLUME:
1882 case ARIZONA_DSP1LMIX_INPUT_2_SOURCE:
1883 case ARIZONA_DSP1LMIX_INPUT_2_VOLUME:
1884 case ARIZONA_DSP1LMIX_INPUT_3_SOURCE:
1885 case ARIZONA_DSP1LMIX_INPUT_3_VOLUME:
1886 case ARIZONA_DSP1LMIX_INPUT_4_SOURCE:
1887 case ARIZONA_DSP1LMIX_INPUT_4_VOLUME:
1888 case ARIZONA_DSP1RMIX_INPUT_1_SOURCE:
1889 case ARIZONA_DSP1RMIX_INPUT_1_VOLUME:
1890 case ARIZONA_DSP1RMIX_INPUT_2_SOURCE:
1891 case ARIZONA_DSP1RMIX_INPUT_2_VOLUME:
1892 case ARIZONA_DSP1RMIX_INPUT_3_SOURCE:
1893 case ARIZONA_DSP1RMIX_INPUT_3_VOLUME:
1894 case ARIZONA_DSP1RMIX_INPUT_4_SOURCE:
1895 case ARIZONA_DSP1RMIX_INPUT_4_VOLUME:
1896 case ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE:
1897 case ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE:
1898 case ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE:
1899 case ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE:
1900 case ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE:
1901 case ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE:
1902 case ARIZONA_DSP2LMIX_INPUT_1_SOURCE:
1903 case ARIZONA_DSP2LMIX_INPUT_1_VOLUME:
1904 case ARIZONA_DSP2LMIX_INPUT_2_SOURCE:
1905 case ARIZONA_DSP2LMIX_INPUT_2_VOLUME:
1906 case ARIZONA_DSP2LMIX_INPUT_3_SOURCE:
1907 case ARIZONA_DSP2LMIX_INPUT_3_VOLUME:
1908 case ARIZONA_DSP2LMIX_INPUT_4_SOURCE:
1909 case ARIZONA_DSP2LMIX_INPUT_4_VOLUME:
1910 case ARIZONA_DSP2RMIX_INPUT_1_SOURCE:
1911 case ARIZONA_DSP2RMIX_INPUT_1_VOLUME:
1912 case ARIZONA_DSP2RMIX_INPUT_2_SOURCE:
1913 case ARIZONA_DSP2RMIX_INPUT_2_VOLUME:
1914 case ARIZONA_DSP2RMIX_INPUT_3_SOURCE:
1915 case ARIZONA_DSP2RMIX_INPUT_3_VOLUME:
1916 case ARIZONA_DSP2RMIX_INPUT_4_SOURCE:
1917 case ARIZONA_DSP2RMIX_INPUT_4_VOLUME:
1918 case ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE:
1919 case ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE:
1920 case ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE:
1921 case ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE:
1922 case ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE:
1923 case ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE:
1924 case ARIZONA_DSP3LMIX_INPUT_1_SOURCE:
1925 case ARIZONA_DSP3LMIX_INPUT_1_VOLUME:
1926 case ARIZONA_DSP3LMIX_INPUT_2_SOURCE:
1927 case ARIZONA_DSP3LMIX_INPUT_2_VOLUME:
1928 case ARIZONA_DSP3LMIX_INPUT_3_SOURCE:
1929 case ARIZONA_DSP3LMIX_INPUT_3_VOLUME:
1930 case ARIZONA_DSP3LMIX_INPUT_4_SOURCE:
1931 case ARIZONA_DSP3LMIX_INPUT_4_VOLUME:
1932 case ARIZONA_DSP3RMIX_INPUT_1_SOURCE:
1933 case ARIZONA_DSP3RMIX_INPUT_1_VOLUME:
1934 case ARIZONA_DSP3RMIX_INPUT_2_SOURCE:
1935 case ARIZONA_DSP3RMIX_INPUT_2_VOLUME:
1936 case ARIZONA_DSP3RMIX_INPUT_3_SOURCE:
1937 case ARIZONA_DSP3RMIX_INPUT_3_VOLUME:
1938 case ARIZONA_DSP3RMIX_INPUT_4_SOURCE:
1939 case ARIZONA_DSP3RMIX_INPUT_4_VOLUME:
1940 case ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE:
1941 case ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE:
1942 case ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE:
1943 case ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE:
1944 case ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE:
1945 case ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE:
1946 case ARIZONA_DSP4LMIX_INPUT_1_SOURCE:
1947 case ARIZONA_DSP4LMIX_INPUT_1_VOLUME:
1948 case ARIZONA_DSP4LMIX_INPUT_2_SOURCE:
1949 case ARIZONA_DSP4LMIX_INPUT_2_VOLUME:
1950 case ARIZONA_DSP4LMIX_INPUT_3_SOURCE:
1951 case ARIZONA_DSP4LMIX_INPUT_3_VOLUME:
1952 case ARIZONA_DSP4LMIX_INPUT_4_SOURCE:
1953 case ARIZONA_DSP4LMIX_INPUT_4_VOLUME:
1954 case ARIZONA_DSP4RMIX_INPUT_1_SOURCE:
1955 case ARIZONA_DSP4RMIX_INPUT_1_VOLUME:
1956 case ARIZONA_DSP4RMIX_INPUT_2_SOURCE:
1957 case ARIZONA_DSP4RMIX_INPUT_2_VOLUME:
1958 case ARIZONA_DSP4RMIX_INPUT_3_SOURCE:
1959 case ARIZONA_DSP4RMIX_INPUT_3_VOLUME:
1960 case ARIZONA_DSP4RMIX_INPUT_4_SOURCE:
1961 case ARIZONA_DSP4RMIX_INPUT_4_VOLUME:
1962 case ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE:
1963 case ARIZONA_DSP4AUX2MIX_INPUT_1_SOURCE:
1964 case ARIZONA_DSP4AUX3MIX_INPUT_1_SOURCE:
1965 case ARIZONA_DSP4AUX4MIX_INPUT_1_SOURCE:
1966 case ARIZONA_DSP4AUX5MIX_INPUT_1_SOURCE:
1967 case ARIZONA_DSP4AUX6MIX_INPUT_1_SOURCE:
1968 case ARIZONA_ASRC1LMIX_INPUT_1_SOURCE:
1969 case ARIZONA_ASRC1RMIX_INPUT_1_SOURCE:
1970 case ARIZONA_ASRC2LMIX_INPUT_1_SOURCE:
1971 case ARIZONA_ASRC2RMIX_INPUT_1_SOURCE:
1972 case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE:
1973 case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE:
1974 case ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE:
1975 case ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE:
1976 case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE:
1977 case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE:
1978 case ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE:
1979 case ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE:
1980 case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE:
1981 case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE:
1982 case ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE:
1983 case ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE:
1984 case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE:
1985 case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE:
1986 case ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE:
1987 case ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE:
1988 case ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE:
1989 case ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE:
1990 case ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE:
1991 case ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE:
1992 case ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE:
1993 case ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE:
1994 case ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE:
1995 case ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE:
1996 case ARIZONA_GPIO1_CTRL:
1997 case ARIZONA_GPIO2_CTRL:
1998 case ARIZONA_GPIO3_CTRL:
1999 case ARIZONA_GPIO4_CTRL:
2000 case ARIZONA_GPIO5_CTRL:
2001 case ARIZONA_IRQ_CTRL_1:
2002 case ARIZONA_GPIO_DEBOUNCE_CONFIG:
2003 case ARIZONA_MISC_PAD_CTRL_1:
2004 case ARIZONA_MISC_PAD_CTRL_2:
2005 case ARIZONA_MISC_PAD_CTRL_3:
2006 case ARIZONA_MISC_PAD_CTRL_4:
2007 case ARIZONA_MISC_PAD_CTRL_5:
2008 case ARIZONA_MISC_PAD_CTRL_6:
2009 case ARIZONA_MISC_PAD_CTRL_7:
2010 case ARIZONA_MISC_PAD_CTRL_8:
2011 case ARIZONA_MISC_PAD_CTRL_9:
2012 case ARIZONA_MISC_PAD_CTRL_10:
2013 case ARIZONA_MISC_PAD_CTRL_11:
2014 case ARIZONA_MISC_PAD_CTRL_12:
2015 case ARIZONA_MISC_PAD_CTRL_13:
2016 case ARIZONA_MISC_PAD_CTRL_14:
2017 case ARIZONA_MISC_PAD_CTRL_15:
2018 case ARIZONA_MISC_PAD_CTRL_16:
2019 case ARIZONA_MISC_PAD_CTRL_17:
2020 case ARIZONA_MISC_PAD_CTRL_18:
2021 case ARIZONA_INTERRUPT_STATUS_1:
2022 case ARIZONA_INTERRUPT_STATUS_2:
2023 case ARIZONA_INTERRUPT_STATUS_3:
2024 case ARIZONA_INTERRUPT_STATUS_4:
2025 case ARIZONA_INTERRUPT_STATUS_5:
2026 case ARIZONA_INTERRUPT_STATUS_1_MASK:
2027 case ARIZONA_INTERRUPT_STATUS_2_MASK:
2028 case ARIZONA_INTERRUPT_STATUS_3_MASK:
2029 case ARIZONA_INTERRUPT_STATUS_4_MASK:
2030 case ARIZONA_INTERRUPT_STATUS_5_MASK:
2031 case ARIZONA_INTERRUPT_CONTROL:
2032 case ARIZONA_IRQ2_STATUS_1:
2033 case ARIZONA_IRQ2_STATUS_2:
2034 case ARIZONA_IRQ2_STATUS_3:
2035 case ARIZONA_IRQ2_STATUS_4:
2036 case ARIZONA_IRQ2_STATUS_5:
2037 case ARIZONA_IRQ2_STATUS_1_MASK:
2038 case ARIZONA_IRQ2_STATUS_2_MASK:
2039 case ARIZONA_IRQ2_STATUS_3_MASK:
2040 case ARIZONA_IRQ2_STATUS_4_MASK:
2041 case ARIZONA_IRQ2_STATUS_5_MASK:
2042 case ARIZONA_IRQ2_CONTROL:
2043 case ARIZONA_INTERRUPT_RAW_STATUS_2:
2044 case ARIZONA_INTERRUPT_RAW_STATUS_3:
2045 case ARIZONA_INTERRUPT_RAW_STATUS_4:
2046 case ARIZONA_INTERRUPT_RAW_STATUS_5:
2047 case ARIZONA_INTERRUPT_RAW_STATUS_6:
2048 case ARIZONA_INTERRUPT_RAW_STATUS_7:
2049 case ARIZONA_INTERRUPT_RAW_STATUS_8:
2050 case ARIZONA_IRQ_PIN_STATUS:
2051 case ARIZONA_AOD_WKUP_AND_TRIG:
2052 case ARIZONA_AOD_IRQ1:
2053 case ARIZONA_AOD_IRQ2:
2054 case ARIZONA_AOD_IRQ_MASK_IRQ1:
2055 case ARIZONA_AOD_IRQ_MASK_IRQ2:
2056 case ARIZONA_AOD_IRQ_RAW_STATUS:
2057 case ARIZONA_JACK_DETECT_DEBOUNCE:
2058 case ARIZONA_FX_CTRL1:
2059 case ARIZONA_FX_CTRL2:
2060 case ARIZONA_EQ1_1:
2061 case ARIZONA_EQ1_2:
2062 case ARIZONA_EQ1_3:
2063 case ARIZONA_EQ1_4:
2064 case ARIZONA_EQ1_5:
2065 case ARIZONA_EQ1_6:
2066 case ARIZONA_EQ1_7:
2067 case ARIZONA_EQ1_8:
2068 case ARIZONA_EQ1_9:
2069 case ARIZONA_EQ1_10:
2070 case ARIZONA_EQ1_11:
2071 case ARIZONA_EQ1_12:
2072 case ARIZONA_EQ1_13:
2073 case ARIZONA_EQ1_14:
2074 case ARIZONA_EQ1_15:
2075 case ARIZONA_EQ1_16:
2076 case ARIZONA_EQ1_17:
2077 case ARIZONA_EQ1_18:
2078 case ARIZONA_EQ1_19:
2079 case ARIZONA_EQ1_20:
2080 case ARIZONA_EQ1_21:
2081 case ARIZONA_EQ2_1:
2082 case ARIZONA_EQ2_2:
2083 case ARIZONA_EQ2_3:
2084 case ARIZONA_EQ2_4:
2085 case ARIZONA_EQ2_5:
2086 case ARIZONA_EQ2_6:
2087 case ARIZONA_EQ2_7:
2088 case ARIZONA_EQ2_8:
2089 case ARIZONA_EQ2_9:
2090 case ARIZONA_EQ2_10:
2091 case ARIZONA_EQ2_11:
2092 case ARIZONA_EQ2_12:
2093 case ARIZONA_EQ2_13:
2094 case ARIZONA_EQ2_14:
2095 case ARIZONA_EQ2_15:
2096 case ARIZONA_EQ2_16:
2097 case ARIZONA_EQ2_17:
2098 case ARIZONA_EQ2_18:
2099 case ARIZONA_EQ2_19:
2100 case ARIZONA_EQ2_20:
2101 case ARIZONA_EQ2_21:
2102 case ARIZONA_EQ3_1:
2103 case ARIZONA_EQ3_2:
2104 case ARIZONA_EQ3_3:
2105 case ARIZONA_EQ3_4:
2106 case ARIZONA_EQ3_5:
2107 case ARIZONA_EQ3_6:
2108 case ARIZONA_EQ3_7:
2109 case ARIZONA_EQ3_8:
2110 case ARIZONA_EQ3_9:
2111 case ARIZONA_EQ3_10:
2112 case ARIZONA_EQ3_11:
2113 case ARIZONA_EQ3_12:
2114 case ARIZONA_EQ3_13:
2115 case ARIZONA_EQ3_14:
2116 case ARIZONA_EQ3_15:
2117 case ARIZONA_EQ3_16:
2118 case ARIZONA_EQ3_17:
2119 case ARIZONA_EQ3_18:
2120 case ARIZONA_EQ3_19:
2121 case ARIZONA_EQ3_20:
2122 case ARIZONA_EQ3_21:
2123 case ARIZONA_EQ4_1:
2124 case ARIZONA_EQ4_2:
2125 case ARIZONA_EQ4_3:
2126 case ARIZONA_EQ4_4:
2127 case ARIZONA_EQ4_5:
2128 case ARIZONA_EQ4_6:
2129 case ARIZONA_EQ4_7:
2130 case ARIZONA_EQ4_8:
2131 case ARIZONA_EQ4_9:
2132 case ARIZONA_EQ4_10:
2133 case ARIZONA_EQ4_11:
2134 case ARIZONA_EQ4_12:
2135 case ARIZONA_EQ4_13:
2136 case ARIZONA_EQ4_14:
2137 case ARIZONA_EQ4_15:
2138 case ARIZONA_EQ4_16:
2139 case ARIZONA_EQ4_17:
2140 case ARIZONA_EQ4_18:
2141 case ARIZONA_EQ4_19:
2142 case ARIZONA_EQ4_20:
2143 case ARIZONA_EQ4_21:
2144 case ARIZONA_DRC1_CTRL1:
2145 case ARIZONA_DRC1_CTRL2:
2146 case ARIZONA_DRC1_CTRL3:
2147 case ARIZONA_DRC1_CTRL4:
2148 case ARIZONA_DRC1_CTRL5:
2149 case ARIZONA_DRC2_CTRL1:
2150 case ARIZONA_DRC2_CTRL2:
2151 case ARIZONA_DRC2_CTRL3:
2152 case ARIZONA_DRC2_CTRL4:
2153 case ARIZONA_DRC2_CTRL5:
2154 case ARIZONA_HPLPF1_1:
2155 case ARIZONA_HPLPF1_2:
2156 case ARIZONA_HPLPF2_1:
2157 case ARIZONA_HPLPF2_2:
2158 case ARIZONA_HPLPF3_1:
2159 case ARIZONA_HPLPF3_2:
2160 case ARIZONA_HPLPF4_1:
2161 case ARIZONA_HPLPF4_2:
2162 case ARIZONA_ASRC_ENABLE:
2163 case ARIZONA_ASRC_STATUS:
2164 case ARIZONA_ASRC_RATE1:
2165 case ARIZONA_ISRC_1_CTRL_1:
2166 case ARIZONA_ISRC_1_CTRL_2:
2167 case ARIZONA_ISRC_1_CTRL_3:
2168 case ARIZONA_ISRC_2_CTRL_1:
2169 case ARIZONA_ISRC_2_CTRL_2:
2170 case ARIZONA_ISRC_2_CTRL_3:
2171 case ARIZONA_ISRC_3_CTRL_1:
2172 case ARIZONA_ISRC_3_CTRL_2:
2173 case ARIZONA_ISRC_3_CTRL_3:
2174 case ARIZONA_CLOCK_CONTROL:
2175 case ARIZONA_ANC_SRC:
2176 case ARIZONA_DSP_STATUS:
2177 case ARIZONA_DSP1_CONTROL_1:
2178 case ARIZONA_DSP1_CLOCKING_1:
2179 case ARIZONA_DSP1_STATUS_1:
2180 case ARIZONA_DSP1_STATUS_2:
2181 case ARIZONA_DSP2_CONTROL_1:
2182 case ARIZONA_DSP2_CLOCKING_1:
2183 case ARIZONA_DSP2_STATUS_1:
2184 case ARIZONA_DSP2_STATUS_2:
2185 case ARIZONA_DSP3_CONTROL_1:
2186 case ARIZONA_DSP3_CLOCKING_1:
2187 case ARIZONA_DSP3_STATUS_1:
2188 case ARIZONA_DSP3_STATUS_2:
2189 case ARIZONA_DSP4_CONTROL_1:
2190 case ARIZONA_DSP4_CLOCKING_1:
2191 case ARIZONA_DSP4_STATUS_1:
2192 case ARIZONA_DSP4_STATUS_2:
2193 return true;
2194 default:
2195 return false;
2196 }
2197}
2198
2199static bool wm5110_volatile_register(struct device *dev, unsigned int reg)
2200{
2201 switch (reg) {
2202 case ARIZONA_SOFTWARE_RESET:
2203 case ARIZONA_DEVICE_REVISION:
2204 case ARIZONA_HAPTICS_STATUS:
2205 case ARIZONA_SAMPLE_RATE_1_STATUS:
2206 case ARIZONA_SAMPLE_RATE_2_STATUS:
2207 case ARIZONA_SAMPLE_RATE_3_STATUS:
2208 case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
2209 case ARIZONA_MIC_DETECT_3:
2210 case ARIZONA_HEADPHONE_DETECT_2:
2211 case ARIZONA_INPUT_ENABLES_STATUS:
2212 case ARIZONA_OUTPUT_STATUS_1:
2213 case ARIZONA_RAW_OUTPUT_STATUS_1:
2214 case ARIZONA_SLIMBUS_RX_PORT_STATUS:
2215 case ARIZONA_SLIMBUS_TX_PORT_STATUS:
2216 case ARIZONA_INTERRUPT_STATUS_1:
2217 case ARIZONA_INTERRUPT_STATUS_2:
2218 case ARIZONA_INTERRUPT_STATUS_3:
2219 case ARIZONA_INTERRUPT_STATUS_4:
2220 case ARIZONA_INTERRUPT_STATUS_5:
2221 case ARIZONA_IRQ2_STATUS_1:
2222 case ARIZONA_IRQ2_STATUS_2:
2223 case ARIZONA_IRQ2_STATUS_3:
2224 case ARIZONA_IRQ2_STATUS_4:
2225 case ARIZONA_IRQ2_STATUS_5:
2226 case ARIZONA_INTERRUPT_RAW_STATUS_2:
2227 case ARIZONA_INTERRUPT_RAW_STATUS_3:
2228 case ARIZONA_INTERRUPT_RAW_STATUS_4:
2229 case ARIZONA_INTERRUPT_RAW_STATUS_5:
2230 case ARIZONA_INTERRUPT_RAW_STATUS_6:
2231 case ARIZONA_INTERRUPT_RAW_STATUS_7:
2232 case ARIZONA_INTERRUPT_RAW_STATUS_8:
2233 case ARIZONA_IRQ_PIN_STATUS:
2234 case ARIZONA_AOD_IRQ1:
2235 case ARIZONA_AOD_IRQ2:
2236 case ARIZONA_ASRC_STATUS:
2237 case ARIZONA_DSP_STATUS:
2238 case ARIZONA_DSP1_CONTROL_1:
2239 case ARIZONA_DSP1_CLOCKING_1:
2240 case ARIZONA_DSP1_STATUS_1:
2241 case ARIZONA_DSP1_STATUS_2:
2242 case ARIZONA_DSP2_STATUS_1:
2243 case ARIZONA_DSP2_STATUS_2:
2244 case ARIZONA_DSP3_STATUS_1:
2245 case ARIZONA_DSP3_STATUS_2:
2246 case ARIZONA_DSP4_STATUS_1:
2247 case ARIZONA_DSP4_STATUS_2:
2248 return true;
2249 default:
2250 return false;
2251 }
2252}
2253
2254const struct regmap_config wm5110_spi_regmap = {
2255 .reg_bits = 32,
2256 .pad_bits = 16,
2257 .val_bits = 16,
2258
2259 .max_register = ARIZONA_DSP1_STATUS_2,
2260 .readable_reg = wm5110_readable_register,
2261 .volatile_reg = wm5110_volatile_register,
2262
2263 .cache_type = REGCACHE_RBTREE,
2264 .reg_defaults = wm5110_reg_default,
2265 .num_reg_defaults = ARRAY_SIZE(wm5110_reg_default),
2266};
2267EXPORT_SYMBOL_GPL(wm5110_spi_regmap);
2268
2269const struct regmap_config wm5110_i2c_regmap = {
2270 .reg_bits = 32,
2271 .val_bits = 16,
2272
2273 .max_register = ARIZONA_DSP1_STATUS_2,
2274 .readable_reg = wm5110_readable_register,
2275 .volatile_reg = wm5110_volatile_register,
2276
2277 .cache_type = REGCACHE_RBTREE,
2278 .reg_defaults = wm5110_reg_default,
2279 .num_reg_defaults = ARRAY_SIZE(wm5110_reg_default),
2280};
2281EXPORT_SYMBOL_GPL(wm5110_i2c_regmap);
diff --git a/drivers/mfd/wm8350-core.c b/drivers/mfd/wm8350-core.c
index 8a9b11ca076a..7c1ae24605d9 100644
--- a/drivers/mfd/wm8350-core.c
+++ b/drivers/mfd/wm8350-core.c
@@ -32,9 +32,6 @@
32#include <linux/mfd/wm8350/supply.h> 32#include <linux/mfd/wm8350/supply.h>
33#include <linux/mfd/wm8350/wdt.h> 33#include <linux/mfd/wm8350/wdt.h>
34 34
35#define WM8350_UNLOCK_KEY 0x0013
36#define WM8350_LOCK_KEY 0x0000
37
38#define WM8350_CLOCK_CONTROL_1 0x28 35#define WM8350_CLOCK_CONTROL_1 0x28
39#define WM8350_AIF_TEST 0x74 36#define WM8350_AIF_TEST 0x74
40 37
@@ -63,181 +60,32 @@
63/* 60/*
64 * WM8350 Device IO 61 * WM8350 Device IO
65 */ 62 */
66static DEFINE_MUTEX(io_mutex);
67static DEFINE_MUTEX(reg_lock_mutex); 63static DEFINE_MUTEX(reg_lock_mutex);
68 64
69/* Perform a physical read from the device.
70 */
71static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
72 u16 *dest)
73{
74 int i, ret;
75 int bytes = num_regs * 2;
76
77 dev_dbg(wm8350->dev, "volatile read\n");
78 ret = regmap_raw_read(wm8350->regmap, reg, dest, bytes);
79
80 for (i = reg; i < reg + num_regs; i++) {
81 /* Cache is CPU endian */
82 dest[i - reg] = be16_to_cpu(dest[i - reg]);
83
84 /* Mask out non-readable bits */
85 dest[i - reg] &= wm8350_reg_io_map[i].readable;
86 }
87
88 dump(num_regs, dest);
89
90 return ret;
91}
92
93static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
94{
95 int i;
96 int end = reg + num_regs;
97 int ret = 0;
98 int bytes = num_regs * 2;
99
100 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
101 dev_err(wm8350->dev, "invalid reg %x\n",
102 reg + num_regs - 1);
103 return -EINVAL;
104 }
105
106 dev_dbg(wm8350->dev,
107 "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
108
109#if WM8350_BUS_DEBUG
110 /* we can _safely_ read any register, but warn if read not supported */
111 for (i = reg; i < end; i++) {
112 if (!wm8350_reg_io_map[i].readable)
113 dev_warn(wm8350->dev,
114 "reg R%d is not readable\n", i);
115 }
116#endif
117
118 /* if any volatile registers are required, then read back all */
119 for (i = reg; i < end; i++)
120 if (wm8350_reg_io_map[i].vol)
121 return wm8350_phys_read(wm8350, reg, num_regs, dest);
122
123 /* no volatiles, then cache is good */
124 dev_dbg(wm8350->dev, "cache read\n");
125 memcpy(dest, &wm8350->reg_cache[reg], bytes);
126 dump(num_regs, dest);
127 return ret;
128}
129
130static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
131{
132 if (reg == WM8350_SECURITY ||
133 wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
134 return 0;
135
136 if ((reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
137 reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
138 (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
139 reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
140 return 1;
141 return 0;
142}
143
144static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
145{
146 int i;
147 int end = reg + num_regs;
148 int bytes = num_regs * 2;
149
150 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
151 dev_err(wm8350->dev, "invalid reg %x\n",
152 reg + num_regs - 1);
153 return -EINVAL;
154 }
155
156 /* it's generally not a good idea to write to RO or locked registers */
157 for (i = reg; i < end; i++) {
158 if (!wm8350_reg_io_map[i].writable) {
159 dev_err(wm8350->dev,
160 "attempted write to read only reg R%d\n", i);
161 return -EINVAL;
162 }
163
164 if (is_reg_locked(wm8350, i)) {
165 dev_err(wm8350->dev,
166 "attempted write to locked reg R%d\n", i);
167 return -EINVAL;
168 }
169
170 src[i - reg] &= wm8350_reg_io_map[i].writable;
171
172 wm8350->reg_cache[i] =
173 (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
174 | src[i - reg];
175
176 src[i - reg] = cpu_to_be16(src[i - reg]);
177 }
178
179 /* Actually write it out */
180 return regmap_raw_write(wm8350->regmap, reg, src, bytes);
181}
182
183/* 65/*
184 * Safe read, modify, write methods 66 * Safe read, modify, write methods
185 */ 67 */
186int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask) 68int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
187{ 69{
188 u16 data; 70 return regmap_update_bits(wm8350->regmap, reg, mask, 0);
189 int err;
190
191 mutex_lock(&io_mutex);
192 err = wm8350_read(wm8350, reg, 1, &data);
193 if (err) {
194 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
195 goto out;
196 }
197
198 data &= ~mask;
199 err = wm8350_write(wm8350, reg, 1, &data);
200 if (err)
201 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
202out:
203 mutex_unlock(&io_mutex);
204 return err;
205} 71}
206EXPORT_SYMBOL_GPL(wm8350_clear_bits); 72EXPORT_SYMBOL_GPL(wm8350_clear_bits);
207 73
208int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask) 74int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
209{ 75{
210 u16 data; 76 return regmap_update_bits(wm8350->regmap, reg, mask, mask);
211 int err;
212
213 mutex_lock(&io_mutex);
214 err = wm8350_read(wm8350, reg, 1, &data);
215 if (err) {
216 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
217 goto out;
218 }
219
220 data |= mask;
221 err = wm8350_write(wm8350, reg, 1, &data);
222 if (err)
223 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
224out:
225 mutex_unlock(&io_mutex);
226 return err;
227} 77}
228EXPORT_SYMBOL_GPL(wm8350_set_bits); 78EXPORT_SYMBOL_GPL(wm8350_set_bits);
229 79
230u16 wm8350_reg_read(struct wm8350 *wm8350, int reg) 80u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
231{ 81{
232 u16 data; 82 unsigned int data;
233 int err; 83 int err;
234 84
235 mutex_lock(&io_mutex); 85 err = regmap_read(wm8350->regmap, reg, &data);
236 err = wm8350_read(wm8350, reg, 1, &data);
237 if (err) 86 if (err)
238 dev_err(wm8350->dev, "read from reg R%d failed\n", reg); 87 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
239 88
240 mutex_unlock(&io_mutex);
241 return data; 89 return data;
242} 90}
243EXPORT_SYMBOL_GPL(wm8350_reg_read); 91EXPORT_SYMBOL_GPL(wm8350_reg_read);
@@ -245,13 +93,11 @@ EXPORT_SYMBOL_GPL(wm8350_reg_read);
245int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val) 93int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
246{ 94{
247 int ret; 95 int ret;
248 u16 data = val;
249 96
250 mutex_lock(&io_mutex); 97 ret = regmap_write(wm8350->regmap, reg, val);
251 ret = wm8350_write(wm8350, reg, 1, &data); 98
252 if (ret) 99 if (ret)
253 dev_err(wm8350->dev, "write to reg R%d failed\n", reg); 100 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
254 mutex_unlock(&io_mutex);
255 return ret; 101 return ret;
256} 102}
257EXPORT_SYMBOL_GPL(wm8350_reg_write); 103EXPORT_SYMBOL_GPL(wm8350_reg_write);
@@ -261,12 +107,11 @@ int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
261{ 107{
262 int err = 0; 108 int err = 0;
263 109
264 mutex_lock(&io_mutex); 110 err = regmap_bulk_read(wm8350->regmap, start_reg, dest, regs);
265 err = wm8350_read(wm8350, start_reg, regs, dest);
266 if (err) 111 if (err)
267 dev_err(wm8350->dev, "block read starting from R%d failed\n", 112 dev_err(wm8350->dev, "block read starting from R%d failed\n",
268 start_reg); 113 start_reg);
269 mutex_unlock(&io_mutex); 114
270 return err; 115 return err;
271} 116}
272EXPORT_SYMBOL_GPL(wm8350_block_read); 117EXPORT_SYMBOL_GPL(wm8350_block_read);
@@ -276,12 +121,11 @@ int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
276{ 121{
277 int ret = 0; 122 int ret = 0;
278 123
279 mutex_lock(&io_mutex); 124 ret = regmap_bulk_write(wm8350->regmap, start_reg, src, regs);
280 ret = wm8350_write(wm8350, start_reg, regs, src);
281 if (ret) 125 if (ret)
282 dev_err(wm8350->dev, "block write starting at R%d failed\n", 126 dev_err(wm8350->dev, "block write starting at R%d failed\n",
283 start_reg); 127 start_reg);
284 mutex_unlock(&io_mutex); 128
285 return ret; 129 return ret;
286} 130}
287EXPORT_SYMBOL_GPL(wm8350_block_write); 131EXPORT_SYMBOL_GPL(wm8350_block_write);
@@ -295,15 +139,20 @@ EXPORT_SYMBOL_GPL(wm8350_block_write);
295 */ 139 */
296int wm8350_reg_lock(struct wm8350 *wm8350) 140int wm8350_reg_lock(struct wm8350 *wm8350)
297{ 141{
298 u16 key = WM8350_LOCK_KEY;
299 int ret; 142 int ret;
300 143
144 mutex_lock(&reg_lock_mutex);
145
301 ldbg(__func__); 146 ldbg(__func__);
302 mutex_lock(&io_mutex); 147
303 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key); 148 ret = wm8350_reg_write(wm8350, WM8350_SECURITY, WM8350_LOCK_KEY);
304 if (ret) 149 if (ret)
305 dev_err(wm8350->dev, "lock failed\n"); 150 dev_err(wm8350->dev, "lock failed\n");
306 mutex_unlock(&io_mutex); 151
152 wm8350->unlocked = false;
153
154 mutex_unlock(&reg_lock_mutex);
155
307 return ret; 156 return ret;
308} 157}
309EXPORT_SYMBOL_GPL(wm8350_reg_lock); 158EXPORT_SYMBOL_GPL(wm8350_reg_lock);
@@ -319,15 +168,20 @@ EXPORT_SYMBOL_GPL(wm8350_reg_lock);
319 */ 168 */
320int wm8350_reg_unlock(struct wm8350 *wm8350) 169int wm8350_reg_unlock(struct wm8350 *wm8350)
321{ 170{
322 u16 key = WM8350_UNLOCK_KEY;
323 int ret; 171 int ret;
324 172
173 mutex_lock(&reg_lock_mutex);
174
325 ldbg(__func__); 175 ldbg(__func__);
326 mutex_lock(&io_mutex); 176
327 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key); 177 ret = wm8350_reg_write(wm8350, WM8350_SECURITY, WM8350_UNLOCK_KEY);
328 if (ret) 178 if (ret)
329 dev_err(wm8350->dev, "unlock failed\n"); 179 dev_err(wm8350->dev, "unlock failed\n");
330 mutex_unlock(&io_mutex); 180
181 wm8350->unlocked = true;
182
183 mutex_unlock(&reg_lock_mutex);
184
331 return ret; 185 return ret;
332} 186}
333EXPORT_SYMBOL_GPL(wm8350_reg_unlock); 187EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
@@ -395,146 +249,6 @@ static irqreturn_t wm8350_auxadc_irq(int irq, void *irq_data)
395} 249}
396 250
397/* 251/*
398 * Cache is always host endian.
399 */
400static int wm8350_create_cache(struct wm8350 *wm8350, int type, int mode)
401{
402 int i, ret = 0;
403 u16 value;
404 const u16 *reg_map;
405
406 switch (type) {
407 case 0:
408 switch (mode) {
409#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
410 case 0:
411 reg_map = wm8350_mode0_defaults;
412 break;
413#endif
414#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
415 case 1:
416 reg_map = wm8350_mode1_defaults;
417 break;
418#endif
419#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
420 case 2:
421 reg_map = wm8350_mode2_defaults;
422 break;
423#endif
424#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
425 case 3:
426 reg_map = wm8350_mode3_defaults;
427 break;
428#endif
429 default:
430 dev_err(wm8350->dev,
431 "WM8350 configuration mode %d not supported\n",
432 mode);
433 return -EINVAL;
434 }
435 break;
436
437 case 1:
438 switch (mode) {
439#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_0
440 case 0:
441 reg_map = wm8351_mode0_defaults;
442 break;
443#endif
444#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_1
445 case 1:
446 reg_map = wm8351_mode1_defaults;
447 break;
448#endif
449#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_2
450 case 2:
451 reg_map = wm8351_mode2_defaults;
452 break;
453#endif
454#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_3
455 case 3:
456 reg_map = wm8351_mode3_defaults;
457 break;
458#endif
459 default:
460 dev_err(wm8350->dev,
461 "WM8351 configuration mode %d not supported\n",
462 mode);
463 return -EINVAL;
464 }
465 break;
466
467 case 2:
468 switch (mode) {
469#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_0
470 case 0:
471 reg_map = wm8352_mode0_defaults;
472 break;
473#endif
474#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_1
475 case 1:
476 reg_map = wm8352_mode1_defaults;
477 break;
478#endif
479#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_2
480 case 2:
481 reg_map = wm8352_mode2_defaults;
482 break;
483#endif
484#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_3
485 case 3:
486 reg_map = wm8352_mode3_defaults;
487 break;
488#endif
489 default:
490 dev_err(wm8350->dev,
491 "WM8352 configuration mode %d not supported\n",
492 mode);
493 return -EINVAL;
494 }
495 break;
496
497 default:
498 dev_err(wm8350->dev,
499 "WM835x configuration mode %d not supported\n",
500 mode);
501 return -EINVAL;
502 }
503
504 wm8350->reg_cache =
505 kmalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
506 if (wm8350->reg_cache == NULL)
507 return -ENOMEM;
508
509 /* Read the initial cache state back from the device - this is
510 * a PMIC so the device many not be in a virgin state and we
511 * can't rely on the silicon values.
512 */
513 ret = regmap_raw_read(wm8350->regmap, 0, wm8350->reg_cache,
514 sizeof(u16) * (WM8350_MAX_REGISTER + 1));
515 if (ret < 0) {
516 dev_err(wm8350->dev,
517 "failed to read initial cache values\n");
518 goto out;
519 }
520
521 /* Mask out uncacheable/unreadable bits and the audio. */
522 for (i = 0; i < WM8350_MAX_REGISTER; i++) {
523 if (wm8350_reg_io_map[i].readable &&
524 (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
525 value = be16_to_cpu(wm8350->reg_cache[i]);
526 value &= wm8350_reg_io_map[i].readable;
527 wm8350->reg_cache[i] = value;
528 } else
529 wm8350->reg_cache[i] = reg_map[i];
530 }
531
532out:
533 kfree(wm8350->reg_cache);
534 return ret;
535}
536
537/*
538 * Register a client device. This is non-fatal since there is no need to 252 * Register a client device. This is non-fatal since there is no need to
539 * fail the entire device init due to a single platform device failing. 253 * fail the entire device init due to a single platform device failing.
540 */ 254 */
@@ -681,18 +395,12 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
681 goto err; 395 goto err;
682 } 396 }
683 397
684 ret = wm8350_create_cache(wm8350, mask_rev, mode);
685 if (ret < 0) {
686 dev_err(wm8350->dev, "Failed to create register cache\n");
687 return ret;
688 }
689
690 mutex_init(&wm8350->auxadc_mutex); 398 mutex_init(&wm8350->auxadc_mutex);
691 init_completion(&wm8350->auxadc_done); 399 init_completion(&wm8350->auxadc_done);
692 400
693 ret = wm8350_irq_init(wm8350, irq, pdata); 401 ret = wm8350_irq_init(wm8350, irq, pdata);
694 if (ret < 0) 402 if (ret < 0)
695 goto err_free; 403 goto err;
696 404
697 if (wm8350->irq_base) { 405 if (wm8350->irq_base) {
698 ret = request_threaded_irq(wm8350->irq_base + 406 ret = request_threaded_irq(wm8350->irq_base +
@@ -730,8 +438,6 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
730 438
731err_irq: 439err_irq:
732 wm8350_irq_exit(wm8350); 440 wm8350_irq_exit(wm8350);
733err_free:
734 kfree(wm8350->reg_cache);
735err: 441err:
736 return ret; 442 return ret;
737} 443}
@@ -758,8 +464,6 @@ void wm8350_device_exit(struct wm8350 *wm8350)
758 free_irq(wm8350->irq_base + WM8350_IRQ_AUXADC_DATARDY, wm8350); 464 free_irq(wm8350->irq_base + WM8350_IRQ_AUXADC_DATARDY, wm8350);
759 465
760 wm8350_irq_exit(wm8350); 466 wm8350_irq_exit(wm8350);
761
762 kfree(wm8350->reg_cache);
763} 467}
764EXPORT_SYMBOL_GPL(wm8350_device_exit); 468EXPORT_SYMBOL_GPL(wm8350_device_exit);
765 469
diff --git a/drivers/mfd/wm8350-i2c.c b/drivers/mfd/wm8350-i2c.c
index a68aceb4e48c..2e57101c8d3d 100644
--- a/drivers/mfd/wm8350-i2c.c
+++ b/drivers/mfd/wm8350-i2c.c
@@ -23,11 +23,6 @@
23#include <linux/regmap.h> 23#include <linux/regmap.h>
24#include <linux/slab.h> 24#include <linux/slab.h>
25 25
26static const struct regmap_config wm8350_regmap = {
27 .reg_bits = 8,
28 .val_bits = 16,
29};
30
31static int wm8350_i2c_probe(struct i2c_client *i2c, 26static int wm8350_i2c_probe(struct i2c_client *i2c,
32 const struct i2c_device_id *id) 27 const struct i2c_device_id *id)
33{ 28{
diff --git a/drivers/mfd/wm8350-irq.c b/drivers/mfd/wm8350-irq.c
index 9fd01bf63c51..624ff90501cd 100644
--- a/drivers/mfd/wm8350-irq.c
+++ b/drivers/mfd/wm8350-irq.c
@@ -432,11 +432,9 @@ static void wm8350_irq_sync_unlock(struct irq_data *data)
432 for (i = 0; i < ARRAY_SIZE(wm8350->irq_masks); i++) { 432 for (i = 0; i < ARRAY_SIZE(wm8350->irq_masks); i++) {
433 /* If there's been a change in the mask write it back 433 /* If there's been a change in the mask write it back
434 * to the hardware. */ 434 * to the hardware. */
435 if (wm8350->irq_masks[i] != 435 WARN_ON(regmap_update_bits(wm8350->regmap,
436 wm8350->reg_cache[WM8350_INT_STATUS_1_MASK + i]) 436 WM8350_INT_STATUS_1_MASK + i,
437 WARN_ON(wm8350_reg_write(wm8350, 437 0xffff, wm8350->irq_masks[i]));
438 WM8350_INT_STATUS_1_MASK + i,
439 wm8350->irq_masks[i]));
440 } 438 }
441 439
442 mutex_unlock(&wm8350->irq_lock); 440 mutex_unlock(&wm8350->irq_lock);
diff --git a/drivers/mfd/wm8350-regmap.c b/drivers/mfd/wm8350-regmap.c
index e965139e5cd5..9efc64750fb6 100644
--- a/drivers/mfd/wm8350-regmap.c
+++ b/drivers/mfd/wm8350-regmap.c
@@ -14,3170 +14,18 @@
14 14
15#include <linux/mfd/wm8350/core.h> 15#include <linux/mfd/wm8350/core.h>
16 16
17#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
18
19#undef WM8350_HAVE_CONFIG_MODE
20#define WM8350_HAVE_CONFIG_MODE
21
22const u16 wm8350_mode0_defaults[] = {
23 0x17FF, /* R0 - Reset/ID */
24 0x1000, /* R1 - ID */
25 0x0000, /* R2 */
26 0x1002, /* R3 - System Control 1 */
27 0x0004, /* R4 - System Control 2 */
28 0x0000, /* R5 - System Hibernate */
29 0x8A00, /* R6 - Interface Control */
30 0x0000, /* R7 */
31 0x8000, /* R8 - Power mgmt (1) */
32 0x0000, /* R9 - Power mgmt (2) */
33 0x0000, /* R10 - Power mgmt (3) */
34 0x2000, /* R11 - Power mgmt (4) */
35 0x0E00, /* R12 - Power mgmt (5) */
36 0x0000, /* R13 - Power mgmt (6) */
37 0x0000, /* R14 - Power mgmt (7) */
38 0x0000, /* R15 */
39 0x0000, /* R16 - RTC Seconds/Minutes */
40 0x0100, /* R17 - RTC Hours/Day */
41 0x0101, /* R18 - RTC Date/Month */
42 0x1400, /* R19 - RTC Year */
43 0x0000, /* R20 - Alarm Seconds/Minutes */
44 0x0000, /* R21 - Alarm Hours/Day */
45 0x0000, /* R22 - Alarm Date/Month */
46 0x0320, /* R23 - RTC Time Control */
47 0x0000, /* R24 - System Interrupts */
48 0x0000, /* R25 - Interrupt Status 1 */
49 0x0000, /* R26 - Interrupt Status 2 */
50 0x0000, /* R27 - Power Up Interrupt Status */
51 0x0000, /* R28 - Under Voltage Interrupt status */
52 0x0000, /* R29 - Over Current Interrupt status */
53 0x0000, /* R30 - GPIO Interrupt Status */
54 0x0000, /* R31 - Comparator Interrupt Status */
55 0x3FFF, /* R32 - System Interrupts Mask */
56 0x0000, /* R33 - Interrupt Status 1 Mask */
57 0x0000, /* R34 - Interrupt Status 2 Mask */
58 0x0000, /* R35 - Power Up Interrupt Status Mask */
59 0x0000, /* R36 - Under Voltage Interrupt status Mask */
60 0x0000, /* R37 - Over Current Interrupt status Mask */
61 0x0000, /* R38 - GPIO Interrupt Status Mask */
62 0x0000, /* R39 - Comparator Interrupt Status Mask */
63 0x0040, /* R40 - Clock Control 1 */
64 0x0000, /* R41 - Clock Control 2 */
65 0x3B00, /* R42 - FLL Control 1 */
66 0x7086, /* R43 - FLL Control 2 */
67 0xC226, /* R44 - FLL Control 3 */
68 0x0000, /* R45 - FLL Control 4 */
69 0x0000, /* R46 */
70 0x0000, /* R47 */
71 0x0000, /* R48 - DAC Control */
72 0x0000, /* R49 */
73 0x00C0, /* R50 - DAC Digital Volume L */
74 0x00C0, /* R51 - DAC Digital Volume R */
75 0x0000, /* R52 */
76 0x0040, /* R53 - DAC LR Rate */
77 0x0000, /* R54 - DAC Clock Control */
78 0x0000, /* R55 */
79 0x0000, /* R56 */
80 0x0000, /* R57 */
81 0x4000, /* R58 - DAC Mute */
82 0x0000, /* R59 - DAC Mute Volume */
83 0x0000, /* R60 - DAC Side */
84 0x0000, /* R61 */
85 0x0000, /* R62 */
86 0x0000, /* R63 */
87 0x8000, /* R64 - ADC Control */
88 0x0000, /* R65 */
89 0x00C0, /* R66 - ADC Digital Volume L */
90 0x00C0, /* R67 - ADC Digital Volume R */
91 0x0000, /* R68 - ADC Divider */
92 0x0000, /* R69 */
93 0x0040, /* R70 - ADC LR Rate */
94 0x0000, /* R71 */
95 0x0303, /* R72 - Input Control */
96 0x0000, /* R73 - IN3 Input Control */
97 0x0000, /* R74 - Mic Bias Control */
98 0x0000, /* R75 */
99 0x0000, /* R76 - Output Control */
100 0x0000, /* R77 - Jack Detect */
101 0x0000, /* R78 - Anti Pop Control */
102 0x0000, /* R79 */
103 0x0040, /* R80 - Left Input Volume */
104 0x0040, /* R81 - Right Input Volume */
105 0x0000, /* R82 */
106 0x0000, /* R83 */
107 0x0000, /* R84 */
108 0x0000, /* R85 */
109 0x0000, /* R86 */
110 0x0000, /* R87 */
111 0x0800, /* R88 - Left Mixer Control */
112 0x1000, /* R89 - Right Mixer Control */
113 0x0000, /* R90 */
114 0x0000, /* R91 */
115 0x0000, /* R92 - OUT3 Mixer Control */
116 0x0000, /* R93 - OUT4 Mixer Control */
117 0x0000, /* R94 */
118 0x0000, /* R95 */
119 0x0000, /* R96 - Output Left Mixer Volume */
120 0x0000, /* R97 - Output Right Mixer Volume */
121 0x0000, /* R98 - Input Mixer Volume L */
122 0x0000, /* R99 - Input Mixer Volume R */
123 0x0000, /* R100 - Input Mixer Volume */
124 0x0000, /* R101 */
125 0x0000, /* R102 */
126 0x0000, /* R103 */
127 0x00E4, /* R104 - LOUT1 Volume */
128 0x00E4, /* R105 - ROUT1 Volume */
129 0x00E4, /* R106 - LOUT2 Volume */
130 0x02E4, /* R107 - ROUT2 Volume */
131 0x0000, /* R108 */
132 0x0000, /* R109 */
133 0x0000, /* R110 */
134 0x0000, /* R111 - BEEP Volume */
135 0x0A00, /* R112 - AI Formating */
136 0x0000, /* R113 - ADC DAC COMP */
137 0x0020, /* R114 - AI ADC Control */
138 0x0020, /* R115 - AI DAC Control */
139 0x0000, /* R116 - AIF Test */
140 0x0000, /* R117 */
141 0x0000, /* R118 */
142 0x0000, /* R119 */
143 0x0000, /* R120 */
144 0x0000, /* R121 */
145 0x0000, /* R122 */
146 0x0000, /* R123 */
147 0x0000, /* R124 */
148 0x0000, /* R125 */
149 0x0000, /* R126 */
150 0x0000, /* R127 */
151 0x1FFF, /* R128 - GPIO Debounce */
152 0x0000, /* R129 - GPIO Pin pull up Control */
153 0x03FC, /* R130 - GPIO Pull down Control */
154 0x0000, /* R131 - GPIO Interrupt Mode */
155 0x0000, /* R132 */
156 0x0000, /* R133 - GPIO Control */
157 0x0FFC, /* R134 - GPIO Configuration (i/o) */
158 0x0FFC, /* R135 - GPIO Pin Polarity / Type */
159 0x0000, /* R136 */
160 0x0000, /* R137 */
161 0x0000, /* R138 */
162 0x0000, /* R139 */
163 0x0013, /* R140 - GPIO Function Select 1 */
164 0x0000, /* R141 - GPIO Function Select 2 */
165 0x0000, /* R142 - GPIO Function Select 3 */
166 0x0003, /* R143 - GPIO Function Select 4 */
167 0x0000, /* R144 - Digitiser Control (1) */
168 0x0002, /* R145 - Digitiser Control (2) */
169 0x0000, /* R146 */
170 0x0000, /* R147 */
171 0x0000, /* R148 */
172 0x0000, /* R149 */
173 0x0000, /* R150 */
174 0x0000, /* R151 */
175 0x7000, /* R152 - AUX1 Readback */
176 0x7000, /* R153 - AUX2 Readback */
177 0x7000, /* R154 - AUX3 Readback */
178 0x7000, /* R155 - AUX4 Readback */
179 0x0000, /* R156 - USB Voltage Readback */
180 0x0000, /* R157 - LINE Voltage Readback */
181 0x0000, /* R158 - BATT Voltage Readback */
182 0x0000, /* R159 - Chip Temp Readback */
183 0x0000, /* R160 */
184 0x0000, /* R161 */
185 0x0000, /* R162 */
186 0x0000, /* R163 - Generic Comparator Control */
187 0x0000, /* R164 - Generic comparator 1 */
188 0x0000, /* R165 - Generic comparator 2 */
189 0x0000, /* R166 - Generic comparator 3 */
190 0x0000, /* R167 - Generic comparator 4 */
191 0xA00F, /* R168 - Battery Charger Control 1 */
192 0x0B06, /* R169 - Battery Charger Control 2 */
193 0x0000, /* R170 - Battery Charger Control 3 */
194 0x0000, /* R171 */
195 0x0000, /* R172 - Current Sink Driver A */
196 0x0000, /* R173 - CSA Flash control */
197 0x0000, /* R174 - Current Sink Driver B */
198 0x0000, /* R175 - CSB Flash control */
199 0x0000, /* R176 - DCDC/LDO requested */
200 0x002D, /* R177 - DCDC Active options */
201 0x0000, /* R178 - DCDC Sleep options */
202 0x0025, /* R179 - Power-check comparator */
203 0x000E, /* R180 - DCDC1 Control */
204 0x0000, /* R181 - DCDC1 Timeouts */
205 0x1006, /* R182 - DCDC1 Low Power */
206 0x0018, /* R183 - DCDC2 Control */
207 0x0000, /* R184 - DCDC2 Timeouts */
208 0x0000, /* R185 */
209 0x0000, /* R186 - DCDC3 Control */
210 0x0000, /* R187 - DCDC3 Timeouts */
211 0x0006, /* R188 - DCDC3 Low Power */
212 0x0000, /* R189 - DCDC4 Control */
213 0x0000, /* R190 - DCDC4 Timeouts */
214 0x0006, /* R191 - DCDC4 Low Power */
215 0x0008, /* R192 - DCDC5 Control */
216 0x0000, /* R193 - DCDC5 Timeouts */
217 0x0000, /* R194 */
218 0x0000, /* R195 - DCDC6 Control */
219 0x0000, /* R196 - DCDC6 Timeouts */
220 0x0006, /* R197 - DCDC6 Low Power */
221 0x0000, /* R198 */
222 0x0003, /* R199 - Limit Switch Control */
223 0x001C, /* R200 - LDO1 Control */
224 0x0000, /* R201 - LDO1 Timeouts */
225 0x001C, /* R202 - LDO1 Low Power */
226 0x001B, /* R203 - LDO2 Control */
227 0x0000, /* R204 - LDO2 Timeouts */
228 0x001C, /* R205 - LDO2 Low Power */
229 0x001B, /* R206 - LDO3 Control */
230 0x0000, /* R207 - LDO3 Timeouts */
231 0x001C, /* R208 - LDO3 Low Power */
232 0x001B, /* R209 - LDO4 Control */
233 0x0000, /* R210 - LDO4 Timeouts */
234 0x001C, /* R211 - LDO4 Low Power */
235 0x0000, /* R212 */
236 0x0000, /* R213 */
237 0x0000, /* R214 */
238 0x0000, /* R215 - VCC_FAULT Masks */
239 0x001F, /* R216 - Main Bandgap Control */
240 0x0000, /* R217 - OSC Control */
241 0x9000, /* R218 - RTC Tick Control */
242 0x0000, /* R219 */
243 0x4000, /* R220 - RAM BIST 1 */
244 0x0000, /* R221 */
245 0x0000, /* R222 */
246 0x0000, /* R223 */
247 0x0000, /* R224 */
248 0x0000, /* R225 - DCDC/LDO status */
249 0x0000, /* R226 */
250 0x0000, /* R227 */
251 0x0000, /* R228 */
252 0x0000, /* R229 */
253 0xE000, /* R230 - GPIO Pin Status */
254 0x0000, /* R231 */
255 0x0000, /* R232 */
256 0x0000, /* R233 */
257 0x0000, /* R234 */
258 0x0000, /* R235 */
259 0x0000, /* R236 */
260 0x0000, /* R237 */
261 0x0000, /* R238 */
262 0x0000, /* R239 */
263 0x0000, /* R240 */
264 0x0000, /* R241 */
265 0x0000, /* R242 */
266 0x0000, /* R243 */
267 0x0000, /* R244 */
268 0x0000, /* R245 */
269 0x0000, /* R246 */
270 0x0000, /* R247 */
271 0x0000, /* R248 */
272 0x0000, /* R249 */
273 0x0000, /* R250 */
274 0x0000, /* R251 */
275 0x0000, /* R252 */
276 0x0000, /* R253 */
277 0x0000, /* R254 */
278 0x0000, /* R255 */
279};
280#endif
281
282#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
283
284#undef WM8350_HAVE_CONFIG_MODE
285#define WM8350_HAVE_CONFIG_MODE
286
287const u16 wm8350_mode1_defaults[] = {
288 0x17FF, /* R0 - Reset/ID */
289 0x1000, /* R1 - ID */
290 0x0000, /* R2 */
291 0x1002, /* R3 - System Control 1 */
292 0x0014, /* R4 - System Control 2 */
293 0x0000, /* R5 - System Hibernate */
294 0x8A00, /* R6 - Interface Control */
295 0x0000, /* R7 */
296 0x8000, /* R8 - Power mgmt (1) */
297 0x0000, /* R9 - Power mgmt (2) */
298 0x0000, /* R10 - Power mgmt (3) */
299 0x2000, /* R11 - Power mgmt (4) */
300 0x0E00, /* R12 - Power mgmt (5) */
301 0x0000, /* R13 - Power mgmt (6) */
302 0x0000, /* R14 - Power mgmt (7) */
303 0x0000, /* R15 */
304 0x0000, /* R16 - RTC Seconds/Minutes */
305 0x0100, /* R17 - RTC Hours/Day */
306 0x0101, /* R18 - RTC Date/Month */
307 0x1400, /* R19 - RTC Year */
308 0x0000, /* R20 - Alarm Seconds/Minutes */
309 0x0000, /* R21 - Alarm Hours/Day */
310 0x0000, /* R22 - Alarm Date/Month */
311 0x0320, /* R23 - RTC Time Control */
312 0x0000, /* R24 - System Interrupts */
313 0x0000, /* R25 - Interrupt Status 1 */
314 0x0000, /* R26 - Interrupt Status 2 */
315 0x0000, /* R27 - Power Up Interrupt Status */
316 0x0000, /* R28 - Under Voltage Interrupt status */
317 0x0000, /* R29 - Over Current Interrupt status */
318 0x0000, /* R30 - GPIO Interrupt Status */
319 0x0000, /* R31 - Comparator Interrupt Status */
320 0x3FFF, /* R32 - System Interrupts Mask */
321 0x0000, /* R33 - Interrupt Status 1 Mask */
322 0x0000, /* R34 - Interrupt Status 2 Mask */
323 0x0000, /* R35 - Power Up Interrupt Status Mask */
324 0x0000, /* R36 - Under Voltage Interrupt status Mask */
325 0x0000, /* R37 - Over Current Interrupt status Mask */
326 0x0000, /* R38 - GPIO Interrupt Status Mask */
327 0x0000, /* R39 - Comparator Interrupt Status Mask */
328 0x0040, /* R40 - Clock Control 1 */
329 0x0000, /* R41 - Clock Control 2 */
330 0x3B00, /* R42 - FLL Control 1 */
331 0x7086, /* R43 - FLL Control 2 */
332 0xC226, /* R44 - FLL Control 3 */
333 0x0000, /* R45 - FLL Control 4 */
334 0x0000, /* R46 */
335 0x0000, /* R47 */
336 0x0000, /* R48 - DAC Control */
337 0x0000, /* R49 */
338 0x00C0, /* R50 - DAC Digital Volume L */
339 0x00C0, /* R51 - DAC Digital Volume R */
340 0x0000, /* R52 */
341 0x0040, /* R53 - DAC LR Rate */
342 0x0000, /* R54 - DAC Clock Control */
343 0x0000, /* R55 */
344 0x0000, /* R56 */
345 0x0000, /* R57 */
346 0x4000, /* R58 - DAC Mute */
347 0x0000, /* R59 - DAC Mute Volume */
348 0x0000, /* R60 - DAC Side */
349 0x0000, /* R61 */
350 0x0000, /* R62 */
351 0x0000, /* R63 */
352 0x8000, /* R64 - ADC Control */
353 0x0000, /* R65 */
354 0x00C0, /* R66 - ADC Digital Volume L */
355 0x00C0, /* R67 - ADC Digital Volume R */
356 0x0000, /* R68 - ADC Divider */
357 0x0000, /* R69 */
358 0x0040, /* R70 - ADC LR Rate */
359 0x0000, /* R71 */
360 0x0303, /* R72 - Input Control */
361 0x0000, /* R73 - IN3 Input Control */
362 0x0000, /* R74 - Mic Bias Control */
363 0x0000, /* R75 */
364 0x0000, /* R76 - Output Control */
365 0x0000, /* R77 - Jack Detect */
366 0x0000, /* R78 - Anti Pop Control */
367 0x0000, /* R79 */
368 0x0040, /* R80 - Left Input Volume */
369 0x0040, /* R81 - Right Input Volume */
370 0x0000, /* R82 */
371 0x0000, /* R83 */
372 0x0000, /* R84 */
373 0x0000, /* R85 */
374 0x0000, /* R86 */
375 0x0000, /* R87 */
376 0x0800, /* R88 - Left Mixer Control */
377 0x1000, /* R89 - Right Mixer Control */
378 0x0000, /* R90 */
379 0x0000, /* R91 */
380 0x0000, /* R92 - OUT3 Mixer Control */
381 0x0000, /* R93 - OUT4 Mixer Control */
382 0x0000, /* R94 */
383 0x0000, /* R95 */
384 0x0000, /* R96 - Output Left Mixer Volume */
385 0x0000, /* R97 - Output Right Mixer Volume */
386 0x0000, /* R98 - Input Mixer Volume L */
387 0x0000, /* R99 - Input Mixer Volume R */
388 0x0000, /* R100 - Input Mixer Volume */
389 0x0000, /* R101 */
390 0x0000, /* R102 */
391 0x0000, /* R103 */
392 0x00E4, /* R104 - LOUT1 Volume */
393 0x00E4, /* R105 - ROUT1 Volume */
394 0x00E4, /* R106 - LOUT2 Volume */
395 0x02E4, /* R107 - ROUT2 Volume */
396 0x0000, /* R108 */
397 0x0000, /* R109 */
398 0x0000, /* R110 */
399 0x0000, /* R111 - BEEP Volume */
400 0x0A00, /* R112 - AI Formating */
401 0x0000, /* R113 - ADC DAC COMP */
402 0x0020, /* R114 - AI ADC Control */
403 0x0020, /* R115 - AI DAC Control */
404 0x0000, /* R116 - AIF Test */
405 0x0000, /* R117 */
406 0x0000, /* R118 */
407 0x0000, /* R119 */
408 0x0000, /* R120 */
409 0x0000, /* R121 */
410 0x0000, /* R122 */
411 0x0000, /* R123 */
412 0x0000, /* R124 */
413 0x0000, /* R125 */
414 0x0000, /* R126 */
415 0x0000, /* R127 */
416 0x1FFF, /* R128 - GPIO Debounce */
417 0x0000, /* R129 - GPIO Pin pull up Control */
418 0x03FC, /* R130 - GPIO Pull down Control */
419 0x0000, /* R131 - GPIO Interrupt Mode */
420 0x0000, /* R132 */
421 0x0000, /* R133 - GPIO Control */
422 0x00FB, /* R134 - GPIO Configuration (i/o) */
423 0x04FE, /* R135 - GPIO Pin Polarity / Type */
424 0x0000, /* R136 */
425 0x0000, /* R137 */
426 0x0000, /* R138 */
427 0x0000, /* R139 */
428 0x0312, /* R140 - GPIO Function Select 1 */
429 0x1003, /* R141 - GPIO Function Select 2 */
430 0x1331, /* R142 - GPIO Function Select 3 */
431 0x0003, /* R143 - GPIO Function Select 4 */
432 0x0000, /* R144 - Digitiser Control (1) */
433 0x0002, /* R145 - Digitiser Control (2) */
434 0x0000, /* R146 */
435 0x0000, /* R147 */
436 0x0000, /* R148 */
437 0x0000, /* R149 */
438 0x0000, /* R150 */
439 0x0000, /* R151 */
440 0x7000, /* R152 - AUX1 Readback */
441 0x7000, /* R153 - AUX2 Readback */
442 0x7000, /* R154 - AUX3 Readback */
443 0x7000, /* R155 - AUX4 Readback */
444 0x0000, /* R156 - USB Voltage Readback */
445 0x0000, /* R157 - LINE Voltage Readback */
446 0x0000, /* R158 - BATT Voltage Readback */
447 0x0000, /* R159 - Chip Temp Readback */
448 0x0000, /* R160 */
449 0x0000, /* R161 */
450 0x0000, /* R162 */
451 0x0000, /* R163 - Generic Comparator Control */
452 0x0000, /* R164 - Generic comparator 1 */
453 0x0000, /* R165 - Generic comparator 2 */
454 0x0000, /* R166 - Generic comparator 3 */
455 0x0000, /* R167 - Generic comparator 4 */
456 0xA00F, /* R168 - Battery Charger Control 1 */
457 0x0B06, /* R169 - Battery Charger Control 2 */
458 0x0000, /* R170 - Battery Charger Control 3 */
459 0x0000, /* R171 */
460 0x0000, /* R172 - Current Sink Driver A */
461 0x0000, /* R173 - CSA Flash control */
462 0x0000, /* R174 - Current Sink Driver B */
463 0x0000, /* R175 - CSB Flash control */
464 0x0000, /* R176 - DCDC/LDO requested */
465 0x002D, /* R177 - DCDC Active options */
466 0x0000, /* R178 - DCDC Sleep options */
467 0x0025, /* R179 - Power-check comparator */
468 0x0062, /* R180 - DCDC1 Control */
469 0x0400, /* R181 - DCDC1 Timeouts */
470 0x1006, /* R182 - DCDC1 Low Power */
471 0x0018, /* R183 - DCDC2 Control */
472 0x0000, /* R184 - DCDC2 Timeouts */
473 0x0000, /* R185 */
474 0x0026, /* R186 - DCDC3 Control */
475 0x0400, /* R187 - DCDC3 Timeouts */
476 0x0006, /* R188 - DCDC3 Low Power */
477 0x0062, /* R189 - DCDC4 Control */
478 0x0400, /* R190 - DCDC4 Timeouts */
479 0x0006, /* R191 - DCDC4 Low Power */
480 0x0008, /* R192 - DCDC5 Control */
481 0x0000, /* R193 - DCDC5 Timeouts */
482 0x0000, /* R194 */
483 0x0026, /* R195 - DCDC6 Control */
484 0x0800, /* R196 - DCDC6 Timeouts */
485 0x0006, /* R197 - DCDC6 Low Power */
486 0x0000, /* R198 */
487 0x0003, /* R199 - Limit Switch Control */
488 0x0006, /* R200 - LDO1 Control */
489 0x0400, /* R201 - LDO1 Timeouts */
490 0x001C, /* R202 - LDO1 Low Power */
491 0x0006, /* R203 - LDO2 Control */
492 0x0400, /* R204 - LDO2 Timeouts */
493 0x001C, /* R205 - LDO2 Low Power */
494 0x001B, /* R206 - LDO3 Control */
495 0x0000, /* R207 - LDO3 Timeouts */
496 0x001C, /* R208 - LDO3 Low Power */
497 0x001B, /* R209 - LDO4 Control */
498 0x0000, /* R210 - LDO4 Timeouts */
499 0x001C, /* R211 - LDO4 Low Power */
500 0x0000, /* R212 */
501 0x0000, /* R213 */
502 0x0000, /* R214 */
503 0x0000, /* R215 - VCC_FAULT Masks */
504 0x001F, /* R216 - Main Bandgap Control */
505 0x0000, /* R217 - OSC Control */
506 0x9000, /* R218 - RTC Tick Control */
507 0x0000, /* R219 */
508 0x4000, /* R220 - RAM BIST 1 */
509 0x0000, /* R221 */
510 0x0000, /* R222 */
511 0x0000, /* R223 */
512 0x0000, /* R224 */
513 0x0000, /* R225 - DCDC/LDO status */
514 0x0000, /* R226 */
515 0x0000, /* R227 */
516 0x0000, /* R228 */
517 0x0000, /* R229 */
518 0xE000, /* R230 - GPIO Pin Status */
519 0x0000, /* R231 */
520 0x0000, /* R232 */
521 0x0000, /* R233 */
522 0x0000, /* R234 */
523 0x0000, /* R235 */
524 0x0000, /* R236 */
525 0x0000, /* R237 */
526 0x0000, /* R238 */
527 0x0000, /* R239 */
528 0x0000, /* R240 */
529 0x0000, /* R241 */
530 0x0000, /* R242 */
531 0x0000, /* R243 */
532 0x0000, /* R244 */
533 0x0000, /* R245 */
534 0x0000, /* R246 */
535 0x0000, /* R247 */
536 0x0000, /* R248 */
537 0x0000, /* R249 */
538 0x0000, /* R250 */
539 0x0000, /* R251 */
540 0x0000, /* R252 */
541 0x0000, /* R253 */
542 0x0000, /* R254 */
543 0x0000, /* R255 */
544};
545#endif
546
547#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
548
549#undef WM8350_HAVE_CONFIG_MODE
550#define WM8350_HAVE_CONFIG_MODE
551
552const u16 wm8350_mode2_defaults[] = {
553 0x17FF, /* R0 - Reset/ID */
554 0x1000, /* R1 - ID */
555 0x0000, /* R2 */
556 0x1002, /* R3 - System Control 1 */
557 0x0014, /* R4 - System Control 2 */
558 0x0000, /* R5 - System Hibernate */
559 0x8A00, /* R6 - Interface Control */
560 0x0000, /* R7 */
561 0x8000, /* R8 - Power mgmt (1) */
562 0x0000, /* R9 - Power mgmt (2) */
563 0x0000, /* R10 - Power mgmt (3) */
564 0x2000, /* R11 - Power mgmt (4) */
565 0x0E00, /* R12 - Power mgmt (5) */
566 0x0000, /* R13 - Power mgmt (6) */
567 0x0000, /* R14 - Power mgmt (7) */
568 0x0000, /* R15 */
569 0x0000, /* R16 - RTC Seconds/Minutes */
570 0x0100, /* R17 - RTC Hours/Day */
571 0x0101, /* R18 - RTC Date/Month */
572 0x1400, /* R19 - RTC Year */
573 0x0000, /* R20 - Alarm Seconds/Minutes */
574 0x0000, /* R21 - Alarm Hours/Day */
575 0x0000, /* R22 - Alarm Date/Month */
576 0x0320, /* R23 - RTC Time Control */
577 0x0000, /* R24 - System Interrupts */
578 0x0000, /* R25 - Interrupt Status 1 */
579 0x0000, /* R26 - Interrupt Status 2 */
580 0x0000, /* R27 - Power Up Interrupt Status */
581 0x0000, /* R28 - Under Voltage Interrupt status */
582 0x0000, /* R29 - Over Current Interrupt status */
583 0x0000, /* R30 - GPIO Interrupt Status */
584 0x0000, /* R31 - Comparator Interrupt Status */
585 0x3FFF, /* R32 - System Interrupts Mask */
586 0x0000, /* R33 - Interrupt Status 1 Mask */
587 0x0000, /* R34 - Interrupt Status 2 Mask */
588 0x0000, /* R35 - Power Up Interrupt Status Mask */
589 0x0000, /* R36 - Under Voltage Interrupt status Mask */
590 0x0000, /* R37 - Over Current Interrupt status Mask */
591 0x0000, /* R38 - GPIO Interrupt Status Mask */
592 0x0000, /* R39 - Comparator Interrupt Status Mask */
593 0x0040, /* R40 - Clock Control 1 */
594 0x0000, /* R41 - Clock Control 2 */
595 0x3B00, /* R42 - FLL Control 1 */
596 0x7086, /* R43 - FLL Control 2 */
597 0xC226, /* R44 - FLL Control 3 */
598 0x0000, /* R45 - FLL Control 4 */
599 0x0000, /* R46 */
600 0x0000, /* R47 */
601 0x0000, /* R48 - DAC Control */
602 0x0000, /* R49 */
603 0x00C0, /* R50 - DAC Digital Volume L */
604 0x00C0, /* R51 - DAC Digital Volume R */
605 0x0000, /* R52 */
606 0x0040, /* R53 - DAC LR Rate */
607 0x0000, /* R54 - DAC Clock Control */
608 0x0000, /* R55 */
609 0x0000, /* R56 */
610 0x0000, /* R57 */
611 0x4000, /* R58 - DAC Mute */
612 0x0000, /* R59 - DAC Mute Volume */
613 0x0000, /* R60 - DAC Side */
614 0x0000, /* R61 */
615 0x0000, /* R62 */
616 0x0000, /* R63 */
617 0x8000, /* R64 - ADC Control */
618 0x0000, /* R65 */
619 0x00C0, /* R66 - ADC Digital Volume L */
620 0x00C0, /* R67 - ADC Digital Volume R */
621 0x0000, /* R68 - ADC Divider */
622 0x0000, /* R69 */
623 0x0040, /* R70 - ADC LR Rate */
624 0x0000, /* R71 */
625 0x0303, /* R72 - Input Control */
626 0x0000, /* R73 - IN3 Input Control */
627 0x0000, /* R74 - Mic Bias Control */
628 0x0000, /* R75 */
629 0x0000, /* R76 - Output Control */
630 0x0000, /* R77 - Jack Detect */
631 0x0000, /* R78 - Anti Pop Control */
632 0x0000, /* R79 */
633 0x0040, /* R80 - Left Input Volume */
634 0x0040, /* R81 - Right Input Volume */
635 0x0000, /* R82 */
636 0x0000, /* R83 */
637 0x0000, /* R84 */
638 0x0000, /* R85 */
639 0x0000, /* R86 */
640 0x0000, /* R87 */
641 0x0800, /* R88 - Left Mixer Control */
642 0x1000, /* R89 - Right Mixer Control */
643 0x0000, /* R90 */
644 0x0000, /* R91 */
645 0x0000, /* R92 - OUT3 Mixer Control */
646 0x0000, /* R93 - OUT4 Mixer Control */
647 0x0000, /* R94 */
648 0x0000, /* R95 */
649 0x0000, /* R96 - Output Left Mixer Volume */
650 0x0000, /* R97 - Output Right Mixer Volume */
651 0x0000, /* R98 - Input Mixer Volume L */
652 0x0000, /* R99 - Input Mixer Volume R */
653 0x0000, /* R100 - Input Mixer Volume */
654 0x0000, /* R101 */
655 0x0000, /* R102 */
656 0x0000, /* R103 */
657 0x00E4, /* R104 - LOUT1 Volume */
658 0x00E4, /* R105 - ROUT1 Volume */
659 0x00E4, /* R106 - LOUT2 Volume */
660 0x02E4, /* R107 - ROUT2 Volume */
661 0x0000, /* R108 */
662 0x0000, /* R109 */
663 0x0000, /* R110 */
664 0x0000, /* R111 - BEEP Volume */
665 0x0A00, /* R112 - AI Formating */
666 0x0000, /* R113 - ADC DAC COMP */
667 0x0020, /* R114 - AI ADC Control */
668 0x0020, /* R115 - AI DAC Control */
669 0x0000, /* R116 - AIF Test */
670 0x0000, /* R117 */
671 0x0000, /* R118 */
672 0x0000, /* R119 */
673 0x0000, /* R120 */
674 0x0000, /* R121 */
675 0x0000, /* R122 */
676 0x0000, /* R123 */
677 0x0000, /* R124 */
678 0x0000, /* R125 */
679 0x0000, /* R126 */
680 0x0000, /* R127 */
681 0x1FFF, /* R128 - GPIO Debounce */
682 0x0000, /* R129 - GPIO Pin pull up Control */
683 0x03FC, /* R130 - GPIO Pull down Control */
684 0x0000, /* R131 - GPIO Interrupt Mode */
685 0x0000, /* R132 */
686 0x0000, /* R133 - GPIO Control */
687 0x08FB, /* R134 - GPIO Configuration (i/o) */
688 0x0CFE, /* R135 - GPIO Pin Polarity / Type */
689 0x0000, /* R136 */
690 0x0000, /* R137 */
691 0x0000, /* R138 */
692 0x0000, /* R139 */
693 0x0312, /* R140 - GPIO Function Select 1 */
694 0x0003, /* R141 - GPIO Function Select 2 */
695 0x2331, /* R142 - GPIO Function Select 3 */
696 0x0003, /* R143 - GPIO Function Select 4 */
697 0x0000, /* R144 - Digitiser Control (1) */
698 0x0002, /* R145 - Digitiser Control (2) */
699 0x0000, /* R146 */
700 0x0000, /* R147 */
701 0x0000, /* R148 */
702 0x0000, /* R149 */
703 0x0000, /* R150 */
704 0x0000, /* R151 */
705 0x7000, /* R152 - AUX1 Readback */
706 0x7000, /* R153 - AUX2 Readback */
707 0x7000, /* R154 - AUX3 Readback */
708 0x7000, /* R155 - AUX4 Readback */
709 0x0000, /* R156 - USB Voltage Readback */
710 0x0000, /* R157 - LINE Voltage Readback */
711 0x0000, /* R158 - BATT Voltage Readback */
712 0x0000, /* R159 - Chip Temp Readback */
713 0x0000, /* R160 */
714 0x0000, /* R161 */
715 0x0000, /* R162 */
716 0x0000, /* R163 - Generic Comparator Control */
717 0x0000, /* R164 - Generic comparator 1 */
718 0x0000, /* R165 - Generic comparator 2 */
719 0x0000, /* R166 - Generic comparator 3 */
720 0x0000, /* R167 - Generic comparator 4 */
721 0xA00F, /* R168 - Battery Charger Control 1 */
722 0x0B06, /* R169 - Battery Charger Control 2 */
723 0x0000, /* R170 - Battery Charger Control 3 */
724 0x0000, /* R171 */
725 0x0000, /* R172 - Current Sink Driver A */
726 0x0000, /* R173 - CSA Flash control */
727 0x0000, /* R174 - Current Sink Driver B */
728 0x0000, /* R175 - CSB Flash control */
729 0x0000, /* R176 - DCDC/LDO requested */
730 0x002D, /* R177 - DCDC Active options */
731 0x0000, /* R178 - DCDC Sleep options */
732 0x0025, /* R179 - Power-check comparator */
733 0x000E, /* R180 - DCDC1 Control */
734 0x0400, /* R181 - DCDC1 Timeouts */
735 0x1006, /* R182 - DCDC1 Low Power */
736 0x0018, /* R183 - DCDC2 Control */
737 0x0000, /* R184 - DCDC2 Timeouts */
738 0x0000, /* R185 */
739 0x002E, /* R186 - DCDC3 Control */
740 0x0800, /* R187 - DCDC3 Timeouts */
741 0x0006, /* R188 - DCDC3 Low Power */
742 0x000E, /* R189 - DCDC4 Control */
743 0x0800, /* R190 - DCDC4 Timeouts */
744 0x0006, /* R191 - DCDC4 Low Power */
745 0x0008, /* R192 - DCDC5 Control */
746 0x0000, /* R193 - DCDC5 Timeouts */
747 0x0000, /* R194 */
748 0x0026, /* R195 - DCDC6 Control */
749 0x0C00, /* R196 - DCDC6 Timeouts */
750 0x0006, /* R197 - DCDC6 Low Power */
751 0x0000, /* R198 */
752 0x0003, /* R199 - Limit Switch Control */
753 0x001A, /* R200 - LDO1 Control */
754 0x0800, /* R201 - LDO1 Timeouts */
755 0x001C, /* R202 - LDO1 Low Power */
756 0x0010, /* R203 - LDO2 Control */
757 0x0800, /* R204 - LDO2 Timeouts */
758 0x001C, /* R205 - LDO2 Low Power */
759 0x000A, /* R206 - LDO3 Control */
760 0x0C00, /* R207 - LDO3 Timeouts */
761 0x001C, /* R208 - LDO3 Low Power */
762 0x001A, /* R209 - LDO4 Control */
763 0x0800, /* R210 - LDO4 Timeouts */
764 0x001C, /* R211 - LDO4 Low Power */
765 0x0000, /* R212 */
766 0x0000, /* R213 */
767 0x0000, /* R214 */
768 0x0000, /* R215 - VCC_FAULT Masks */
769 0x001F, /* R216 - Main Bandgap Control */
770 0x0000, /* R217 - OSC Control */
771 0x9000, /* R218 - RTC Tick Control */
772 0x0000, /* R219 */
773 0x4000, /* R220 - RAM BIST 1 */
774 0x0000, /* R221 */
775 0x0000, /* R222 */
776 0x0000, /* R223 */
777 0x0000, /* R224 */
778 0x0000, /* R225 - DCDC/LDO status */
779 0x0000, /* R226 */
780 0x0000, /* R227 */
781 0x0000, /* R228 */
782 0x0000, /* R229 */
783 0xE000, /* R230 - GPIO Pin Status */
784 0x0000, /* R231 */
785 0x0000, /* R232 */
786 0x0000, /* R233 */
787 0x0000, /* R234 */
788 0x0000, /* R235 */
789 0x0000, /* R236 */
790 0x0000, /* R237 */
791 0x0000, /* R238 */
792 0x0000, /* R239 */
793 0x0000, /* R240 */
794 0x0000, /* R241 */
795 0x0000, /* R242 */
796 0x0000, /* R243 */
797 0x0000, /* R244 */
798 0x0000, /* R245 */
799 0x0000, /* R246 */
800 0x0000, /* R247 */
801 0x0000, /* R248 */
802 0x0000, /* R249 */
803 0x0000, /* R250 */
804 0x0000, /* R251 */
805 0x0000, /* R252 */
806 0x0000, /* R253 */
807 0x0000, /* R254 */
808 0x0000, /* R255 */
809};
810#endif
811
812#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
813
814#undef WM8350_HAVE_CONFIG_MODE
815#define WM8350_HAVE_CONFIG_MODE
816
817const u16 wm8350_mode3_defaults[] = {
818 0x17FF, /* R0 - Reset/ID */
819 0x1000, /* R1 - ID */
820 0x0000, /* R2 */
821 0x1000, /* R3 - System Control 1 */
822 0x0004, /* R4 - System Control 2 */
823 0x0000, /* R5 - System Hibernate */
824 0x8A00, /* R6 - Interface Control */
825 0x0000, /* R7 */
826 0x8000, /* R8 - Power mgmt (1) */
827 0x0000, /* R9 - Power mgmt (2) */
828 0x0000, /* R10 - Power mgmt (3) */
829 0x2000, /* R11 - Power mgmt (4) */
830 0x0E00, /* R12 - Power mgmt (5) */
831 0x0000, /* R13 - Power mgmt (6) */
832 0x0000, /* R14 - Power mgmt (7) */
833 0x0000, /* R15 */
834 0x0000, /* R16 - RTC Seconds/Minutes */
835 0x0100, /* R17 - RTC Hours/Day */
836 0x0101, /* R18 - RTC Date/Month */
837 0x1400, /* R19 - RTC Year */
838 0x0000, /* R20 - Alarm Seconds/Minutes */
839 0x0000, /* R21 - Alarm Hours/Day */
840 0x0000, /* R22 - Alarm Date/Month */
841 0x0320, /* R23 - RTC Time Control */
842 0x0000, /* R24 - System Interrupts */
843 0x0000, /* R25 - Interrupt Status 1 */
844 0x0000, /* R26 - Interrupt Status 2 */
845 0x0000, /* R27 - Power Up Interrupt Status */
846 0x0000, /* R28 - Under Voltage Interrupt status */
847 0x0000, /* R29 - Over Current Interrupt status */
848 0x0000, /* R30 - GPIO Interrupt Status */
849 0x0000, /* R31 - Comparator Interrupt Status */
850 0x3FFF, /* R32 - System Interrupts Mask */
851 0x0000, /* R33 - Interrupt Status 1 Mask */
852 0x0000, /* R34 - Interrupt Status 2 Mask */
853 0x0000, /* R35 - Power Up Interrupt Status Mask */
854 0x0000, /* R36 - Under Voltage Interrupt status Mask */
855 0x0000, /* R37 - Over Current Interrupt status Mask */
856 0x0000, /* R38 - GPIO Interrupt Status Mask */
857 0x0000, /* R39 - Comparator Interrupt Status Mask */
858 0x0040, /* R40 - Clock Control 1 */
859 0x0000, /* R41 - Clock Control 2 */
860 0x3B00, /* R42 - FLL Control 1 */
861 0x7086, /* R43 - FLL Control 2 */
862 0xC226, /* R44 - FLL Control 3 */
863 0x0000, /* R45 - FLL Control 4 */
864 0x0000, /* R46 */
865 0x0000, /* R47 */
866 0x0000, /* R48 - DAC Control */
867 0x0000, /* R49 */
868 0x00C0, /* R50 - DAC Digital Volume L */
869 0x00C0, /* R51 - DAC Digital Volume R */
870 0x0000, /* R52 */
871 0x0040, /* R53 - DAC LR Rate */
872 0x0000, /* R54 - DAC Clock Control */
873 0x0000, /* R55 */
874 0x0000, /* R56 */
875 0x0000, /* R57 */
876 0x4000, /* R58 - DAC Mute */
877 0x0000, /* R59 - DAC Mute Volume */
878 0x0000, /* R60 - DAC Side */
879 0x0000, /* R61 */
880 0x0000, /* R62 */
881 0x0000, /* R63 */
882 0x8000, /* R64 - ADC Control */
883 0x0000, /* R65 */
884 0x00C0, /* R66 - ADC Digital Volume L */
885 0x00C0, /* R67 - ADC Digital Volume R */
886 0x0000, /* R68 - ADC Divider */
887 0x0000, /* R69 */
888 0x0040, /* R70 - ADC LR Rate */
889 0x0000, /* R71 */
890 0x0303, /* R72 - Input Control */
891 0x0000, /* R73 - IN3 Input Control */
892 0x0000, /* R74 - Mic Bias Control */
893 0x0000, /* R75 */
894 0x0000, /* R76 - Output Control */
895 0x0000, /* R77 - Jack Detect */
896 0x0000, /* R78 - Anti Pop Control */
897 0x0000, /* R79 */
898 0x0040, /* R80 - Left Input Volume */
899 0x0040, /* R81 - Right Input Volume */
900 0x0000, /* R82 */
901 0x0000, /* R83 */
902 0x0000, /* R84 */
903 0x0000, /* R85 */
904 0x0000, /* R86 */
905 0x0000, /* R87 */
906 0x0800, /* R88 - Left Mixer Control */
907 0x1000, /* R89 - Right Mixer Control */
908 0x0000, /* R90 */
909 0x0000, /* R91 */
910 0x0000, /* R92 - OUT3 Mixer Control */
911 0x0000, /* R93 - OUT4 Mixer Control */
912 0x0000, /* R94 */
913 0x0000, /* R95 */
914 0x0000, /* R96 - Output Left Mixer Volume */
915 0x0000, /* R97 - Output Right Mixer Volume */
916 0x0000, /* R98 - Input Mixer Volume L */
917 0x0000, /* R99 - Input Mixer Volume R */
918 0x0000, /* R100 - Input Mixer Volume */
919 0x0000, /* R101 */
920 0x0000, /* R102 */
921 0x0000, /* R103 */
922 0x00E4, /* R104 - LOUT1 Volume */
923 0x00E4, /* R105 - ROUT1 Volume */
924 0x00E4, /* R106 - LOUT2 Volume */
925 0x02E4, /* R107 - ROUT2 Volume */
926 0x0000, /* R108 */
927 0x0000, /* R109 */
928 0x0000, /* R110 */
929 0x0000, /* R111 - BEEP Volume */
930 0x0A00, /* R112 - AI Formating */
931 0x0000, /* R113 - ADC DAC COMP */
932 0x0020, /* R114 - AI ADC Control */
933 0x0020, /* R115 - AI DAC Control */
934 0x0000, /* R116 - AIF Test */
935 0x0000, /* R117 */
936 0x0000, /* R118 */
937 0x0000, /* R119 */
938 0x0000, /* R120 */
939 0x0000, /* R121 */
940 0x0000, /* R122 */
941 0x0000, /* R123 */
942 0x0000, /* R124 */
943 0x0000, /* R125 */
944 0x0000, /* R126 */
945 0x0000, /* R127 */
946 0x1FFF, /* R128 - GPIO Debounce */
947 0x0000, /* R129 - GPIO Pin pull up Control */
948 0x03FC, /* R130 - GPIO Pull down Control */
949 0x0000, /* R131 - GPIO Interrupt Mode */
950 0x0000, /* R132 */
951 0x0000, /* R133 - GPIO Control */
952 0x0A7B, /* R134 - GPIO Configuration (i/o) */
953 0x06FE, /* R135 - GPIO Pin Polarity / Type */
954 0x0000, /* R136 */
955 0x0000, /* R137 */
956 0x0000, /* R138 */
957 0x0000, /* R139 */
958 0x1312, /* R140 - GPIO Function Select 1 */
959 0x1030, /* R141 - GPIO Function Select 2 */
960 0x2231, /* R142 - GPIO Function Select 3 */
961 0x0003, /* R143 - GPIO Function Select 4 */
962 0x0000, /* R144 - Digitiser Control (1) */
963 0x0002, /* R145 - Digitiser Control (2) */
964 0x0000, /* R146 */
965 0x0000, /* R147 */
966 0x0000, /* R148 */
967 0x0000, /* R149 */
968 0x0000, /* R150 */
969 0x0000, /* R151 */
970 0x7000, /* R152 - AUX1 Readback */
971 0x7000, /* R153 - AUX2 Readback */
972 0x7000, /* R154 - AUX3 Readback */
973 0x7000, /* R155 - AUX4 Readback */
974 0x0000, /* R156 - USB Voltage Readback */
975 0x0000, /* R157 - LINE Voltage Readback */
976 0x0000, /* R158 - BATT Voltage Readback */
977 0x0000, /* R159 - Chip Temp Readback */
978 0x0000, /* R160 */
979 0x0000, /* R161 */
980 0x0000, /* R162 */
981 0x0000, /* R163 - Generic Comparator Control */
982 0x0000, /* R164 - Generic comparator 1 */
983 0x0000, /* R165 - Generic comparator 2 */
984 0x0000, /* R166 - Generic comparator 3 */
985 0x0000, /* R167 - Generic comparator 4 */
986 0xA00F, /* R168 - Battery Charger Control 1 */
987 0x0B06, /* R169 - Battery Charger Control 2 */
988 0x0000, /* R170 - Battery Charger Control 3 */
989 0x0000, /* R171 */
990 0x0000, /* R172 - Current Sink Driver A */
991 0x0000, /* R173 - CSA Flash control */
992 0x0000, /* R174 - Current Sink Driver B */
993 0x0000, /* R175 - CSB Flash control */
994 0x0000, /* R176 - DCDC/LDO requested */
995 0x002D, /* R177 - DCDC Active options */
996 0x0000, /* R178 - DCDC Sleep options */
997 0x0025, /* R179 - Power-check comparator */
998 0x000E, /* R180 - DCDC1 Control */
999 0x0400, /* R181 - DCDC1 Timeouts */
1000 0x1006, /* R182 - DCDC1 Low Power */
1001 0x0018, /* R183 - DCDC2 Control */
1002 0x0000, /* R184 - DCDC2 Timeouts */
1003 0x0000, /* R185 */
1004 0x000E, /* R186 - DCDC3 Control */
1005 0x0400, /* R187 - DCDC3 Timeouts */
1006 0x0006, /* R188 - DCDC3 Low Power */
1007 0x0026, /* R189 - DCDC4 Control */
1008 0x0400, /* R190 - DCDC4 Timeouts */
1009 0x0006, /* R191 - DCDC4 Low Power */
1010 0x0008, /* R192 - DCDC5 Control */
1011 0x0000, /* R193 - DCDC5 Timeouts */
1012 0x0000, /* R194 */
1013 0x0026, /* R195 - DCDC6 Control */
1014 0x0400, /* R196 - DCDC6 Timeouts */
1015 0x0006, /* R197 - DCDC6 Low Power */
1016 0x0000, /* R198 */
1017 0x0003, /* R199 - Limit Switch Control */
1018 0x001C, /* R200 - LDO1 Control */
1019 0x0000, /* R201 - LDO1 Timeouts */
1020 0x001C, /* R202 - LDO1 Low Power */
1021 0x001C, /* R203 - LDO2 Control */
1022 0x0400, /* R204 - LDO2 Timeouts */
1023 0x001C, /* R205 - LDO2 Low Power */
1024 0x001C, /* R206 - LDO3 Control */
1025 0x0400, /* R207 - LDO3 Timeouts */
1026 0x001C, /* R208 - LDO3 Low Power */
1027 0x001F, /* R209 - LDO4 Control */
1028 0x0400, /* R210 - LDO4 Timeouts */
1029 0x001C, /* R211 - LDO4 Low Power */
1030 0x0000, /* R212 */
1031 0x0000, /* R213 */
1032 0x0000, /* R214 */
1033 0x0000, /* R215 - VCC_FAULT Masks */
1034 0x001F, /* R216 - Main Bandgap Control */
1035 0x0000, /* R217 - OSC Control */
1036 0x9000, /* R218 - RTC Tick Control */
1037 0x0000, /* R219 */
1038 0x4000, /* R220 - RAM BIST 1 */
1039 0x0000, /* R221 */
1040 0x0000, /* R222 */
1041 0x0000, /* R223 */
1042 0x0000, /* R224 */
1043 0x0000, /* R225 - DCDC/LDO status */
1044 0x0000, /* R226 */
1045 0x0000, /* R227 */
1046 0x0000, /* R228 */
1047 0x0000, /* R229 */
1048 0xE000, /* R230 - GPIO Pin Status */
1049 0x0000, /* R231 */
1050 0x0000, /* R232 */
1051 0x0000, /* R233 */
1052 0x0000, /* R234 */
1053 0x0000, /* R235 */
1054 0x0000, /* R236 */
1055 0x0000, /* R237 */
1056 0x0000, /* R238 */
1057 0x0000, /* R239 */
1058 0x0000, /* R240 */
1059 0x0000, /* R241 */
1060 0x0000, /* R242 */
1061 0x0000, /* R243 */
1062 0x0000, /* R244 */
1063 0x0000, /* R245 */
1064 0x0000, /* R246 */
1065 0x0000, /* R247 */
1066 0x0000, /* R248 */
1067 0x0000, /* R249 */
1068 0x0000, /* R250 */
1069 0x0000, /* R251 */
1070 0x0000, /* R252 */
1071 0x0000, /* R253 */
1072 0x0000, /* R254 */
1073 0x0000, /* R255 */
1074};
1075#endif
1076
1077#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_0
1078
1079#undef WM8350_HAVE_CONFIG_MODE
1080#define WM8350_HAVE_CONFIG_MODE
1081
1082const u16 wm8351_mode0_defaults[] = {
1083 0x6143, /* R0 - Reset/ID */
1084 0x0000, /* R1 - ID */
1085 0x0001, /* R2 - Revision */
1086 0x1C02, /* R3 - System Control 1 */
1087 0x0004, /* R4 - System Control 2 */
1088 0x0000, /* R5 - System Hibernate */
1089 0x8A00, /* R6 - Interface Control */
1090 0x0000, /* R7 */
1091 0x8000, /* R8 - Power mgmt (1) */
1092 0x0000, /* R9 - Power mgmt (2) */
1093 0x0000, /* R10 - Power mgmt (3) */
1094 0x2000, /* R11 - Power mgmt (4) */
1095 0x0E00, /* R12 - Power mgmt (5) */
1096 0x0000, /* R13 - Power mgmt (6) */
1097 0x0000, /* R14 - Power mgmt (7) */
1098 0x0000, /* R15 */
1099 0x0000, /* R16 - RTC Seconds/Minutes */
1100 0x0100, /* R17 - RTC Hours/Day */
1101 0x0101, /* R18 - RTC Date/Month */
1102 0x1400, /* R19 - RTC Year */
1103 0x0000, /* R20 - Alarm Seconds/Minutes */
1104 0x0000, /* R21 - Alarm Hours/Day */
1105 0x0000, /* R22 - Alarm Date/Month */
1106 0x0320, /* R23 - RTC Time Control */
1107 0x0000, /* R24 - System Interrupts */
1108 0x0000, /* R25 - Interrupt Status 1 */
1109 0x0000, /* R26 - Interrupt Status 2 */
1110 0x0000, /* R27 */
1111 0x0000, /* R28 - Under Voltage Interrupt status */
1112 0x0000, /* R29 - Over Current Interrupt status */
1113 0x0000, /* R30 - GPIO Interrupt Status */
1114 0x0000, /* R31 - Comparator Interrupt Status */
1115 0x3FFF, /* R32 - System Interrupts Mask */
1116 0x0000, /* R33 - Interrupt Status 1 Mask */
1117 0x0000, /* R34 - Interrupt Status 2 Mask */
1118 0x0000, /* R35 */
1119 0x0000, /* R36 - Under Voltage Interrupt status Mask */
1120 0x0000, /* R37 - Over Current Interrupt status Mask */
1121 0x0000, /* R38 - GPIO Interrupt Status Mask */
1122 0x0000, /* R39 - Comparator Interrupt Status Mask */
1123 0x0040, /* R40 - Clock Control 1 */
1124 0x0000, /* R41 - Clock Control 2 */
1125 0x3A00, /* R42 - FLL Control 1 */
1126 0x7086, /* R43 - FLL Control 2 */
1127 0xC226, /* R44 - FLL Control 3 */
1128 0x0000, /* R45 - FLL Control 4 */
1129 0x0000, /* R46 */
1130 0x0000, /* R47 */
1131 0x0000, /* R48 - DAC Control */
1132 0x0000, /* R49 */
1133 0x00C0, /* R50 - DAC Digital Volume L */
1134 0x00C0, /* R51 - DAC Digital Volume R */
1135 0x0000, /* R52 */
1136 0x0040, /* R53 - DAC LR Rate */
1137 0x0000, /* R54 - DAC Clock Control */
1138 0x0000, /* R55 */
1139 0x0000, /* R56 */
1140 0x0000, /* R57 */
1141 0x4000, /* R58 - DAC Mute */
1142 0x0000, /* R59 - DAC Mute Volume */
1143 0x0000, /* R60 - DAC Side */
1144 0x0000, /* R61 */
1145 0x0000, /* R62 */
1146 0x0000, /* R63 */
1147 0x8000, /* R64 - ADC Control */
1148 0x0000, /* R65 */
1149 0x00C0, /* R66 - ADC Digital Volume L */
1150 0x00C0, /* R67 - ADC Digital Volume R */
1151 0x0000, /* R68 - ADC Divider */
1152 0x0000, /* R69 */
1153 0x0040, /* R70 - ADC LR Rate */
1154 0x0000, /* R71 */
1155 0x0303, /* R72 - Input Control */
1156 0x0000, /* R73 - IN3 Input Control */
1157 0x0000, /* R74 - Mic Bias Control */
1158 0x0000, /* R75 */
1159 0x0000, /* R76 - Output Control */
1160 0x0000, /* R77 - Jack Detect */
1161 0x0000, /* R78 - Anti Pop Control */
1162 0x0000, /* R79 */
1163 0x0040, /* R80 - Left Input Volume */
1164 0x0040, /* R81 - Right Input Volume */
1165 0x0000, /* R82 */
1166 0x0000, /* R83 */
1167 0x0000, /* R84 */
1168 0x0000, /* R85 */
1169 0x0000, /* R86 */
1170 0x0000, /* R87 */
1171 0x0800, /* R88 - Left Mixer Control */
1172 0x1000, /* R89 - Right Mixer Control */
1173 0x0000, /* R90 */
1174 0x0000, /* R91 */
1175 0x0000, /* R92 - OUT3 Mixer Control */
1176 0x0000, /* R93 - OUT4 Mixer Control */
1177 0x0000, /* R94 */
1178 0x0000, /* R95 */
1179 0x0000, /* R96 - Output Left Mixer Volume */
1180 0x0000, /* R97 - Output Right Mixer Volume */
1181 0x0000, /* R98 - Input Mixer Volume L */
1182 0x0000, /* R99 - Input Mixer Volume R */
1183 0x0000, /* R100 - Input Mixer Volume */
1184 0x0000, /* R101 */
1185 0x0000, /* R102 */
1186 0x0000, /* R103 */
1187 0x00E4, /* R104 - OUT1L Volume */
1188 0x00E4, /* R105 - OUT1R Volume */
1189 0x00E4, /* R106 - OUT2L Volume */
1190 0x02E4, /* R107 - OUT2R Volume */
1191 0x0000, /* R108 */
1192 0x0000, /* R109 */
1193 0x0000, /* R110 */
1194 0x0000, /* R111 - BEEP Volume */
1195 0x0A00, /* R112 - AI Formating */
1196 0x0000, /* R113 - ADC DAC COMP */
1197 0x0020, /* R114 - AI ADC Control */
1198 0x0020, /* R115 - AI DAC Control */
1199 0x0000, /* R116 */
1200 0x0000, /* R117 */
1201 0x0000, /* R118 */
1202 0x0000, /* R119 */
1203 0x0000, /* R120 */
1204 0x0000, /* R121 */
1205 0x0000, /* R122 */
1206 0x0000, /* R123 */
1207 0x0000, /* R124 */
1208 0x0000, /* R125 */
1209 0x0000, /* R126 */
1210 0x0000, /* R127 */
1211 0x1FFF, /* R128 - GPIO Debounce */
1212 0x0000, /* R129 - GPIO Pin pull up Control */
1213 0x0000, /* R130 - GPIO Pull down Control */
1214 0x0000, /* R131 - GPIO Interrupt Mode */
1215 0x0000, /* R132 */
1216 0x0000, /* R133 - GPIO Control */
1217 0x0FFC, /* R134 - GPIO Configuration (i/o) */
1218 0x0FFC, /* R135 - GPIO Pin Polarity / Type */
1219 0x0000, /* R136 */
1220 0x0000, /* R137 */
1221 0x0000, /* R138 */
1222 0x0000, /* R139 */
1223 0x0013, /* R140 - GPIO Function Select 1 */
1224 0x0000, /* R141 - GPIO Function Select 2 */
1225 0x0000, /* R142 - GPIO Function Select 3 */
1226 0x0003, /* R143 - GPIO Function Select 4 */
1227 0x0000, /* R144 - Digitiser Control (1) */
1228 0x0002, /* R145 - Digitiser Control (2) */
1229 0x0000, /* R146 */
1230 0x0000, /* R147 */
1231 0x0000, /* R148 */
1232 0x0000, /* R149 */
1233 0x0000, /* R150 */
1234 0x0000, /* R151 */
1235 0x7000, /* R152 - AUX1 Readback */
1236 0x7000, /* R153 - AUX2 Readback */
1237 0x7000, /* R154 - AUX3 Readback */
1238 0x7000, /* R155 - AUX4 Readback */
1239 0x0000, /* R156 - USB Voltage Readback */
1240 0x0000, /* R157 - LINE Voltage Readback */
1241 0x0000, /* R158 - BATT Voltage Readback */
1242 0x0000, /* R159 - Chip Temp Readback */
1243 0x0000, /* R160 */
1244 0x0000, /* R161 */
1245 0x0000, /* R162 */
1246 0x0000, /* R163 - Generic Comparator Control */
1247 0x0000, /* R164 - Generic comparator 1 */
1248 0x0000, /* R165 - Generic comparator 2 */
1249 0x0000, /* R166 - Generic comparator 3 */
1250 0x0000, /* R167 - Generic comparator 4 */
1251 0xA00F, /* R168 - Battery Charger Control 1 */
1252 0x0B06, /* R169 - Battery Charger Control 2 */
1253 0x0000, /* R170 - Battery Charger Control 3 */
1254 0x0000, /* R171 */
1255 0x0000, /* R172 - Current Sink Driver A */
1256 0x0000, /* R173 - CSA Flash control */
1257 0x0000, /* R174 */
1258 0x0000, /* R175 */
1259 0x0000, /* R176 - DCDC/LDO requested */
1260 0x032D, /* R177 - DCDC Active options */
1261 0x0000, /* R178 - DCDC Sleep options */
1262 0x0025, /* R179 - Power-check comparator */
1263 0x000E, /* R180 - DCDC1 Control */
1264 0x0000, /* R181 - DCDC1 Timeouts */
1265 0x1006, /* R182 - DCDC1 Low Power */
1266 0x0018, /* R183 - DCDC2 Control */
1267 0x0000, /* R184 - DCDC2 Timeouts */
1268 0x0000, /* R185 */
1269 0x0000, /* R186 - DCDC3 Control */
1270 0x0000, /* R187 - DCDC3 Timeouts */
1271 0x0006, /* R188 - DCDC3 Low Power */
1272 0x0000, /* R189 - DCDC4 Control */
1273 0x0000, /* R190 - DCDC4 Timeouts */
1274 0x0006, /* R191 - DCDC4 Low Power */
1275 0x0008, /* R192 */
1276 0x0000, /* R193 */
1277 0x0000, /* R194 */
1278 0x0000, /* R195 */
1279 0x0000, /* R196 */
1280 0x0006, /* R197 */
1281 0x0000, /* R198 */
1282 0x0003, /* R199 - Limit Switch Control */
1283 0x001C, /* R200 - LDO1 Control */
1284 0x0000, /* R201 - LDO1 Timeouts */
1285 0x001C, /* R202 - LDO1 Low Power */
1286 0x001B, /* R203 - LDO2 Control */
1287 0x0000, /* R204 - LDO2 Timeouts */
1288 0x001C, /* R205 - LDO2 Low Power */
1289 0x001B, /* R206 - LDO3 Control */
1290 0x0000, /* R207 - LDO3 Timeouts */
1291 0x001C, /* R208 - LDO3 Low Power */
1292 0x001B, /* R209 - LDO4 Control */
1293 0x0000, /* R210 - LDO4 Timeouts */
1294 0x001C, /* R211 - LDO4 Low Power */
1295 0x0000, /* R212 */
1296 0x0000, /* R213 */
1297 0x0000, /* R214 */
1298 0x0000, /* R215 - VCC_FAULT Masks */
1299 0x001F, /* R216 - Main Bandgap Control */
1300 0x0000, /* R217 - OSC Control */
1301 0x9000, /* R218 - RTC Tick Control */
1302 0x0000, /* R219 - Security1 */
1303 0x4000, /* R220 */
1304 0x0000, /* R221 */
1305 0x0000, /* R222 */
1306 0x0000, /* R223 */
1307 0x0000, /* R224 - Signal overrides */
1308 0x0000, /* R225 - DCDC/LDO status */
1309 0x0000, /* R226 - Charger Overides/status */
1310 0x0000, /* R227 - misc overrides */
1311 0x0000, /* R228 - Supply overrides/status 1 */
1312 0x0000, /* R229 - Supply overrides/status 2 */
1313 0xE000, /* R230 - GPIO Pin Status */
1314 0x0000, /* R231 - comparotor overrides */
1315 0x0000, /* R232 */
1316 0x0000, /* R233 - State Machine status */
1317 0x1200, /* R234 - FLL Test 1 */
1318 0x0000, /* R235 */
1319 0x8000, /* R236 */
1320 0x0000, /* R237 */
1321 0x0000, /* R238 */
1322 0x0000, /* R239 */
1323 0x0003, /* R240 */
1324 0x0000, /* R241 */
1325 0x0000, /* R242 */
1326 0x0004, /* R243 */
1327 0x0300, /* R244 */
1328 0x0000, /* R245 */
1329 0x0200, /* R246 */
1330 0x0000, /* R247 */
1331 0x1000, /* R248 - DCDC1 Test Controls */
1332 0x1000, /* R249 */
1333 0x1000, /* R250 - DCDC3 Test Controls */
1334 0x1000, /* R251 - DCDC4 Test Controls */
1335};
1336#endif
1337
1338#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_1
1339
1340#undef WM8350_HAVE_CONFIG_MODE
1341#define WM8350_HAVE_CONFIG_MODE
1342
1343const u16 wm8351_mode1_defaults[] = {
1344 0x6143, /* R0 - Reset/ID */
1345 0x0000, /* R1 - ID */
1346 0x0001, /* R2 - Revision */
1347 0x1C02, /* R3 - System Control 1 */
1348 0x0204, /* R4 - System Control 2 */
1349 0x0000, /* R5 - System Hibernate */
1350 0x8A00, /* R6 - Interface Control */
1351 0x0000, /* R7 */
1352 0x8000, /* R8 - Power mgmt (1) */
1353 0x0000, /* R9 - Power mgmt (2) */
1354 0x0000, /* R10 - Power mgmt (3) */
1355 0x2000, /* R11 - Power mgmt (4) */
1356 0x0E00, /* R12 - Power mgmt (5) */
1357 0x0000, /* R13 - Power mgmt (6) */
1358 0x0000, /* R14 - Power mgmt (7) */
1359 0x0000, /* R15 */
1360 0x0000, /* R16 - RTC Seconds/Minutes */
1361 0x0100, /* R17 - RTC Hours/Day */
1362 0x0101, /* R18 - RTC Date/Month */
1363 0x1400, /* R19 - RTC Year */
1364 0x0000, /* R20 - Alarm Seconds/Minutes */
1365 0x0000, /* R21 - Alarm Hours/Day */
1366 0x0000, /* R22 - Alarm Date/Month */
1367 0x0320, /* R23 - RTC Time Control */
1368 0x0000, /* R24 - System Interrupts */
1369 0x0000, /* R25 - Interrupt Status 1 */
1370 0x0000, /* R26 - Interrupt Status 2 */
1371 0x0000, /* R27 */
1372 0x0000, /* R28 - Under Voltage Interrupt status */
1373 0x0000, /* R29 - Over Current Interrupt status */
1374 0x0000, /* R30 - GPIO Interrupt Status */
1375 0x0000, /* R31 - Comparator Interrupt Status */
1376 0x3FFF, /* R32 - System Interrupts Mask */
1377 0x0000, /* R33 - Interrupt Status 1 Mask */
1378 0x0000, /* R34 - Interrupt Status 2 Mask */
1379 0x0000, /* R35 */
1380 0x0000, /* R36 - Under Voltage Interrupt status Mask */
1381 0x0000, /* R37 - Over Current Interrupt status Mask */
1382 0x0000, /* R38 - GPIO Interrupt Status Mask */
1383 0x0000, /* R39 - Comparator Interrupt Status Mask */
1384 0x0040, /* R40 - Clock Control 1 */
1385 0x0000, /* R41 - Clock Control 2 */
1386 0x3A00, /* R42 - FLL Control 1 */
1387 0x7086, /* R43 - FLL Control 2 */
1388 0xC226, /* R44 - FLL Control 3 */
1389 0x0000, /* R45 - FLL Control 4 */
1390 0x0000, /* R46 */
1391 0x0000, /* R47 */
1392 0x0000, /* R48 - DAC Control */
1393 0x0000, /* R49 */
1394 0x00C0, /* R50 - DAC Digital Volume L */
1395 0x00C0, /* R51 - DAC Digital Volume R */
1396 0x0000, /* R52 */
1397 0x0040, /* R53 - DAC LR Rate */
1398 0x0000, /* R54 - DAC Clock Control */
1399 0x0000, /* R55 */
1400 0x0000, /* R56 */
1401 0x0000, /* R57 */
1402 0x4000, /* R58 - DAC Mute */
1403 0x0000, /* R59 - DAC Mute Volume */
1404 0x0000, /* R60 - DAC Side */
1405 0x0000, /* R61 */
1406 0x0000, /* R62 */
1407 0x0000, /* R63 */
1408 0x8000, /* R64 - ADC Control */
1409 0x0000, /* R65 */
1410 0x00C0, /* R66 - ADC Digital Volume L */
1411 0x00C0, /* R67 - ADC Digital Volume R */
1412 0x0000, /* R68 - ADC Divider */
1413 0x0000, /* R69 */
1414 0x0040, /* R70 - ADC LR Rate */
1415 0x0000, /* R71 */
1416 0x0303, /* R72 - Input Control */
1417 0x0000, /* R73 - IN3 Input Control */
1418 0x0000, /* R74 - Mic Bias Control */
1419 0x0000, /* R75 */
1420 0x0000, /* R76 - Output Control */
1421 0x0000, /* R77 - Jack Detect */
1422 0x0000, /* R78 - Anti Pop Control */
1423 0x0000, /* R79 */
1424 0x0040, /* R80 - Left Input Volume */
1425 0x0040, /* R81 - Right Input Volume */
1426 0x0000, /* R82 */
1427 0x0000, /* R83 */
1428 0x0000, /* R84 */
1429 0x0000, /* R85 */
1430 0x0000, /* R86 */
1431 0x0000, /* R87 */
1432 0x0800, /* R88 - Left Mixer Control */
1433 0x1000, /* R89 - Right Mixer Control */
1434 0x0000, /* R90 */
1435 0x0000, /* R91 */
1436 0x0000, /* R92 - OUT3 Mixer Control */
1437 0x0000, /* R93 - OUT4 Mixer Control */
1438 0x0000, /* R94 */
1439 0x0000, /* R95 */
1440 0x0000, /* R96 - Output Left Mixer Volume */
1441 0x0000, /* R97 - Output Right Mixer Volume */
1442 0x0000, /* R98 - Input Mixer Volume L */
1443 0x0000, /* R99 - Input Mixer Volume R */
1444 0x0000, /* R100 - Input Mixer Volume */
1445 0x0000, /* R101 */
1446 0x0000, /* R102 */
1447 0x0000, /* R103 */
1448 0x00E4, /* R104 - OUT1L Volume */
1449 0x00E4, /* R105 - OUT1R Volume */
1450 0x00E4, /* R106 - OUT2L Volume */
1451 0x02E4, /* R107 - OUT2R Volume */
1452 0x0000, /* R108 */
1453 0x0000, /* R109 */
1454 0x0000, /* R110 */
1455 0x0000, /* R111 - BEEP Volume */
1456 0x0A00, /* R112 - AI Formating */
1457 0x0000, /* R113 - ADC DAC COMP */
1458 0x0020, /* R114 - AI ADC Control */
1459 0x0020, /* R115 - AI DAC Control */
1460 0x0000, /* R116 */
1461 0x0000, /* R117 */
1462 0x0000, /* R118 */
1463 0x0000, /* R119 */
1464 0x0000, /* R120 */
1465 0x0000, /* R121 */
1466 0x0000, /* R122 */
1467 0x0000, /* R123 */
1468 0x0000, /* R124 */
1469 0x0000, /* R125 */
1470 0x0000, /* R126 */
1471 0x0000, /* R127 */
1472 0x1FFF, /* R128 - GPIO Debounce */
1473 0x0000, /* R129 - GPIO Pin pull up Control */
1474 0x0000, /* R130 - GPIO Pull down Control */
1475 0x0000, /* R131 - GPIO Interrupt Mode */
1476 0x0000, /* R132 */
1477 0x0000, /* R133 - GPIO Control */
1478 0x0CFB, /* R134 - GPIO Configuration (i/o) */
1479 0x0C1F, /* R135 - GPIO Pin Polarity / Type */
1480 0x0000, /* R136 */
1481 0x0000, /* R137 */
1482 0x0000, /* R138 */
1483 0x0000, /* R139 */
1484 0x0300, /* R140 - GPIO Function Select 1 */
1485 0x1110, /* R141 - GPIO Function Select 2 */
1486 0x0013, /* R142 - GPIO Function Select 3 */
1487 0x0003, /* R143 - GPIO Function Select 4 */
1488 0x0000, /* R144 - Digitiser Control (1) */
1489 0x0002, /* R145 - Digitiser Control (2) */
1490 0x0000, /* R146 */
1491 0x0000, /* R147 */
1492 0x0000, /* R148 */
1493 0x0000, /* R149 */
1494 0x0000, /* R150 */
1495 0x0000, /* R151 */
1496 0x7000, /* R152 - AUX1 Readback */
1497 0x7000, /* R153 - AUX2 Readback */
1498 0x7000, /* R154 - AUX3 Readback */
1499 0x7000, /* R155 - AUX4 Readback */
1500 0x0000, /* R156 - USB Voltage Readback */
1501 0x0000, /* R157 - LINE Voltage Readback */
1502 0x0000, /* R158 - BATT Voltage Readback */
1503 0x0000, /* R159 - Chip Temp Readback */
1504 0x0000, /* R160 */
1505 0x0000, /* R161 */
1506 0x0000, /* R162 */
1507 0x0000, /* R163 - Generic Comparator Control */
1508 0x0000, /* R164 - Generic comparator 1 */
1509 0x0000, /* R165 - Generic comparator 2 */
1510 0x0000, /* R166 - Generic comparator 3 */
1511 0x0000, /* R167 - Generic comparator 4 */
1512 0xA00F, /* R168 - Battery Charger Control 1 */
1513 0x0B06, /* R169 - Battery Charger Control 2 */
1514 0x0000, /* R170 - Battery Charger Control 3 */
1515 0x0000, /* R171 */
1516 0x0000, /* R172 - Current Sink Driver A */
1517 0x0000, /* R173 - CSA Flash control */
1518 0x0000, /* R174 */
1519 0x0000, /* R175 */
1520 0x0000, /* R176 - DCDC/LDO requested */
1521 0x032D, /* R177 - DCDC Active options */
1522 0x0000, /* R178 - DCDC Sleep options */
1523 0x0025, /* R179 - Power-check comparator */
1524 0x000E, /* R180 - DCDC1 Control */
1525 0x0C00, /* R181 - DCDC1 Timeouts */
1526 0x1006, /* R182 - DCDC1 Low Power */
1527 0x0018, /* R183 - DCDC2 Control */
1528 0x0000, /* R184 - DCDC2 Timeouts */
1529 0x0000, /* R185 */
1530 0x0026, /* R186 - DCDC3 Control */
1531 0x0400, /* R187 - DCDC3 Timeouts */
1532 0x0006, /* R188 - DCDC3 Low Power */
1533 0x0062, /* R189 - DCDC4 Control */
1534 0x0800, /* R190 - DCDC4 Timeouts */
1535 0x0006, /* R191 - DCDC4 Low Power */
1536 0x0008, /* R192 */
1537 0x0000, /* R193 */
1538 0x0000, /* R194 */
1539 0x000A, /* R195 */
1540 0x1000, /* R196 */
1541 0x0006, /* R197 */
1542 0x0000, /* R198 */
1543 0x0003, /* R199 - Limit Switch Control */
1544 0x0006, /* R200 - LDO1 Control */
1545 0x0000, /* R201 - LDO1 Timeouts */
1546 0x001C, /* R202 - LDO1 Low Power */
1547 0x0010, /* R203 - LDO2 Control */
1548 0x0C00, /* R204 - LDO2 Timeouts */
1549 0x001C, /* R205 - LDO2 Low Power */
1550 0x001F, /* R206 - LDO3 Control */
1551 0x0800, /* R207 - LDO3 Timeouts */
1552 0x001C, /* R208 - LDO3 Low Power */
1553 0x000A, /* R209 - LDO4 Control */
1554 0x0800, /* R210 - LDO4 Timeouts */
1555 0x001C, /* R211 - LDO4 Low Power */
1556 0x0000, /* R212 */
1557 0x0000, /* R213 */
1558 0x0000, /* R214 */
1559 0x0000, /* R215 - VCC_FAULT Masks */
1560 0x001F, /* R216 - Main Bandgap Control */
1561 0x0000, /* R217 - OSC Control */
1562 0x9000, /* R218 - RTC Tick Control */
1563 0x0000, /* R219 - Security1 */
1564 0x4000, /* R220 */
1565 0x0000, /* R221 */
1566 0x0000, /* R222 */
1567 0x0000, /* R223 */
1568 0x0000, /* R224 - Signal overrides */
1569 0x0000, /* R225 - DCDC/LDO status */
1570 0x0000, /* R226 - Charger Overides/status */
1571 0x0000, /* R227 - misc overrides */
1572 0x0000, /* R228 - Supply overrides/status 1 */
1573 0x0000, /* R229 - Supply overrides/status 2 */
1574 0xE000, /* R230 - GPIO Pin Status */
1575 0x0000, /* R231 - comparotor overrides */
1576 0x0000, /* R232 */
1577 0x0000, /* R233 - State Machine status */
1578 0x1200, /* R234 - FLL Test 1 */
1579 0x0000, /* R235 */
1580 0x8000, /* R236 */
1581 0x0000, /* R237 */
1582 0x0000, /* R238 */
1583 0x0000, /* R239 */
1584 0x0003, /* R240 */
1585 0x0000, /* R241 */
1586 0x0000, /* R242 */
1587 0x0004, /* R243 */
1588 0x0300, /* R244 */
1589 0x0000, /* R245 */
1590 0x0200, /* R246 */
1591 0x1000, /* R247 */
1592 0x1000, /* R248 - DCDC1 Test Controls */
1593 0x1000, /* R249 */
1594 0x1000, /* R250 - DCDC3 Test Controls */
1595 0x1000, /* R251 - DCDC4 Test Controls */
1596};
1597#endif
1598
1599#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_2
1600
1601#undef WM8350_HAVE_CONFIG_MODE
1602#define WM8350_HAVE_CONFIG_MODE
1603
1604const u16 wm8351_mode2_defaults[] = {
1605 0x6143, /* R0 - Reset/ID */
1606 0x0000, /* R1 - ID */
1607 0x0001, /* R2 - Revision */
1608 0x1C02, /* R3 - System Control 1 */
1609 0x0214, /* R4 - System Control 2 */
1610 0x0000, /* R5 - System Hibernate */
1611 0x8A00, /* R6 - Interface Control */
1612 0x0000, /* R7 */
1613 0x8000, /* R8 - Power mgmt (1) */
1614 0x0000, /* R9 - Power mgmt (2) */
1615 0x0000, /* R10 - Power mgmt (3) */
1616 0x2000, /* R11 - Power mgmt (4) */
1617 0x0E00, /* R12 - Power mgmt (5) */
1618 0x0000, /* R13 - Power mgmt (6) */
1619 0x0000, /* R14 - Power mgmt (7) */
1620 0x0000, /* R15 */
1621 0x0000, /* R16 - RTC Seconds/Minutes */
1622 0x0100, /* R17 - RTC Hours/Day */
1623 0x0101, /* R18 - RTC Date/Month */
1624 0x1400, /* R19 - RTC Year */
1625 0x0000, /* R20 - Alarm Seconds/Minutes */
1626 0x0000, /* R21 - Alarm Hours/Day */
1627 0x0000, /* R22 - Alarm Date/Month */
1628 0x0320, /* R23 - RTC Time Control */
1629 0x0000, /* R24 - System Interrupts */
1630 0x0000, /* R25 - Interrupt Status 1 */
1631 0x0000, /* R26 - Interrupt Status 2 */
1632 0x0000, /* R27 */
1633 0x0000, /* R28 - Under Voltage Interrupt status */
1634 0x0000, /* R29 - Over Current Interrupt status */
1635 0x0000, /* R30 - GPIO Interrupt Status */
1636 0x0000, /* R31 - Comparator Interrupt Status */
1637 0x3FFF, /* R32 - System Interrupts Mask */
1638 0x0000, /* R33 - Interrupt Status 1 Mask */
1639 0x0000, /* R34 - Interrupt Status 2 Mask */
1640 0x0000, /* R35 */
1641 0x0000, /* R36 - Under Voltage Interrupt status Mask */
1642 0x0000, /* R37 - Over Current Interrupt status Mask */
1643 0x0000, /* R38 - GPIO Interrupt Status Mask */
1644 0x0000, /* R39 - Comparator Interrupt Status Mask */
1645 0x0040, /* R40 - Clock Control 1 */
1646 0x0000, /* R41 - Clock Control 2 */
1647 0x3A00, /* R42 - FLL Control 1 */
1648 0x7086, /* R43 - FLL Control 2 */
1649 0xC226, /* R44 - FLL Control 3 */
1650 0x0000, /* R45 - FLL Control 4 */
1651 0x0000, /* R46 */
1652 0x0000, /* R47 */
1653 0x0000, /* R48 - DAC Control */
1654 0x0000, /* R49 */
1655 0x00C0, /* R50 - DAC Digital Volume L */
1656 0x00C0, /* R51 - DAC Digital Volume R */
1657 0x0000, /* R52 */
1658 0x0040, /* R53 - DAC LR Rate */
1659 0x0000, /* R54 - DAC Clock Control */
1660 0x0000, /* R55 */
1661 0x0000, /* R56 */
1662 0x0000, /* R57 */
1663 0x4000, /* R58 - DAC Mute */
1664 0x0000, /* R59 - DAC Mute Volume */
1665 0x0000, /* R60 - DAC Side */
1666 0x0000, /* R61 */
1667 0x0000, /* R62 */
1668 0x0000, /* R63 */
1669 0x8000, /* R64 - ADC Control */
1670 0x0000, /* R65 */
1671 0x00C0, /* R66 - ADC Digital Volume L */
1672 0x00C0, /* R67 - ADC Digital Volume R */
1673 0x0000, /* R68 - ADC Divider */
1674 0x0000, /* R69 */
1675 0x0040, /* R70 - ADC LR Rate */
1676 0x0000, /* R71 */
1677 0x0303, /* R72 - Input Control */
1678 0x0000, /* R73 - IN3 Input Control */
1679 0x0000, /* R74 - Mic Bias Control */
1680 0x0000, /* R75 */
1681 0x0000, /* R76 - Output Control */
1682 0x0000, /* R77 - Jack Detect */
1683 0x0000, /* R78 - Anti Pop Control */
1684 0x0000, /* R79 */
1685 0x0040, /* R80 - Left Input Volume */
1686 0x0040, /* R81 - Right Input Volume */
1687 0x0000, /* R82 */
1688 0x0000, /* R83 */
1689 0x0000, /* R84 */
1690 0x0000, /* R85 */
1691 0x0000, /* R86 */
1692 0x0000, /* R87 */
1693 0x0800, /* R88 - Left Mixer Control */
1694 0x1000, /* R89 - Right Mixer Control */
1695 0x0000, /* R90 */
1696 0x0000, /* R91 */
1697 0x0000, /* R92 - OUT3 Mixer Control */
1698 0x0000, /* R93 - OUT4 Mixer Control */
1699 0x0000, /* R94 */
1700 0x0000, /* R95 */
1701 0x0000, /* R96 - Output Left Mixer Volume */
1702 0x0000, /* R97 - Output Right Mixer Volume */
1703 0x0000, /* R98 - Input Mixer Volume L */
1704 0x0000, /* R99 - Input Mixer Volume R */
1705 0x0000, /* R100 - Input Mixer Volume */
1706 0x0000, /* R101 */
1707 0x0000, /* R102 */
1708 0x0000, /* R103 */
1709 0x00E4, /* R104 - OUT1L Volume */
1710 0x00E4, /* R105 - OUT1R Volume */
1711 0x00E4, /* R106 - OUT2L Volume */
1712 0x02E4, /* R107 - OUT2R Volume */
1713 0x0000, /* R108 */
1714 0x0000, /* R109 */
1715 0x0000, /* R110 */
1716 0x0000, /* R111 - BEEP Volume */
1717 0x0A00, /* R112 - AI Formating */
1718 0x0000, /* R113 - ADC DAC COMP */
1719 0x0020, /* R114 - AI ADC Control */
1720 0x0020, /* R115 - AI DAC Control */
1721 0x0000, /* R116 */
1722 0x0000, /* R117 */
1723 0x0000, /* R118 */
1724 0x0000, /* R119 */
1725 0x0000, /* R120 */
1726 0x0000, /* R121 */
1727 0x0000, /* R122 */
1728 0x0000, /* R123 */
1729 0x0000, /* R124 */
1730 0x0000, /* R125 */
1731 0x0000, /* R126 */
1732 0x0000, /* R127 */
1733 0x1FFF, /* R128 - GPIO Debounce */
1734 0x0000, /* R129 - GPIO Pin pull up Control */
1735 0x0110, /* R130 - GPIO Pull down Control */
1736 0x0000, /* R131 - GPIO Interrupt Mode */
1737 0x0000, /* R132 */
1738 0x0000, /* R133 - GPIO Control */
1739 0x09FA, /* R134 - GPIO Configuration (i/o) */
1740 0x0DF6, /* R135 - GPIO Pin Polarity / Type */
1741 0x0000, /* R136 */
1742 0x0000, /* R137 */
1743 0x0000, /* R138 */
1744 0x0000, /* R139 */
1745 0x1310, /* R140 - GPIO Function Select 1 */
1746 0x0003, /* R141 - GPIO Function Select 2 */
1747 0x2000, /* R142 - GPIO Function Select 3 */
1748 0x0000, /* R143 - GPIO Function Select 4 */
1749 0x0000, /* R144 - Digitiser Control (1) */
1750 0x0002, /* R145 - Digitiser Control (2) */
1751 0x0000, /* R146 */
1752 0x0000, /* R147 */
1753 0x0000, /* R148 */
1754 0x0000, /* R149 */
1755 0x0000, /* R150 */
1756 0x0000, /* R151 */
1757 0x7000, /* R152 - AUX1 Readback */
1758 0x7000, /* R153 - AUX2 Readback */
1759 0x7000, /* R154 - AUX3 Readback */
1760 0x7000, /* R155 - AUX4 Readback */
1761 0x0000, /* R156 - USB Voltage Readback */
1762 0x0000, /* R157 - LINE Voltage Readback */
1763 0x0000, /* R158 - BATT Voltage Readback */
1764 0x0000, /* R159 - Chip Temp Readback */
1765 0x0000, /* R160 */
1766 0x0000, /* R161 */
1767 0x0000, /* R162 */
1768 0x0000, /* R163 - Generic Comparator Control */
1769 0x0000, /* R164 - Generic comparator 1 */
1770 0x0000, /* R165 - Generic comparator 2 */
1771 0x0000, /* R166 - Generic comparator 3 */
1772 0x0000, /* R167 - Generic comparator 4 */
1773 0xA00F, /* R168 - Battery Charger Control 1 */
1774 0x0B06, /* R169 - Battery Charger Control 2 */
1775 0x0000, /* R170 - Battery Charger Control 3 */
1776 0x0000, /* R171 */
1777 0x0000, /* R172 - Current Sink Driver A */
1778 0x0000, /* R173 - CSA Flash control */
1779 0x0000, /* R174 */
1780 0x0000, /* R175 */
1781 0x0000, /* R176 - DCDC/LDO requested */
1782 0x032D, /* R177 - DCDC Active options */
1783 0x0000, /* R178 - DCDC Sleep options */
1784 0x0025, /* R179 - Power-check comparator */
1785 0x001A, /* R180 - DCDC1 Control */
1786 0x0800, /* R181 - DCDC1 Timeouts */
1787 0x1006, /* R182 - DCDC1 Low Power */
1788 0x0018, /* R183 - DCDC2 Control */
1789 0x0000, /* R184 - DCDC2 Timeouts */
1790 0x0000, /* R185 */
1791 0x0056, /* R186 - DCDC3 Control */
1792 0x0400, /* R187 - DCDC3 Timeouts */
1793 0x0006, /* R188 - DCDC3 Low Power */
1794 0x0026, /* R189 - DCDC4 Control */
1795 0x0C00, /* R190 - DCDC4 Timeouts */
1796 0x0006, /* R191 - DCDC4 Low Power */
1797 0x0008, /* R192 */
1798 0x0000, /* R193 */
1799 0x0000, /* R194 */
1800 0x0026, /* R195 */
1801 0x0C00, /* R196 */
1802 0x0006, /* R197 */
1803 0x0000, /* R198 */
1804 0x0003, /* R199 - Limit Switch Control */
1805 0x001C, /* R200 - LDO1 Control */
1806 0x0400, /* R201 - LDO1 Timeouts */
1807 0x001C, /* R202 - LDO1 Low Power */
1808 0x0010, /* R203 - LDO2 Control */
1809 0x0C00, /* R204 - LDO2 Timeouts */
1810 0x001C, /* R205 - LDO2 Low Power */
1811 0x0015, /* R206 - LDO3 Control */
1812 0x0000, /* R207 - LDO3 Timeouts */
1813 0x001C, /* R208 - LDO3 Low Power */
1814 0x001A, /* R209 - LDO4 Control */
1815 0x0000, /* R210 - LDO4 Timeouts */
1816 0x001C, /* R211 - LDO4 Low Power */
1817 0x0000, /* R212 */
1818 0x0000, /* R213 */
1819 0x0000, /* R214 */
1820 0x0000, /* R215 - VCC_FAULT Masks */
1821 0x001F, /* R216 - Main Bandgap Control */
1822 0x0000, /* R217 - OSC Control */
1823 0x9000, /* R218 - RTC Tick Control */
1824 0x0000, /* R219 - Security1 */
1825 0x4000, /* R220 */
1826 0x0000, /* R221 */
1827 0x0000, /* R222 */
1828 0x0000, /* R223 */
1829 0x0000, /* R224 - Signal overrides */
1830 0x0000, /* R225 - DCDC/LDO status */
1831 0x0000, /* R226 - Charger Overides/status */
1832 0x0000, /* R227 - misc overrides */
1833 0x0000, /* R228 - Supply overrides/status 1 */
1834 0x0000, /* R229 - Supply overrides/status 2 */
1835 0xE000, /* R230 - GPIO Pin Status */
1836 0x0000, /* R231 - comparotor overrides */
1837 0x0000, /* R232 */
1838 0x0000, /* R233 - State Machine status */
1839 0x1200, /* R234 - FLL Test 1 */
1840 0x0000, /* R235 */
1841 0x8000, /* R236 */
1842 0x0000, /* R237 */
1843 0x0000, /* R238 */
1844 0x0000, /* R239 */
1845 0x0003, /* R240 */
1846 0x0000, /* R241 */
1847 0x0000, /* R242 */
1848 0x0004, /* R243 */
1849 0x0300, /* R244 */
1850 0x0000, /* R245 */
1851 0x0200, /* R246 */
1852 0x0000, /* R247 */
1853 0x1000, /* R248 - DCDC1 Test Controls */
1854 0x1000, /* R249 */
1855 0x1000, /* R250 - DCDC3 Test Controls */
1856 0x1000, /* R251 - DCDC4 Test Controls */
1857};
1858#endif
1859
1860#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_3
1861
1862#undef WM8350_HAVE_CONFIG_MODE
1863#define WM8350_HAVE_CONFIG_MODE
1864
1865const u16 wm8351_mode3_defaults[] = {
1866 0x6143, /* R0 - Reset/ID */
1867 0x0000, /* R1 - ID */
1868 0x0001, /* R2 - Revision */
1869 0x1C02, /* R3 - System Control 1 */
1870 0x0204, /* R4 - System Control 2 */
1871 0x0000, /* R5 - System Hibernate */
1872 0x8A00, /* R6 - Interface Control */
1873 0x0000, /* R7 */
1874 0x8000, /* R8 - Power mgmt (1) */
1875 0x0000, /* R9 - Power mgmt (2) */
1876 0x0000, /* R10 - Power mgmt (3) */
1877 0x2000, /* R11 - Power mgmt (4) */
1878 0x0E00, /* R12 - Power mgmt (5) */
1879 0x0000, /* R13 - Power mgmt (6) */
1880 0x0000, /* R14 - Power mgmt (7) */
1881 0x0000, /* R15 */
1882 0x0000, /* R16 - RTC Seconds/Minutes */
1883 0x0100, /* R17 - RTC Hours/Day */
1884 0x0101, /* R18 - RTC Date/Month */
1885 0x1400, /* R19 - RTC Year */
1886 0x0000, /* R20 - Alarm Seconds/Minutes */
1887 0x0000, /* R21 - Alarm Hours/Day */
1888 0x0000, /* R22 - Alarm Date/Month */
1889 0x0320, /* R23 - RTC Time Control */
1890 0x0000, /* R24 - System Interrupts */
1891 0x0000, /* R25 - Interrupt Status 1 */
1892 0x0000, /* R26 - Interrupt Status 2 */
1893 0x0000, /* R27 */
1894 0x0000, /* R28 - Under Voltage Interrupt status */
1895 0x0000, /* R29 - Over Current Interrupt status */
1896 0x0000, /* R30 - GPIO Interrupt Status */
1897 0x0000, /* R31 - Comparator Interrupt Status */
1898 0x3FFF, /* R32 - System Interrupts Mask */
1899 0x0000, /* R33 - Interrupt Status 1 Mask */
1900 0x0000, /* R34 - Interrupt Status 2 Mask */
1901 0x0000, /* R35 */
1902 0x0000, /* R36 - Under Voltage Interrupt status Mask */
1903 0x0000, /* R37 - Over Current Interrupt status Mask */
1904 0x0000, /* R38 - GPIO Interrupt Status Mask */
1905 0x0000, /* R39 - Comparator Interrupt Status Mask */
1906 0x0040, /* R40 - Clock Control 1 */
1907 0x0000, /* R41 - Clock Control 2 */
1908 0x3A00, /* R42 - FLL Control 1 */
1909 0x7086, /* R43 - FLL Control 2 */
1910 0xC226, /* R44 - FLL Control 3 */
1911 0x0000, /* R45 - FLL Control 4 */
1912 0x0000, /* R46 */
1913 0x0000, /* R47 */
1914 0x0000, /* R48 - DAC Control */
1915 0x0000, /* R49 */
1916 0x00C0, /* R50 - DAC Digital Volume L */
1917 0x00C0, /* R51 - DAC Digital Volume R */
1918 0x0000, /* R52 */
1919 0x0040, /* R53 - DAC LR Rate */
1920 0x0000, /* R54 - DAC Clock Control */
1921 0x0000, /* R55 */
1922 0x0000, /* R56 */
1923 0x0000, /* R57 */
1924 0x4000, /* R58 - DAC Mute */
1925 0x0000, /* R59 - DAC Mute Volume */
1926 0x0000, /* R60 - DAC Side */
1927 0x0000, /* R61 */
1928 0x0000, /* R62 */
1929 0x0000, /* R63 */
1930 0x8000, /* R64 - ADC Control */
1931 0x0000, /* R65 */
1932 0x00C0, /* R66 - ADC Digital Volume L */
1933 0x00C0, /* R67 - ADC Digital Volume R */
1934 0x0000, /* R68 - ADC Divider */
1935 0x0000, /* R69 */
1936 0x0040, /* R70 - ADC LR Rate */
1937 0x0000, /* R71 */
1938 0x0303, /* R72 - Input Control */
1939 0x0000, /* R73 - IN3 Input Control */
1940 0x0000, /* R74 - Mic Bias Control */
1941 0x0000, /* R75 */
1942 0x0000, /* R76 - Output Control */
1943 0x0000, /* R77 - Jack Detect */
1944 0x0000, /* R78 - Anti Pop Control */
1945 0x0000, /* R79 */
1946 0x0040, /* R80 - Left Input Volume */
1947 0x0040, /* R81 - Right Input Volume */
1948 0x0000, /* R82 */
1949 0x0000, /* R83 */
1950 0x0000, /* R84 */
1951 0x0000, /* R85 */
1952 0x0000, /* R86 */
1953 0x0000, /* R87 */
1954 0x0800, /* R88 - Left Mixer Control */
1955 0x1000, /* R89 - Right Mixer Control */
1956 0x0000, /* R90 */
1957 0x0000, /* R91 */
1958 0x0000, /* R92 - OUT3 Mixer Control */
1959 0x0000, /* R93 - OUT4 Mixer Control */
1960 0x0000, /* R94 */
1961 0x0000, /* R95 */
1962 0x0000, /* R96 - Output Left Mixer Volume */
1963 0x0000, /* R97 - Output Right Mixer Volume */
1964 0x0000, /* R98 - Input Mixer Volume L */
1965 0x0000, /* R99 - Input Mixer Volume R */
1966 0x0000, /* R100 - Input Mixer Volume */
1967 0x0000, /* R101 */
1968 0x0000, /* R102 */
1969 0x0000, /* R103 */
1970 0x00E4, /* R104 - OUT1L Volume */
1971 0x00E4, /* R105 - OUT1R Volume */
1972 0x00E4, /* R106 - OUT2L Volume */
1973 0x02E4, /* R107 - OUT2R Volume */
1974 0x0000, /* R108 */
1975 0x0000, /* R109 */
1976 0x0000, /* R110 */
1977 0x0000, /* R111 - BEEP Volume */
1978 0x0A00, /* R112 - AI Formating */
1979 0x0000, /* R113 - ADC DAC COMP */
1980 0x0020, /* R114 - AI ADC Control */
1981 0x0020, /* R115 - AI DAC Control */
1982 0x0000, /* R116 */
1983 0x0000, /* R117 */
1984 0x0000, /* R118 */
1985 0x0000, /* R119 */
1986 0x0000, /* R120 */
1987 0x0000, /* R121 */
1988 0x0000, /* R122 */
1989 0x0000, /* R123 */
1990 0x0000, /* R124 */
1991 0x0000, /* R125 */
1992 0x0000, /* R126 */
1993 0x0000, /* R127 */
1994 0x1FFF, /* R128 - GPIO Debounce */
1995 0x0010, /* R129 - GPIO Pin pull up Control */
1996 0x0000, /* R130 - GPIO Pull down Control */
1997 0x0000, /* R131 - GPIO Interrupt Mode */
1998 0x0000, /* R132 */
1999 0x0000, /* R133 - GPIO Control */
2000 0x0BFB, /* R134 - GPIO Configuration (i/o) */
2001 0x0FFD, /* R135 - GPIO Pin Polarity / Type */
2002 0x0000, /* R136 */
2003 0x0000, /* R137 */
2004 0x0000, /* R138 */
2005 0x0000, /* R139 */
2006 0x0310, /* R140 - GPIO Function Select 1 */
2007 0x0001, /* R141 - GPIO Function Select 2 */
2008 0x2300, /* R142 - GPIO Function Select 3 */
2009 0x0003, /* R143 - GPIO Function Select 4 */
2010 0x0000, /* R144 - Digitiser Control (1) */
2011 0x0002, /* R145 - Digitiser Control (2) */
2012 0x0000, /* R146 */
2013 0x0000, /* R147 */
2014 0x0000, /* R148 */
2015 0x0000, /* R149 */
2016 0x0000, /* R150 */
2017 0x0000, /* R151 */
2018 0x7000, /* R152 - AUX1 Readback */
2019 0x7000, /* R153 - AUX2 Readback */
2020 0x7000, /* R154 - AUX3 Readback */
2021 0x7000, /* R155 - AUX4 Readback */
2022 0x0000, /* R156 - USB Voltage Readback */
2023 0x0000, /* R157 - LINE Voltage Readback */
2024 0x0000, /* R158 - BATT Voltage Readback */
2025 0x0000, /* R159 - Chip Temp Readback */
2026 0x0000, /* R160 */
2027 0x0000, /* R161 */
2028 0x0000, /* R162 */
2029 0x0000, /* R163 - Generic Comparator Control */
2030 0x0000, /* R164 - Generic comparator 1 */
2031 0x0000, /* R165 - Generic comparator 2 */
2032 0x0000, /* R166 - Generic comparator 3 */
2033 0x0000, /* R167 - Generic comparator 4 */
2034 0xA00F, /* R168 - Battery Charger Control 1 */
2035 0x0B06, /* R169 - Battery Charger Control 2 */
2036 0x0000, /* R170 - Battery Charger Control 3 */
2037 0x0000, /* R171 */
2038 0x0000, /* R172 - Current Sink Driver A */
2039 0x0000, /* R173 - CSA Flash control */
2040 0x0000, /* R174 */
2041 0x0000, /* R175 */
2042 0x0000, /* R176 - DCDC/LDO requested */
2043 0x032D, /* R177 - DCDC Active options */
2044 0x0000, /* R178 - DCDC Sleep options */
2045 0x0025, /* R179 - Power-check comparator */
2046 0x000E, /* R180 - DCDC1 Control */
2047 0x0400, /* R181 - DCDC1 Timeouts */
2048 0x1006, /* R182 - DCDC1 Low Power */
2049 0x0018, /* R183 - DCDC2 Control */
2050 0x0000, /* R184 - DCDC2 Timeouts */
2051 0x0000, /* R185 */
2052 0x0026, /* R186 - DCDC3 Control */
2053 0x0800, /* R187 - DCDC3 Timeouts */
2054 0x0006, /* R188 - DCDC3 Low Power */
2055 0x0062, /* R189 - DCDC4 Control */
2056 0x1400, /* R190 - DCDC4 Timeouts */
2057 0x0006, /* R191 - DCDC4 Low Power */
2058 0x0008, /* R192 */
2059 0x0000, /* R193 */
2060 0x0000, /* R194 */
2061 0x0026, /* R195 */
2062 0x0400, /* R196 */
2063 0x0006, /* R197 */
2064 0x0000, /* R198 */
2065 0x0003, /* R199 - Limit Switch Control */
2066 0x0006, /* R200 - LDO1 Control */
2067 0x0C00, /* R201 - LDO1 Timeouts */
2068 0x001C, /* R202 - LDO1 Low Power */
2069 0x0016, /* R203 - LDO2 Control */
2070 0x0000, /* R204 - LDO2 Timeouts */
2071 0x001C, /* R205 - LDO2 Low Power */
2072 0x0019, /* R206 - LDO3 Control */
2073 0x0000, /* R207 - LDO3 Timeouts */
2074 0x001C, /* R208 - LDO3 Low Power */
2075 0x001A, /* R209 - LDO4 Control */
2076 0x1000, /* R210 - LDO4 Timeouts */
2077 0x001C, /* R211 - LDO4 Low Power */
2078 0x0000, /* R212 */
2079 0x0000, /* R213 */
2080 0x0000, /* R214 */
2081 0x0000, /* R215 - VCC_FAULT Masks */
2082 0x001F, /* R216 - Main Bandgap Control */
2083 0x0000, /* R217 - OSC Control */
2084 0x9000, /* R218 - RTC Tick Control */
2085 0x0000, /* R219 - Security1 */
2086 0x4000, /* R220 */
2087 0x0000, /* R221 */
2088 0x0000, /* R222 */
2089 0x0000, /* R223 */
2090 0x0000, /* R224 - Signal overrides */
2091 0x0000, /* R225 - DCDC/LDO status */
2092 0x0000, /* R226 - Charger Overides/status */
2093 0x0000, /* R227 - misc overrides */
2094 0x0000, /* R228 - Supply overrides/status 1 */
2095 0x0000, /* R229 - Supply overrides/status 2 */
2096 0xE000, /* R230 - GPIO Pin Status */
2097 0x0000, /* R231 - comparotor overrides */
2098 0x0000, /* R232 */
2099 0x0000, /* R233 - State Machine status */
2100 0x1200, /* R234 - FLL Test 1 */
2101 0x0000, /* R235 */
2102 0x8000, /* R236 */
2103 0x0000, /* R237 */
2104 0x0000, /* R238 */
2105 0x0000, /* R239 */
2106 0x0003, /* R240 */
2107 0x0000, /* R241 */
2108 0x0000, /* R242 */
2109 0x0004, /* R243 */
2110 0x0300, /* R244 */
2111 0x0000, /* R245 */
2112 0x0200, /* R246 */
2113 0x0000, /* R247 */
2114 0x1000, /* R248 - DCDC1 Test Controls */
2115 0x1000, /* R249 */
2116 0x1000, /* R250 - DCDC3 Test Controls */
2117 0x1000, /* R251 - DCDC4 Test Controls */
2118};
2119#endif
2120
2121#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_0
2122
2123#undef WM8350_HAVE_CONFIG_MODE
2124#define WM8350_HAVE_CONFIG_MODE
2125
2126const u16 wm8352_mode0_defaults[] = {
2127 0x6143, /* R0 - Reset/ID */
2128 0x0000, /* R1 - ID */
2129 0x0002, /* R2 - Revision */
2130 0x1C02, /* R3 - System Control 1 */
2131 0x0004, /* R4 - System Control 2 */
2132 0x0000, /* R5 - System Hibernate */
2133 0x8A00, /* R6 - Interface Control */
2134 0x0000, /* R7 */
2135 0x8000, /* R8 - Power mgmt (1) */
2136 0x0000, /* R9 - Power mgmt (2) */
2137 0x0000, /* R10 - Power mgmt (3) */
2138 0x2000, /* R11 - Power mgmt (4) */
2139 0x0E00, /* R12 - Power mgmt (5) */
2140 0x0000, /* R13 - Power mgmt (6) */
2141 0x0000, /* R14 - Power mgmt (7) */
2142 0x0000, /* R15 */
2143 0x0000, /* R16 - RTC Seconds/Minutes */
2144 0x0100, /* R17 - RTC Hours/Day */
2145 0x0101, /* R18 - RTC Date/Month */
2146 0x1400, /* R19 - RTC Year */
2147 0x0000, /* R20 - Alarm Seconds/Minutes */
2148 0x0000, /* R21 - Alarm Hours/Day */
2149 0x0000, /* R22 - Alarm Date/Month */
2150 0x0320, /* R23 - RTC Time Control */
2151 0x0000, /* R24 - System Interrupts */
2152 0x0000, /* R25 - Interrupt Status 1 */
2153 0x0000, /* R26 - Interrupt Status 2 */
2154 0x0000, /* R27 */
2155 0x0000, /* R28 - Under Voltage Interrupt status */
2156 0x0000, /* R29 - Over Current Interrupt status */
2157 0x0000, /* R30 - GPIO Interrupt Status */
2158 0x0000, /* R31 - Comparator Interrupt Status */
2159 0x3FFF, /* R32 - System Interrupts Mask */
2160 0x0000, /* R33 - Interrupt Status 1 Mask */
2161 0x0000, /* R34 - Interrupt Status 2 Mask */
2162 0x0000, /* R35 */
2163 0x0000, /* R36 - Under Voltage Interrupt status Mask */
2164 0x0000, /* R37 - Over Current Interrupt status Mask */
2165 0x0000, /* R38 - GPIO Interrupt Status Mask */
2166 0x0000, /* R39 - Comparator Interrupt Status Mask */
2167 0x0040, /* R40 - Clock Control 1 */
2168 0x0000, /* R41 - Clock Control 2 */
2169 0x3A00, /* R42 - FLL Control 1 */
2170 0x7086, /* R43 - FLL Control 2 */
2171 0xC226, /* R44 - FLL Control 3 */
2172 0x0000, /* R45 - FLL Control 4 */
2173 0x0000, /* R46 */
2174 0x0000, /* R47 */
2175 0x0000, /* R48 - DAC Control */
2176 0x0000, /* R49 */
2177 0x00C0, /* R50 - DAC Digital Volume L */
2178 0x00C0, /* R51 - DAC Digital Volume R */
2179 0x0000, /* R52 */
2180 0x0040, /* R53 - DAC LR Rate */
2181 0x0000, /* R54 - DAC Clock Control */
2182 0x0000, /* R55 */
2183 0x0000, /* R56 */
2184 0x0000, /* R57 */
2185 0x4000, /* R58 - DAC Mute */
2186 0x0000, /* R59 - DAC Mute Volume */
2187 0x0000, /* R60 - DAC Side */
2188 0x0000, /* R61 */
2189 0x0000, /* R62 */
2190 0x0000, /* R63 */
2191 0x8000, /* R64 - ADC Control */
2192 0x0000, /* R65 */
2193 0x00C0, /* R66 - ADC Digital Volume L */
2194 0x00C0, /* R67 - ADC Digital Volume R */
2195 0x0000, /* R68 - ADC Divider */
2196 0x0000, /* R69 */
2197 0x0040, /* R70 - ADC LR Rate */
2198 0x0000, /* R71 */
2199 0x0303, /* R72 - Input Control */
2200 0x0000, /* R73 - IN3 Input Control */
2201 0x0000, /* R74 - Mic Bias Control */
2202 0x0000, /* R75 */
2203 0x0000, /* R76 - Output Control */
2204 0x0000, /* R77 - Jack Detect */
2205 0x0000, /* R78 - Anti Pop Control */
2206 0x0000, /* R79 */
2207 0x0040, /* R80 - Left Input Volume */
2208 0x0040, /* R81 - Right Input Volume */
2209 0x0000, /* R82 */
2210 0x0000, /* R83 */
2211 0x0000, /* R84 */
2212 0x0000, /* R85 */
2213 0x0000, /* R86 */
2214 0x0000, /* R87 */
2215 0x0800, /* R88 - Left Mixer Control */
2216 0x1000, /* R89 - Right Mixer Control */
2217 0x0000, /* R90 */
2218 0x0000, /* R91 */
2219 0x0000, /* R92 - OUT3 Mixer Control */
2220 0x0000, /* R93 - OUT4 Mixer Control */
2221 0x0000, /* R94 */
2222 0x0000, /* R95 */
2223 0x0000, /* R96 - Output Left Mixer Volume */
2224 0x0000, /* R97 - Output Right Mixer Volume */
2225 0x0000, /* R98 - Input Mixer Volume L */
2226 0x0000, /* R99 - Input Mixer Volume R */
2227 0x0000, /* R100 - Input Mixer Volume */
2228 0x0000, /* R101 */
2229 0x0000, /* R102 */
2230 0x0000, /* R103 */
2231 0x00E4, /* R104 - OUT1L Volume */
2232 0x00E4, /* R105 - OUT1R Volume */
2233 0x00E4, /* R106 - OUT2L Volume */
2234 0x02E4, /* R107 - OUT2R Volume */
2235 0x0000, /* R108 */
2236 0x0000, /* R109 */
2237 0x0000, /* R110 */
2238 0x0000, /* R111 - BEEP Volume */
2239 0x0A00, /* R112 - AI Formating */
2240 0x0000, /* R113 - ADC DAC COMP */
2241 0x0020, /* R114 - AI ADC Control */
2242 0x0020, /* R115 - AI DAC Control */
2243 0x0000, /* R116 */
2244 0x0000, /* R117 */
2245 0x0000, /* R118 */
2246 0x0000, /* R119 */
2247 0x0000, /* R120 */
2248 0x0000, /* R121 */
2249 0x0000, /* R122 */
2250 0x0000, /* R123 */
2251 0x0000, /* R124 */
2252 0x0000, /* R125 */
2253 0x0000, /* R126 */
2254 0x0000, /* R127 */
2255 0x1FFF, /* R128 - GPIO Debounce */
2256 0x0000, /* R129 - GPIO Pin pull up Control */
2257 0x0000, /* R130 - GPIO Pull down Control */
2258 0x0000, /* R131 - GPIO Interrupt Mode */
2259 0x0000, /* R132 */
2260 0x0000, /* R133 - GPIO Control */
2261 0x0FFC, /* R134 - GPIO Configuration (i/o) */
2262 0x0FFC, /* R135 - GPIO Pin Polarity / Type */
2263 0x0000, /* R136 */
2264 0x0000, /* R137 */
2265 0x0000, /* R138 */
2266 0x0000, /* R139 */
2267 0x0013, /* R140 - GPIO Function Select 1 */
2268 0x0000, /* R141 - GPIO Function Select 2 */
2269 0x0000, /* R142 - GPIO Function Select 3 */
2270 0x0003, /* R143 - GPIO Function Select 4 */
2271 0x0000, /* R144 - Digitiser Control (1) */
2272 0x0002, /* R145 - Digitiser Control (2) */
2273 0x0000, /* R146 */
2274 0x0000, /* R147 */
2275 0x0000, /* R148 */
2276 0x0000, /* R149 */
2277 0x0000, /* R150 */
2278 0x0000, /* R151 */
2279 0x7000, /* R152 - AUX1 Readback */
2280 0x7000, /* R153 - AUX2 Readback */
2281 0x7000, /* R154 - AUX3 Readback */
2282 0x7000, /* R155 - AUX4 Readback */
2283 0x0000, /* R156 - USB Voltage Readback */
2284 0x0000, /* R157 - LINE Voltage Readback */
2285 0x0000, /* R158 - BATT Voltage Readback */
2286 0x0000, /* R159 - Chip Temp Readback */
2287 0x0000, /* R160 */
2288 0x0000, /* R161 */
2289 0x0000, /* R162 */
2290 0x0000, /* R163 - Generic Comparator Control */
2291 0x0000, /* R164 - Generic comparator 1 */
2292 0x0000, /* R165 - Generic comparator 2 */
2293 0x0000, /* R166 - Generic comparator 3 */
2294 0x0000, /* R167 - Generic comparator 4 */
2295 0xA00F, /* R168 - Battery Charger Control 1 */
2296 0x0B06, /* R169 - Battery Charger Control 2 */
2297 0x0000, /* R170 - Battery Charger Control 3 */
2298 0x0000, /* R171 */
2299 0x0000, /* R172 - Current Sink Driver A */
2300 0x0000, /* R173 - CSA Flash control */
2301 0x0000, /* R174 - Current Sink Driver B */
2302 0x0000, /* R175 - CSB Flash control */
2303 0x0000, /* R176 - DCDC/LDO requested */
2304 0x032D, /* R177 - DCDC Active options */
2305 0x0000, /* R178 - DCDC Sleep options */
2306 0x0025, /* R179 - Power-check comparator */
2307 0x000E, /* R180 - DCDC1 Control */
2308 0x0000, /* R181 - DCDC1 Timeouts */
2309 0x1006, /* R182 - DCDC1 Low Power */
2310 0x0018, /* R183 - DCDC2 Control */
2311 0x0000, /* R184 - DCDC2 Timeouts */
2312 0x0000, /* R185 */
2313 0x0000, /* R186 - DCDC3 Control */
2314 0x0000, /* R187 - DCDC3 Timeouts */
2315 0x0006, /* R188 - DCDC3 Low Power */
2316 0x0000, /* R189 - DCDC4 Control */
2317 0x0000, /* R190 - DCDC4 Timeouts */
2318 0x0006, /* R191 - DCDC4 Low Power */
2319 0x0008, /* R192 - DCDC5 Control */
2320 0x0000, /* R193 - DCDC5 Timeouts */
2321 0x0000, /* R194 */
2322 0x0000, /* R195 - DCDC6 Control */
2323 0x0000, /* R196 - DCDC6 Timeouts */
2324 0x0006, /* R197 - DCDC6 Low Power */
2325 0x0000, /* R198 */
2326 0x0003, /* R199 - Limit Switch Control */
2327 0x001C, /* R200 - LDO1 Control */
2328 0x0000, /* R201 - LDO1 Timeouts */
2329 0x001C, /* R202 - LDO1 Low Power */
2330 0x001B, /* R203 - LDO2 Control */
2331 0x0000, /* R204 - LDO2 Timeouts */
2332 0x001C, /* R205 - LDO2 Low Power */
2333 0x001B, /* R206 - LDO3 Control */
2334 0x0000, /* R207 - LDO3 Timeouts */
2335 0x001C, /* R208 - LDO3 Low Power */
2336 0x001B, /* R209 - LDO4 Control */
2337 0x0000, /* R210 - LDO4 Timeouts */
2338 0x001C, /* R211 - LDO4 Low Power */
2339 0x0000, /* R212 */
2340 0x0000, /* R213 */
2341 0x0000, /* R214 */
2342 0x0000, /* R215 - VCC_FAULT Masks */
2343 0x001F, /* R216 - Main Bandgap Control */
2344 0x0000, /* R217 - OSC Control */
2345 0x9000, /* R218 - RTC Tick Control */
2346 0x0000, /* R219 - Security1 */
2347 0x4000, /* R220 */
2348 0x0000, /* R221 */
2349 0x0000, /* R222 */
2350 0x0000, /* R223 */
2351 0x0000, /* R224 - Signal overrides */
2352 0x0000, /* R225 - DCDC/LDO status */
2353 0x0000, /* R226 - Charger Overides/status */
2354 0x0000, /* R227 - misc overrides */
2355 0x0000, /* R228 - Supply overrides/status 1 */
2356 0x0000, /* R229 - Supply overrides/status 2 */
2357 0xE000, /* R230 - GPIO Pin Status */
2358 0x0000, /* R231 - comparotor overrides */
2359 0x0000, /* R232 */
2360 0x0000, /* R233 - State Machine status */
2361 0x1200, /* R234 */
2362 0x0000, /* R235 */
2363 0x8000, /* R236 */
2364 0x0000, /* R237 */
2365 0x0000, /* R238 */
2366 0x0000, /* R239 */
2367 0x0003, /* R240 */
2368 0x0000, /* R241 */
2369 0x0000, /* R242 */
2370 0x0004, /* R243 */
2371 0x0300, /* R244 */
2372 0x0000, /* R245 */
2373 0x0200, /* R246 */
2374 0x0000, /* R247 */
2375 0x1000, /* R248 - DCDC1 Test Controls */
2376 0x5000, /* R249 */
2377 0x1000, /* R250 - DCDC3 Test Controls */
2378 0x1000, /* R251 - DCDC4 Test Controls */
2379 0x5100, /* R252 */
2380 0x1000, /* R253 - DCDC6 Test Controls */
2381};
2382#endif
2383
2384#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_1
2385
2386#undef WM8350_HAVE_CONFIG_MODE
2387#define WM8350_HAVE_CONFIG_MODE
2388
2389const u16 wm8352_mode1_defaults[] = {
2390 0x6143, /* R0 - Reset/ID */
2391 0x0000, /* R1 - ID */
2392 0x0002, /* R2 - Revision */
2393 0x1C02, /* R3 - System Control 1 */
2394 0x0204, /* R4 - System Control 2 */
2395 0x0000, /* R5 - System Hibernate */
2396 0x8A00, /* R6 - Interface Control */
2397 0x0000, /* R7 */
2398 0x8000, /* R8 - Power mgmt (1) */
2399 0x0000, /* R9 - Power mgmt (2) */
2400 0x0000, /* R10 - Power mgmt (3) */
2401 0x2000, /* R11 - Power mgmt (4) */
2402 0x0E00, /* R12 - Power mgmt (5) */
2403 0x0000, /* R13 - Power mgmt (6) */
2404 0x0000, /* R14 - Power mgmt (7) */
2405 0x0000, /* R15 */
2406 0x0000, /* R16 - RTC Seconds/Minutes */
2407 0x0100, /* R17 - RTC Hours/Day */
2408 0x0101, /* R18 - RTC Date/Month */
2409 0x1400, /* R19 - RTC Year */
2410 0x0000, /* R20 - Alarm Seconds/Minutes */
2411 0x0000, /* R21 - Alarm Hours/Day */
2412 0x0000, /* R22 - Alarm Date/Month */
2413 0x0320, /* R23 - RTC Time Control */
2414 0x0000, /* R24 - System Interrupts */
2415 0x0000, /* R25 - Interrupt Status 1 */
2416 0x0000, /* R26 - Interrupt Status 2 */
2417 0x0000, /* R27 */
2418 0x0000, /* R28 - Under Voltage Interrupt status */
2419 0x0000, /* R29 - Over Current Interrupt status */
2420 0x0000, /* R30 - GPIO Interrupt Status */
2421 0x0000, /* R31 - Comparator Interrupt Status */
2422 0x3FFF, /* R32 - System Interrupts Mask */
2423 0x0000, /* R33 - Interrupt Status 1 Mask */
2424 0x0000, /* R34 - Interrupt Status 2 Mask */
2425 0x0000, /* R35 */
2426 0x0000, /* R36 - Under Voltage Interrupt status Mask */
2427 0x0000, /* R37 - Over Current Interrupt status Mask */
2428 0x0000, /* R38 - GPIO Interrupt Status Mask */
2429 0x0000, /* R39 - Comparator Interrupt Status Mask */
2430 0x0040, /* R40 - Clock Control 1 */
2431 0x0000, /* R41 - Clock Control 2 */
2432 0x3A00, /* R42 - FLL Control 1 */
2433 0x7086, /* R43 - FLL Control 2 */
2434 0xC226, /* R44 - FLL Control 3 */
2435 0x0000, /* R45 - FLL Control 4 */
2436 0x0000, /* R46 */
2437 0x0000, /* R47 */
2438 0x0000, /* R48 - DAC Control */
2439 0x0000, /* R49 */
2440 0x00C0, /* R50 - DAC Digital Volume L */
2441 0x00C0, /* R51 - DAC Digital Volume R */
2442 0x0000, /* R52 */
2443 0x0040, /* R53 - DAC LR Rate */
2444 0x0000, /* R54 - DAC Clock Control */
2445 0x0000, /* R55 */
2446 0x0000, /* R56 */
2447 0x0000, /* R57 */
2448 0x4000, /* R58 - DAC Mute */
2449 0x0000, /* R59 - DAC Mute Volume */
2450 0x0000, /* R60 - DAC Side */
2451 0x0000, /* R61 */
2452 0x0000, /* R62 */
2453 0x0000, /* R63 */
2454 0x8000, /* R64 - ADC Control */
2455 0x0000, /* R65 */
2456 0x00C0, /* R66 - ADC Digital Volume L */
2457 0x00C0, /* R67 - ADC Digital Volume R */
2458 0x0000, /* R68 - ADC Divider */
2459 0x0000, /* R69 */
2460 0x0040, /* R70 - ADC LR Rate */
2461 0x0000, /* R71 */
2462 0x0303, /* R72 - Input Control */
2463 0x0000, /* R73 - IN3 Input Control */
2464 0x0000, /* R74 - Mic Bias Control */
2465 0x0000, /* R75 */
2466 0x0000, /* R76 - Output Control */
2467 0x0000, /* R77 - Jack Detect */
2468 0x0000, /* R78 - Anti Pop Control */
2469 0x0000, /* R79 */
2470 0x0040, /* R80 - Left Input Volume */
2471 0x0040, /* R81 - Right Input Volume */
2472 0x0000, /* R82 */
2473 0x0000, /* R83 */
2474 0x0000, /* R84 */
2475 0x0000, /* R85 */
2476 0x0000, /* R86 */
2477 0x0000, /* R87 */
2478 0x0800, /* R88 - Left Mixer Control */
2479 0x1000, /* R89 - Right Mixer Control */
2480 0x0000, /* R90 */
2481 0x0000, /* R91 */
2482 0x0000, /* R92 - OUT3 Mixer Control */
2483 0x0000, /* R93 - OUT4 Mixer Control */
2484 0x0000, /* R94 */
2485 0x0000, /* R95 */
2486 0x0000, /* R96 - Output Left Mixer Volume */
2487 0x0000, /* R97 - Output Right Mixer Volume */
2488 0x0000, /* R98 - Input Mixer Volume L */
2489 0x0000, /* R99 - Input Mixer Volume R */
2490 0x0000, /* R100 - Input Mixer Volume */
2491 0x0000, /* R101 */
2492 0x0000, /* R102 */
2493 0x0000, /* R103 */
2494 0x00E4, /* R104 - OUT1L Volume */
2495 0x00E4, /* R105 - OUT1R Volume */
2496 0x00E4, /* R106 - OUT2L Volume */
2497 0x02E4, /* R107 - OUT2R Volume */
2498 0x0000, /* R108 */
2499 0x0000, /* R109 */
2500 0x0000, /* R110 */
2501 0x0000, /* R111 - BEEP Volume */
2502 0x0A00, /* R112 - AI Formating */
2503 0x0000, /* R113 - ADC DAC COMP */
2504 0x0020, /* R114 - AI ADC Control */
2505 0x0020, /* R115 - AI DAC Control */
2506 0x0000, /* R116 */
2507 0x0000, /* R117 */
2508 0x0000, /* R118 */
2509 0x0000, /* R119 */
2510 0x0000, /* R120 */
2511 0x0000, /* R121 */
2512 0x0000, /* R122 */
2513 0x0000, /* R123 */
2514 0x0000, /* R124 */
2515 0x0000, /* R125 */
2516 0x0000, /* R126 */
2517 0x0000, /* R127 */
2518 0x1FFF, /* R128 - GPIO Debounce */
2519 0x0000, /* R129 - GPIO Pin pull up Control */
2520 0x0000, /* R130 - GPIO Pull down Control */
2521 0x0000, /* R131 - GPIO Interrupt Mode */
2522 0x0000, /* R132 */
2523 0x0000, /* R133 - GPIO Control */
2524 0x0BFB, /* R134 - GPIO Configuration (i/o) */
2525 0x0FFF, /* R135 - GPIO Pin Polarity / Type */
2526 0x0000, /* R136 */
2527 0x0000, /* R137 */
2528 0x0000, /* R138 */
2529 0x0000, /* R139 */
2530 0x0300, /* R140 - GPIO Function Select 1 */
2531 0x0000, /* R141 - GPIO Function Select 2 */
2532 0x2300, /* R142 - GPIO Function Select 3 */
2533 0x0003, /* R143 - GPIO Function Select 4 */
2534 0x0000, /* R144 - Digitiser Control (1) */
2535 0x0002, /* R145 - Digitiser Control (2) */
2536 0x0000, /* R146 */
2537 0x0000, /* R147 */
2538 0x0000, /* R148 */
2539 0x0000, /* R149 */
2540 0x0000, /* R150 */
2541 0x0000, /* R151 */
2542 0x7000, /* R152 - AUX1 Readback */
2543 0x7000, /* R153 - AUX2 Readback */
2544 0x7000, /* R154 - AUX3 Readback */
2545 0x7000, /* R155 - AUX4 Readback */
2546 0x0000, /* R156 - USB Voltage Readback */
2547 0x0000, /* R157 - LINE Voltage Readback */
2548 0x0000, /* R158 - BATT Voltage Readback */
2549 0x0000, /* R159 - Chip Temp Readback */
2550 0x0000, /* R160 */
2551 0x0000, /* R161 */
2552 0x0000, /* R162 */
2553 0x0000, /* R163 - Generic Comparator Control */
2554 0x0000, /* R164 - Generic comparator 1 */
2555 0x0000, /* R165 - Generic comparator 2 */
2556 0x0000, /* R166 - Generic comparator 3 */
2557 0x0000, /* R167 - Generic comparator 4 */
2558 0xA00F, /* R168 - Battery Charger Control 1 */
2559 0x0B06, /* R169 - Battery Charger Control 2 */
2560 0x0000, /* R170 - Battery Charger Control 3 */
2561 0x0000, /* R171 */
2562 0x0000, /* R172 - Current Sink Driver A */
2563 0x0000, /* R173 - CSA Flash control */
2564 0x0000, /* R174 - Current Sink Driver B */
2565 0x0000, /* R175 - CSB Flash control */
2566 0x0000, /* R176 - DCDC/LDO requested */
2567 0x032D, /* R177 - DCDC Active options */
2568 0x0000, /* R178 - DCDC Sleep options */
2569 0x0025, /* R179 - Power-check comparator */
2570 0x0062, /* R180 - DCDC1 Control */
2571 0x0400, /* R181 - DCDC1 Timeouts */
2572 0x1006, /* R182 - DCDC1 Low Power */
2573 0x0018, /* R183 - DCDC2 Control */
2574 0x0000, /* R184 - DCDC2 Timeouts */
2575 0x0000, /* R185 */
2576 0x0006, /* R186 - DCDC3 Control */
2577 0x0800, /* R187 - DCDC3 Timeouts */
2578 0x0006, /* R188 - DCDC3 Low Power */
2579 0x0006, /* R189 - DCDC4 Control */
2580 0x0C00, /* R190 - DCDC4 Timeouts */
2581 0x0006, /* R191 - DCDC4 Low Power */
2582 0x0008, /* R192 - DCDC5 Control */
2583 0x0000, /* R193 - DCDC5 Timeouts */
2584 0x0000, /* R194 */
2585 0x0026, /* R195 - DCDC6 Control */
2586 0x1000, /* R196 - DCDC6 Timeouts */
2587 0x0006, /* R197 - DCDC6 Low Power */
2588 0x0000, /* R198 */
2589 0x0003, /* R199 - Limit Switch Control */
2590 0x0002, /* R200 - LDO1 Control */
2591 0x0000, /* R201 - LDO1 Timeouts */
2592 0x001C, /* R202 - LDO1 Low Power */
2593 0x001A, /* R203 - LDO2 Control */
2594 0x0000, /* R204 - LDO2 Timeouts */
2595 0x001C, /* R205 - LDO2 Low Power */
2596 0x001F, /* R206 - LDO3 Control */
2597 0x0000, /* R207 - LDO3 Timeouts */
2598 0x001C, /* R208 - LDO3 Low Power */
2599 0x001F, /* R209 - LDO4 Control */
2600 0x0000, /* R210 - LDO4 Timeouts */
2601 0x001C, /* R211 - LDO4 Low Power */
2602 0x0000, /* R212 */
2603 0x0000, /* R213 */
2604 0x0000, /* R214 */
2605 0x0000, /* R215 - VCC_FAULT Masks */
2606 0x001F, /* R216 - Main Bandgap Control */
2607 0x0000, /* R217 - OSC Control */
2608 0x9000, /* R218 - RTC Tick Control */
2609 0x0000, /* R219 - Security1 */
2610 0x4000, /* R220 */
2611 0x0000, /* R221 */
2612 0x0000, /* R222 */
2613 0x0000, /* R223 */
2614 0x0000, /* R224 - Signal overrides */
2615 0x0000, /* R225 - DCDC/LDO status */
2616 0x0000, /* R226 - Charger Overides/status */
2617 0x0000, /* R227 - misc overrides */
2618 0x0000, /* R228 - Supply overrides/status 1 */
2619 0x0000, /* R229 - Supply overrides/status 2 */
2620 0xE000, /* R230 - GPIO Pin Status */
2621 0x0000, /* R231 - comparotor overrides */
2622 0x0000, /* R232 */
2623 0x0000, /* R233 - State Machine status */
2624 0x1200, /* R234 */
2625 0x0000, /* R235 */
2626 0x8000, /* R236 */
2627 0x0000, /* R237 */
2628 0x0000, /* R238 */
2629 0x0000, /* R239 */
2630 0x0003, /* R240 */
2631 0x0000, /* R241 */
2632 0x0000, /* R242 */
2633 0x0004, /* R243 */
2634 0x0300, /* R244 */
2635 0x0000, /* R245 */
2636 0x0200, /* R246 */
2637 0x0000, /* R247 */
2638 0x1000, /* R248 - DCDC1 Test Controls */
2639 0x5000, /* R249 */
2640 0x1000, /* R250 - DCDC3 Test Controls */
2641 0x1000, /* R251 - DCDC4 Test Controls */
2642 0x5100, /* R252 */
2643 0x1000, /* R253 - DCDC6 Test Controls */
2644};
2645#endif
2646
2647#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_2
2648
2649#undef WM8350_HAVE_CONFIG_MODE
2650#define WM8350_HAVE_CONFIG_MODE
2651
2652const u16 wm8352_mode2_defaults[] = {
2653 0x6143, /* R0 - Reset/ID */
2654 0x0000, /* R1 - ID */
2655 0x0002, /* R2 - Revision */
2656 0x1C02, /* R3 - System Control 1 */
2657 0x0204, /* R4 - System Control 2 */
2658 0x0000, /* R5 - System Hibernate */
2659 0x8A00, /* R6 - Interface Control */
2660 0x0000, /* R7 */
2661 0x8000, /* R8 - Power mgmt (1) */
2662 0x0000, /* R9 - Power mgmt (2) */
2663 0x0000, /* R10 - Power mgmt (3) */
2664 0x2000, /* R11 - Power mgmt (4) */
2665 0x0E00, /* R12 - Power mgmt (5) */
2666 0x0000, /* R13 - Power mgmt (6) */
2667 0x0000, /* R14 - Power mgmt (7) */
2668 0x0000, /* R15 */
2669 0x0000, /* R16 - RTC Seconds/Minutes */
2670 0x0100, /* R17 - RTC Hours/Day */
2671 0x0101, /* R18 - RTC Date/Month */
2672 0x1400, /* R19 - RTC Year */
2673 0x0000, /* R20 - Alarm Seconds/Minutes */
2674 0x0000, /* R21 - Alarm Hours/Day */
2675 0x0000, /* R22 - Alarm Date/Month */
2676 0x0320, /* R23 - RTC Time Control */
2677 0x0000, /* R24 - System Interrupts */
2678 0x0000, /* R25 - Interrupt Status 1 */
2679 0x0000, /* R26 - Interrupt Status 2 */
2680 0x0000, /* R27 */
2681 0x0000, /* R28 - Under Voltage Interrupt status */
2682 0x0000, /* R29 - Over Current Interrupt status */
2683 0x0000, /* R30 - GPIO Interrupt Status */
2684 0x0000, /* R31 - Comparator Interrupt Status */
2685 0x3FFF, /* R32 - System Interrupts Mask */
2686 0x0000, /* R33 - Interrupt Status 1 Mask */
2687 0x0000, /* R34 - Interrupt Status 2 Mask */
2688 0x0000, /* R35 */
2689 0x0000, /* R36 - Under Voltage Interrupt status Mask */
2690 0x0000, /* R37 - Over Current Interrupt status Mask */
2691 0x0000, /* R38 - GPIO Interrupt Status Mask */
2692 0x0000, /* R39 - Comparator Interrupt Status Mask */
2693 0x0040, /* R40 - Clock Control 1 */
2694 0x0000, /* R41 - Clock Control 2 */
2695 0x3A00, /* R42 - FLL Control 1 */
2696 0x7086, /* R43 - FLL Control 2 */
2697 0xC226, /* R44 - FLL Control 3 */
2698 0x0000, /* R45 - FLL Control 4 */
2699 0x0000, /* R46 */
2700 0x0000, /* R47 */
2701 0x0000, /* R48 - DAC Control */
2702 0x0000, /* R49 */
2703 0x00C0, /* R50 - DAC Digital Volume L */
2704 0x00C0, /* R51 - DAC Digital Volume R */
2705 0x0000, /* R52 */
2706 0x0040, /* R53 - DAC LR Rate */
2707 0x0000, /* R54 - DAC Clock Control */
2708 0x0000, /* R55 */
2709 0x0000, /* R56 */
2710 0x0000, /* R57 */
2711 0x4000, /* R58 - DAC Mute */
2712 0x0000, /* R59 - DAC Mute Volume */
2713 0x0000, /* R60 - DAC Side */
2714 0x0000, /* R61 */
2715 0x0000, /* R62 */
2716 0x0000, /* R63 */
2717 0x8000, /* R64 - ADC Control */
2718 0x0000, /* R65 */
2719 0x00C0, /* R66 - ADC Digital Volume L */
2720 0x00C0, /* R67 - ADC Digital Volume R */
2721 0x0000, /* R68 - ADC Divider */
2722 0x0000, /* R69 */
2723 0x0040, /* R70 - ADC LR Rate */
2724 0x0000, /* R71 */
2725 0x0303, /* R72 - Input Control */
2726 0x0000, /* R73 - IN3 Input Control */
2727 0x0000, /* R74 - Mic Bias Control */
2728 0x0000, /* R75 */
2729 0x0000, /* R76 - Output Control */
2730 0x0000, /* R77 - Jack Detect */
2731 0x0000, /* R78 - Anti Pop Control */
2732 0x0000, /* R79 */
2733 0x0040, /* R80 - Left Input Volume */
2734 0x0040, /* R81 - Right Input Volume */
2735 0x0000, /* R82 */
2736 0x0000, /* R83 */
2737 0x0000, /* R84 */
2738 0x0000, /* R85 */
2739 0x0000, /* R86 */
2740 0x0000, /* R87 */
2741 0x0800, /* R88 - Left Mixer Control */
2742 0x1000, /* R89 - Right Mixer Control */
2743 0x0000, /* R90 */
2744 0x0000, /* R91 */
2745 0x0000, /* R92 - OUT3 Mixer Control */
2746 0x0000, /* R93 - OUT4 Mixer Control */
2747 0x0000, /* R94 */
2748 0x0000, /* R95 */
2749 0x0000, /* R96 - Output Left Mixer Volume */
2750 0x0000, /* R97 - Output Right Mixer Volume */
2751 0x0000, /* R98 - Input Mixer Volume L */
2752 0x0000, /* R99 - Input Mixer Volume R */
2753 0x0000, /* R100 - Input Mixer Volume */
2754 0x0000, /* R101 */
2755 0x0000, /* R102 */
2756 0x0000, /* R103 */
2757 0x00E4, /* R104 - OUT1L Volume */
2758 0x00E4, /* R105 - OUT1R Volume */
2759 0x00E4, /* R106 - OUT2L Volume */
2760 0x02E4, /* R107 - OUT2R Volume */
2761 0x0000, /* R108 */
2762 0x0000, /* R109 */
2763 0x0000, /* R110 */
2764 0x0000, /* R111 - BEEP Volume */
2765 0x0A00, /* R112 - AI Formating */
2766 0x0000, /* R113 - ADC DAC COMP */
2767 0x0020, /* R114 - AI ADC Control */
2768 0x0020, /* R115 - AI DAC Control */
2769 0x0000, /* R116 */
2770 0x0000, /* R117 */
2771 0x0000, /* R118 */
2772 0x0000, /* R119 */
2773 0x0000, /* R120 */
2774 0x0000, /* R121 */
2775 0x0000, /* R122 */
2776 0x0000, /* R123 */
2777 0x0000, /* R124 */
2778 0x0000, /* R125 */
2779 0x0000, /* R126 */
2780 0x0000, /* R127 */
2781 0x1FFF, /* R128 - GPIO Debounce */
2782 0x0000, /* R129 - GPIO Pin pull up Control */
2783 0x0110, /* R130 - GPIO Pull down Control */
2784 0x0000, /* R131 - GPIO Interrupt Mode */
2785 0x0000, /* R132 */
2786 0x0000, /* R133 - GPIO Control */
2787 0x09DA, /* R134 - GPIO Configuration (i/o) */
2788 0x0DD6, /* R135 - GPIO Pin Polarity / Type */
2789 0x0000, /* R136 */
2790 0x0000, /* R137 */
2791 0x0000, /* R138 */
2792 0x0000, /* R139 */
2793 0x1310, /* R140 - GPIO Function Select 1 */
2794 0x0033, /* R141 - GPIO Function Select 2 */
2795 0x2000, /* R142 - GPIO Function Select 3 */
2796 0x0000, /* R143 - GPIO Function Select 4 */
2797 0x0000, /* R144 - Digitiser Control (1) */
2798 0x0002, /* R145 - Digitiser Control (2) */
2799 0x0000, /* R146 */
2800 0x0000, /* R147 */
2801 0x0000, /* R148 */
2802 0x0000, /* R149 */
2803 0x0000, /* R150 */
2804 0x0000, /* R151 */
2805 0x7000, /* R152 - AUX1 Readback */
2806 0x7000, /* R153 - AUX2 Readback */
2807 0x7000, /* R154 - AUX3 Readback */
2808 0x7000, /* R155 - AUX4 Readback */
2809 0x0000, /* R156 - USB Voltage Readback */
2810 0x0000, /* R157 - LINE Voltage Readback */
2811 0x0000, /* R158 - BATT Voltage Readback */
2812 0x0000, /* R159 - Chip Temp Readback */
2813 0x0000, /* R160 */
2814 0x0000, /* R161 */
2815 0x0000, /* R162 */
2816 0x0000, /* R163 - Generic Comparator Control */
2817 0x0000, /* R164 - Generic comparator 1 */
2818 0x0000, /* R165 - Generic comparator 2 */
2819 0x0000, /* R166 - Generic comparator 3 */
2820 0x0000, /* R167 - Generic comparator 4 */
2821 0xA00F, /* R168 - Battery Charger Control 1 */
2822 0x0B06, /* R169 - Battery Charger Control 2 */
2823 0x0000, /* R170 - Battery Charger Control 3 */
2824 0x0000, /* R171 */
2825 0x0000, /* R172 - Current Sink Driver A */
2826 0x0000, /* R173 - CSA Flash control */
2827 0x0000, /* R174 - Current Sink Driver B */
2828 0x0000, /* R175 - CSB Flash control */
2829 0x0000, /* R176 - DCDC/LDO requested */
2830 0x032D, /* R177 - DCDC Active options */
2831 0x0000, /* R178 - DCDC Sleep options */
2832 0x0025, /* R179 - Power-check comparator */
2833 0x000E, /* R180 - DCDC1 Control */
2834 0x0800, /* R181 - DCDC1 Timeouts */
2835 0x1006, /* R182 - DCDC1 Low Power */
2836 0x0018, /* R183 - DCDC2 Control */
2837 0x0000, /* R184 - DCDC2 Timeouts */
2838 0x0000, /* R185 */
2839 0x0056, /* R186 - DCDC3 Control */
2840 0x1800, /* R187 - DCDC3 Timeouts */
2841 0x0006, /* R188 - DCDC3 Low Power */
2842 0x000E, /* R189 - DCDC4 Control */
2843 0x1000, /* R190 - DCDC4 Timeouts */
2844 0x0006, /* R191 - DCDC4 Low Power */
2845 0x0008, /* R192 - DCDC5 Control */
2846 0x0000, /* R193 - DCDC5 Timeouts */
2847 0x0000, /* R194 */
2848 0x0026, /* R195 - DCDC6 Control */
2849 0x0C00, /* R196 - DCDC6 Timeouts */
2850 0x0006, /* R197 - DCDC6 Low Power */
2851 0x0000, /* R198 */
2852 0x0003, /* R199 - Limit Switch Control */
2853 0x001C, /* R200 - LDO1 Control */
2854 0x0000, /* R201 - LDO1 Timeouts */
2855 0x001C, /* R202 - LDO1 Low Power */
2856 0x0006, /* R203 - LDO2 Control */
2857 0x0400, /* R204 - LDO2 Timeouts */
2858 0x001C, /* R205 - LDO2 Low Power */
2859 0x001C, /* R206 - LDO3 Control */
2860 0x1400, /* R207 - LDO3 Timeouts */
2861 0x001C, /* R208 - LDO3 Low Power */
2862 0x001A, /* R209 - LDO4 Control */
2863 0x0000, /* R210 - LDO4 Timeouts */
2864 0x001C, /* R211 - LDO4 Low Power */
2865 0x0000, /* R212 */
2866 0x0000, /* R213 */
2867 0x0000, /* R214 */
2868 0x0000, /* R215 - VCC_FAULT Masks */
2869 0x001F, /* R216 - Main Bandgap Control */
2870 0x0000, /* R217 - OSC Control */
2871 0x9000, /* R218 - RTC Tick Control */
2872 0x0000, /* R219 - Security1 */
2873 0x4000, /* R220 */
2874 0x0000, /* R221 */
2875 0x0000, /* R222 */
2876 0x0000, /* R223 */
2877 0x0000, /* R224 - Signal overrides */
2878 0x0000, /* R225 - DCDC/LDO status */
2879 0x0000, /* R226 - Charger Overides/status */
2880 0x0000, /* R227 - misc overrides */
2881 0x0000, /* R228 - Supply overrides/status 1 */
2882 0x0000, /* R229 - Supply overrides/status 2 */
2883 0xE000, /* R230 - GPIO Pin Status */
2884 0x0000, /* R231 - comparotor overrides */
2885 0x0000, /* R232 */
2886 0x0000, /* R233 - State Machine status */
2887 0x1200, /* R234 */
2888 0x0000, /* R235 */
2889 0x8000, /* R236 */
2890 0x0000, /* R237 */
2891 0x0000, /* R238 */
2892 0x0000, /* R239 */
2893 0x0003, /* R240 */
2894 0x0000, /* R241 */
2895 0x0000, /* R242 */
2896 0x0004, /* R243 */
2897 0x0300, /* R244 */
2898 0x0000, /* R245 */
2899 0x0200, /* R246 */
2900 0x0000, /* R247 */
2901 0x1000, /* R248 - DCDC1 Test Controls */
2902 0x5000, /* R249 */
2903 0x1000, /* R250 - DCDC3 Test Controls */
2904 0x1000, /* R251 - DCDC4 Test Controls */
2905 0x5100, /* R252 */
2906 0x1000, /* R253 - DCDC6 Test Controls */
2907};
2908#endif
2909
2910#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_3
2911
2912#undef WM8350_HAVE_CONFIG_MODE
2913#define WM8350_HAVE_CONFIG_MODE
2914
2915const u16 wm8352_mode3_defaults[] = {
2916 0x6143, /* R0 - Reset/ID */
2917 0x0000, /* R1 - ID */
2918 0x0002, /* R2 - Revision */
2919 0x1C02, /* R3 - System Control 1 */
2920 0x0204, /* R4 - System Control 2 */
2921 0x0000, /* R5 - System Hibernate */
2922 0x8A00, /* R6 - Interface Control */
2923 0x0000, /* R7 */
2924 0x8000, /* R8 - Power mgmt (1) */
2925 0x0000, /* R9 - Power mgmt (2) */
2926 0x0000, /* R10 - Power mgmt (3) */
2927 0x2000, /* R11 - Power mgmt (4) */
2928 0x0E00, /* R12 - Power mgmt (5) */
2929 0x0000, /* R13 - Power mgmt (6) */
2930 0x0000, /* R14 - Power mgmt (7) */
2931 0x0000, /* R15 */
2932 0x0000, /* R16 - RTC Seconds/Minutes */
2933 0x0100, /* R17 - RTC Hours/Day */
2934 0x0101, /* R18 - RTC Date/Month */
2935 0x1400, /* R19 - RTC Year */
2936 0x0000, /* R20 - Alarm Seconds/Minutes */
2937 0x0000, /* R21 - Alarm Hours/Day */
2938 0x0000, /* R22 - Alarm Date/Month */
2939 0x0320, /* R23 - RTC Time Control */
2940 0x0000, /* R24 - System Interrupts */
2941 0x0000, /* R25 - Interrupt Status 1 */
2942 0x0000, /* R26 - Interrupt Status 2 */
2943 0x0000, /* R27 */
2944 0x0000, /* R28 - Under Voltage Interrupt status */
2945 0x0000, /* R29 - Over Current Interrupt status */
2946 0x0000, /* R30 - GPIO Interrupt Status */
2947 0x0000, /* R31 - Comparator Interrupt Status */
2948 0x3FFF, /* R32 - System Interrupts Mask */
2949 0x0000, /* R33 - Interrupt Status 1 Mask */
2950 0x0000, /* R34 - Interrupt Status 2 Mask */
2951 0x0000, /* R35 */
2952 0x0000, /* R36 - Under Voltage Interrupt status Mask */
2953 0x0000, /* R37 - Over Current Interrupt status Mask */
2954 0x0000, /* R38 - GPIO Interrupt Status Mask */
2955 0x0000, /* R39 - Comparator Interrupt Status Mask */
2956 0x0040, /* R40 - Clock Control 1 */
2957 0x0000, /* R41 - Clock Control 2 */
2958 0x3A00, /* R42 - FLL Control 1 */
2959 0x7086, /* R43 - FLL Control 2 */
2960 0xC226, /* R44 - FLL Control 3 */
2961 0x0000, /* R45 - FLL Control 4 */
2962 0x0000, /* R46 */
2963 0x0000, /* R47 */
2964 0x0000, /* R48 - DAC Control */
2965 0x0000, /* R49 */
2966 0x00C0, /* R50 - DAC Digital Volume L */
2967 0x00C0, /* R51 - DAC Digital Volume R */
2968 0x0000, /* R52 */
2969 0x0040, /* R53 - DAC LR Rate */
2970 0x0000, /* R54 - DAC Clock Control */
2971 0x0000, /* R55 */
2972 0x0000, /* R56 */
2973 0x0000, /* R57 */
2974 0x4000, /* R58 - DAC Mute */
2975 0x0000, /* R59 - DAC Mute Volume */
2976 0x0000, /* R60 - DAC Side */
2977 0x0000, /* R61 */
2978 0x0000, /* R62 */
2979 0x0000, /* R63 */
2980 0x8000, /* R64 - ADC Control */
2981 0x0000, /* R65 */
2982 0x00C0, /* R66 - ADC Digital Volume L */
2983 0x00C0, /* R67 - ADC Digital Volume R */
2984 0x0000, /* R68 - ADC Divider */
2985 0x0000, /* R69 */
2986 0x0040, /* R70 - ADC LR Rate */
2987 0x0000, /* R71 */
2988 0x0303, /* R72 - Input Control */
2989 0x0000, /* R73 - IN3 Input Control */
2990 0x0000, /* R74 - Mic Bias Control */
2991 0x0000, /* R75 */
2992 0x0000, /* R76 - Output Control */
2993 0x0000, /* R77 - Jack Detect */
2994 0x0000, /* R78 - Anti Pop Control */
2995 0x0000, /* R79 */
2996 0x0040, /* R80 - Left Input Volume */
2997 0x0040, /* R81 - Right Input Volume */
2998 0x0000, /* R82 */
2999 0x0000, /* R83 */
3000 0x0000, /* R84 */
3001 0x0000, /* R85 */
3002 0x0000, /* R86 */
3003 0x0000, /* R87 */
3004 0x0800, /* R88 - Left Mixer Control */
3005 0x1000, /* R89 - Right Mixer Control */
3006 0x0000, /* R90 */
3007 0x0000, /* R91 */
3008 0x0000, /* R92 - OUT3 Mixer Control */
3009 0x0000, /* R93 - OUT4 Mixer Control */
3010 0x0000, /* R94 */
3011 0x0000, /* R95 */
3012 0x0000, /* R96 - Output Left Mixer Volume */
3013 0x0000, /* R97 - Output Right Mixer Volume */
3014 0x0000, /* R98 - Input Mixer Volume L */
3015 0x0000, /* R99 - Input Mixer Volume R */
3016 0x0000, /* R100 - Input Mixer Volume */
3017 0x0000, /* R101 */
3018 0x0000, /* R102 */
3019 0x0000, /* R103 */
3020 0x00E4, /* R104 - OUT1L Volume */
3021 0x00E4, /* R105 - OUT1R Volume */
3022 0x00E4, /* R106 - OUT2L Volume */
3023 0x02E4, /* R107 - OUT2R Volume */
3024 0x0000, /* R108 */
3025 0x0000, /* R109 */
3026 0x0000, /* R110 */
3027 0x0000, /* R111 - BEEP Volume */
3028 0x0A00, /* R112 - AI Formating */
3029 0x0000, /* R113 - ADC DAC COMP */
3030 0x0020, /* R114 - AI ADC Control */
3031 0x0020, /* R115 - AI DAC Control */
3032 0x0000, /* R116 */
3033 0x0000, /* R117 */
3034 0x0000, /* R118 */
3035 0x0000, /* R119 */
3036 0x0000, /* R120 */
3037 0x0000, /* R121 */
3038 0x0000, /* R122 */
3039 0x0000, /* R123 */
3040 0x0000, /* R124 */
3041 0x0000, /* R125 */
3042 0x0000, /* R126 */
3043 0x0000, /* R127 */
3044 0x1FFF, /* R128 - GPIO Debounce */
3045 0x0010, /* R129 - GPIO Pin pull up Control */
3046 0x0000, /* R130 - GPIO Pull down Control */
3047 0x0000, /* R131 - GPIO Interrupt Mode */
3048 0x0000, /* R132 */
3049 0x0000, /* R133 - GPIO Control */
3050 0x0BFB, /* R134 - GPIO Configuration (i/o) */
3051 0x0FFD, /* R135 - GPIO Pin Polarity / Type */
3052 0x0000, /* R136 */
3053 0x0000, /* R137 */
3054 0x0000, /* R138 */
3055 0x0000, /* R139 */
3056 0x0310, /* R140 - GPIO Function Select 1 */
3057 0x0001, /* R141 - GPIO Function Select 2 */
3058 0x2300, /* R142 - GPIO Function Select 3 */
3059 0x0003, /* R143 - GPIO Function Select 4 */
3060 0x0000, /* R144 - Digitiser Control (1) */
3061 0x0002, /* R145 - Digitiser Control (2) */
3062 0x0000, /* R146 */
3063 0x0000, /* R147 */
3064 0x0000, /* R148 */
3065 0x0000, /* R149 */
3066 0x0000, /* R150 */
3067 0x0000, /* R151 */
3068 0x7000, /* R152 - AUX1 Readback */
3069 0x7000, /* R153 - AUX2 Readback */
3070 0x7000, /* R154 - AUX3 Readback */
3071 0x7000, /* R155 - AUX4 Readback */
3072 0x0000, /* R156 - USB Voltage Readback */
3073 0x0000, /* R157 - LINE Voltage Readback */
3074 0x0000, /* R158 - BATT Voltage Readback */
3075 0x0000, /* R159 - Chip Temp Readback */
3076 0x0000, /* R160 */
3077 0x0000, /* R161 */
3078 0x0000, /* R162 */
3079 0x0000, /* R163 - Generic Comparator Control */
3080 0x0000, /* R164 - Generic comparator 1 */
3081 0x0000, /* R165 - Generic comparator 2 */
3082 0x0000, /* R166 - Generic comparator 3 */
3083 0x0000, /* R167 - Generic comparator 4 */
3084 0xA00F, /* R168 - Battery Charger Control 1 */
3085 0x0B06, /* R169 - Battery Charger Control 2 */
3086 0x0000, /* R170 - Battery Charger Control 3 */
3087 0x0000, /* R171 */
3088 0x0000, /* R172 - Current Sink Driver A */
3089 0x0000, /* R173 - CSA Flash control */
3090 0x0000, /* R174 - Current Sink Driver B */
3091 0x0000, /* R175 - CSB Flash control */
3092 0x0000, /* R176 - DCDC/LDO requested */
3093 0x032D, /* R177 - DCDC Active options */
3094 0x0000, /* R178 - DCDC Sleep options */
3095 0x0025, /* R179 - Power-check comparator */
3096 0x0006, /* R180 - DCDC1 Control */
3097 0x0400, /* R181 - DCDC1 Timeouts */
3098 0x1006, /* R182 - DCDC1 Low Power */
3099 0x0018, /* R183 - DCDC2 Control */
3100 0x0000, /* R184 - DCDC2 Timeouts */
3101 0x0000, /* R185 */
3102 0x0050, /* R186 - DCDC3 Control */
3103 0x0C00, /* R187 - DCDC3 Timeouts */
3104 0x0006, /* R188 - DCDC3 Low Power */
3105 0x000E, /* R189 - DCDC4 Control */
3106 0x0400, /* R190 - DCDC4 Timeouts */
3107 0x0006, /* R191 - DCDC4 Low Power */
3108 0x0008, /* R192 - DCDC5 Control */
3109 0x0000, /* R193 - DCDC5 Timeouts */
3110 0x0000, /* R194 */
3111 0x0029, /* R195 - DCDC6 Control */
3112 0x0800, /* R196 - DCDC6 Timeouts */
3113 0x0006, /* R197 - DCDC6 Low Power */
3114 0x0000, /* R198 */
3115 0x0003, /* R199 - Limit Switch Control */
3116 0x001D, /* R200 - LDO1 Control */
3117 0x1000, /* R201 - LDO1 Timeouts */
3118 0x001C, /* R202 - LDO1 Low Power */
3119 0x0017, /* R203 - LDO2 Control */
3120 0x1000, /* R204 - LDO2 Timeouts */
3121 0x001C, /* R205 - LDO2 Low Power */
3122 0x0006, /* R206 - LDO3 Control */
3123 0x1000, /* R207 - LDO3 Timeouts */
3124 0x001C, /* R208 - LDO3 Low Power */
3125 0x0010, /* R209 - LDO4 Control */
3126 0x1000, /* R210 - LDO4 Timeouts */
3127 0x001C, /* R211 - LDO4 Low Power */
3128 0x0000, /* R212 */
3129 0x0000, /* R213 */
3130 0x0000, /* R214 */
3131 0x0000, /* R215 - VCC_FAULT Masks */
3132 0x001F, /* R216 - Main Bandgap Control */
3133 0x0000, /* R217 - OSC Control */
3134 0x9000, /* R218 - RTC Tick Control */
3135 0x0000, /* R219 - Security1 */
3136 0x4000, /* R220 */
3137 0x0000, /* R221 */
3138 0x0000, /* R222 */
3139 0x0000, /* R223 */
3140 0x0000, /* R224 - Signal overrides */
3141 0x0000, /* R225 - DCDC/LDO status */
3142 0x0000, /* R226 - Charger Overides/status */
3143 0x0000, /* R227 - misc overrides */
3144 0x0000, /* R228 - Supply overrides/status 1 */
3145 0x0000, /* R229 - Supply overrides/status 2 */
3146 0xE000, /* R230 - GPIO Pin Status */
3147 0x0000, /* R231 - comparotor overrides */
3148 0x0000, /* R232 */
3149 0x0000, /* R233 - State Machine status */
3150 0x1200, /* R234 */
3151 0x0000, /* R235 */
3152 0x8000, /* R236 */
3153 0x0000, /* R237 */
3154 0x0000, /* R238 */
3155 0x0000, /* R239 */
3156 0x0003, /* R240 */
3157 0x0000, /* R241 */
3158 0x0000, /* R242 */
3159 0x0004, /* R243 */
3160 0x0300, /* R244 */
3161 0x0000, /* R245 */
3162 0x0200, /* R246 */
3163 0x0000, /* R247 */
3164 0x1000, /* R248 - DCDC1 Test Controls */
3165 0x5000, /* R249 */
3166 0x1000, /* R250 - DCDC3 Test Controls */
3167 0x1000, /* R251 - DCDC4 Test Controls */
3168 0x5100, /* R252 */
3169 0x1000, /* R253 - DCDC6 Test Controls */
3170};
3171#endif
3172
3173/* 17/*
3174 * Access masks. 18 * Access masks.
3175 */ 19 */
3176 20
3177const struct wm8350_reg_access wm8350_reg_io_map[] = { 21static const struct wm8350_reg_access {
22 u16 readable; /* Mask of readable bits */
23 u16 writable; /* Mask of writable bits */
24 u16 vol; /* Mask of volatile bits */
25} wm8350_reg_io_map[] = {
3178 /* read write volatile */ 26 /* read write volatile */
3179 { 0xFFFF, 0xFFFF, 0xFFFF }, /* R0 - Reset/ID */ 27 { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Reset/ID */
3180 { 0x7CFF, 0x0C00, 0x7FFF }, /* R1 - ID */ 28 { 0x7CFF, 0x0C00, 0x0000 }, /* R1 - ID */
3181 { 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */ 29 { 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */
3182 { 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */ 30 { 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */
3183 { 0xFEF7, 0xFEF7, 0xF800 }, /* R4 - System Control 2 */ 31 { 0xFEF7, 0xFEF7, 0xF800 }, /* R4 - System Control 2 */
@@ -3433,3 +281,59 @@ const struct wm8350_reg_access wm8350_reg_io_map[] = {
3433 { 0x0000, 0x0000, 0x0000 }, /* R254 */ 281 { 0x0000, 0x0000, 0x0000 }, /* R254 */
3434 { 0x0000, 0x0000, 0x0000 }, /* R255 */ 282 { 0x0000, 0x0000, 0x0000 }, /* R255 */
3435}; 283};
284
285static bool wm8350_readable(struct device *dev, unsigned int reg)
286{
287 return wm8350_reg_io_map[reg].readable;
288}
289
290static bool wm8350_writeable(struct device *dev, unsigned int reg)
291{
292 struct wm8350 *wm8350 = dev_get_drvdata(dev);
293
294 if (!wm8350->unlocked) {
295 if ((reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
296 reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
297 (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
298 reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
299 return false;
300 }
301
302 return wm8350_reg_io_map[reg].writable;
303}
304
305static bool wm8350_volatile(struct device *dev, unsigned int reg)
306{
307 return wm8350_reg_io_map[reg].vol;
308}
309
310static bool wm8350_precious(struct device *dev, unsigned int reg)
311{
312 switch (reg) {
313 case WM8350_SYSTEM_INTERRUPTS:
314 case WM8350_INT_STATUS_1:
315 case WM8350_INT_STATUS_2:
316 case WM8350_POWER_UP_INT_STATUS:
317 case WM8350_UNDER_VOLTAGE_INT_STATUS:
318 case WM8350_OVER_CURRENT_INT_STATUS:
319 case WM8350_GPIO_INT_STATUS:
320 case WM8350_COMPARATOR_INT_STATUS:
321 return true;
322
323 default:
324 return false;
325 }
326}
327
328const struct regmap_config wm8350_regmap = {
329 .reg_bits = 8,
330 .val_bits = 16,
331
332 .cache_type = REGCACHE_RBTREE,
333
334 .max_register = WM8350_MAX_REGISTER,
335 .readable_reg = wm8350_readable,
336 .writeable_reg = wm8350_writeable,
337 .volatile_reg = wm8350_volatile,
338 .precious_reg = wm8350_precious,
339};
diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c
index 1e321d349777..eec74aa55fdf 100644
--- a/drivers/mfd/wm8994-core.c
+++ b/drivers/mfd/wm8994-core.c
@@ -283,9 +283,24 @@ static int wm8994_suspend(struct device *dev)
283 wm8994_reg_write(wm8994, WM8994_SOFTWARE_RESET, 283 wm8994_reg_write(wm8994, WM8994_SOFTWARE_RESET,
284 wm8994_reg_read(wm8994, WM8994_SOFTWARE_RESET)); 284 wm8994_reg_read(wm8994, WM8994_SOFTWARE_RESET));
285 285
286 regcache_cache_only(wm8994->regmap, true);
287 regcache_mark_dirty(wm8994->regmap); 286 regcache_mark_dirty(wm8994->regmap);
288 287
288 /* Restore GPIO registers to prevent problems with mismatched
289 * pin configurations.
290 */
291 ret = regcache_sync_region(wm8994->regmap, WM8994_GPIO_1,
292 WM8994_GPIO_11);
293 if (ret != 0)
294 dev_err(dev, "Failed to restore GPIO registers: %d\n", ret);
295
296 /* In case one of the GPIOs is used as a wake input. */
297 ret = regcache_sync_region(wm8994->regmap,
298 WM8994_INTERRUPT_STATUS_1_MASK,
299 WM8994_INTERRUPT_STATUS_1_MASK);
300 if (ret != 0)
301 dev_err(dev, "Failed to restore interrupt mask: %d\n", ret);
302
303 regcache_cache_only(wm8994->regmap, true);
289 wm8994->suspended = true; 304 wm8994->suspended = true;
290 305
291 ret = regulator_bulk_disable(wm8994->num_supplies, 306 ret = regulator_bulk_disable(wm8994->num_supplies,
diff --git a/drivers/mfd/wm8994-irq.c b/drivers/mfd/wm8994-irq.c
index f1837f669755..0aac4aff17a5 100644
--- a/drivers/mfd/wm8994-irq.c
+++ b/drivers/mfd/wm8994-irq.c
@@ -21,6 +21,7 @@
21#include <linux/regmap.h> 21#include <linux/regmap.h>
22 22
23#include <linux/mfd/wm8994/core.h> 23#include <linux/mfd/wm8994/core.h>
24#include <linux/mfd/wm8994/pdata.h>
24#include <linux/mfd/wm8994/registers.h> 25#include <linux/mfd/wm8994/registers.h>
25 26
26#include <linux/delay.h> 27#include <linux/delay.h>
@@ -139,6 +140,8 @@ static struct regmap_irq_chip wm8994_irq_chip = {
139int wm8994_irq_init(struct wm8994 *wm8994) 140int wm8994_irq_init(struct wm8994 *wm8994)
140{ 141{
141 int ret; 142 int ret;
143 unsigned long irqflags;
144 struct wm8994_pdata *pdata = wm8994->dev->platform_data;
142 145
143 if (!wm8994->irq) { 146 if (!wm8994->irq) {
144 dev_warn(wm8994->dev, 147 dev_warn(wm8994->dev,
@@ -147,8 +150,13 @@ int wm8994_irq_init(struct wm8994 *wm8994)
147 return 0; 150 return 0;
148 } 151 }
149 152
153 /* select user or default irq flags */
154 irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
155 if (pdata->irq_flags)
156 irqflags = pdata->irq_flags;
157
150 ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq, 158 ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq,
151 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 159 irqflags,
152 wm8994->irq_base, &wm8994_irq_chip, 160 wm8994->irq_base, &wm8994_irq_chip,
153 &wm8994->irq_data); 161 &wm8994->irq_data);
154 if (ret != 0) { 162 if (ret != 0) {
diff --git a/drivers/misc/ab8500-pwm.c b/drivers/misc/ab8500-pwm.c
index 042a8fe4efaa..d7a9aa14e5d5 100644
--- a/drivers/misc/ab8500-pwm.c
+++ b/drivers/misc/ab8500-pwm.c
@@ -142,16 +142,10 @@ static int __devexit ab8500_pwm_remove(struct platform_device *pdev)
142 return 0; 142 return 0;
143} 143}
144 144
145static const struct of_device_id ab8500_pwm_match[] = {
146 { .compatible = "stericsson,ab8500-pwm", },
147 {}
148};
149
150static struct platform_driver ab8500_pwm_driver = { 145static struct platform_driver ab8500_pwm_driver = {
151 .driver = { 146 .driver = {
152 .name = "ab8500-pwm", 147 .name = "ab8500-pwm",
153 .owner = THIS_MODULE, 148 .owner = THIS_MODULE,
154 .of_match_table = ab8500_pwm_match,
155 }, 149 },
156 .probe = ab8500_pwm_probe, 150 .probe = ab8500_pwm_probe,
157 .remove = __devexit_p(ab8500_pwm_remove), 151 .remove = __devexit_p(ab8500_pwm_remove),
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index f34c3be6c9fe..4e932cc695e9 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -272,7 +272,7 @@ config REGULATOR_S2MPS11
272 272
273config REGULATOR_S5M8767 273config REGULATOR_S5M8767
274 tristate "Samsung S5M8767A voltage regulator" 274 tristate "Samsung S5M8767A voltage regulator"
275 depends on MFD_S5M_CORE 275 depends on MFD_SEC_CORE
276 help 276 help
277 This driver supports a Samsung S5M8767A voltage output regulator 277 This driver supports a Samsung S5M8767A voltage output regulator
278 via I2C bus. S5M8767A have 9 Bucks and 28 LDOs output and 278 via I2C bus. S5M8767A have 9 Bucks and 28 LDOs output and
diff --git a/drivers/regulator/ab8500.c b/drivers/regulator/ab8500.c
index 13d424fc1c14..10f2f4d4d190 100644
--- a/drivers/regulator/ab8500.c
+++ b/drivers/regulator/ab8500.c
@@ -848,18 +848,12 @@ static __devexit int ab8500_regulator_remove(struct platform_device *pdev)
848 return 0; 848 return 0;
849} 849}
850 850
851static const struct of_device_id ab8500_regulator_match[] = {
852 { .compatible = "stericsson,ab8500-regulator", },
853 {}
854};
855
856static struct platform_driver ab8500_regulator_driver = { 851static struct platform_driver ab8500_regulator_driver = {
857 .probe = ab8500_regulator_probe, 852 .probe = ab8500_regulator_probe,
858 .remove = __devexit_p(ab8500_regulator_remove), 853 .remove = __devexit_p(ab8500_regulator_remove),
859 .driver = { 854 .driver = {
860 .name = "ab8500-regulator", 855 .name = "ab8500-regulator",
861 .owner = THIS_MODULE, 856 .owner = THIS_MODULE,
862 .of_match_table = ab8500_regulator_match,
863 }, 857 },
864}; 858};
865 859
diff --git a/drivers/regulator/db8500-prcmu.c b/drivers/regulator/db8500-prcmu.c
index 9dbb491b6efa..359f8d18fc3f 100644
--- a/drivers/regulator/db8500-prcmu.c
+++ b/drivers/regulator/db8500-prcmu.c
@@ -547,16 +547,10 @@ static int __exit db8500_regulator_remove(struct platform_device *pdev)
547 return 0; 547 return 0;
548} 548}
549 549
550static const struct of_device_id db8500_prcmu_regulator_match[] = {
551 { .compatible = "stericsson,db8500-prcmu-regulator", },
552 {}
553};
554
555static struct platform_driver db8500_regulator_driver = { 550static struct platform_driver db8500_regulator_driver = {
556 .driver = { 551 .driver = {
557 .name = "db8500-prcmu-regulators", 552 .name = "db8500-prcmu-regulators",
558 .owner = THIS_MODULE, 553 .owner = THIS_MODULE,
559 .of_match_table = db8500_prcmu_regulator_match,
560 }, 554 },
561 .probe = db8500_regulator_probe, 555 .probe = db8500_regulator_probe,
562 .remove = __exit_p(db8500_regulator_remove), 556 .remove = __exit_p(db8500_regulator_remove),
diff --git a/drivers/regulator/s5m8767.c b/drivers/regulator/s5m8767.c
index 102287fa7ecb..5a0d18a7aa2a 100644
--- a/drivers/regulator/s5m8767.c
+++ b/drivers/regulator/s5m8767.c
@@ -19,15 +19,15 @@
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/regulator/driver.h> 20#include <linux/regulator/driver.h>
21#include <linux/regulator/machine.h> 21#include <linux/regulator/machine.h>
22#include <linux/mfd/s5m87xx/s5m-core.h> 22#include <linux/mfd/samsung/core.h>
23#include <linux/mfd/s5m87xx/s5m-pmic.h> 23#include <linux/mfd/samsung/s5m8767.h>
24 24
25struct s5m8767_info { 25struct s5m8767_info {
26 struct device *dev; 26 struct device *dev;
27 struct s5m87xx_dev *iodev; 27 struct sec_pmic_dev *iodev;
28 int num_regulators; 28 int num_regulators;
29 struct regulator_dev **rdev; 29 struct regulator_dev **rdev;
30 struct s5m_opmode_data *opmode; 30 struct sec_opmode_data *opmode;
31 31
32 int ramp_delay; 32 int ramp_delay;
33 bool buck2_ramp; 33 bool buck2_ramp;
@@ -45,43 +45,43 @@ struct s5m8767_info {
45 int buck_gpioindex; 45 int buck_gpioindex;
46}; 46};
47 47
48struct s5m_voltage_desc { 48struct sec_voltage_desc {
49 int max; 49 int max;
50 int min; 50 int min;
51 int step; 51 int step;
52}; 52};
53 53
54static const struct s5m_voltage_desc buck_voltage_val1 = { 54static const struct sec_voltage_desc buck_voltage_val1 = {
55 .max = 2225000, 55 .max = 2225000,
56 .min = 650000, 56 .min = 650000,
57 .step = 6250, 57 .step = 6250,
58}; 58};
59 59
60static const struct s5m_voltage_desc buck_voltage_val2 = { 60static const struct sec_voltage_desc buck_voltage_val2 = {
61 .max = 1600000, 61 .max = 1600000,
62 .min = 600000, 62 .min = 600000,
63 .step = 6250, 63 .step = 6250,
64}; 64};
65 65
66static const struct s5m_voltage_desc buck_voltage_val3 = { 66static const struct sec_voltage_desc buck_voltage_val3 = {
67 .max = 3000000, 67 .max = 3000000,
68 .min = 750000, 68 .min = 750000,
69 .step = 12500, 69 .step = 12500,
70}; 70};
71 71
72static const struct s5m_voltage_desc ldo_voltage_val1 = { 72static const struct sec_voltage_desc ldo_voltage_val1 = {
73 .max = 3950000, 73 .max = 3950000,
74 .min = 800000, 74 .min = 800000,
75 .step = 50000, 75 .step = 50000,
76}; 76};
77 77
78static const struct s5m_voltage_desc ldo_voltage_val2 = { 78static const struct sec_voltage_desc ldo_voltage_val2 = {
79 .max = 2375000, 79 .max = 2375000,
80 .min = 800000, 80 .min = 800000,
81 .step = 25000, 81 .step = 25000,
82}; 82};
83 83
84static const struct s5m_voltage_desc *reg_voltage_map[] = { 84static const struct sec_voltage_desc *reg_voltage_map[] = {
85 [S5M8767_LDO1] = &ldo_voltage_val2, 85 [S5M8767_LDO1] = &ldo_voltage_val2,
86 [S5M8767_LDO2] = &ldo_voltage_val2, 86 [S5M8767_LDO2] = &ldo_voltage_val2,
87 [S5M8767_LDO3] = &ldo_voltage_val1, 87 [S5M8767_LDO3] = &ldo_voltage_val1,
@@ -213,7 +213,7 @@ static int s5m8767_reg_is_enabled(struct regulator_dev *rdev)
213 else if (ret) 213 else if (ret)
214 return ret; 214 return ret;
215 215
216 ret = s5m_reg_read(s5m8767->iodev, reg, &val); 216 ret = sec_reg_read(s5m8767->iodev, reg, &val);
217 if (ret) 217 if (ret)
218 return ret; 218 return ret;
219 219
@@ -230,7 +230,7 @@ static int s5m8767_reg_enable(struct regulator_dev *rdev)
230 if (ret) 230 if (ret)
231 return ret; 231 return ret;
232 232
233 return s5m_reg_update(s5m8767->iodev, reg, enable_ctrl, mask); 233 return sec_reg_update(s5m8767->iodev, reg, enable_ctrl, mask);
234} 234}
235 235
236static int s5m8767_reg_disable(struct regulator_dev *rdev) 236static int s5m8767_reg_disable(struct regulator_dev *rdev)
@@ -243,7 +243,7 @@ static int s5m8767_reg_disable(struct regulator_dev *rdev)
243 if (ret) 243 if (ret)
244 return ret; 244 return ret;
245 245
246 return s5m_reg_update(s5m8767->iodev, reg, ~mask, mask); 246 return sec_reg_update(s5m8767->iodev, reg, ~mask, mask);
247} 247}
248 248
249static int s5m8767_get_voltage_register(struct regulator_dev *rdev, int *_reg) 249static int s5m8767_get_voltage_register(struct regulator_dev *rdev, int *_reg)
@@ -305,7 +305,7 @@ static int s5m8767_get_voltage_sel(struct regulator_dev *rdev)
305 305
306 mask = (reg_id < S5M8767_BUCK1) ? 0x3f : 0xff; 306 mask = (reg_id < S5M8767_BUCK1) ? 0x3f : 0xff;
307 307
308 ret = s5m_reg_read(s5m8767->iodev, reg, &val); 308 ret = sec_reg_read(s5m8767->iodev, reg, &val);
309 if (ret) 309 if (ret)
310 return ret; 310 return ret;
311 311
@@ -315,7 +315,7 @@ static int s5m8767_get_voltage_sel(struct regulator_dev *rdev)
315} 315}
316 316
317static int s5m8767_convert_voltage_to_sel( 317static int s5m8767_convert_voltage_to_sel(
318 const struct s5m_voltage_desc *desc, 318 const struct sec_voltage_desc *desc,
319 int min_vol, int max_vol) 319 int min_vol, int max_vol)
320{ 320{
321 int selector = 0; 321 int selector = 0;
@@ -407,7 +407,7 @@ static int s5m8767_set_voltage_sel(struct regulator_dev *rdev,
407 if (ret) 407 if (ret)
408 return ret; 408 return ret;
409 409
410 return s5m_reg_update(s5m8767->iodev, reg, selector, mask); 410 return sec_reg_update(s5m8767->iodev, reg, selector, mask);
411 } 411 }
412} 412}
413 413
@@ -416,7 +416,7 @@ static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev,
416 unsigned int new_sel) 416 unsigned int new_sel)
417{ 417{
418 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev); 418 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
419 const struct s5m_voltage_desc *desc; 419 const struct sec_voltage_desc *desc;
420 int reg_id = rdev_get_id(rdev); 420 int reg_id = rdev_get_id(rdev);
421 421
422 desc = reg_voltage_map[reg_id]; 422 desc = reg_voltage_map[reg_id];
@@ -501,8 +501,8 @@ static struct regulator_desc regulators[] = {
501 501
502static __devinit int s5m8767_pmic_probe(struct platform_device *pdev) 502static __devinit int s5m8767_pmic_probe(struct platform_device *pdev)
503{ 503{
504 struct s5m87xx_dev *iodev = dev_get_drvdata(pdev->dev.parent); 504 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
505 struct s5m_platform_data *pdata = dev_get_platdata(iodev->dev); 505 struct sec_platform_data *pdata = dev_get_platdata(iodev->dev);
506 struct regulator_config config = { }; 506 struct regulator_config config = { };
507 struct regulator_dev **rdev; 507 struct regulator_dev **rdev;
508 struct s5m8767_info *s5m8767; 508 struct s5m8767_info *s5m8767;
@@ -671,13 +671,13 @@ static __devinit int s5m8767_pmic_probe(struct platform_device *pdev)
671 671
672 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs || 672 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
673 pdata->buck4_gpiodvs) { 673 pdata->buck4_gpiodvs) {
674 s5m_reg_update(s5m8767->iodev, S5M8767_REG_BUCK2CTRL, 674 sec_reg_update(s5m8767->iodev, S5M8767_REG_BUCK2CTRL,
675 (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1), 675 (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1),
676 1 << 1); 676 1 << 1);
677 s5m_reg_update(s5m8767->iodev, S5M8767_REG_BUCK3CTRL, 677 sec_reg_update(s5m8767->iodev, S5M8767_REG_BUCK3CTRL,
678 (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1), 678 (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1),
679 1 << 1); 679 1 << 1);
680 s5m_reg_update(s5m8767->iodev, S5M8767_REG_BUCK4CTRL, 680 sec_reg_update(s5m8767->iodev, S5M8767_REG_BUCK4CTRL,
681 (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1), 681 (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1),
682 1 << 1); 682 1 << 1);
683 } 683 }
@@ -685,61 +685,61 @@ static __devinit int s5m8767_pmic_probe(struct platform_device *pdev)
685 /* Initialize GPIO DVS registers */ 685 /* Initialize GPIO DVS registers */
686 for (i = 0; i < 8; i++) { 686 for (i = 0; i < 8; i++) {
687 if (s5m8767->buck2_gpiodvs) { 687 if (s5m8767->buck2_gpiodvs) {
688 s5m_reg_write(s5m8767->iodev, S5M8767_REG_BUCK2DVS1 + i, 688 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK2DVS1 + i,
689 s5m8767->buck2_vol[i]); 689 s5m8767->buck2_vol[i]);
690 } 690 }
691 691
692 if (s5m8767->buck3_gpiodvs) { 692 if (s5m8767->buck3_gpiodvs) {
693 s5m_reg_write(s5m8767->iodev, S5M8767_REG_BUCK3DVS1 + i, 693 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK3DVS1 + i,
694 s5m8767->buck3_vol[i]); 694 s5m8767->buck3_vol[i]);
695 } 695 }
696 696
697 if (s5m8767->buck4_gpiodvs) { 697 if (s5m8767->buck4_gpiodvs) {
698 s5m_reg_write(s5m8767->iodev, S5M8767_REG_BUCK4DVS1 + i, 698 sec_reg_write(s5m8767->iodev, S5M8767_REG_BUCK4DVS1 + i,
699 s5m8767->buck4_vol[i]); 699 s5m8767->buck4_vol[i]);
700 } 700 }
701 } 701 }
702 702
703 if (s5m8767->buck2_ramp) 703 if (s5m8767->buck2_ramp)
704 s5m_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x08, 0x08); 704 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x08, 0x08);
705 705
706 if (s5m8767->buck3_ramp) 706 if (s5m8767->buck3_ramp)
707 s5m_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x04, 0x04); 707 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x04, 0x04);
708 708
709 if (s5m8767->buck4_ramp) 709 if (s5m8767->buck4_ramp)
710 s5m_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x02, 0x02); 710 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 0x02, 0x02);
711 711
712 if (s5m8767->buck2_ramp || s5m8767->buck3_ramp 712 if (s5m8767->buck2_ramp || s5m8767->buck3_ramp
713 || s5m8767->buck4_ramp) { 713 || s5m8767->buck4_ramp) {
714 switch (s5m8767->ramp_delay) { 714 switch (s5m8767->ramp_delay) {
715 case 5: 715 case 5:
716 s5m_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 716 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
717 0x40, 0xf0); 717 0x40, 0xf0);
718 break; 718 break;
719 case 10: 719 case 10:
720 s5m_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 720 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
721 0x90, 0xf0); 721 0x90, 0xf0);
722 break; 722 break;
723 case 25: 723 case 25:
724 s5m_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 724 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
725 0xd0, 0xf0); 725 0xd0, 0xf0);
726 break; 726 break;
727 case 50: 727 case 50:
728 s5m_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 728 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
729 0xe0, 0xf0); 729 0xe0, 0xf0);
730 break; 730 break;
731 case 100: 731 case 100:
732 s5m_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 732 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
733 0xf0, 0xf0); 733 0xf0, 0xf0);
734 break; 734 break;
735 default: 735 default:
736 s5m_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP, 736 sec_reg_update(s5m8767->iodev, S5M8767_REG_DVSRAMP,
737 0x90, 0xf0); 737 0x90, 0xf0);
738 } 738 }
739 } 739 }
740 740
741 for (i = 0; i < pdata->num_regulators; i++) { 741 for (i = 0; i < pdata->num_regulators; i++) {
742 const struct s5m_voltage_desc *desc; 742 const struct sec_voltage_desc *desc;
743 int id = pdata->regulators[i].id; 743 int id = pdata->regulators[i].id;
744 744
745 desc = reg_voltage_map[id]; 745 desc = reg_voltage_map[id];
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 08cbdb900a18..f049c02413ce 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -135,6 +135,16 @@ config RTC_DRV_88PM860X
135 This driver can also be built as a module. If so, the module 135 This driver can also be built as a module. If so, the module
136 will be called rtc-88pm860x. 136 will be called rtc-88pm860x.
137 137
138config RTC_DRV_88PM80X
139 tristate "Marvell 88PM80x"
140 depends on RTC_CLASS && I2C && MFD_88PM800
141 help
142 If you say yes here you get support for RTC function in Marvell
143 88PM80x chips.
144
145 This driver can also be built as a module. If so, the module
146 will be called rtc-88pm80x.
147
138config RTC_DRV_DS1307 148config RTC_DRV_DS1307
139 tristate "Dallas/Maxim DS1307/37/38/39/40, ST M41T00, EPSON RX-8025" 149 tristate "Dallas/Maxim DS1307/37/38/39/40, ST M41T00, EPSON RX-8025"
140 help 150 help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 2973921c30d8..0d5b2b66f90d 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -16,6 +16,7 @@ rtc-core-$(CONFIG_RTC_INTF_SYSFS) += rtc-sysfs.o
16# Keep the list ordered. 16# Keep the list ordered.
17 17
18obj-$(CONFIG_RTC_DRV_88PM860X) += rtc-88pm860x.o 18obj-$(CONFIG_RTC_DRV_88PM860X) += rtc-88pm860x.o
19obj-$(CONFIG_RTC_DRV_88PM80X) += rtc-88pm80x.o
19obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o 20obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o
20obj-$(CONFIG_RTC_DRV_AB8500) += rtc-ab8500.o 21obj-$(CONFIG_RTC_DRV_AB8500) += rtc-ab8500.o
21obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o 22obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o
diff --git a/drivers/rtc/rtc-88pm80x.c b/drivers/rtc/rtc-88pm80x.c
new file mode 100644
index 000000000000..a2f956d90de0
--- /dev/null
+++ b/drivers/rtc/rtc-88pm80x.c
@@ -0,0 +1,371 @@
1/*
2 * Real Time Clock driver for Marvell 88PM80x PMIC
3 *
4 * Copyright (c) 2012 Marvell International Ltd.
5 * Wenzeng Chen<wzch@marvell.com>
6 * Qiao Zhou <zhouqiao@marvell.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file "COPYING" in the main directory of this
10 * archive for more details.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/regmap.h>
26#include <linux/mfd/core.h>
27#include <linux/mfd/88pm80x.h>
28#include <linux/rtc.h>
29
30#define PM800_RTC_COUNTER1 (0xD1)
31#define PM800_RTC_COUNTER2 (0xD2)
32#define PM800_RTC_COUNTER3 (0xD3)
33#define PM800_RTC_COUNTER4 (0xD4)
34#define PM800_RTC_EXPIRE1_1 (0xD5)
35#define PM800_RTC_EXPIRE1_2 (0xD6)
36#define PM800_RTC_EXPIRE1_3 (0xD7)
37#define PM800_RTC_EXPIRE1_4 (0xD8)
38#define PM800_RTC_TRIM1 (0xD9)
39#define PM800_RTC_TRIM2 (0xDA)
40#define PM800_RTC_TRIM3 (0xDB)
41#define PM800_RTC_TRIM4 (0xDC)
42#define PM800_RTC_EXPIRE2_1 (0xDD)
43#define PM800_RTC_EXPIRE2_2 (0xDE)
44#define PM800_RTC_EXPIRE2_3 (0xDF)
45#define PM800_RTC_EXPIRE2_4 (0xE0)
46
47#define PM800_POWER_DOWN_LOG1 (0xE5)
48#define PM800_POWER_DOWN_LOG2 (0xE6)
49
50struct pm80x_rtc_info {
51 struct pm80x_chip *chip;
52 struct regmap *map;
53 struct rtc_device *rtc_dev;
54 struct device *dev;
55 struct delayed_work calib_work;
56
57 int irq;
58 int vrtc;
59};
60
61static irqreturn_t rtc_update_handler(int irq, void *data)
62{
63 struct pm80x_rtc_info *info = (struct pm80x_rtc_info *)data;
64 int mask;
65
66 mask = PM800_ALARM | PM800_ALARM_WAKEUP;
67 regmap_update_bits(info->map, PM800_RTC_CONTROL, mask | PM800_ALARM1_EN,
68 mask);
69 rtc_update_irq(info->rtc_dev, 1, RTC_AF);
70 return IRQ_HANDLED;
71}
72
73static int pm80x_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
74{
75 struct pm80x_rtc_info *info = dev_get_drvdata(dev);
76
77 if (enabled)
78 regmap_update_bits(info->map, PM800_RTC_CONTROL,
79 PM800_ALARM1_EN, PM800_ALARM1_EN);
80 else
81 regmap_update_bits(info->map, PM800_RTC_CONTROL,
82 PM800_ALARM1_EN, 0);
83 return 0;
84}
85
86/*
87 * Calculate the next alarm time given the requested alarm time mask
88 * and the current time.
89 */
90static void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now,
91 struct rtc_time *alrm)
92{
93 unsigned long next_time;
94 unsigned long now_time;
95
96 next->tm_year = now->tm_year;
97 next->tm_mon = now->tm_mon;
98 next->tm_mday = now->tm_mday;
99 next->tm_hour = alrm->tm_hour;
100 next->tm_min = alrm->tm_min;
101 next->tm_sec = alrm->tm_sec;
102
103 rtc_tm_to_time(now, &now_time);
104 rtc_tm_to_time(next, &next_time);
105
106 if (next_time < now_time) {
107 /* Advance one day */
108 next_time += 60 * 60 * 24;
109 rtc_time_to_tm(next_time, next);
110 }
111}
112
113static int pm80x_rtc_read_time(struct device *dev, struct rtc_time *tm)
114{
115 struct pm80x_rtc_info *info = dev_get_drvdata(dev);
116 unsigned char buf[4];
117 unsigned long ticks, base, data;
118 regmap_raw_read(info->map, PM800_RTC_EXPIRE2_1, buf, 4);
119 base = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
120 dev_dbg(info->dev, "%x-%x-%x-%x\n", buf[0], buf[1], buf[2], buf[3]);
121
122 /* load 32-bit read-only counter */
123 regmap_raw_read(info->map, PM800_RTC_COUNTER1, buf, 4);
124 data = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
125 ticks = base + data;
126 dev_dbg(info->dev, "get base:0x%lx, RO count:0x%lx, ticks:0x%lx\n",
127 base, data, ticks);
128 rtc_time_to_tm(ticks, tm);
129 return 0;
130}
131
132static int pm80x_rtc_set_time(struct device *dev, struct rtc_time *tm)
133{
134 struct pm80x_rtc_info *info = dev_get_drvdata(dev);
135 unsigned char buf[4];
136 unsigned long ticks, base, data;
137 if ((tm->tm_year < 70) || (tm->tm_year > 138)) {
138 dev_dbg(info->dev,
139 "Set time %d out of range. Please set time between 1970 to 2038.\n",
140 1900 + tm->tm_year);
141 return -EINVAL;
142 }
143 rtc_tm_to_time(tm, &ticks);
144
145 /* load 32-bit read-only counter */
146 regmap_raw_read(info->map, PM800_RTC_COUNTER1, buf, 4);
147 data = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
148 base = ticks - data;
149 dev_dbg(info->dev, "set base:0x%lx, RO count:0x%lx, ticks:0x%lx\n",
150 base, data, ticks);
151 buf[0] = base & 0xFF;
152 buf[1] = (base >> 8) & 0xFF;
153 buf[2] = (base >> 16) & 0xFF;
154 buf[3] = (base >> 24) & 0xFF;
155 regmap_raw_write(info->map, PM800_RTC_EXPIRE2_1, buf, 4);
156
157 return 0;
158}
159
160static int pm80x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
161{
162 struct pm80x_rtc_info *info = dev_get_drvdata(dev);
163 unsigned char buf[4];
164 unsigned long ticks, base, data;
165 int ret;
166
167 regmap_raw_read(info->map, PM800_RTC_EXPIRE2_1, buf, 4);
168 base = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
169 dev_dbg(info->dev, "%x-%x-%x-%x\n", buf[0], buf[1], buf[2], buf[3]);
170
171 regmap_raw_read(info->map, PM800_RTC_EXPIRE1_1, buf, 4);
172 data = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
173 ticks = base + data;
174 dev_dbg(info->dev, "get base:0x%lx, RO count:0x%lx, ticks:0x%lx\n",
175 base, data, ticks);
176
177 rtc_time_to_tm(ticks, &alrm->time);
178 regmap_read(info->map, PM800_RTC_CONTROL, &ret);
179 alrm->enabled = (ret & PM800_ALARM1_EN) ? 1 : 0;
180 alrm->pending = (ret & (PM800_ALARM | PM800_ALARM_WAKEUP)) ? 1 : 0;
181 return 0;
182}
183
184static int pm80x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
185{
186 struct pm80x_rtc_info *info = dev_get_drvdata(dev);
187 struct rtc_time now_tm, alarm_tm;
188 unsigned long ticks, base, data;
189 unsigned char buf[4];
190 int mask;
191
192 regmap_update_bits(info->map, PM800_RTC_CONTROL, PM800_ALARM1_EN, 0);
193
194 regmap_raw_read(info->map, PM800_RTC_EXPIRE2_1, buf, 4);
195 base = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
196 dev_dbg(info->dev, "%x-%x-%x-%x\n", buf[0], buf[1], buf[2], buf[3]);
197
198 /* load 32-bit read-only counter */
199 regmap_raw_read(info->map, PM800_RTC_COUNTER1, buf, 4);
200 data = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
201 ticks = base + data;
202 dev_dbg(info->dev, "get base:0x%lx, RO count:0x%lx, ticks:0x%lx\n",
203 base, data, ticks);
204
205 rtc_time_to_tm(ticks, &now_tm);
206 dev_dbg(info->dev, "%s, now time : %lu\n", __func__, ticks);
207 rtc_next_alarm_time(&alarm_tm, &now_tm, &alrm->time);
208 /* get new ticks for alarm in 24 hours */
209 rtc_tm_to_time(&alarm_tm, &ticks);
210 dev_dbg(info->dev, "%s, alarm time: %lu\n", __func__, ticks);
211 data = ticks - base;
212
213 buf[0] = data & 0xff;
214 buf[1] = (data >> 8) & 0xff;
215 buf[2] = (data >> 16) & 0xff;
216 buf[3] = (data >> 24) & 0xff;
217 regmap_raw_write(info->map, PM800_RTC_EXPIRE1_1, buf, 4);
218 if (alrm->enabled) {
219 mask = PM800_ALARM | PM800_ALARM_WAKEUP | PM800_ALARM1_EN;
220 regmap_update_bits(info->map, PM800_RTC_CONTROL, mask, mask);
221 } else {
222 mask = PM800_ALARM | PM800_ALARM_WAKEUP | PM800_ALARM1_EN;
223 regmap_update_bits(info->map, PM800_RTC_CONTROL, mask,
224 PM800_ALARM | PM800_ALARM_WAKEUP);
225 }
226 return 0;
227}
228
229static const struct rtc_class_ops pm80x_rtc_ops = {
230 .read_time = pm80x_rtc_read_time,
231 .set_time = pm80x_rtc_set_time,
232 .read_alarm = pm80x_rtc_read_alarm,
233 .set_alarm = pm80x_rtc_set_alarm,
234 .alarm_irq_enable = pm80x_rtc_alarm_irq_enable,
235};
236
237#ifdef CONFIG_PM
238static int pm80x_rtc_suspend(struct device *dev)
239{
240 return pm80x_dev_suspend(dev);
241}
242
243static int pm80x_rtc_resume(struct device *dev)
244{
245 return pm80x_dev_resume(dev);
246}
247#endif
248
249static SIMPLE_DEV_PM_OPS(pm80x_rtc_pm_ops, pm80x_rtc_suspend, pm80x_rtc_resume);
250
251static int __devinit pm80x_rtc_probe(struct platform_device *pdev)
252{
253 struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
254 struct pm80x_platform_data *pm80x_pdata;
255 struct pm80x_rtc_pdata *pdata = NULL;
256 struct pm80x_rtc_info *info;
257 struct rtc_time tm;
258 unsigned long ticks = 0;
259 int ret;
260
261 pdata = pdev->dev.platform_data;
262 if (pdata == NULL)
263 dev_warn(&pdev->dev, "No platform data!\n");
264
265 info =
266 devm_kzalloc(&pdev->dev, sizeof(struct pm80x_rtc_info), GFP_KERNEL);
267 if (!info)
268 return -ENOMEM;
269 info->irq = platform_get_irq(pdev, 0);
270 if (info->irq < 0) {
271 dev_err(&pdev->dev, "No IRQ resource!\n");
272 ret = -EINVAL;
273 goto out;
274 }
275
276 info->chip = chip;
277 info->map = chip->regmap;
278 if (!info->map) {
279 dev_err(&pdev->dev, "no regmap!\n");
280 ret = -EINVAL;
281 goto out;
282 }
283
284 info->dev = &pdev->dev;
285 dev_set_drvdata(&pdev->dev, info);
286
287 ret = pm80x_request_irq(chip, info->irq, rtc_update_handler,
288 IRQF_ONESHOT, "rtc", info);
289 if (ret < 0) {
290 dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
291 info->irq, ret);
292 goto out;
293 }
294
295 ret = pm80x_rtc_read_time(&pdev->dev, &tm);
296 if (ret < 0) {
297 dev_err(&pdev->dev, "Failed to read initial time.\n");
298 goto out_rtc;
299 }
300 if ((tm.tm_year < 70) || (tm.tm_year > 138)) {
301 tm.tm_year = 70;
302 tm.tm_mon = 0;
303 tm.tm_mday = 1;
304 tm.tm_hour = 0;
305 tm.tm_min = 0;
306 tm.tm_sec = 0;
307 ret = pm80x_rtc_set_time(&pdev->dev, &tm);
308 if (ret < 0) {
309 dev_err(&pdev->dev, "Failed to set initial time.\n");
310 goto out_rtc;
311 }
312 }
313 rtc_tm_to_time(&tm, &ticks);
314
315 info->rtc_dev = rtc_device_register("88pm80x-rtc", &pdev->dev,
316 &pm80x_rtc_ops, THIS_MODULE);
317 ret = PTR_ERR(info->rtc_dev);
318 if (IS_ERR(info->rtc_dev)) {
319 dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
320 goto out_rtc;
321 }
322 /*
323 * enable internal XO instead of internal 3.25MHz clock since it can
324 * free running in PMIC power-down state.
325 */
326 regmap_update_bits(info->map, PM800_RTC_CONTROL, PM800_RTC1_USE_XO,
327 PM800_RTC1_USE_XO);
328
329 if (pdev->dev.parent->platform_data) {
330 pm80x_pdata = pdev->dev.parent->platform_data;
331 pdata = pm80x_pdata->rtc;
332 if (pdata)
333 info->rtc_dev->dev.platform_data = &pdata->rtc_wakeup;
334 }
335
336 device_init_wakeup(&pdev->dev, 1);
337
338 return 0;
339out_rtc:
340 pm80x_free_irq(chip, info->irq, info);
341out:
342 devm_kfree(&pdev->dev, info);
343 return ret;
344}
345
346static int __devexit pm80x_rtc_remove(struct platform_device *pdev)
347{
348 struct pm80x_rtc_info *info = platform_get_drvdata(pdev);
349 platform_set_drvdata(pdev, NULL);
350 rtc_device_unregister(info->rtc_dev);
351 pm80x_free_irq(info->chip, info->irq, info);
352 devm_kfree(&pdev->dev, info);
353 return 0;
354}
355
356static struct platform_driver pm80x_rtc_driver = {
357 .driver = {
358 .name = "88pm80x-rtc",
359 .owner = THIS_MODULE,
360 .pm = &pm80x_rtc_pm_ops,
361 },
362 .probe = pm80x_rtc_probe,
363 .remove = __devexit_p(pm80x_rtc_remove),
364};
365
366module_platform_driver(pm80x_rtc_driver);
367
368MODULE_LICENSE("GPL");
369MODULE_DESCRIPTION("Marvell 88PM80x RTC driver");
370MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
371MODULE_ALIAS("platform:88pm80x-rtc");
diff --git a/drivers/rtc/rtc-max8925.c b/drivers/rtc/rtc-max8925.c
index 1459055a83aa..34e4349611db 100644
--- a/drivers/rtc/rtc-max8925.c
+++ b/drivers/rtc/rtc-max8925.c
@@ -69,6 +69,7 @@ struct max8925_rtc_info {
69 struct max8925_chip *chip; 69 struct max8925_chip *chip;
70 struct i2c_client *rtc; 70 struct i2c_client *rtc;
71 struct device *dev; 71 struct device *dev;
72 int irq;
72}; 73};
73 74
74static irqreturn_t rtc_update_handler(int irq, void *data) 75static irqreturn_t rtc_update_handler(int irq, void *data)
@@ -250,7 +251,7 @@ static int __devinit max8925_rtc_probe(struct platform_device *pdev)
250{ 251{
251 struct max8925_chip *chip = dev_get_drvdata(pdev->dev.parent); 252 struct max8925_chip *chip = dev_get_drvdata(pdev->dev.parent);
252 struct max8925_rtc_info *info; 253 struct max8925_rtc_info *info;
253 int irq, ret; 254 int ret;
254 255
255 info = kzalloc(sizeof(struct max8925_rtc_info), GFP_KERNEL); 256 info = kzalloc(sizeof(struct max8925_rtc_info), GFP_KERNEL);
256 if (!info) 257 if (!info)
@@ -258,13 +259,13 @@ static int __devinit max8925_rtc_probe(struct platform_device *pdev)
258 info->chip = chip; 259 info->chip = chip;
259 info->rtc = chip->rtc; 260 info->rtc = chip->rtc;
260 info->dev = &pdev->dev; 261 info->dev = &pdev->dev;
261 irq = chip->irq_base + MAX8925_IRQ_RTC_ALARM0; 262 info->irq = platform_get_irq(pdev, 0);
262 263
263 ret = request_threaded_irq(irq, NULL, rtc_update_handler, 264 ret = request_threaded_irq(info->irq, NULL, rtc_update_handler,
264 IRQF_ONESHOT, "rtc-alarm0", info); 265 IRQF_ONESHOT, "rtc-alarm0", info);
265 if (ret < 0) { 266 if (ret < 0) {
266 dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n", 267 dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
267 irq, ret); 268 info->irq, ret);
268 goto out_irq; 269 goto out_irq;
269 } 270 }
270 271
@@ -285,7 +286,7 @@ static int __devinit max8925_rtc_probe(struct platform_device *pdev)
285 return 0; 286 return 0;
286out_rtc: 287out_rtc:
287 platform_set_drvdata(pdev, NULL); 288 platform_set_drvdata(pdev, NULL);
288 free_irq(chip->irq_base + MAX8925_IRQ_RTC_ALARM0, info); 289 free_irq(info->irq, info);
289out_irq: 290out_irq:
290 kfree(info); 291 kfree(info);
291 return ret; 292 return ret;
@@ -296,7 +297,7 @@ static int __devexit max8925_rtc_remove(struct platform_device *pdev)
296 struct max8925_rtc_info *info = platform_get_drvdata(pdev); 297 struct max8925_rtc_info *info = platform_get_drvdata(pdev);
297 298
298 if (info) { 299 if (info) {
299 free_irq(info->chip->irq_base + MAX8925_IRQ_RTC_ALARM0, info); 300 free_irq(info->irq, info);
300 rtc_device_unregister(info->rtc_dev); 301 rtc_device_unregister(info->rtc_dev);
301 kfree(info); 302 kfree(info);
302 } 303 }
diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
index ec21f4a4a056..bb55eb4a7d48 100644
--- a/drivers/usb/host/ehci-omap.c
+++ b/drivers/usb/host/ehci-omap.c
@@ -152,14 +152,14 @@ static int omap_ehci_init(struct usb_hcd *hcd)
152 struct ehci_hcd_omap_platform_data *pdata; 152 struct ehci_hcd_omap_platform_data *pdata;
153 153
154 pdata = hcd->self.controller->platform_data; 154 pdata = hcd->self.controller->platform_data;
155
156 /* Hold PHYs in reset while initializing EHCI controller */
155 if (pdata->phy_reset) { 157 if (pdata->phy_reset) {
156 if (gpio_is_valid(pdata->reset_gpio_port[0])) 158 if (gpio_is_valid(pdata->reset_gpio_port[0]))
157 gpio_request_one(pdata->reset_gpio_port[0], 159 gpio_set_value_cansleep(pdata->reset_gpio_port[0], 0);
158 GPIOF_OUT_INIT_LOW, "USB1 PHY reset");
159 160
160 if (gpio_is_valid(pdata->reset_gpio_port[1])) 161 if (gpio_is_valid(pdata->reset_gpio_port[1]))
161 gpio_request_one(pdata->reset_gpio_port[1], 162 gpio_set_value_cansleep(pdata->reset_gpio_port[1], 0);
162 GPIOF_OUT_INIT_LOW, "USB2 PHY reset");
163 163
164 /* Hold the PHY in RESET for enough time till DIR is high */ 164 /* Hold the PHY in RESET for enough time till DIR is high */
165 udelay(10); 165 udelay(10);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 18:39:09 -0500