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authorViresh KUMAR <viresh.kumar@st.com>2011-03-04 05:12:51 -0500
committerVinod Koul <vinod.koul@intel.com>2011-03-06 14:42:28 -0500
commitee66509d7f354eecb45ac99f21ea6aa8650dea7e (patch)
tree206438e7c0ef9a7f0633fe44d6f306fdbf4b0b4e /drivers
parent59c22fc11d12b69da36c6585a38229863ba0bb16 (diff)
dw_dmac: Allow src/dst msize & flow controller to be configured at runtime
Msize or Burst Size is peripheral dependent in case of prep_slave_sg and cyclic_prep transfers, and in case of memcpy transfers it is platform dependent. So msize configuration must come from platform data. Also some peripherals (ex: JPEG), need to be flow controller for dma transfers, so this information in case of slave_sg & cyclic_prep transfers must come from platform data. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/dma/dw_dmac.c14
-rw-r--r--drivers/dma/dw_dmac_regs.h1
2 files changed, 9 insertions, 6 deletions
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index 318a342fc7ec..90ea08a53d62 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -36,9 +36,11 @@
36 struct dw_dma_slave *__slave = (private); \ 36 struct dw_dma_slave *__slave = (private); \
37 int dms = __slave ? __slave->dst_master : 0; \ 37 int dms = __slave ? __slave->dst_master : 0; \
38 int sms = __slave ? __slave->src_master : 1; \ 38 int sms = __slave ? __slave->src_master : 1; \
39 u8 smsize = __slave ? __slave->src_msize : 0; \
40 u8 dmsize = __slave ? __slave->dst_msize : 0; \
39 \ 41 \
40 (DWC_CTLL_DST_MSIZE(0) \ 42 (DWC_CTLL_DST_MSIZE(dmsize) \
41 | DWC_CTLL_SRC_MSIZE(0) \ 43 | DWC_CTLL_SRC_MSIZE(smsize) \
42 | DWC_CTLL_LLP_D_EN \ 44 | DWC_CTLL_LLP_D_EN \
43 | DWC_CTLL_LLP_S_EN \ 45 | DWC_CTLL_LLP_S_EN \
44 | DWC_CTLL_DMS(dms) \ 46 | DWC_CTLL_DMS(dms) \
@@ -683,7 +685,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
683 | DWC_CTLL_DST_WIDTH(reg_width) 685 | DWC_CTLL_DST_WIDTH(reg_width)
684 | DWC_CTLL_DST_FIX 686 | DWC_CTLL_DST_FIX
685 | DWC_CTLL_SRC_INC 687 | DWC_CTLL_SRC_INC
686 | DWC_CTLL_FC_M2P); 688 | DWC_CTLL_FC(dws->fc));
687 reg = dws->tx_reg; 689 reg = dws->tx_reg;
688 for_each_sg(sgl, sg, sg_len, i) { 690 for_each_sg(sgl, sg, sg_len, i) {
689 struct dw_desc *desc; 691 struct dw_desc *desc;
@@ -728,7 +730,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
728 | DWC_CTLL_SRC_WIDTH(reg_width) 730 | DWC_CTLL_SRC_WIDTH(reg_width)
729 | DWC_CTLL_DST_INC 731 | DWC_CTLL_DST_INC
730 | DWC_CTLL_SRC_FIX 732 | DWC_CTLL_SRC_FIX
731 | DWC_CTLL_FC_P2M); 733 | DWC_CTLL_FC(dws->fc));
732 734
733 reg = dws->rx_reg; 735 reg = dws->rx_reg;
734 for_each_sg(sgl, sg, sg_len, i) { 736 for_each_sg(sgl, sg, sg_len, i) {
@@ -1146,7 +1148,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1146 | DWC_CTLL_SRC_WIDTH(reg_width) 1148 | DWC_CTLL_SRC_WIDTH(reg_width)
1147 | DWC_CTLL_DST_FIX 1149 | DWC_CTLL_DST_FIX
1148 | DWC_CTLL_SRC_INC 1150 | DWC_CTLL_SRC_INC
1149 | DWC_CTLL_FC_M2P 1151 | DWC_CTLL_FC(dws->fc)
1150 | DWC_CTLL_INT_EN); 1152 | DWC_CTLL_INT_EN);
1151 break; 1153 break;
1152 case DMA_FROM_DEVICE: 1154 case DMA_FROM_DEVICE:
@@ -1157,7 +1159,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1157 | DWC_CTLL_DST_WIDTH(reg_width) 1159 | DWC_CTLL_DST_WIDTH(reg_width)
1158 | DWC_CTLL_DST_INC 1160 | DWC_CTLL_DST_INC
1159 | DWC_CTLL_SRC_FIX 1161 | DWC_CTLL_SRC_FIX
1160 | DWC_CTLL_FC_P2M 1162 | DWC_CTLL_FC(dws->fc)
1161 | DWC_CTLL_INT_EN); 1163 | DWC_CTLL_INT_EN);
1162 break; 1164 break;
1163 default: 1165 default:
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index 6a8e6d35f359..9a32964bf795 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -86,6 +86,7 @@ struct dw_dma_regs {
86#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) 86#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
87#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */ 87#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
88#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */ 88#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
89#define DWC_CTLL_FC(n) ((n) << 20)
89#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */ 90#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
90#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ 91#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
91#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ 92#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */