diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2012-10-01 09:27:04 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-02 04:28:18 -0400 |
commit | ac82ea2e97a32f9c49d0746874b4cd1d8904d10f (patch) | |
tree | 33e3ab959431fce936b581424f1b26bc13cbe820 /drivers | |
parent | 3bc2913e2cb74aac8af90b46fa251dfb8d854665 (diff) |
drm/i915: Actually invalidate the TLB for the SandyBridge HW contexts w/a
A side-effect of commit 7d54a904285b6e780291b91a518267bec5591913
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Aug 10 10:18:10 2012 +0100
drm/i915: Apply post-sync write for pipe control invalidates
was that only a request to emit invalidate flush would result in the
TLB being invalidated (since it requires synchronisation and so incurs a
performance penalty). However, the stated w/a for hardware contexts is
that the TLBs must be invalidated prior to a MI_SET_CONTEXT, yet the w/a
itself did not request the TLBs to be invalidated...
Note this w/a does not prevent the hard system hang I experience when
using hw contexts (with rc6 enabled) on SNB GT1.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_context.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 4aa7ecf77ede..b8d9fbb41f65 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c | |||
@@ -328,7 +328,7 @@ mi_set_context(struct intel_ring_buffer *ring, | |||
328 | * itlb_before_ctx_switch. | 328 | * itlb_before_ctx_switch. |
329 | */ | 329 | */ |
330 | if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { | 330 | if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { |
331 | ret = ring->flush(ring, 0, 0); | 331 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); |
332 | if (ret) | 332 | if (ret) |
333 | return ret; | 333 | return ret; |
334 | } | 334 | } |