Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
  drm/i915: fix page flip finish vs. prepare on plane B
  drm/i915: change default panel fitting mode to preserve aspect ratio
  drm/i915: fix uninitialized variable warning in i915_setup_compression()
  drm/i915: take struct_mutex in i915_dma_cleanup()
  drm/i915: Fix CRT hotplug regression in 2.6.35-rc1
  i915: fix ironlake edp panel setup (v4)
  drm/i915: don't access FW_BLC_SELF on 965G
  drm/i915: Account for space on the ring buffer consumed whilst wrapping.
  drm/i915: gen3 page flipping fixes
  drm/i915: don't queue flips during a flip pending event
  drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer.
  drm/i915: Turn on 945 self-refresh only if single CRTC is active
  drm/i915/gen4: Fix interrupt setup ordering
  drm/i915: Use RSEN instead of HTPLG for tfp410 monitor detection.
  drm/i915: Move non-phys cursors into the GTT
  Revert "drm/i915: Don't enable pipe/plane/VCO early (wait for DPMS on)."

(Included the "fix page flip finish vs.  prepare on plane B" patch from
Jesse on top of the pull request from Eric.   -- Linus)

12 files changed, 140 insertions, 64 deletions

diff --git a/drivers/gpu/drm/i915/dvo_tfp410.c b/drivers/gpu/drm/i915/dvo_tfp410.c
index 66c697bc9b22..56f66426207f 100644
--- a/drivers/gpu/drm/i915/dvo_tfp410.c
+++ b/drivers/gpu/drm/i915/dvo_tfp410.c
@@ -208,7 +208,7 @@ static enum drm_connector_status tfp410_detect(struct intel_dvo_device *dvo)
         uint8_t ctl2;
 
         if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) {
-                if (ctl2 & TFP410_CTL_2_HTPLG)
+                if (ctl2 & TFP410_CTL_2_RSEN)
                         ret = connector_status_connected;
                 else
                         ret = connector_status_disconnected;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 52510ad8b25d..aee83fa178f6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -620,7 +620,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
         drm_i915_private_t *dev_priv = dev->dev_private;
         bool sr_enabled = false;
 
-        if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev))
+        if (IS_I965GM(dev) || IS_I945G(dev) || IS_I945GM(dev))
                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
         else if (IS_I915GM(dev))
                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 59a2bf8592ec..f00c5ae9556c 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -128,9 +128,11 @@ static int i915_dma_cleanup(struct drm_device * dev)
         if (dev->irq_enabled)
                 drm_irq_uninstall(dev);
 
+        mutex_lock(&dev->struct_mutex);
         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
         if (HAS_BSD(dev))
                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
+        mutex_unlock(&dev->struct_mutex);
 
         /* Clear the HWS virtual address at teardown */
         if (I915_NEED_GFX_HWS(dev))
@@ -1229,7 +1231,7 @@ static void i915_warn_stolen(struct drm_device *dev)
 static void i915_setup_compression(struct drm_device *dev, int size)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
-        struct drm_mm_node *compressed_fb, *compressed_llb;
+        struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
         unsigned long cfb_base;
         unsigned long ll_base = 0;
 
@@ -1410,6 +1412,10 @@ static int i915_load_modeset_init(struct drm_device *dev,
         if (ret)
                 goto cleanup_vga_client;
 
+        /* IIR "flip pending" bit means done if this bit is set */
+        if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
+                dev_priv->flip_pending_is_done = true;
+
         intel_modeset_init(dev);
 
         ret = drm_irq_install(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 276583159847..d147ab2f5bfc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -596,6 +596,7 @@ typedef struct drm_i915_private {
         struct drm_crtc *plane_to_crtc_mapping[2];
         struct drm_crtc *pipe_to_crtc_mapping[2];
         wait_queue_head_t pending_flip_queue;
+        bool flip_pending_is_done;
 
         /* Reclocking support */
         bool render_reclock_avail;
@@ -1076,7 +1077,7 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
         drm_i915_private_t *dev_priv = dev->dev_private;                \
         if (I915_VERBOSE)                                               \
                 DRM_DEBUG("   BEGIN_LP_RING %x\n", (int)(n));           \
-        intel_ring_begin(dev, &dev_priv->render_ring, 4*(n));           \
+        intel_ring_begin(dev, &dev_priv->render_ring, (n));             \
 } while (0)
 
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2479be001e40..dba53d4b9fb3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -940,22 +940,30 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
                         DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
 
-                if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
+                if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
                         intel_prepare_page_flip(dev, 0);
+                        if (dev_priv->flip_pending_is_done)
+                                intel_finish_page_flip_plane(dev, 0);
+                }
 
-                if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
+                if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
                         intel_prepare_page_flip(dev, 1);
+                        if (dev_priv->flip_pending_is_done)
+                                intel_finish_page_flip_plane(dev, 1);
+                }
 
                 if (pipea_stats & vblank_status) {
                         vblank++;
                         drm_handle_vblank(dev, 0);
-                        intel_finish_page_flip(dev, 0);
+                        if (!dev_priv->flip_pending_is_done)
+                                intel_finish_page_flip(dev, 0);
                 }
 
                 if (pipeb_stats & vblank_status) {
                         vblank++;
                         drm_handle_vblank(dev, 1);
-                        intel_finish_page_flip(dev, 1);
+                        if (!dev_priv->flip_pending_is_done)
+                                intel_finish_page_flip(dev, 1);
                 }
 
                 if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
@@ -1387,29 +1395,10 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
         dev_priv->pipestat[1] = 0;
 
         if (I915_HAS_HOTPLUG(dev)) {
-                u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
-
-                /* Note HDMI and DP share bits */
-                if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
-                        hotplug_en |= HDMIB_HOTPLUG_INT_EN;
-                if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
-                        hotplug_en |= HDMIC_HOTPLUG_INT_EN;
-                if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
-                        hotplug_en |= HDMID_HOTPLUG_INT_EN;
-                if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
-                        hotplug_en |= SDVOC_HOTPLUG_INT_EN;
-                if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
-                        hotplug_en |= SDVOB_HOTPLUG_INT_EN;
-                if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
-                        hotplug_en |= CRT_HOTPLUG_INT_EN;
-                /* Ignore TV since it's buggy */
-
-                I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
-
                 /* Enable in IER... */
                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
                 /* and unmask in IMR */
-                i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
+                dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
         }
 
         /*
@@ -1427,16 +1416,41 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
         }
         I915_WRITE(EMR, error_mask);
 
-        /* Disable pipe interrupt enables, clear pending pipe status */
-        I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
-        I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
-        /* Clear pending interrupt status */
-        I915_WRITE(IIR, I915_READ(IIR));
-
-        I915_WRITE(IER, enable_mask);
         I915_WRITE(IMR, dev_priv->irq_mask_reg);
+        I915_WRITE(IER, enable_mask);
         (void) I915_READ(IER);
 
+        if (I915_HAS_HOTPLUG(dev)) {
+                u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
+
+                /* Note HDMI and DP share bits */
+                if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMIB_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMIC_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMID_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
+                        hotplug_en |= SDVOC_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
+                        hotplug_en |= SDVOB_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
+                        hotplug_en |= CRT_HOTPLUG_INT_EN;
+
+                        /* Programming the CRT detection parameters tends
+                           to generate a spurious hotplug event about three
+                           seconds later.  So just do it once.
+                        */
+                        if (IS_G4X(dev))
+                                hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
+                        hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
+                }
+
+                /* Ignore TV since it's buggy */
+
+                I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
+        }
+
         opregion_enable_asle(dev);
 
         return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64b0a3afd92b..150400f40534 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -178,6 +178,7 @@
 #define   MI_OVERLAY_OFF        (0x2<<21)
 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
 #define MI_DISPLAY_FLIP         MI_INSTR(0x14, 2)
+#define MI_DISPLAY_FLIP_I915    MI_INSTR(0x14, 1)
 #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
 #define MI_STORE_DWORD_IMM      MI_INSTR(0x20, 1)
 #define   MI_MEM_VIRTUAL        (1 << 22) /* 965+ only */
@@ -368,6 +369,9 @@
 #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
 #define BB_ADDR         0x02140 /* 8 bytes */
 #define GFX_FLSH_CNTL   0x02170 /* 915+ only */
+#define ECOSKPD         0x021d0
+#define   ECO_GATING_CX_ONLY    (1<<3)
+#define   ECO_FLIP_DONE         (1<<0)
 
 /* GEN6 interrupt control */
 #define GEN6_RENDER_HWSTAM      0x2098
@@ -1130,7 +1134,6 @@
 #define CRT_HOTPLUG_DETECT_DELAY_2G             (1 << 4)
 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV        (0 << 2)
 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV        (1 << 2)
-#define CRT_HOTPLUG_MASK                        (0x3fc) /* Bits 9-2 */
 
 #define PORT_HOTPLUG_STAT       0x61114
 #define   HDMIB_HOTPLUG_INT_STATUS              (1 << 29)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 22ff38455731..ee0732b222a1 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -234,14 +234,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
         else
                 tries = 1;
         hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
-        hotplug_en &= CRT_HOTPLUG_MASK;
         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
 
-        if (IS_G4X(dev))
-                hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
-
-        hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
-
         for (i = 0; i < tries ; i++) {
                 unsigned long timeout;
                 /* turn on the FORCE_DETECT */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cc8131ff319f..68dcf36e2793 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2970,11 +2970,13 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
                 if (srwm < 0)
                         srwm = 1;
                 srwm &= 0x3f;
-                I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
+                if (IS_I965GM(dev))
+                        I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
         } else {
                 /* Turn off self refresh if both pipes are enabled */
-                I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
-                                        & ~FW_BLC_SELF_EN);
+                if (IS_I965GM(dev))
+                        I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
+                                   & ~FW_BLC_SELF_EN);
         }
 
         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
@@ -4483,6 +4485,7 @@ static void intel_idle_update(struct work_struct *work)
         struct drm_device *dev = dev_priv->dev;
         struct drm_crtc *crtc;
         struct intel_crtc *intel_crtc;
+        int enabled = 0;
 
         if (!i915_powersave)
                 return;
@@ -4491,21 +4494,22 @@ static void intel_idle_update(struct work_struct *work)
 
         i915_update_gfx_val(dev_priv);
 
-        if (IS_I945G(dev) || IS_I945GM(dev)) {
-                DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
-                I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
-        }
-
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                 /* Skip inactive CRTCs */
                 if (!crtc->fb)
                         continue;
 
+                enabled++;
                 intel_crtc = to_intel_crtc(crtc);
                 if (!intel_crtc->busy)
                         intel_decrease_pllclock(crtc);
         }
 
+        if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
+                DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
+                I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
+        }
+
         mutex_unlock(&dev->struct_mutex);
 }
 
@@ -4601,10 +4605,10 @@ static void intel_unpin_work_fn(struct work_struct *__work)
         kfree(work);
 }
 
-void intel_finish_page_flip(struct drm_device *dev, int pipe)
+static void do_intel_finish_page_flip(struct drm_device *dev,
+                                      struct drm_crtc *crtc)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
-        struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct intel_unpin_work *work;
         struct drm_i915_gem_object *obj_priv;
@@ -4648,6 +4652,22 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe)
         schedule_work(&work->work);
 }
 
+void intel_finish_page_flip(struct drm_device *dev, int pipe)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+
+        do_intel_finish_page_flip(dev, crtc);
+}
+
+void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
+
+        do_intel_finish_page_flip(dev, crtc);
+}
+
 void intel_prepare_page_flip(struct drm_device *dev, int plane)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
@@ -4678,6 +4698,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         unsigned long flags;
         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
         int ret, pipesrc;
+        u32 flip_mask;
 
         work = kzalloc(sizeof *work, GFP_KERNEL);
         if (work == NULL)
@@ -4731,15 +4752,28 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         atomic_inc(&obj_priv->pending_flip);
         work->pending_flip_obj = obj;
 
+        if (intel_crtc->plane)
+                flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+        else
+                flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+
+        /* Wait for any previous flip to finish */
+        if (IS_GEN3(dev))
+                while (I915_READ(ISR) & flip_mask)
+                        ;
+
         BEGIN_LP_RING(4);
-        OUT_RING(MI_DISPLAY_FLIP |
-                 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-        OUT_RING(fb->pitch);
         if (IS_I965G(dev)) {
+                OUT_RING(MI_DISPLAY_FLIP |
+                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+                OUT_RING(fb->pitch);
                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
                 pipesrc = I915_READ(pipesrc_reg); 
                 OUT_RING(pipesrc & 0x0fff0fff);
         } else {
+                OUT_RING(MI_DISPLAY_FLIP_I915 |
+                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+                OUT_RING(fb->pitch);
                 OUT_RING(obj_priv->gtt_offset);
                 OUT_RING(MI_NOOP);
         }
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 49b54f05d3cf..1aac59e83bff 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -136,6 +136,12 @@ intel_dp_link_required(struct drm_device *dev,
 }
 
 static int
+intel_dp_max_data_rate(int max_link_clock, int max_lanes)
+{
+        return (max_link_clock * max_lanes * 8) / 10;
+}
+
+static int
 intel_dp_mode_valid(struct drm_connector *connector,
                     struct drm_display_mode *mode)
 {
@@ -144,8 +150,11 @@ intel_dp_mode_valid(struct drm_connector *connector,
         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
         int max_lanes = intel_dp_max_lane_count(intel_encoder);
 
-        if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
-                        > max_link_clock * max_lanes)
+        /* only refuse the mode on non eDP since we have seen some wierd eDP panels
+           which are outside spec tolerances but somehow work by magic */
+        if (!IS_eDP(intel_encoder) &&
+            (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
+             > intel_dp_max_data_rate(max_link_clock, max_lanes)))
                 return MODE_CLOCK_HIGH;
 
         if (mode->clock < 10000)
@@ -506,7 +515,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 
         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
                 for (clock = 0; clock <= max_clock; clock++) {
-                        int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
+                        int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 
                         if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
                                         <= link_avail) {
@@ -521,6 +530,18 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
                         }
                 }
         }
+
+        if (IS_eDP(intel_encoder)) {
+                /* okay we failed just pick the highest */
+                dp_priv->lane_count = max_lane_count;
+                dp_priv->link_bw = bws[max_clock];
+                adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
+                DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
+                              "count %d clock %d\n",
+                              dp_priv->link_bw, dp_priv->lane_count,
+                              adjusted_mode->clock);
+                return true;
+        }
         return false;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index df931f787665..72206f37c4fb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -224,6 +224,7 @@ extern void intel_fbdev_fini(struct drm_device *dev);
 
 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
+extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 
 extern void intel_setup_overlay(struct drm_device *dev);
 extern void intel_cleanup_overlay(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 6a1accd83aec..31df55f0a0a7 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -983,8 +983,8 @@ void intel_lvds_init(struct drm_device *dev)
 
         drm_connector_attach_property(&intel_connector->base,
                                       dev->mode_config.scaling_mode_property,
-                                      DRM_MODE_SCALE_FULLSCREEN);
-        lvds_priv->fitting_mode = DRM_MODE_SCALE_FULLSCREEN;
+                                      DRM_MODE_SCALE_ASPECT);
+        lvds_priv->fitting_mode = DRM_MODE_SCALE_ASPECT;
         /*
          * LVDS discovery:
          * 1) check for EDID on DDC
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cea4f1a8709e..26362f8495a8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -94,7 +94,7 @@ render_ring_flush(struct drm_device *dev,
 #if WATCH_EXEC
                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 #endif
-                intel_ring_begin(dev, ring, 8);
+                intel_ring_begin(dev, ring, 2);
                 intel_ring_emit(dev, ring, cmd);
                 intel_ring_emit(dev, ring, MI_NOOP);
                 intel_ring_advance(dev, ring);
@@ -358,7 +358,7 @@ bsd_ring_flush(struct drm_device *dev,
                 u32     invalidate_domains,
                 u32     flush_domains)
 {
-        intel_ring_begin(dev, ring, 8);
+        intel_ring_begin(dev, ring, 2);
         intel_ring_emit(dev, ring, MI_FLUSH);
         intel_ring_emit(dev, ring, MI_NOOP);
         intel_ring_advance(dev, ring);
@@ -687,6 +687,7 @@ int intel_wrap_ring_buffer(struct drm_device *dev,
                 *virt++ = MI_NOOP;
 
         ring->tail = 0;
+        ring->space = ring->head - 8;
 
         return 0;
 }
@@ -721,8 +722,9 @@ int intel_wait_ring_buffer(struct drm_device *dev,
 }
 
 void intel_ring_begin(struct drm_device *dev,
-                struct intel_ring_buffer *ring, int n)
+                struct intel_ring_buffer *ring, int num_dwords)
 {
+        int n = 4*num_dwords;
         if (unlikely(ring->tail + n > ring->size))
                 intel_wrap_ring_buffer(dev, ring);
         if (unlikely(ring->space < n))
@@ -752,7 +754,7 @@ void intel_fill_struct(struct drm_device *dev,
 {
         unsigned int *virt = ring->virtual_start + ring->tail;
         BUG_ON((len&~(4-1)) != 0);
-        intel_ring_begin(dev, ring, len);
+        intel_ring_begin(dev, ring, len/4);
         memcpy(virt, data, len);
         ring->tail += len;
         ring->tail &= ring->size - 1;