aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2008-08-13 23:48:46 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-08-13 23:48:46 -0400
commit7a49efae71397cf7e9299bbb22b2d12f7cf12428 (patch)
treed4e47542448b0018f4f684e4097efb05db6bd355 /drivers
parent0ff8285075a1242dbc969b6b4b1719d692931a02 (diff)
parent877acedc0d3ea07f7b36573ed2f1f479c2c1eefd (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (56 commits) netns: Fix crash by making igmp per namespace bnx2x: Version update bnx2x: Checkpatch compliance bnx2x: Spelling mistakes bnx2x: Minor code improvements bnx2x: Driver info bnx2x: 1G LED does not turn off bnx2x: 8073 PHY changes bnx2x: Change GPIO for any port bnx2x: Pause settings bnx2x: Link order with external PHY bnx2x: No LRO without Rx checksum bnx2x: Wrong structure size bnx2x: WoL capability bnx2x: Clearing MAC addresses filters bnx2x: Delay in while loops bnx2x: PBA Table Page Alignment Workaround bnx2x: Self-test false positive bnx2x: Memory allocation bnx2x: HW attention lock ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2x.h87
-rw-r--r--drivers/net/bnx2x_fw_defs.h160
-rw-r--r--drivers/net/bnx2x_hsi.h16
-rw-r--r--drivers/net/bnx2x_init.h26
-rw-r--r--drivers/net/bnx2x_init_values.h533
-rw-r--r--drivers/net/bnx2x_link.c1258
-rw-r--r--drivers/net/bnx2x_link.h11
-rw-r--r--drivers/net/bnx2x_main.c1212
-rw-r--r--drivers/net/bnx2x_reg.h210
9 files changed, 2033 insertions, 1480 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 4bf4f7b205f2..b468f904c7f8 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -40,20 +40,20 @@
40#define DP(__mask, __fmt, __args...) do { \ 40#define DP(__mask, __fmt, __args...) do { \
41 if (bp->msglevel & (__mask)) \ 41 if (bp->msglevel & (__mask)) \
42 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ 42 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
43 bp->dev?(bp->dev->name):"?", ##__args); \ 43 bp->dev ? (bp->dev->name) : "?", ##__args); \
44 } while (0) 44 } while (0)
45 45
46/* errors debug print */ 46/* errors debug print */
47#define BNX2X_DBG_ERR(__fmt, __args...) do { \ 47#define BNX2X_DBG_ERR(__fmt, __args...) do { \
48 if (bp->msglevel & NETIF_MSG_PROBE) \ 48 if (bp->msglevel & NETIF_MSG_PROBE) \
49 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ 49 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
50 bp->dev?(bp->dev->name):"?", ##__args); \ 50 bp->dev ? (bp->dev->name) : "?", ##__args); \
51 } while (0) 51 } while (0)
52 52
53/* for errors (never masked) */ 53/* for errors (never masked) */
54#define BNX2X_ERR(__fmt, __args...) do { \ 54#define BNX2X_ERR(__fmt, __args...) do { \
55 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ 55 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
56 bp->dev?(bp->dev->name):"?", ##__args); \ 56 bp->dev ? (bp->dev->name) : "?", ##__args); \
57 } while (0) 57 } while (0)
58 58
59/* before we have a dev->name use dev_info() */ 59/* before we have a dev->name use dev_info() */
@@ -120,16 +120,8 @@
120#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 120#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
121#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 121#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
122 122
123#define NIG_WR(reg, val) REG_WR(bp, reg, val) 123#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
124#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val) 124#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
125#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
126
127
128#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
129
130#define for_each_nondefault_queue(bp, var) \
131 for (var = 1; var < bp->num_queues; var++)
132#define is_multi(bp) (bp->num_queues > 1)
133 125
134 126
135/* fast path */ 127/* fast path */
@@ -163,7 +155,7 @@ struct sw_rx_page {
163#define NUM_RX_SGE_PAGES 2 155#define NUM_RX_SGE_PAGES 2
164#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 156#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
165#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) 157#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
166/* RX_SGE_CNT is promissed to be a power of 2 */ 158/* RX_SGE_CNT is promised to be a power of 2 */
167#define RX_SGE_MASK (RX_SGE_CNT - 1) 159#define RX_SGE_MASK (RX_SGE_CNT - 1)
168#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 160#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
169#define MAX_RX_SGE (NUM_RX_SGE - 1) 161#define MAX_RX_SGE (NUM_RX_SGE - 1)
@@ -258,8 +250,7 @@ struct bnx2x_fastpath {
258 250
259 unsigned long tx_pkt, 251 unsigned long tx_pkt,
260 rx_pkt, 252 rx_pkt,
261 rx_calls, 253 rx_calls;
262 rx_alloc_failed;
263 /* TPA related */ 254 /* TPA related */
264 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; 255 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
265 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; 256 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
@@ -275,6 +266,15 @@ struct bnx2x_fastpath {
275 266
276#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) 267#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
277 268
269#define BNX2X_HAS_TX_WORK(fp) \
270 ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || \
271 (fp->tx_pkt_prod != fp->tx_pkt_cons))
272
273#define BNX2X_HAS_RX_WORK(fp) \
274 (fp->rx_comp_cons != le16_to_cpu(*fp->rx_cons_sb))
275
276#define BNX2X_HAS_WORK(fp) (BNX2X_HAS_RX_WORK(fp) || BNX2X_HAS_TX_WORK(fp))
277
278 278
279/* MC hsi */ 279/* MC hsi */
280#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 280#define MAX_FETCH_BD 13 /* HW max BDs per packet */
@@ -317,7 +317,7 @@ struct bnx2x_fastpath {
317#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 317#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
318 318
319 319
320/* This is needed for determening of last_max */ 320/* This is needed for determining of last_max */
321#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 321#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
322 322
323#define __SGE_MASK_SET_BIT(el, bit) \ 323#define __SGE_MASK_SET_BIT(el, bit) \
@@ -386,20 +386,28 @@ struct bnx2x_fastpath {
386#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \ 386#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
387 (TPA_TYPE_START | TPA_TYPE_END)) 387 (TPA_TYPE_START | TPA_TYPE_END))
388 388
389#define BNX2X_RX_SUM_OK(cqe) \ 389#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
390 (!(cqe->fast_path_cqe.status_flags & \ 390
391 (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \ 391#define BNX2X_IP_CSUM_ERR(cqe) \
392 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG))) 392 (!((cqe)->fast_path_cqe.status_flags & \
393 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
394 ((cqe)->fast_path_cqe.type_error_flags & \
395 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
396
397#define BNX2X_L4_CSUM_ERR(cqe) \
398 (!((cqe)->fast_path_cqe.status_flags & \
399 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
400 ((cqe)->fast_path_cqe.type_error_flags & \
401 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
402
403#define BNX2X_RX_CSUM_OK(cqe) \
404 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
393 405
394#define BNX2X_RX_SUM_FIX(cqe) \ 406#define BNX2X_RX_SUM_FIX(cqe) \
395 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \ 407 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
396 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \ 408 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
397 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT)) 409 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
398 410
399#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
400 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
401 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
402
403 411
404#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES) 412#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
405#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES) 413#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
@@ -647,6 +655,8 @@ struct bnx2x_eth_stats {
647 655
648 u32 brb_drop_hi; 656 u32 brb_drop_hi;
649 u32 brb_drop_lo; 657 u32 brb_drop_lo;
658 u32 brb_truncate_hi;
659 u32 brb_truncate_lo;
650 660
651 u32 jabber_packets_received; 661 u32 jabber_packets_received;
652 662
@@ -663,6 +673,9 @@ struct bnx2x_eth_stats {
663 u32 mac_discard; 673 u32 mac_discard;
664 674
665 u32 driver_xoff; 675 u32 driver_xoff;
676 u32 rx_err_discard_pkt;
677 u32 rx_skb_alloc_failed;
678 u32 hw_csum_err;
666}; 679};
667 680
668#define STATS_OFFSET32(stat_name) \ 681#define STATS_OFFSET32(stat_name) \
@@ -753,7 +766,6 @@ struct bnx2x {
753 u16 def_att_idx; 766 u16 def_att_idx;
754 u32 attn_state; 767 u32 attn_state;
755 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 768 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
756 u32 aeu_mask;
757 u32 nig_mask; 769 u32 nig_mask;
758 770
759 /* slow path ring */ 771 /* slow path ring */
@@ -772,7 +784,7 @@ struct bnx2x {
772 u8 stats_pending; 784 u8 stats_pending;
773 u8 set_mac_pending; 785 u8 set_mac_pending;
774 786
775 /* End of fileds used in the performance code paths */ 787 /* End of fields used in the performance code paths */
776 788
777 int panic; 789 int panic;
778 int msglevel; 790 int msglevel;
@@ -794,9 +806,6 @@ struct bnx2x {
794#define BP_FUNC(bp) (bp->func) 806#define BP_FUNC(bp) (bp->func)
795#define BP_E1HVN(bp) (bp->func >> 1) 807#define BP_E1HVN(bp) (bp->func >> 1)
796#define BP_L_ID(bp) (BP_E1HVN(bp) << 2) 808#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
797/* assorted E1HVN */
798#define IS_E1HMF(bp) (bp->e1hmf != 0)
799#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
800 809
801 int pm_cap; 810 int pm_cap;
802 int pcie_cap; 811 int pcie_cap;
@@ -821,6 +830,7 @@ struct bnx2x {
821 u32 mf_config; 830 u32 mf_config;
822 u16 e1hov; 831 u16 e1hov;
823 u8 e1hmf; 832 u8 e1hmf;
833#define IS_E1HMF(bp) (bp->e1hmf != 0)
824 834
825 u8 wol; 835 u8 wol;
826 836
@@ -836,7 +846,6 @@ struct bnx2x {
836 u16 rx_ticks_int; 846 u16 rx_ticks_int;
837 u16 rx_ticks; 847 u16 rx_ticks;
838 848
839 u32 stats_ticks;
840 u32 lin_cnt; 849 u32 lin_cnt;
841 850
842 int state; 851 int state;
@@ -852,6 +861,7 @@ struct bnx2x {
852#define BNX2X_STATE_ERROR 0xf000 861#define BNX2X_STATE_ERROR 0xf000
853 862
854 int num_queues; 863 int num_queues;
864#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
855 865
856 u32 rx_mode; 866 u32 rx_mode;
857#define BNX2X_RX_MODE_NONE 0 867#define BNX2X_RX_MODE_NONE 0
@@ -902,10 +912,17 @@ struct bnx2x {
902}; 912};
903 913
904 914
915#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
916
917#define for_each_nondefault_queue(bp, var) \
918 for (var = 1; var < bp->num_queues; var++)
919#define is_multi(bp) (bp->num_queues > 1)
920
921
905void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 922void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
906void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 923void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
907 u32 len32); 924 u32 len32);
908int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); 925int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
909 926
910static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 927static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
911 int wait) 928 int wait)
@@ -976,7 +993,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
976#define PCICFG_LINK_SPEED_SHIFT 16 993#define PCICFG_LINK_SPEED_SHIFT 16
977 994
978 995
979#define BNX2X_NUM_STATS 39 996#define BNX2X_NUM_STATS 42
980#define BNX2X_NUM_TESTS 8 997#define BNX2X_NUM_TESTS 8
981 998
982#define BNX2X_MAC_LOOPBACK 0 999#define BNX2X_MAC_LOOPBACK 0
@@ -1007,10 +1024,10 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1007/* resolution of the rate shaping timer - 100 usec */ 1024/* resolution of the rate shaping timer - 100 usec */
1008#define RS_PERIODIC_TIMEOUT_USEC 100 1025#define RS_PERIODIC_TIMEOUT_USEC 100
1009/* resolution of fairness algorithm in usecs - 1026/* resolution of fairness algorithm in usecs -
1010 coefficient for clauclating the actuall t fair */ 1027 coefficient for calculating the actual t fair */
1011#define T_FAIR_COEF 10000000 1028#define T_FAIR_COEF 10000000
1012/* number of bytes in single QM arbitration cycle - 1029/* number of bytes in single QM arbitration cycle -
1013 coeffiecnt for calculating the fairness timer */ 1030 coefficient for calculating the fairness timer */
1014#define QM_ARB_BYTES 40000 1031#define QM_ARB_BYTES 40000
1015#define FAIR_MEM 2 1032#define FAIR_MEM 2
1016 1033
diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h
index e3da7f69d27b..192fa981b930 100644
--- a/drivers/net/bnx2x_fw_defs.h
+++ b/drivers/net/bnx2x_fw_defs.h
@@ -9,165 +9,171 @@
9 9
10 10
11#define CSTORM_ASSERT_LIST_INDEX_OFFSET \ 11#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
12 (IS_E1H_OFFSET? 0x7000 : 0x1000) 12 (IS_E1H_OFFSET ? 0x7000 : 0x1000)
13#define CSTORM_ASSERT_LIST_OFFSET(idx) \ 13#define CSTORM_ASSERT_LIST_OFFSET(idx) \
14 (IS_E1H_OFFSET? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 14 (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
15#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 15#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
16 (IS_E1H_OFFSET? (0x8522 + ((function>>1) * 0x40) + ((function&1) \ 16 (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \
17 * 0x100) + (index * 0x4)) : (0x1922 + (function * 0x40) + (index \ 17 ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
18 * 0x4))) 18 0x40) + (index * 0x4)))
19#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ 19#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
20 (IS_E1H_OFFSET? (0x8500 + ((function>>1) * 0x40) + ((function&1) \ 20 (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \
21 * 0x100)) : (0x1900 + (function * 0x40))) 21 ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
22#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ 22#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
23 (IS_E1H_OFFSET? (0x8508 + ((function>>1) * 0x40) + ((function&1) \ 23 (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \
24 * 0x100)) : (0x1908 + (function * 0x40))) 24 ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
25#define CSTORM_FUNCTION_MODE_OFFSET \ 25#define CSTORM_FUNCTION_MODE_OFFSET \
26 (IS_E1H_OFFSET? 0x11e8 : 0xffffffff) 26 (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
27#define CSTORM_HC_BTR_OFFSET(port) \ 27#define CSTORM_HC_BTR_OFFSET(port) \
28 (IS_E1H_OFFSET? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) 28 (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
29#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ 29#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
30 (IS_E1H_OFFSET? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \ 30 (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
31 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ 31 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
32 (index * 0x4))) 32 (index * 0x4)))
33#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ 33#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
34 (IS_E1H_OFFSET? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \ 34 (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
35 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ 35 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
36 (index * 0x4))) 36 (index * 0x4)))
37#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ 37#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
38 (IS_E1H_OFFSET? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \ 38 (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
39 (0x1400 + (port * 0x280) + (cpu_id * 0x28))) 39 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
40#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ 40#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
41 (IS_E1H_OFFSET? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \ 41 (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
42 (0x1408 + (port * 0x280) + (cpu_id * 0x28))) 42 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
43#define CSTORM_STATS_FLAGS_OFFSET(function) \ 43#define CSTORM_STATS_FLAGS_OFFSET(function) \
44 (IS_E1H_OFFSET? (0x1108 + (function * 0x8)) : (0x5108 + \ 44 (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
45 (function * 0x8))) 45 (function * 0x8)))
46#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \ 46#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
47 (IS_E1H_OFFSET? (0x31c0 + (function * 0x20)) : 0xffffffff) 47 (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff)
48#define TSTORM_ASSERT_LIST_INDEX_OFFSET \ 48#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
49 (IS_E1H_OFFSET? 0xa000 : 0x1000) 49 (IS_E1H_OFFSET ? 0xa000 : 0x1000)
50#define TSTORM_ASSERT_LIST_OFFSET(idx) \ 50#define TSTORM_ASSERT_LIST_OFFSET(idx) \
51 (IS_E1H_OFFSET? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 51 (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
52#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \ 52#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
53 (IS_E1H_OFFSET? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) : \ 53 (IS_E1H_OFFSET ? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) \
54 (0x9c8 + (port * 0x2f8) + (client_id * 0x28))) 54 : (0x9c8 + (port * 0x2f8) + (client_id * 0x28)))
55#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 55#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
56 (IS_E1H_OFFSET? (0xb01a + ((function>>1) * 0x28) + ((function&1) \ 56 (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
57 * 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \ 57 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
58 0x4))) 58 0x28) + (index * 0x4)))
59#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ 59#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
60 (IS_E1H_OFFSET? (0xb000 + ((function>>1) * 0x28) + ((function&1) \ 60 (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
61 * 0xa0)) : (0x1400 + (function * 0x28))) 61 ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
62#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ 62#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
63 (IS_E1H_OFFSET? (0xb008 + ((function>>1) * 0x28) + ((function&1) \ 63 (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
64 * 0xa0)) : (0x1408 + (function * 0x28))) 64 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
65#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ 65#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
66 (IS_E1H_OFFSET? (0x2b80 + (function * 0x8)) : (0x4b68 + \ 66 (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \
67 (function * 0x8))) 67 (function * 0x8)))
68#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \ 68#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
69 (IS_E1H_OFFSET? (0x3000 + (function * 0x38)) : (0x1500 + \ 69 (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \
70 (function * 0x38))) 70 (function * 0x38)))
71#define TSTORM_FUNCTION_MODE_OFFSET \ 71#define TSTORM_FUNCTION_MODE_OFFSET \
72 (IS_E1H_OFFSET? 0x1ad0 : 0xffffffff) 72 (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff)
73#define TSTORM_HC_BTR_OFFSET(port) \ 73#define TSTORM_HC_BTR_OFFSET(port) \
74 (IS_E1H_OFFSET? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18))) 74 (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
75#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \ 75#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
76 (IS_E1H_OFFSET? (0x12c8 + (function * 0x80)) : (0x22c8 + \ 76 (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
77 (function * 0x80))) 77 (function * 0x80)))
78#define TSTORM_INDIRECTION_TABLE_SIZE 0x80 78#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
79#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \ 79#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
80 (IS_E1H_OFFSET? (0x3008 + (function * 0x38)) : (0x1508 + \ 80 (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \
81 (function * 0x38))) 81 (function * 0x38)))
82#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
83 (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
84 0x50)) : (0x4000 + (port * 0x3f0) + (stats_counter_id * 0x38)))
82#define TSTORM_RX_PRODS_OFFSET(port, client_id) \ 85#define TSTORM_RX_PRODS_OFFSET(port, client_id) \
83 (IS_E1H_OFFSET? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) : \ 86 (IS_E1H_OFFSET ? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) \
84 (0x9c0 + (port * 0x2f8) + (client_id * 0x28))) 87 : (0x9c0 + (port * 0x2f8) + (client_id * 0x28)))
85#define TSTORM_STATS_FLAGS_OFFSET(function) \ 88#define TSTORM_STATS_FLAGS_OFFSET(function) \
86 (IS_E1H_OFFSET? (0x2c00 + (function * 0x8)) : (0x4b88 + \ 89 (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
87 (function * 0x8))) 90 (function * 0x8)))
88#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET? 0x3b30 : 0x1c20) 91#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3b30 : 0x1c20)
89#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET? 0xa040 : 0x2c10) 92#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
90#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET? 0x2440 : 0x1200) 93#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
91#define USTORM_ASSERT_LIST_INDEX_OFFSET \ 94#define USTORM_ASSERT_LIST_INDEX_OFFSET \
92 (IS_E1H_OFFSET? 0x8000 : 0x1000) 95 (IS_E1H_OFFSET ? 0x8000 : 0x1000)
93#define USTORM_ASSERT_LIST_OFFSET(idx) \ 96#define USTORM_ASSERT_LIST_OFFSET(idx) \
94 (IS_E1H_OFFSET? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 97 (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
95#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \ 98#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
96 (IS_E1H_OFFSET? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \ 99 (IS_E1H_OFFSET ? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \
97 (0x5450 + (port * 0x1c8) + (clientId * 0x18))) 100 (0x5450 + (port * 0x1c8) + (clientId * 0x18)))
98#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 101#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
99 (IS_E1H_OFFSET? (0x951a + ((function>>1) * 0x28) + ((function&1) \ 102 (IS_E1H_OFFSET ? (0x951a + ((function>>1) * 0x28) + \
100 * 0xa0) + (index * 0x4)) : (0x191a + (function * 0x28) + (index * \ 103 ((function&1) * 0xa0) + (index * 0x4)) : (0x191a + (function * \
101 0x4))) 104 0x28) + (index * 0x4)))
102#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ 105#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
103 (IS_E1H_OFFSET? (0x9500 + ((function>>1) * 0x28) + ((function&1) \ 106 (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x28) + \
104 * 0xa0)) : (0x1900 + (function * 0x28))) 107 ((function&1) * 0xa0)) : (0x1900 + (function * 0x28)))
105#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ 108#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
106 (IS_E1H_OFFSET? (0x9508 + ((function>>1) * 0x28) + ((function&1) \ 109 (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x28) + \
107 * 0xa0)) : (0x1908 + (function * 0x28))) 110 ((function&1) * 0xa0)) : (0x1908 + (function * 0x28)))
108#define USTORM_FUNCTION_MODE_OFFSET \ 111#define USTORM_FUNCTION_MODE_OFFSET \
109 (IS_E1H_OFFSET? 0x2448 : 0xffffffff) 112 (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
110#define USTORM_HC_BTR_OFFSET(port) \ 113#define USTORM_HC_BTR_OFFSET(port) \
111 (IS_E1H_OFFSET? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8))) 114 (IS_E1H_OFFSET ? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8)))
112#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \ 115#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
113 (IS_E1H_OFFSET? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \ 116 (IS_E1H_OFFSET ? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \
114 (0x5448 + (port * 0x1c8) + (clientId * 0x18))) 117 (0x5448 + (port * 0x1c8) + (clientId * 0x18)))
115#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \ 118#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
116 (IS_E1H_OFFSET? (0x2408 + (function * 0x8)) : (0x5408 + \ 119 (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5408 + \
117 (function * 0x8))) 120 (function * 0x8)))
118#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ 121#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
119 (IS_E1H_OFFSET? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \ 122 (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
120 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ 123 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
121 (index * 0x4))) 124 (index * 0x4)))
122#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ 125#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
123 (IS_E1H_OFFSET? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \ 126 (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
124 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ 127 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
125 (index * 0x4))) 128 (index * 0x4)))
126#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ 129#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
127 (IS_E1H_OFFSET? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \ 130 (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
128 (0x1400 + (port * 0x280) + (cpu_id * 0x28))) 131 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
129#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ 132#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
130 (IS_E1H_OFFSET? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \ 133 (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
131 (0x1408 + (port * 0x280) + (cpu_id * 0x28))) 134 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
132#define XSTORM_ASSERT_LIST_INDEX_OFFSET \ 135#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
133 (IS_E1H_OFFSET? 0x9000 : 0x1000) 136 (IS_E1H_OFFSET ? 0x9000 : 0x1000)
134#define XSTORM_ASSERT_LIST_OFFSET(idx) \ 137#define XSTORM_ASSERT_LIST_OFFSET(idx) \
135 (IS_E1H_OFFSET? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 138 (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
136#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \ 139#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
137 (IS_E1H_OFFSET? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40))) 140 (IS_E1H_OFFSET ? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40)))
138#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 141#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
139 (IS_E1H_OFFSET? (0xa01a + ((function>>1) * 0x28) + ((function&1) \ 142 (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
140 * 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \ 143 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
141 0x4))) 144 0x28) + (index * 0x4)))
142#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ 145#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
143 (IS_E1H_OFFSET? (0xa000 + ((function>>1) * 0x28) + ((function&1) \ 146 (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
144 * 0xa0)) : (0x1400 + (function * 0x28))) 147 ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
145#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ 148#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
146 (IS_E1H_OFFSET? (0xa008 + ((function>>1) * 0x28) + ((function&1) \ 149 (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
147 * 0xa0)) : (0x1408 + (function * 0x28))) 150 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
148#define XSTORM_E1HOV_OFFSET(function) \ 151#define XSTORM_E1HOV_OFFSET(function) \
149 (IS_E1H_OFFSET? (0x2ab8 + (function * 0x2)) : 0xffffffff) 152 (IS_E1H_OFFSET ? (0x2ab8 + (function * 0x2)) : 0xffffffff)
150#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ 153#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
151 (IS_E1H_OFFSET? (0x2418 + (function * 0x8)) : (0x3b70 + \ 154 (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
152 (function * 0x8))) 155 (function * 0x8)))
153#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \ 156#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
154 (IS_E1H_OFFSET? (0x2568 + (function * 0x70)) : (0x3c60 + \ 157 (IS_E1H_OFFSET ? (0x2568 + (function * 0x70)) : (0x3c60 + \
155 (function * 0x70))) 158 (function * 0x70)))
156#define XSTORM_FUNCTION_MODE_OFFSET \ 159#define XSTORM_FUNCTION_MODE_OFFSET \
157 (IS_E1H_OFFSET? 0x2ac8 : 0xffffffff) 160 (IS_E1H_OFFSET ? 0x2ac8 : 0xffffffff)
158#define XSTORM_HC_BTR_OFFSET(port) \ 161#define XSTORM_HC_BTR_OFFSET(port) \
159 (IS_E1H_OFFSET? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) 162 (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
163#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
164 (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
165 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
160#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \ 166#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
161 (IS_E1H_OFFSET? (0x2528 + (function * 0x70)) : (0x3c20 + \ 167 (IS_E1H_OFFSET ? (0x2528 + (function * 0x70)) : (0x3c20 + \
162 (function * 0x70))) 168 (function * 0x70)))
163#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \ 169#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
164 (IS_E1H_OFFSET? (0x2000 + (function * 0x10)) : (0x3328 + \ 170 (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
165 (function * 0x10))) 171 (function * 0x10)))
166#define XSTORM_SPQ_PROD_OFFSET(function) \ 172#define XSTORM_SPQ_PROD_OFFSET(function) \
167 (IS_E1H_OFFSET? (0x2008 + (function * 0x10)) : (0x3330 + \ 173 (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
168 (function * 0x10))) 174 (function * 0x10)))
169#define XSTORM_STATS_FLAGS_OFFSET(function) \ 175#define XSTORM_STATS_FLAGS_OFFSET(function) \
170 (IS_E1H_OFFSET? (0x23d8 + (function * 0x8)) : (0x3b60 + \ 176 (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \
171 (function * 0x8))) 177 (function * 0x8)))
172#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 178#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
173 179
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
index d3e8198d7dba..efd764427fa1 100644
--- a/drivers/net/bnx2x_hsi.h
+++ b/drivers/net/bnx2x_hsi.h
@@ -1268,7 +1268,7 @@ struct doorbell {
1268 1268
1269 1269
1270/* 1270/*
1271 * IGU driver acknowlegement register 1271 * IGU driver acknowledgement register
1272 */ 1272 */
1273struct igu_ack_register { 1273struct igu_ack_register {
1274#if defined(__BIG_ENDIAN) 1274#if defined(__BIG_ENDIAN)
@@ -1882,7 +1882,7 @@ struct timers_block_context {
1882}; 1882};
1883 1883
1884/* 1884/*
1885 * structure for easy accessability to assembler 1885 * structure for easy accessibility to assembler
1886 */ 1886 */
1887struct eth_tx_bd_flags { 1887struct eth_tx_bd_flags {
1888 u8 as_bitfield; 1888 u8 as_bitfield;
@@ -2044,7 +2044,7 @@ struct eth_context {
2044 2044
2045 2045
2046/* 2046/*
2047 * ethernet doorbell 2047 * Ethernet doorbell
2048 */ 2048 */
2049struct eth_tx_doorbell { 2049struct eth_tx_doorbell {
2050#if defined(__BIG_ENDIAN) 2050#if defined(__BIG_ENDIAN)
@@ -2256,7 +2256,7 @@ struct ramrod_data {
2256}; 2256};
2257 2257
2258/* 2258/*
2259 * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits) 2259 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2260 */ 2260 */
2261union eth_ramrod_data { 2261union eth_ramrod_data {
2262 struct ramrod_data general; 2262 struct ramrod_data general;
@@ -2330,7 +2330,7 @@ struct spe_hdr {
2330}; 2330};
2331 2331
2332/* 2332/*
2333 * ethernet slow path element 2333 * Ethernet slow path element
2334 */ 2334 */
2335union eth_specific_data { 2335union eth_specific_data {
2336 u8 protocol_data[8]; 2336 u8 protocol_data[8];
@@ -2343,7 +2343,7 @@ union eth_specific_data {
2343}; 2343};
2344 2344
2345/* 2345/*
2346 * ethernet slow path element 2346 * Ethernet slow path element
2347 */ 2347 */
2348struct eth_spe { 2348struct eth_spe {
2349 struct spe_hdr hdr; 2349 struct spe_hdr hdr;
@@ -2615,7 +2615,7 @@ struct tstorm_eth_rx_producers {
2615 2615
2616 2616
2617/* 2617/*
2618 * common flag to indicate existance of TPA. 2618 * common flag to indicate existence of TPA.
2619 */ 2619 */
2620struct tstorm_eth_tpa_exist { 2620struct tstorm_eth_tpa_exist {
2621#if defined(__BIG_ENDIAN) 2621#if defined(__BIG_ENDIAN)
@@ -2765,7 +2765,7 @@ struct tstorm_common_stats {
2765}; 2765};
2766 2766
2767/* 2767/*
2768 * Eth statistics query sturcture for the eth_stats_quesry ramrod 2768 * Eth statistics query structure for the eth_stats_query ramrod
2769 */ 2769 */
2770struct eth_stats_query { 2770struct eth_stats_query {
2771 struct xstorm_common_stats xstorm_common; 2771 struct xstorm_common_stats xstorm_common;
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 4c7750789b62..130927cfc75b 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -72,26 +72,26 @@
72 72
73 73
74struct raw_op { 74struct raw_op {
75 u32 op :8; 75 u32 op:8;
76 u32 offset :24; 76 u32 offset:24;
77 u32 raw_data; 77 u32 raw_data;
78}; 78};
79 79
80struct op_read { 80struct op_read {
81 u32 op :8; 81 u32 op:8;
82 u32 offset :24; 82 u32 offset:24;
83 u32 pad; 83 u32 pad;
84}; 84};
85 85
86struct op_write { 86struct op_write {
87 u32 op :8; 87 u32 op:8;
88 u32 offset :24; 88 u32 offset:24;
89 u32 val; 89 u32 val;
90}; 90};
91 91
92struct op_string_write { 92struct op_string_write {
93 u32 op :8; 93 u32 op:8;
94 u32 offset :24; 94 u32 offset:24;
95#ifdef __LITTLE_ENDIAN 95#ifdef __LITTLE_ENDIAN
96 u16 data_off; 96 u16 data_off;
97 u16 data_len; 97 u16 data_len;
@@ -102,8 +102,8 @@ struct op_string_write {
102}; 102};
103 103
104struct op_zero { 104struct op_zero {
105 u32 op :8; 105 u32 op:8;
106 u32 offset :24; 106 u32 offset:24;
107 u32 len; 107 u32 len;
108}; 108};
109 109
@@ -208,7 +208,7 @@ static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
208/********************************************************* 208/*********************************************************
209 There are different blobs for each PRAM section. 209 There are different blobs for each PRAM section.
210 In addition, each blob write operation is divided into a few operations 210 In addition, each blob write operation is divided into a few operations
211 in order to decrease the amount of phys. contigious buffer needed. 211 in order to decrease the amount of phys. contiguous buffer needed.
212 Thus, when we select a blob the address may be with some offset 212 Thus, when we select a blob the address may be with some offset
213 from the beginning of PRAM section. 213 from the beginning of PRAM section.
214 The same holds for the INT_TABLE sections. 214 The same holds for the INT_TABLE sections.
@@ -336,7 +336,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
336 len = op->str_wr.data_len; 336 len = op->str_wr.data_len;
337 data = data_base + op->str_wr.data_off; 337 data = data_base + op->str_wr.data_off;
338 338
339 /* carefull! it must be in order */ 339 /* careful! it must be in order */
340 if (unlikely(op_type > OP_WB)) { 340 if (unlikely(op_type > OP_WB)) {
341 341
342 /* If E1 only */ 342 /* If E1 only */
@@ -740,7 +740,7 @@ static u8 calc_crc8(u32 data, u8 crc)
740 return crc_res; 740 return crc_res;
741} 741}
742 742
743/* regiesers addresses are not in order 743/* registers addresses are not in order
744 so these arrays help simplify the code */ 744 so these arrays help simplify the code */
745static const int cm_start[E1H_FUNC_MAX][9] = { 745static const int cm_start[E1H_FUNC_MAX][9] = {
746 {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START, 746 {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START,
diff --git a/drivers/net/bnx2x_init_values.h b/drivers/net/bnx2x_init_values.h
index 63019055e4bb..9755bf6b08dd 100644
--- a/drivers/net/bnx2x_init_values.h
+++ b/drivers/net/bnx2x_init_values.h
@@ -901,31 +901,28 @@ static const struct raw_op init_ops[] = {
901 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3760, 0x4}, 901 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3760, 0x4},
902 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1e20, 0x42}, 902 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1e20, 0x42},
903 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3738, 0x9}, 903 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3738, 0x9},
904 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x400}, 904 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2},
905 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3738 + 0x24, 0x10293}, 905 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3738 + 0x24, 0x10293},
906 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c00, 0x2}, 906 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x20278},
907 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x42}, 907 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x42},
908 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2c00 + 0x8, 0x20278}, 908 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2},
909 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400}, 909 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400},
910 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2}, 910 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027a},
911 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000, 0x2}, 911 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000, 0x2},
912 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x2027a},
913 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x20294}, 912 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x20294},
914 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2},
915 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b68, 0x2}, 913 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b68, 0x2},
916 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027c},
917 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x20296}, 914 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x20296},
918 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b10, 0x2}, 915 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b10, 0x2},
919 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x20298}, 916 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x20298},
920 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, 917 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
921 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027e}, 918 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027c},
922 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x10029a}, 919 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x10029a},
923 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0}, 920 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
924 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x10028e}, 921 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x10028c},
925 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002aa}, 922 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002aa},
926 {OP_ZP_E1, USEM_REG_INT_TABLE, 0xc20000}, 923 {OP_ZP_E1, USEM_REG_INT_TABLE, 0xc20000},
927 {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xc40000}, 924 {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xc40000},
928 {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029e}, 925 {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029c},
929 {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x368, 0x1302ba}, 926 {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x368, 0x1302ba},
930 {OP_ZP_E1, USEM_REG_PRAM, 0x311c0000}, 927 {OP_ZP_E1, USEM_REG_PRAM, 0x311c0000},
931 {OP_ZP_E1H, USEM_REG_PRAM, 0x31070000}, 928 {OP_ZP_E1H, USEM_REG_PRAM, 0x31070000},
@@ -933,11 +930,11 @@ static const struct raw_op init_ops[] = {
933 {OP_ZP_E1H, USEM_REG_PRAM + 0x8000, 0x330e0c42}, 930 {OP_ZP_E1H, USEM_REG_PRAM + 0x8000, 0x330e0c42},
934 {OP_ZP_E1, USEM_REG_PRAM + 0x10000, 0x38561919}, 931 {OP_ZP_E1, USEM_REG_PRAM + 0x10000, 0x38561919},
935 {OP_ZP_E1H, USEM_REG_PRAM + 0x10000, 0x389b1906}, 932 {OP_ZP_E1H, USEM_REG_PRAM + 0x10000, 0x389b1906},
936 {OP_WR_64_E1, USEM_REG_PRAM + 0x17fe0, 0x500402a0}, 933 {OP_WR_64_E1, USEM_REG_PRAM + 0x17fe0, 0x5004029e},
937 {OP_ZP_E1H, USEM_REG_PRAM + 0x18000, 0x132272d}, 934 {OP_ZP_E1H, USEM_REG_PRAM + 0x18000, 0x132272d},
938 {OP_WR_64_E1H, USEM_REG_PRAM + 0x18250, 0x4fb602bc}, 935 {OP_WR_64_E1H, USEM_REG_PRAM + 0x18250, 0x4fb602bc},
939#define USEM_COMMON_END 790 936#define USEM_COMMON_END 787
940#define USEM_PORT0_START 790 937#define USEM_PORT0_START 787
941 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1400, 0xa0}, 938 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1400, 0xa0},
942 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9000, 0xa0}, 939 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9000, 0xa0},
943 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0xa}, 940 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0xa},
@@ -950,44 +947,27 @@ static const struct raw_op init_ops[] = {
950 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3288, 0x96}, 947 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3288, 0x96},
951 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5440, 0x72}, 948 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5440, 0x72},
952 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x20}, 949 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x20},
953 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x20}, 950 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52},
954 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5100, 0x20}, 951 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5100, 0x20},
955 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3100, 0x20}, 952 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc},
956 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5200, 0x20}, 953 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5200, 0x20},
957 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3200, 0x20},
958 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5300, 0x20}, 954 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5300, 0x20},
959 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3300, 0x20},
960 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5400, 0x20}, 955 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5400, 0x20},
961 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3400, 0x20},
962 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5500, 0x20}, 956 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5500, 0x20},
963 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3500, 0x20},
964 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5600, 0x20}, 957 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5600, 0x20},
965 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3600, 0x20},
966 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5700, 0x20}, 958 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5700, 0x20},
967 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3700, 0x20},
968 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5800, 0x20}, 959 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5800, 0x20},
969 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3800, 0x20},
970 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5900, 0x20}, 960 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5900, 0x20},
971 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3900, 0x20},
972 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a00, 0x20}, 961 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a00, 0x20},
973 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a00, 0x20},
974 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b00, 0x20}, 962 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b00, 0x20},
975 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b00, 0x20},
976 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c00, 0x20}, 963 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c00, 0x20},
977 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c00, 0x20},
978 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d00, 0x20}, 964 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d00, 0x20},
979 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d00, 0x20},
980 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e00, 0x20}, 965 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e00, 0x20},
981 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e00, 0x20},
982 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f00, 0x20}, 966 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f00, 0x20},
983 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f00, 0x20},
984 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b78, 0x52}, 967 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b78, 0x52},
985 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c10, 0x2},
986 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e08, 0xc}, 968 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e08, 0xc},
987 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52}, 969#define USEM_PORT0_END 818
988 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc}, 970#define USEM_PORT1_START 818
989#define USEM_PORT0_END 838
990#define USEM_PORT1_START 838
991 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1680, 0xa0}, 971 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1680, 0xa0},
992 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9280, 0xa0}, 972 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9280, 0xa0},
993 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1928, 0xa}, 973 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1928, 0xa},
@@ -1000,76 +980,59 @@ static const struct raw_op init_ops[] = {
1000 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x34e0, 0x96}, 980 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x34e0, 0x96},
1001 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5608, 0x72}, 981 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5608, 0x72},
1002 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5080, 0x20}, 982 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5080, 0x20},
1003 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3080, 0x20}, 983 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52},
1004 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5180, 0x20}, 984 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5180, 0x20},
1005 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3180, 0x20}, 985 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc},
1006 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5280, 0x20}, 986 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5280, 0x20},
1007 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3280, 0x20},
1008 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5380, 0x20}, 987 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5380, 0x20},
1009 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3380, 0x20},
1010 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5480, 0x20}, 988 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5480, 0x20},
1011 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3480, 0x20},
1012 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5580, 0x20}, 989 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5580, 0x20},
1013 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3580, 0x20},
1014 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5680, 0x20}, 990 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5680, 0x20},
1015 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3680, 0x20},
1016 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5780, 0x20}, 991 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5780, 0x20},
1017 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3780, 0x20},
1018 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5880, 0x20}, 992 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5880, 0x20},
1019 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3880, 0x20},
1020 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5980, 0x20}, 993 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5980, 0x20},
1021 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3980, 0x20},
1022 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a80, 0x20}, 994 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a80, 0x20},
1023 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a80, 0x20},
1024 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b80, 0x20}, 995 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b80, 0x20},
1025 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b80, 0x20},
1026 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c80, 0x20}, 996 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c80, 0x20},
1027 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c80, 0x20},
1028 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d80, 0x20}, 997 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d80, 0x20},
1029 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d80, 0x20},
1030 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e80, 0x20}, 998 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e80, 0x20},
1031 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e80, 0x20},
1032 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f80, 0x20}, 999 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f80, 0x20},
1033 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f80, 0x20},
1034 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52}, 1000 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52},
1035 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c20, 0x2},
1036 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e38, 0xc}, 1001 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e38, 0xc},
1037 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52}, 1002#define USEM_PORT1_END 849
1038 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc}, 1003#define USEM_FUNC0_START 849
1039#define USEM_PORT1_END 886
1040#define USEM_FUNC0_START 886
1041 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3000, 0x4}, 1004 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3000, 0x4},
1042 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4010, 0x2}, 1005 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4010, 0x2},
1043#define USEM_FUNC0_END 888 1006#define USEM_FUNC0_END 851
1044#define USEM_FUNC1_START 888 1007#define USEM_FUNC1_START 851
1045 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3010, 0x4}, 1008 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3010, 0x4},
1046 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4020, 0x2}, 1009 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4020, 0x2},
1047#define USEM_FUNC1_END 890 1010#define USEM_FUNC1_END 853
1048#define USEM_FUNC2_START 890 1011#define USEM_FUNC2_START 853
1049 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3020, 0x4}, 1012 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3020, 0x4},
1050 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4030, 0x2}, 1013 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4030, 0x2},
1051#define USEM_FUNC2_END 892 1014#define USEM_FUNC2_END 855
1052#define USEM_FUNC3_START 892 1015#define USEM_FUNC3_START 855
1053 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3030, 0x4}, 1016 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3030, 0x4},
1054 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4040, 0x2}, 1017 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4040, 0x2},
1055#define USEM_FUNC3_END 894 1018#define USEM_FUNC3_END 857
1056#define USEM_FUNC4_START 894 1019#define USEM_FUNC4_START 857
1057 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3040, 0x4}, 1020 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3040, 0x4},
1058 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4050, 0x2}, 1021 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4050, 0x2},
1059#define USEM_FUNC4_END 896 1022#define USEM_FUNC4_END 859
1060#define USEM_FUNC5_START 896 1023#define USEM_FUNC5_START 859
1061 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3050, 0x4}, 1024 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3050, 0x4},
1062 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4060, 0x2}, 1025 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4060, 0x2},
1063#define USEM_FUNC5_END 898 1026#define USEM_FUNC5_END 861
1064#define USEM_FUNC6_START 898 1027#define USEM_FUNC6_START 861
1065 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3060, 0x4}, 1028 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3060, 0x4},
1066 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4070, 0x2}, 1029 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4070, 0x2},
1067#define USEM_FUNC6_END 900 1030#define USEM_FUNC6_END 863
1068#define USEM_FUNC7_START 900 1031#define USEM_FUNC7_START 863
1069 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3070, 0x4}, 1032 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3070, 0x4},
1070 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4080, 0x2}, 1033 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4080, 0x2},
1071#define USEM_FUNC7_END 902 1034#define USEM_FUNC7_END 865
1072#define CSEM_COMMON_START 902 1035#define CSEM_COMMON_START 865
1073 {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0}, 1036 {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
1074 {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0}, 1037 {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
1075 {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0}, 1038 {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
@@ -1128,29 +1091,29 @@ static const struct raw_op init_ops[] = {
1128 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0}, 1091 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0},
1129 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240}, 1092 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240},
1130 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0}, 1093 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0},
1131 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a2}, 1094 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a0},
1132 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4070, 0x80}, 1095 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4070, 0x80},
1133 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x5280, 0x4}, 1096 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x5280, 0x4},
1134 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6280, 0x240}, 1097 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6280, 0x240},
1135 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x6b88, 0x2002be}, 1098 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x6b88, 0x2002be},
1136 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff}, 1099 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
1137 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002aa}, 1100 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002a8},
1138 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002de}, 1101 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002de},
1139 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0}, 1102 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
1140 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ba}, 1103 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002b8},
1141 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ee}, 1104 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ee},
1142 {OP_ZP_E1, CSEM_REG_INT_TABLE, 0x6e0000}, 1105 {OP_ZP_E1, CSEM_REG_INT_TABLE, 0x6e0000},
1143 {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x6f0000}, 1106 {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x6f0000},
1144 {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002ca}, 1107 {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002c8},
1145 {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x1002fe}, 1108 {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x1002fe},
1146 {OP_ZP_E1, CSEM_REG_PRAM, 0x32580000}, 1109 {OP_ZP_E1, CSEM_REG_PRAM, 0x32580000},
1147 {OP_ZP_E1H, CSEM_REG_PRAM, 0x31fa0000}, 1110 {OP_ZP_E1H, CSEM_REG_PRAM, 0x31fa0000},
1148 {OP_ZP_E1, CSEM_REG_PRAM + 0x8000, 0x18270c96}, 1111 {OP_ZP_E1, CSEM_REG_PRAM + 0x8000, 0x18270c96},
1149 {OP_ZP_E1H, CSEM_REG_PRAM + 0x8000, 0x19040c7f}, 1112 {OP_ZP_E1H, CSEM_REG_PRAM + 0x8000, 0x19040c7f},
1150 {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402cc}, 1113 {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402ca},
1151 {OP_WR_64_E1H, CSEM_REG_PRAM + 0xb430, 0x67e00300}, 1114 {OP_WR_64_E1H, CSEM_REG_PRAM + 0xb430, 0x67e00300},
1152#define CSEM_COMMON_END 981 1115#define CSEM_COMMON_END 944
1153#define CSEM_PORT0_START 981 1116#define CSEM_PORT0_START 944
1154 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0}, 1117 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0},
1155 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8000, 0xa0}, 1118 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8000, 0xa0},
1156 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1900, 0x10}, 1119 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1900, 0x10},
@@ -1163,8 +1126,8 @@ static const struct raw_op init_ops[] = {
1163 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6040, 0x30}, 1126 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6040, 0x30},
1164 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3040, 0x6}, 1127 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3040, 0x6},
1165 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2410, 0x30}, 1128 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2410, 0x30},
1166#define CSEM_PORT0_END 993 1129#define CSEM_PORT0_END 956
1167#define CSEM_PORT1_START 993 1130#define CSEM_PORT1_START 956
1168 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0}, 1131 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0},
1169 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8280, 0xa0}, 1132 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8280, 0xa0},
1170 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1940, 0x10}, 1133 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1940, 0x10},
@@ -1177,43 +1140,43 @@ static const struct raw_op init_ops[] = {
1177 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6100, 0x30}, 1140 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6100, 0x30},
1178 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3058, 0x6}, 1141 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3058, 0x6},
1179 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30}, 1142 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30},
1180#define CSEM_PORT1_END 1005 1143#define CSEM_PORT1_END 968
1181#define CSEM_FUNC0_START 1005 1144#define CSEM_FUNC0_START 968
1182 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1148, 0x0}, 1145 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1148, 0x0},
1183 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3300, 0x2}, 1146 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3300, 0x2},
1184#define CSEM_FUNC0_END 1007 1147#define CSEM_FUNC0_END 970
1185#define CSEM_FUNC1_START 1007 1148#define CSEM_FUNC1_START 970
1186 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x114c, 0x0}, 1149 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x114c, 0x0},
1187 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3308, 0x2}, 1150 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3308, 0x2},
1188#define CSEM_FUNC1_END 1009 1151#define CSEM_FUNC1_END 972
1189#define CSEM_FUNC2_START 1009 1152#define CSEM_FUNC2_START 972
1190 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1150, 0x0}, 1153 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1150, 0x0},
1191 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3310, 0x2}, 1154 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3310, 0x2},
1192#define CSEM_FUNC2_END 1011 1155#define CSEM_FUNC2_END 974
1193#define CSEM_FUNC3_START 1011 1156#define CSEM_FUNC3_START 974
1194 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1154, 0x0}, 1157 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1154, 0x0},
1195 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3318, 0x2}, 1158 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3318, 0x2},
1196#define CSEM_FUNC3_END 1013 1159#define CSEM_FUNC3_END 976
1197#define CSEM_FUNC4_START 1013 1160#define CSEM_FUNC4_START 976
1198 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1158, 0x0}, 1161 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1158, 0x0},
1199 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3320, 0x2}, 1162 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3320, 0x2},
1200#define CSEM_FUNC4_END 1015 1163#define CSEM_FUNC4_END 978
1201#define CSEM_FUNC5_START 1015 1164#define CSEM_FUNC5_START 978
1202 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x115c, 0x0}, 1165 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x115c, 0x0},
1203 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3328, 0x2}, 1166 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3328, 0x2},
1204#define CSEM_FUNC5_END 1017 1167#define CSEM_FUNC5_END 980
1205#define CSEM_FUNC6_START 1017 1168#define CSEM_FUNC6_START 980
1206 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1160, 0x0}, 1169 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1160, 0x0},
1207 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3330, 0x2}, 1170 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3330, 0x2},
1208#define CSEM_FUNC6_END 1019 1171#define CSEM_FUNC6_END 982
1209#define CSEM_FUNC7_START 1019 1172#define CSEM_FUNC7_START 982
1210 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1164, 0x0}, 1173 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1164, 0x0},
1211 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3338, 0x2}, 1174 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3338, 0x2},
1212#define CSEM_FUNC7_END 1021 1175#define CSEM_FUNC7_END 984
1213#define XPB_COMMON_START 1021 1176#define XPB_COMMON_START 984
1214 {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20}, 1177 {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20},
1215#define XPB_COMMON_END 1022 1178#define XPB_COMMON_END 985
1216#define DQ_COMMON_START 1022 1179#define DQ_COMMON_START 985
1217 {OP_WR, DORQ_REG_MODE_ACT, 0x2}, 1180 {OP_WR, DORQ_REG_MODE_ACT, 0x2},
1218 {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3}, 1181 {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
1219 {OP_WR, DORQ_REG_OUTST_REQ, 0x4}, 1182 {OP_WR, DORQ_REG_OUTST_REQ, 0x4},
@@ -1232,8 +1195,8 @@ static const struct raw_op init_ops[] = {
1232 {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c}, 1195 {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
1233 {OP_WR, DORQ_REG_REGN, 0x7c1004}, 1196 {OP_WR, DORQ_REG_REGN, 0x7c1004},
1234 {OP_WR, DORQ_REG_IF_EN, 0xf}, 1197 {OP_WR, DORQ_REG_IF_EN, 0xf},
1235#define DQ_COMMON_END 1040 1198#define DQ_COMMON_END 1003
1236#define TIMERS_COMMON_START 1040 1199#define TIMERS_COMMON_START 1003
1237 {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2}, 1200 {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
1238 {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c}, 1201 {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
1239 {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1}, 1202 {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
@@ -1256,14 +1219,14 @@ static const struct raw_op init_ops[] = {
1256 {OP_WR, TM_REG_EN_CL0_INPUT, 0x1}, 1219 {OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
1257 {OP_WR, TM_REG_EN_CL1_INPUT, 0x1}, 1220 {OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
1258 {OP_WR, TM_REG_EN_CL2_INPUT, 0x1}, 1221 {OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
1259#define TIMERS_COMMON_END 1062 1222#define TIMERS_COMMON_END 1025
1260#define TIMERS_PORT0_START 1062 1223#define TIMERS_PORT0_START 1025
1261 {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2}, 1224 {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
1262#define TIMERS_PORT0_END 1063 1225#define TIMERS_PORT0_END 1026
1263#define TIMERS_PORT1_START 1063 1226#define TIMERS_PORT1_START 1026
1264 {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2}, 1227 {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
1265#define TIMERS_PORT1_END 1064 1228#define TIMERS_PORT1_END 1027
1266#define XSDM_COMMON_START 1064 1229#define XSDM_COMMON_START 1027
1267 {OP_WR_E1, XSDM_REG_CFC_RSP_START_ADDR, 0x614}, 1230 {OP_WR_E1, XSDM_REG_CFC_RSP_START_ADDR, 0x614},
1268 {OP_WR_E1H, XSDM_REG_CFC_RSP_START_ADDR, 0x424}, 1231 {OP_WR_E1H, XSDM_REG_CFC_RSP_START_ADDR, 0x424},
1269 {OP_WR_E1, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600}, 1232 {OP_WR_E1, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600},
@@ -1311,8 +1274,8 @@ static const struct raw_op init_ops[] = {
1311 {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8}, 1274 {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8},
1312 {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1}, 1275 {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1},
1313 {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa}, 1276 {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa},
1314#define XSDM_COMMON_END 1111 1277#define XSDM_COMMON_END 1074
1315#define QM_COMMON_START 1111 1278#define QM_COMMON_START 1074
1316 {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6}, 1279 {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
1317 {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5}, 1280 {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
1318 {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa}, 1281 {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
@@ -1613,8 +1576,8 @@ static const struct raw_op init_ops[] = {
1613 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_6, 0x5}, 1576 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_6, 0x5},
1614 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_7, 0x7}, 1577 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_7, 0x7},
1615 {OP_WR, QM_REG_CMINTEN, 0xff}, 1578 {OP_WR, QM_REG_CMINTEN, 0xff},
1616#define QM_COMMON_END 1411 1579#define QM_COMMON_END 1374
1617#define PBF_COMMON_START 1411 1580#define PBF_COMMON_START 1374
1618 {OP_WR, PBF_REG_INIT, 0x1}, 1581 {OP_WR, PBF_REG_INIT, 0x1},
1619 {OP_WR, PBF_REG_INIT_P4, 0x1}, 1582 {OP_WR, PBF_REG_INIT_P4, 0x1},
1620 {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1}, 1583 {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
@@ -1622,20 +1585,20 @@ static const struct raw_op init_ops[] = {
1622 {OP_WR, PBF_REG_INIT_P4, 0x0}, 1585 {OP_WR, PBF_REG_INIT_P4, 0x0},
1623 {OP_WR, PBF_REG_INIT, 0x0}, 1586 {OP_WR, PBF_REG_INIT, 0x0},
1624 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0}, 1587 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
1625#define PBF_COMMON_END 1418 1588#define PBF_COMMON_END 1381
1626#define PBF_PORT0_START 1418 1589#define PBF_PORT0_START 1381
1627 {OP_WR, PBF_REG_INIT_P0, 0x1}, 1590 {OP_WR, PBF_REG_INIT_P0, 0x1},
1628 {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1}, 1591 {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
1629 {OP_WR, PBF_REG_INIT_P0, 0x0}, 1592 {OP_WR, PBF_REG_INIT_P0, 0x0},
1630 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0}, 1593 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
1631#define PBF_PORT0_END 1422 1594#define PBF_PORT0_END 1385
1632#define PBF_PORT1_START 1422 1595#define PBF_PORT1_START 1385
1633 {OP_WR, PBF_REG_INIT_P1, 0x1}, 1596 {OP_WR, PBF_REG_INIT_P1, 0x1},
1634 {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1}, 1597 {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
1635 {OP_WR, PBF_REG_INIT_P1, 0x0}, 1598 {OP_WR, PBF_REG_INIT_P1, 0x0},
1636 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0}, 1599 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
1637#define PBF_PORT1_END 1426 1600#define PBF_PORT1_END 1389
1638#define XCM_COMMON_START 1426 1601#define XCM_COMMON_START 1389
1639 {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32}, 1602 {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
1640 {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020}, 1603 {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
1641 {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020}, 1604 {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
@@ -1670,7 +1633,7 @@ static const struct raw_op init_ops[] = {
1670 {OP_WR_E1, XCM_REG_XX_MSG_NUM, 0x1f}, 1633 {OP_WR_E1, XCM_REG_XX_MSG_NUM, 0x1f},
1671 {OP_WR_E1H, XCM_REG_XX_MSG_NUM, 0x20}, 1634 {OP_WR_E1H, XCM_REG_XX_MSG_NUM, 0x20},
1672 {OP_ZR, XCM_REG_XX_TABLE, 0x12}, 1635 {OP_ZR, XCM_REG_XX_TABLE, 0x12},
1673 {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02ce}, 1636 {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02cc},
1674 {OP_SW_E1H, XCM_REG_XX_DESCR_TABLE, 0x1f0302}, 1637 {OP_SW_E1H, XCM_REG_XX_DESCR_TABLE, 0x1f0302},
1675 {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf}, 1638 {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
1676 {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7}, 1639 {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
@@ -1700,8 +1663,8 @@ static const struct raw_op init_ops[] = {
1700 {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1}, 1663 {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
1701 {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1}, 1664 {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
1702 {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1}, 1665 {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
1703#define XCM_COMMON_END 1490 1666#define XCM_COMMON_END 1453
1704#define XCM_PORT0_START 1490 1667#define XCM_PORT0_START 1453
1705 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, 1668 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1706 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, 1669 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1707 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, 1670 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1710,8 +1673,8 @@ static const struct raw_op init_ops[] = {
1710 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD10, 0x2}, 1673 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1711 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, 1674 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1712 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, 1675 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1713#define XCM_PORT0_END 1498 1676#define XCM_PORT0_END 1461
1714#define XCM_PORT1_START 1498 1677#define XCM_PORT1_START 1461
1715 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, 1678 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1716 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, 1679 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1717 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, 1680 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1720,8 +1683,8 @@ static const struct raw_op init_ops[] = {
1720 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD11, 0x2}, 1683 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1721 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, 1684 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1722 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, 1685 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1723#define XCM_PORT1_END 1506 1686#define XCM_PORT1_END 1469
1724#define XCM_FUNC0_START 1506 1687#define XCM_FUNC0_START 1469
1725 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, 1688 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1726 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, 1689 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1727 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, 1690 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1731,8 +1694,8 @@ static const struct raw_op init_ops[] = {
1731 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, 1694 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1732 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, 1695 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1733 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, 1696 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1734#define XCM_FUNC0_END 1515 1697#define XCM_FUNC0_END 1478
1735#define XCM_FUNC1_START 1515 1698#define XCM_FUNC1_START 1478
1736 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, 1699 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1737 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, 1700 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1738 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, 1701 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1742,8 +1705,8 @@ static const struct raw_op init_ops[] = {
1742 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, 1705 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1743 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, 1706 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1744 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, 1707 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1745#define XCM_FUNC1_END 1524 1708#define XCM_FUNC1_END 1487
1746#define XCM_FUNC2_START 1524 1709#define XCM_FUNC2_START 1487
1747 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, 1710 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1748 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, 1711 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1749 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, 1712 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1753,8 +1716,8 @@ static const struct raw_op init_ops[] = {
1753 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, 1716 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1754 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, 1717 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1755 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, 1718 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1756#define XCM_FUNC2_END 1533 1719#define XCM_FUNC2_END 1496
1757#define XCM_FUNC3_START 1533 1720#define XCM_FUNC3_START 1496
1758 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, 1721 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1759 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, 1722 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1760 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, 1723 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1764,8 +1727,8 @@ static const struct raw_op init_ops[] = {
1764 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, 1727 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1765 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, 1728 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1766 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, 1729 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1767#define XCM_FUNC3_END 1542 1730#define XCM_FUNC3_END 1505
1768#define XCM_FUNC4_START 1542 1731#define XCM_FUNC4_START 1505
1769 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, 1732 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1770 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, 1733 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1771 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, 1734 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1775,8 +1738,8 @@ static const struct raw_op init_ops[] = {
1775 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, 1738 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1776 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, 1739 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1777 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, 1740 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1778#define XCM_FUNC4_END 1551 1741#define XCM_FUNC4_END 1514
1779#define XCM_FUNC5_START 1551 1742#define XCM_FUNC5_START 1514
1780 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, 1743 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1781 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, 1744 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1782 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, 1745 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1786,8 +1749,8 @@ static const struct raw_op init_ops[] = {
1786 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, 1749 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1787 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, 1750 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1788 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, 1751 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1789#define XCM_FUNC5_END 1560 1752#define XCM_FUNC5_END 1523
1790#define XCM_FUNC6_START 1560 1753#define XCM_FUNC6_START 1523
1791 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, 1754 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1792 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, 1755 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1793 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, 1756 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1797,8 +1760,8 @@ static const struct raw_op init_ops[] = {
1797 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, 1760 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1798 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, 1761 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1799 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, 1762 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1800#define XCM_FUNC6_END 1569 1763#define XCM_FUNC6_END 1532
1801#define XCM_FUNC7_START 1569 1764#define XCM_FUNC7_START 1532
1802 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, 1765 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1803 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, 1766 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1804 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, 1767 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1808,8 +1771,8 @@ static const struct raw_op init_ops[] = {
1808 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, 1771 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1809 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, 1772 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1810 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, 1773 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1811#define XCM_FUNC7_END 1578 1774#define XCM_FUNC7_END 1541
1812#define XSEM_COMMON_START 1578 1775#define XSEM_COMMON_START 1541
1813 {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0}, 1776 {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
1814 {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0}, 1777 {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
1815 {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0}, 1778 {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
@@ -1876,9 +1839,9 @@ static const struct raw_op init_ops[] = {
1876 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9000, 0x2}, 1839 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9000, 0x2},
1877 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3368, 0x0}, 1840 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3368, 0x0},
1878 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86}, 1841 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86},
1879 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202ed}, 1842 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202eb},
1880 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2000, 0x20}, 1843 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2000, 0x20},
1881 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402ef}, 1844 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402ed},
1882 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0}, 1845 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0},
1883 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1518, 0x1}, 1846 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1518, 0x1},
1884 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20321}, 1847 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20321},
@@ -1886,29 +1849,29 @@ static const struct raw_op init_ops[] = {
1886 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2498, 0x40323}, 1849 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2498, 0x40323},
1887 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1838, 0x0}, 1850 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1838, 0x0},
1888 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ac8, 0x0}, 1851 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ac8, 0x0},
1889 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202f3}, 1852 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202f1},
1890 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ab8, 0x0}, 1853 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ab8, 0x0},
1891 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2}, 1854 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2},
1892 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3010, 0x1}, 1855 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3010, 0x1},
1893 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4}, 1856 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4},
1894 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x4040, 0x10}, 1857 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x4040, 0x10},
1895 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f50, 0x202f5}, 1858 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f50, 0x202f3},
1896 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x4000, 0x100327}, 1859 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x4000, 0x100327},
1897 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2}, 1860 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2},
1898 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4}, 1861 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4},
1899 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x83b0, 0x20337}, 1862 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x83b0, 0x20337},
1900 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0}, 1863 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
1901 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002f7}, 1864 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002f5},
1902 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100339}, 1865 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100339},
1903 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, 1866 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
1904 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80307}, 1867 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80305},
1905 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80349}, 1868 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80349},
1906 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000}, 1869 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
1907 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030f}, 1870 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030d},
1908 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80351}, 1871 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80351},
1909 {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xa90000}, 1872 {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xa90000},
1910 {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xac0000}, 1873 {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xac0000},
1911 {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130317}, 1874 {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130315},
1912 {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x368, 0x130359}, 1875 {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x368, 0x130359},
1913 {OP_ZP_E1, XSEM_REG_PRAM, 0x344e0000}, 1876 {OP_ZP_E1, XSEM_REG_PRAM, 0x344e0000},
1914 {OP_ZP_E1H, XSEM_REG_PRAM, 0x34620000}, 1877 {OP_ZP_E1H, XSEM_REG_PRAM, 0x34620000},
@@ -1918,10 +1881,10 @@ static const struct raw_op init_ops[] = {
1918 {OP_ZP_E1H, XSEM_REG_PRAM + 0x10000, 0x3e971b22}, 1881 {OP_ZP_E1H, XSEM_REG_PRAM + 0x10000, 0x3e971b22},
1919 {OP_ZP_E1, XSEM_REG_PRAM + 0x18000, 0x1dd02ad2}, 1882 {OP_ZP_E1, XSEM_REG_PRAM + 0x18000, 0x1dd02ad2},
1920 {OP_ZP_E1H, XSEM_REG_PRAM + 0x18000, 0x21542ac8}, 1883 {OP_ZP_E1H, XSEM_REG_PRAM + 0x18000, 0x21542ac8},
1921 {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0d0, 0x47e60319}, 1884 {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0d0, 0x47e60317},
1922 {OP_WR_64_E1H, XSEM_REG_PRAM + 0x1c8d0, 0x46e6035b}, 1885 {OP_WR_64_E1H, XSEM_REG_PRAM + 0x1c8d0, 0x46e6035b},
1923#define XSEM_COMMON_END 1688 1886#define XSEM_COMMON_END 1651
1924#define XSEM_PORT0_START 1688 1887#define XSEM_PORT0_START 1651
1925 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x10}, 1888 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x10},
1926 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc000, 0xfc}, 1889 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc000, 0xfc},
1927 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c20, 0x1c}, 1890 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c20, 0x1c},
@@ -1934,7 +1897,7 @@ static const struct raw_op init_ops[] = {
1934 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x26e8, 0x1c}, 1897 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x26e8, 0x1c},
1935 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b58, 0x0}, 1898 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b58, 0x0},
1936 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x27c8, 0x1c}, 1899 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x27c8, 0x1c},
1937 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d10, 0x10031b}, 1900 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d10, 0x100319},
1938 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa000, 0x28}, 1901 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa000, 0x28},
1939 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1500, 0x0}, 1902 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1500, 0x0},
1940 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa140, 0xc}, 1903 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa140, 0xc},
@@ -1950,12 +1913,12 @@ static const struct raw_op init_ops[] = {
1950 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2035d}, 1913 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2035d},
1951 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1}, 1914 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1},
1952 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42}, 1915 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42},
1953 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x2032b}, 1916 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x20329},
1954 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4}, 1917 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4},
1955 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42}, 1918 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42},
1956 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4}, 1919 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4},
1957#define XSEM_PORT0_END 1720 1920#define XSEM_PORT0_END 1683
1958#define XSEM_PORT1_START 1720 1921#define XSEM_PORT1_START 1683
1959 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3be0, 0x10}, 1922 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3be0, 0x10},
1960 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc3f0, 0xfc}, 1923 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc3f0, 0xfc},
1961 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c90, 0x1c}, 1924 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c90, 0x1c},
@@ -1968,7 +1931,7 @@ static const struct raw_op init_ops[] = {
1968 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2758, 0x1c}, 1931 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2758, 0x1c},
1969 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b5c, 0x0}, 1932 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b5c, 0x0},
1970 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2838, 0x1c}, 1933 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2838, 0x1c},
1971 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d50, 0x10032d}, 1934 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d50, 0x10032b},
1972 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28}, 1935 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28},
1973 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1504, 0x0}, 1936 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1504, 0x0},
1974 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa170, 0xc}, 1937 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa170, 0xc},
@@ -1984,65 +1947,65 @@ static const struct raw_op init_ops[] = {
1984 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x2035f}, 1947 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x2035f},
1985 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1}, 1948 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1},
1986 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42}, 1949 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42},
1987 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2033d}, 1950 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2033b},
1988 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4}, 1951 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4},
1989 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42}, 1952 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42},
1990 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4}, 1953 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4},
1991#define XSEM_PORT1_END 1752 1954#define XSEM_PORT1_END 1715
1992#define XSEM_FUNC0_START 1752 1955#define XSEM_FUNC0_START 1715
1993 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e0, 0x0}, 1956 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e0, 0x0},
1994 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28b8, 0x100361}, 1957 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28b8, 0x100361},
1995 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5048, 0xe}, 1958 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
1996#define XSEM_FUNC0_END 1755 1959#define XSEM_FUNC0_END 1718
1997#define XSEM_FUNC1_START 1755 1960#define XSEM_FUNC1_START 1718
1998 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e4, 0x0}, 1961 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e4, 0x0},
1999 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28f8, 0x100371}, 1962 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28f8, 0x100371},
2000 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5080, 0xe}, 1963 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
2001#define XSEM_FUNC1_END 1758 1964#define XSEM_FUNC1_END 1721
2002#define XSEM_FUNC2_START 1758 1965#define XSEM_FUNC2_START 1721
2003 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e8, 0x0}, 1966 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e8, 0x0},
2004 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2938, 0x100381}, 1967 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2938, 0x100381},
2005 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe}, 1968 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe},
2006#define XSEM_FUNC2_END 1761 1969#define XSEM_FUNC2_END 1724
2007#define XSEM_FUNC3_START 1761 1970#define XSEM_FUNC3_START 1724
2008 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7ec, 0x0}, 1971 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7ec, 0x0},
2009 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2978, 0x100391}, 1972 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2978, 0x100391},
2010 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe}, 1973 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe},
2011#define XSEM_FUNC3_END 1764 1974#define XSEM_FUNC3_END 1727
2012#define XSEM_FUNC4_START 1764 1975#define XSEM_FUNC4_START 1727
2013 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f0, 0x0}, 1976 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f0, 0x0},
2014 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29b8, 0x1003a1}, 1977 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29b8, 0x1003a1},
2015 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5128, 0xe}, 1978 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5128, 0xe},
2016#define XSEM_FUNC4_END 1767 1979#define XSEM_FUNC4_END 1730
2017#define XSEM_FUNC5_START 1767 1980#define XSEM_FUNC5_START 1730
2018 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f4, 0x0}, 1981 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f4, 0x0},
2019 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29f8, 0x1003b1}, 1982 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29f8, 0x1003b1},
2020 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5160, 0xe}, 1983 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5160, 0xe},
2021#define XSEM_FUNC5_END 1770 1984#define XSEM_FUNC5_END 1733
2022#define XSEM_FUNC6_START 1770 1985#define XSEM_FUNC6_START 1733
2023 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f8, 0x0}, 1986 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f8, 0x0},
2024 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a38, 0x1003c1}, 1987 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a38, 0x1003c1},
2025 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5198, 0xe}, 1988 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5198, 0xe},
2026#define XSEM_FUNC6_END 1773 1989#define XSEM_FUNC6_END 1736
2027#define XSEM_FUNC7_START 1773 1990#define XSEM_FUNC7_START 1736
2028 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7fc, 0x0}, 1991 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7fc, 0x0},
2029 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a78, 0x1003d1}, 1992 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a78, 0x1003d1},
2030 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe}, 1993 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe},
2031#define XSEM_FUNC7_END 1776 1994#define XSEM_FUNC7_END 1739
2032#define CDU_COMMON_START 1776 1995#define CDU_COMMON_START 1739
2033 {OP_WR, CDU_REG_CDU_CONTROL0, 0x1}, 1996 {OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
2034 {OP_WR_E1H, CDU_REG_MF_MODE, 0x1}, 1997 {OP_WR_E1H, CDU_REG_MF_MODE, 0x1},
2035 {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000}, 1998 {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
2036 {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d}, 1999 {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
2037 {OP_WB_E1, CDU_REG_L1TT, 0x200033f}, 2000 {OP_WB_E1, CDU_REG_L1TT, 0x200033d},
2038 {OP_WB_E1H, CDU_REG_L1TT, 0x20003e1}, 2001 {OP_WB_E1H, CDU_REG_L1TT, 0x20003e1},
2039 {OP_WB_E1, CDU_REG_MATT, 0x20053f}, 2002 {OP_WB_E1, CDU_REG_MATT, 0x20053d},
2040 {OP_WB_E1H, CDU_REG_MATT, 0x2805e1}, 2003 {OP_WB_E1H, CDU_REG_MATT, 0x2805e1},
2041 {OP_ZR_E1, CDU_REG_MATT + 0x80, 0x2}, 2004 {OP_ZR_E1, CDU_REG_MATT + 0x80, 0x2},
2042 {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6055f}, 2005 {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6055d},
2043 {OP_ZR, CDU_REG_MATT + 0xa0, 0x18}, 2006 {OP_ZR, CDU_REG_MATT + 0xa0, 0x18},
2044#define CDU_COMMON_END 1787 2007#define CDU_COMMON_END 1750
2045#define DMAE_COMMON_START 1787 2008#define DMAE_COMMON_START 1750
2046 {OP_ZR, DMAE_REG_CMD_MEM, 0xe0}, 2009 {OP_ZR, DMAE_REG_CMD_MEM, 0xe0},
2047 {OP_WR, DMAE_REG_CRC16C_INIT, 0x0}, 2010 {OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
2048 {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1}, 2011 {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
@@ -2050,24 +2013,24 @@ static const struct raw_op init_ops[] = {
2050 {OP_WR_E1H, DMAE_REG_PXP_REQ_INIT_CRD, 0x2}, 2013 {OP_WR_E1H, DMAE_REG_PXP_REQ_INIT_CRD, 0x2},
2051 {OP_WR, DMAE_REG_PCI_IFEN, 0x1}, 2014 {OP_WR, DMAE_REG_PCI_IFEN, 0x1},
2052 {OP_WR, DMAE_REG_GRC_IFEN, 0x1}, 2015 {OP_WR, DMAE_REG_GRC_IFEN, 0x1},
2053#define DMAE_COMMON_END 1794 2016#define DMAE_COMMON_END 1757
2054#define PXP_COMMON_START 1794 2017#define PXP_COMMON_START 1757
2055 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50565}, 2018 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50563},
2056 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x400, 0x50609}, 2019 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x400, 0x50609},
2057 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x5056a}, 2020 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x50568},
2058 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT, 0x5060e}, 2021 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT, 0x5060e},
2059 {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5056f}, 2022 {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5056d},
2060#define PXP_COMMON_END 1799 2023#define PXP_COMMON_END 1762
2061#define CFC_COMMON_START 1799 2024#define CFC_COMMON_START 1762
2062 {OP_ZR_E1H, CFC_REG_LINK_LIST, 0x100}, 2025 {OP_ZR_E1H, CFC_REG_LINK_LIST, 0x100},
2063 {OP_WR, CFC_REG_CONTROL0, 0x10}, 2026 {OP_WR, CFC_REG_CONTROL0, 0x10},
2064 {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff}, 2027 {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
2065 {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a}, 2028 {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
2066#define CFC_COMMON_END 1803 2029#define CFC_COMMON_END 1766
2067#define HC_COMMON_START 1803 2030#define HC_COMMON_START 1766
2068 {OP_ZR_E1, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4}, 2031 {OP_ZR_E1, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4},
2069#define HC_COMMON_END 1804 2032#define HC_COMMON_END 1767
2070#define HC_PORT0_START 1804 2033#define HC_PORT0_START 1767
2071 {OP_WR_E1, HC_REG_CONFIG_0, 0x1080}, 2034 {OP_WR_E1, HC_REG_CONFIG_0, 0x1080},
2072 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_0, 0x2}, 2035 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_0, 0x2},
2073 {OP_WR_E1, HC_REG_ATTN_NUM_P0, 0x10}, 2036 {OP_WR_E1, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2086,8 +2049,8 @@ static const struct raw_op init_ops[] = {
2086 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, 2049 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2087 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, 2050 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2088 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, 2051 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2089#define HC_PORT0_END 1822 2052#define HC_PORT0_END 1785
2090#define HC_PORT1_START 1822 2053#define HC_PORT1_START 1785
2091 {OP_WR_E1, HC_REG_CONFIG_1, 0x1080}, 2054 {OP_WR_E1, HC_REG_CONFIG_1, 0x1080},
2092 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_1, 0x2}, 2055 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_1, 0x2},
2093 {OP_WR_E1, HC_REG_ATTN_NUM_P1, 0x10}, 2056 {OP_WR_E1, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2106,8 +2069,8 @@ static const struct raw_op init_ops[] = {
2106 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, 2069 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2107 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, 2070 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2108 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, 2071 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2109#define HC_PORT1_END 1840 2072#define HC_PORT1_END 1803
2110#define HC_FUNC0_START 1840 2073#define HC_FUNC0_START 1803
2111 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, 2074 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2112 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x0}, 2075 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x0},
2113 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, 2076 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2123,8 +2086,8 @@ static const struct raw_op init_ops[] = {
2123 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, 2086 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2124 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, 2087 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2125 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, 2088 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2126#define HC_FUNC0_END 1855 2089#define HC_FUNC0_END 1818
2127#define HC_FUNC1_START 1855 2090#define HC_FUNC1_START 1818
2128 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, 2091 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2129 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x1}, 2092 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x1},
2130 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, 2093 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2140,8 +2103,8 @@ static const struct raw_op init_ops[] = {
2140 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, 2103 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2141 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, 2104 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2142 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, 2105 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2143#define HC_FUNC1_END 1870 2106#define HC_FUNC1_END 1833
2144#define HC_FUNC2_START 1870 2107#define HC_FUNC2_START 1833
2145 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, 2108 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2146 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x2}, 2109 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x2},
2147 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, 2110 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2157,8 +2120,8 @@ static const struct raw_op init_ops[] = {
2157 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, 2120 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2158 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, 2121 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2159 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, 2122 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2160#define HC_FUNC2_END 1885 2123#define HC_FUNC2_END 1848
2161#define HC_FUNC3_START 1885 2124#define HC_FUNC3_START 1848
2162 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, 2125 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2163 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x3}, 2126 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x3},
2164 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, 2127 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2174,8 +2137,8 @@ static const struct raw_op init_ops[] = {
2174 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, 2137 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2175 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, 2138 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2176 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, 2139 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2177#define HC_FUNC3_END 1900 2140#define HC_FUNC3_END 1863
2178#define HC_FUNC4_START 1900 2141#define HC_FUNC4_START 1863
2179 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, 2142 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2180 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x4}, 2143 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x4},
2181 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, 2144 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2191,8 +2154,8 @@ static const struct raw_op init_ops[] = {
2191 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, 2154 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2192 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, 2155 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2193 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, 2156 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2194#define HC_FUNC4_END 1915 2157#define HC_FUNC4_END 1878
2195#define HC_FUNC5_START 1915 2158#define HC_FUNC5_START 1878
2196 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, 2159 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2197 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x5}, 2160 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x5},
2198 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, 2161 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2208,8 +2171,8 @@ static const struct raw_op init_ops[] = {
2208 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, 2171 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2209 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, 2172 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2210 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, 2173 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2211#define HC_FUNC5_END 1930 2174#define HC_FUNC5_END 1893
2212#define HC_FUNC6_START 1930 2175#define HC_FUNC6_START 1893
2213 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, 2176 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2214 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x6}, 2177 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x6},
2215 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, 2178 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2225,8 +2188,8 @@ static const struct raw_op init_ops[] = {
2225 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, 2188 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2226 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, 2189 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2227 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, 2190 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2228#define HC_FUNC6_END 1945 2191#define HC_FUNC6_END 1908
2229#define HC_FUNC7_START 1945 2192#define HC_FUNC7_START 1908
2230 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, 2193 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2231 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x7}, 2194 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x7},
2232 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, 2195 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2242,8 +2205,8 @@ static const struct raw_op init_ops[] = {
2242 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, 2205 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2243 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, 2206 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2244 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, 2207 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2245#define HC_FUNC7_END 1960 2208#define HC_FUNC7_END 1923
2246#define PXP2_COMMON_START 1960 2209#define PXP2_COMMON_START 1923
2247 {OP_WR_E1, PXP2_REG_PGL_CONTROL0, 0xe38340}, 2210 {OP_WR_E1, PXP2_REG_PGL_CONTROL0, 0xe38340},
2248 {OP_WR_E1H, PXP2_REG_RQ_DRAM_ALIGN, 0x1}, 2211 {OP_WR_E1H, PXP2_REG_RQ_DRAM_ALIGN, 0x1},
2249 {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10}, 2212 {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
@@ -2361,8 +2324,8 @@ static const struct raw_op init_ops[] = {
2361 {OP_WR_E1H, PXP2_REG_RQ_ILT_MODE, 0x1}, 2324 {OP_WR_E1H, PXP2_REG_RQ_ILT_MODE, 0x1},
2362 {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1}, 2325 {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
2363 {OP_WR_E1H, PXP2_REG_PGL_CONTROL0, 0xe38340}, 2326 {OP_WR_E1H, PXP2_REG_PGL_CONTROL0, 0xe38340},
2364#define PXP2_COMMON_END 2077 2327#define PXP2_COMMON_END 2040
2365#define MISC_AEU_COMMON_START 2077 2328#define MISC_AEU_COMMON_START 2040
2366 {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16}, 2329 {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
2367 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000}, 2330 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
2368 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555}, 2331 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
@@ -2382,8 +2345,8 @@ static const struct raw_op init_ops[] = {
2382 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_1, 0x0}, 2345 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
2383 {OP_WR_E1H, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00}, 2346 {OP_WR_E1H, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00},
2384 {OP_WR_E1H, MISC_REG_AEU_GENERAL_MASK, 0x3}, 2347 {OP_WR_E1H, MISC_REG_AEU_GENERAL_MASK, 0x3},
2385#define MISC_AEU_COMMON_END 2096 2348#define MISC_AEU_COMMON_END 2059
2386#define MISC_AEU_PORT0_START 2096 2349#define MISC_AEU_PORT0_START 2059
2387 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000}, 2350 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000},
2388 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000}, 2351 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000},
2389 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef}, 2352 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef},
@@ -2416,8 +2379,8 @@ static const struct raw_op init_ops[] = {
2416 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0}, 2379 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0},
2417 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3}, 2380 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3},
2418 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7}, 2381 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7},
2419#define MISC_AEU_PORT0_END 2128 2382#define MISC_AEU_PORT0_END 2091
2420#define MISC_AEU_PORT1_START 2128 2383#define MISC_AEU_PORT1_START 2091
2421 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000}, 2384 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000},
2422 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000}, 2385 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000},
2423 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef}, 2386 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef},
@@ -2450,7 +2413,7 @@ static const struct raw_op init_ops[] = {
2450 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0}, 2413 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0},
2451 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3}, 2414 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3},
2452 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7}, 2415 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7},
2453#define MISC_AEU_PORT1_END 2160 2416#define MISC_AEU_PORT1_END 2123
2454 2417
2455}; 2418};
2456 2419
@@ -2560,103 +2523,92 @@ static const u32 init_data_e1[] = {
2560 0x00049c00, 0x00051f80, 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 2523 0x00049c00, 0x00051f80, 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80,
2561 0x0007b100, 0x00083480, 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 2524 0x0007b100, 0x00083480, 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280,
2562 0x000ac600, 0x000b4980, 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 2525 0x000ac600, 0x000b4980, 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780,
2563 0x000ddb00, 0x00001900, 0x00000028, 0x00000000, 0x00100000, 0x00000000, 2526 0x000ddb00, 0x00001900, 0x00100000, 0x00000000, 0x00000000, 0xffffffff,
2564 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2565 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2527 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2566 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2528 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2567 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2529 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2568 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2530 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2569 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8,
2570 0x00000000, 0x00001500, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2571 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, 0x40000000,
2572 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2531 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2532 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000, 0x00001500,
2533 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2534 0xffffffff, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2573 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2535 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2574 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2536 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2575 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2537 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2576 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2538 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2577 0x00000000, 0x00007ff8, 0x00000000, 0x00003500, 0x00001000, 0x00002080, 2539 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8,
2578 0x00003100, 0x00004180, 0x00005200, 0x00006280, 0x00007300, 0x00008380, 2540 0x00000000, 0x00003500, 0x00001000, 0x00002080, 0x00003100, 0x00004180,
2579 0x00009400, 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680, 2541 0x00005200, 0x00006280, 0x00007300, 0x00008380, 0x00009400, 0x0000a480,
2580 0x0000f700, 0x00010780, 0x00011800, 0x00012880, 0x00013900, 0x00014980, 2542 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680, 0x0000f700, 0x00010780,
2581 0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80, 2543 0x00011800, 0x00012880, 0x00013900, 0x00014980, 0x00015a00, 0x00016a80,
2582 0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000, 2544 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80, 0x0001bd00, 0x0001cd80,
2583 0x00010001, 0x00000604, 0xccccccc1, 0xffffffff, 0xffffffff, 0xcccc0201, 2545 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000, 0x00010001, 0x00000604,
2584 0xcccccccc, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 2546 0xccccccc1, 0xffffffff, 0xffffffff, 0xcccc0201, 0xcccccccc, 0x00000000,
2547 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2585 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2548 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2586 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2549 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2587 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2550 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2588 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 2551 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2589 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 2552 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000,
2590 0x00007ff8, 0x00000000, 0x00003500, 0x0000ffff, 0x00000000, 0x0000ffff, 2553 0x00003500, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2591 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 2554 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2555 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000,
2592 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 2556 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2593 0x00000000, 0x00100000, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2594 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 2557 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
2595 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 2558 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000,
2596 0x00000000, 0x00100000, 0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c, 2559 0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2597 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 2560 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x30efffff, 0x0c30c30c,
2598 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
2599 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2600 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
2601 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
2602 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
2603 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2604 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c,
2605 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
2606 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
2607 0xcdcdcdcd, 0xfffffff3, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2608 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c,
2609 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 2561 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
2610 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 2562 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
2611 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 2563 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
2612 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 2564 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
2613 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 2565 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
2614 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 2566 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
2615 0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 2567 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2616 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, 2568 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff, 0x0c30c30c,
2617 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 2569 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3,
2618 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 2570 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
2619 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 2571 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2620 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 2572 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c,
2621 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 2573 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406,
2622 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 2574 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c,
2623 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 2575 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2624 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 2576 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c,
2625 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 2577 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7,
2626 0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 2578 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c,
2627 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 2579 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2628 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, 2580 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x31efffff, 0x0c30c30c,
2629 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 2581 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
2630 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 2582 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
2631 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 2583 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2632 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 2584 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
2633 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 2585 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
2634 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 2586 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
2635 0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 2587 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2636 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, 2588 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x056fffff, 0x0c30c30c,
2637 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 2589 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
2638 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 2590 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
2639 0xcdcdcdcd, 0xfffffff3, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 2591 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2640 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c, 2592 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c,
2641 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 2593 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
2642 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 2594 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
2643 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 2595 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
2644 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 2596 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
2645 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 2597 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffff8a,
2646 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 2598 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0010cf3c,
2647 0xcdcdcdcd, 0xffffff97, 0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 2599 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000,
2648 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c, 2600 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c,
2649 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 2601 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3,
2650 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 2602 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
2651 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 2603 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2652 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 2604 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c,
2653 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 2605 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406,
2654 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 2606 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c,
2655 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 2607 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2656 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 2608 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c,
2657 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 2609 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97,
2658 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 2610 0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c,
2659 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 2611 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
2660 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 2612 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2661 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 2613 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff,
2662 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 2614 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c,
@@ -2678,16 +2630,27 @@ static const u32 init_data_e1[] = {
2678 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 2630 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c,
2679 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 2631 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2680 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 2632 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2681 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000, 2633 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff,
2682 0x00070100, 0x00028170, 0x000b8198, 0x00020250, 0x00010270, 0x000f0280, 2634 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c,
2683 0x00010370, 0x00080000, 0x00080080, 0x00028100, 0x000b8128, 0x000201e0, 2635 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2684 0x00010200, 0x00070210, 0x00020280, 0x000f0000, 0x000800f0, 0x00028170, 2636 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2685 0x000b8198, 0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000, 2637 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff,
2686 0x00080100, 0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, 2638 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c,
2687 0x00080380, 0x00028000, 0x000b8028, 0x000200e0, 0x00010100, 0x00008110, 2639 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2688 0x00000118, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 2640 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
2689 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 2641 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff,
2690 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000 2642 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c,
2643 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
2644 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000, 0x00070100, 0x00028170,
2645 0x000b8198, 0x00020250, 0x00010270, 0x000f0280, 0x00010370, 0x00080000,
2646 0x00080080, 0x00028100, 0x000b8128, 0x000201e0, 0x00010200, 0x00070210,
2647 0x00020280, 0x000f0000, 0x000800f0, 0x00028170, 0x000b8198, 0x00020250,
2648 0x00010270, 0x000b8280, 0x00080338, 0x00100000, 0x00080100, 0x00028180,
2649 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, 0x00080380, 0x00028000,
2650 0x000b8028, 0x000200e0, 0x00010100, 0x00008110, 0x00000118, 0xcccccccc,
2651 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc,
2652 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc,
2653 0xcccccccc, 0x00002000
2691}; 2654};
2692 2655
2693static const u32 init_data_e1h[] = { 2656static const u32 init_data_e1h[] = {
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index ff2743db10d9..8b92c6ad0759 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -31,17 +31,16 @@
31 31
32/********************************************************/ 32/********************************************************/
33#define SUPPORT_CL73 0 /* Currently no */ 33#define SUPPORT_CL73 0 /* Currently no */
34#define ETH_HLEN 14 34#define ETH_HLEN 14
35#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/ 35#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
36#define ETH_MIN_PACKET_SIZE 60 36#define ETH_MIN_PACKET_SIZE 60
37#define ETH_MAX_PACKET_SIZE 1500 37#define ETH_MAX_PACKET_SIZE 1500
38#define ETH_MAX_JUMBO_PACKET_SIZE 9600 38#define ETH_MAX_JUMBO_PACKET_SIZE 9600
39#define MDIO_ACCESS_TIMEOUT 1000 39#define MDIO_ACCESS_TIMEOUT 1000
40#define BMAC_CONTROL_RX_ENABLE 2 40#define BMAC_CONTROL_RX_ENABLE 2
41#define MAX_MTU_SIZE 5000
42 41
43/***********************************************************/ 42/***********************************************************/
44/* Shortcut definitions */ 43/* Shortcut definitions */
45/***********************************************************/ 44/***********************************************************/
46 45
47#define NIG_STATUS_XGXS0_LINK10G \ 46#define NIG_STATUS_XGXS0_LINK10G \
@@ -80,12 +79,12 @@
80 79
81#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 80#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
82#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 81#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
83#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 82#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
84#define AUTONEG_PARALLEL \ 83#define AUTONEG_PARALLEL \
85 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 84 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
86#define AUTONEG_SGMII_FIBER_AUTODET \ 85#define AUTONEG_SGMII_FIBER_AUTODET \
87 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 86 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
88#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 87#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
89 88
90#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 89#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
91 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
@@ -202,11 +201,10 @@ static void bnx2x_emac_init(struct link_params *params,
202 /* init emac - use read-modify-write */ 201 /* init emac - use read-modify-write */
203 /* self clear reset */ 202 /* self clear reset */
204 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 203 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
205 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 204 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
206 205
207 timeout = 200; 206 timeout = 200;
208 do 207 do {
209 {
210 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 208 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
211 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); 209 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
212 if (!timeout) { 210 if (!timeout) {
@@ -214,18 +212,18 @@ static void bnx2x_emac_init(struct link_params *params,
214 return; 212 return;
215 } 213 }
216 timeout--; 214 timeout--;
217 }while (val & EMAC_MODE_RESET); 215 } while (val & EMAC_MODE_RESET);
218 216
219 /* Set mac address */ 217 /* Set mac address */
220 val = ((params->mac_addr[0] << 8) | 218 val = ((params->mac_addr[0] << 8) |
221 params->mac_addr[1]); 219 params->mac_addr[1]);
222 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val); 220 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
223 221
224 val = ((params->mac_addr[2] << 24) | 222 val = ((params->mac_addr[2] << 24) |
225 (params->mac_addr[3] << 16) | 223 (params->mac_addr[3] << 16) |
226 (params->mac_addr[4] << 8) | 224 (params->mac_addr[4] << 8) |
227 params->mac_addr[5]); 225 params->mac_addr[5]);
228 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val); 226 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
229} 227}
230 228
231static u8 bnx2x_emac_enable(struct link_params *params, 229static u8 bnx2x_emac_enable(struct link_params *params,
@@ -286,7 +284,7 @@ static u8 bnx2x_emac_enable(struct link_params *params,
286 if (CHIP_REV_IS_SLOW(bp)) { 284 if (CHIP_REV_IS_SLOW(bp)) {
287 /* config GMII mode */ 285 /* config GMII mode */
288 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 286 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
289 EMAC_WR(EMAC_REG_EMAC_MODE, 287 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
290 (val | EMAC_MODE_PORT_GMII)); 288 (val | EMAC_MODE_PORT_GMII));
291 } else { /* ASIC */ 289 } else { /* ASIC */
292 /* pause enable/disable */ 290 /* pause enable/disable */
@@ -298,17 +296,19 @@ static u8 bnx2x_emac_enable(struct link_params *params,
298 EMAC_RX_MODE_FLOW_EN); 296 EMAC_RX_MODE_FLOW_EN);
299 297
300 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 298 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
301 EMAC_TX_MODE_EXT_PAUSE_EN); 299 (EMAC_TX_MODE_EXT_PAUSE_EN |
300 EMAC_TX_MODE_FLOW_EN));
302 if (vars->flow_ctrl & FLOW_CTRL_TX) 301 if (vars->flow_ctrl & FLOW_CTRL_TX)
303 bnx2x_bits_en(bp, emac_base + 302 bnx2x_bits_en(bp, emac_base +
304 EMAC_REG_EMAC_TX_MODE, 303 EMAC_REG_EMAC_TX_MODE,
305 EMAC_TX_MODE_EXT_PAUSE_EN); 304 (EMAC_TX_MODE_EXT_PAUSE_EN |
305 EMAC_TX_MODE_FLOW_EN));
306 } 306 }
307 307
308 /* KEEP_VLAN_TAG, promiscuous */ 308 /* KEEP_VLAN_TAG, promiscuous */
309 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 309 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
310 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 310 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
311 EMAC_WR(EMAC_REG_EMAC_RX_MODE, val); 311 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
312 312
313 /* Set Loopback */ 313 /* Set Loopback */
314 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 314 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
@@ -316,10 +316,10 @@ static u8 bnx2x_emac_enable(struct link_params *params,
316 val |= 0x810; 316 val |= 0x810;
317 else 317 else
318 val &= ~0x810; 318 val &= ~0x810;
319 EMAC_WR(EMAC_REG_EMAC_MODE, val); 319 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
320 320
321 /* enable emac for jumbo packets */ 321 /* enable emac for jumbo packets */
322 EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE, 322 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
323 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 323 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
324 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); 324 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
325 325
@@ -591,9 +591,9 @@ void bnx2x_link_status_update(struct link_params *params,
591 vars->flow_ctrl &= ~FLOW_CTRL_RX; 591 vars->flow_ctrl &= ~FLOW_CTRL_RX;
592 592
593 if (vars->phy_flags & PHY_XGXS_FLAG) { 593 if (vars->phy_flags & PHY_XGXS_FLAG) {
594 if (params->req_line_speed && 594 if (vars->line_speed &&
595 ((params->req_line_speed == SPEED_10) || 595 ((vars->line_speed == SPEED_10) ||
596 (params->req_line_speed == SPEED_100))) { 596 (vars->line_speed == SPEED_100))) {
597 vars->phy_flags |= PHY_SGMII_FLAG; 597 vars->phy_flags |= PHY_SGMII_FLAG;
598 } else { 598 } else {
599 vars->phy_flags &= ~PHY_SGMII_FLAG; 599 vars->phy_flags &= ~PHY_SGMII_FLAG;
@@ -645,7 +645,7 @@ static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
645 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 645 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
646 NIG_REG_INGRESS_BMAC0_MEM; 646 NIG_REG_INGRESS_BMAC0_MEM;
647 u32 wb_data[2]; 647 u32 wb_data[2];
648 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 648 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
649 649
650 /* Only if the bmac is out of reset */ 650 /* Only if the bmac is out of reset */
651 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 651 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
@@ -670,7 +670,6 @@ static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
670 u8 port = params->port; 670 u8 port = params->port;
671 u32 init_crd, crd; 671 u32 init_crd, crd;
672 u32 count = 1000; 672 u32 count = 1000;
673 u32 pause = 0;
674 673
675 /* disable port */ 674 /* disable port */
676 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 675 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
@@ -693,33 +692,25 @@ static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
693 return -EINVAL; 692 return -EINVAL;
694 } 693 }
695 694
696 if (flow_ctrl & FLOW_CTRL_RX) 695 if (flow_ctrl & FLOW_CTRL_RX ||
697 pause = 1; 696 line_speed == SPEED_10 ||
698 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, pause); 697 line_speed == SPEED_100 ||
699 if (pause) { 698 line_speed == SPEED_1000 ||
699 line_speed == SPEED_2500) {
700 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
700 /* update threshold */ 701 /* update threshold */
701 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); 702 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
702 /* update init credit */ 703 /* update init credit */
703 init_crd = 778; /* (800-18-4) */ 704 init_crd = 778; /* (800-18-4) */
704 705
705 } else { 706 } else {
706 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + 707 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
707 ETH_OVREHEAD)/16; 708 ETH_OVREHEAD)/16;
708 709 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
709 /* update threshold */ 710 /* update threshold */
710 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); 711 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
711 /* update init credit */ 712 /* update init credit */
712 switch (line_speed) { 713 switch (line_speed) {
713 case SPEED_10:
714 case SPEED_100:
715 case SPEED_1000:
716 init_crd = thresh + 55 - 22;
717 break;
718
719 case SPEED_2500:
720 init_crd = thresh + 138 - 22;
721 break;
722
723 case SPEED_10000: 714 case SPEED_10000:
724 init_crd = thresh + 553 - 22; 715 init_crd = thresh + 553 - 22;
725 break; 716 break;
@@ -764,10 +755,10 @@ static u32 bnx2x_get_emac_base(u32 ext_phy_type, u8 port)
764 emac_base = GRCBASE_EMAC0; 755 emac_base = GRCBASE_EMAC0;
765 break; 756 break;
766 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 757 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
767 emac_base = (port) ? GRCBASE_EMAC0: GRCBASE_EMAC1; 758 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
768 break; 759 break;
769 default: 760 default:
770 emac_base = (port) ? GRCBASE_EMAC1: GRCBASE_EMAC0; 761 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
771 break; 762 break;
772 } 763 }
773 return emac_base; 764 return emac_base;
@@ -1044,7 +1035,7 @@ static void bnx2x_set_swap_lanes(struct link_params *params)
1044} 1035}
1045 1036
1046static void bnx2x_set_parallel_detection(struct link_params *params, 1037static void bnx2x_set_parallel_detection(struct link_params *params,
1047 u8 phy_flags) 1038 u8 phy_flags)
1048{ 1039{
1049 struct bnx2x *bp = params->bp; 1040 struct bnx2x *bp = params->bp;
1050 u16 control2; 1041 u16 control2;
@@ -1114,7 +1105,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1114 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val); 1105 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1115 1106
1116 /* CL37 Autoneg Enabled */ 1107 /* CL37 Autoneg Enabled */
1117 if (params->req_line_speed == SPEED_AUTO_NEG) 1108 if (vars->line_speed == SPEED_AUTO_NEG)
1118 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 1109 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1119 else /* CL37 Autoneg Disabled */ 1110 else /* CL37 Autoneg Disabled */
1120 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 1111 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
@@ -1132,7 +1123,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1132 MDIO_REG_BANK_SERDES_DIGITAL, 1123 MDIO_REG_BANK_SERDES_DIGITAL,
1133 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val); 1124 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
1134 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN; 1125 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
1135 if (params->req_line_speed == SPEED_AUTO_NEG) 1126 if (vars->line_speed == SPEED_AUTO_NEG)
1136 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 1127 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1137 else 1128 else
1138 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 1129 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
@@ -1148,7 +1139,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1148 MDIO_REG_BANK_BAM_NEXT_PAGE, 1139 MDIO_REG_BANK_BAM_NEXT_PAGE,
1149 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 1140 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1150 &reg_val); 1141 &reg_val);
1151 if (params->req_line_speed == SPEED_AUTO_NEG) { 1142 if (vars->line_speed == SPEED_AUTO_NEG) {
1152 /* Enable BAM aneg Mode and TetonII aneg Mode */ 1143 /* Enable BAM aneg Mode and TetonII aneg Mode */
1153 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 1144 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1154 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 1145 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
@@ -1164,7 +1155,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
1164 reg_val); 1155 reg_val);
1165 1156
1166 /* Enable Clause 73 Aneg */ 1157 /* Enable Clause 73 Aneg */
1167 if ((params->req_line_speed == SPEED_AUTO_NEG) && 1158 if ((vars->line_speed == SPEED_AUTO_NEG) &&
1168 (SUPPORT_CL73)) { 1159 (SUPPORT_CL73)) {
1169 /* Enable BAM Station Manager */ 1160 /* Enable BAM Station Manager */
1170 1161
@@ -1226,7 +1217,8 @@ static void bnx2x_set_autoneg(struct link_params *params,
1226} 1217}
1227 1218
1228/* program SerDes, forced speed */ 1219/* program SerDes, forced speed */
1229static void bnx2x_program_serdes(struct link_params *params) 1220static void bnx2x_program_serdes(struct link_params *params,
1221 struct link_vars *vars)
1230{ 1222{
1231 struct bnx2x *bp = params->bp; 1223 struct bnx2x *bp = params->bp;
1232 u16 reg_val; 1224 u16 reg_val;
@@ -1248,28 +1240,35 @@ static void bnx2x_program_serdes(struct link_params *params)
1248 1240
1249 /* program speed 1241 /* program speed
1250 - needed only if the speed is greater than 1G (2.5G or 10G) */ 1242 - needed only if the speed is greater than 1G (2.5G or 10G) */
1251 if (!((params->req_line_speed == SPEED_1000) || 1243 CL45_RD_OVER_CL22(bp, params->port,
1252 (params->req_line_speed == SPEED_100) ||
1253 (params->req_line_speed == SPEED_10))) {
1254 CL45_RD_OVER_CL22(bp, params->port,
1255 params->phy_addr, 1244 params->phy_addr,
1256 MDIO_REG_BANK_SERDES_DIGITAL, 1245 MDIO_REG_BANK_SERDES_DIGITAL,
1257 MDIO_SERDES_DIGITAL_MISC1, &reg_val); 1246 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
1258 /* clearing the speed value before setting the right speed */ 1247 /* clearing the speed value before setting the right speed */
1259 reg_val &= ~MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK; 1248 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
1249
1250 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
1251 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1252
1253 if (!((vars->line_speed == SPEED_1000) ||
1254 (vars->line_speed == SPEED_100) ||
1255 (vars->line_speed == SPEED_10))) {
1256
1260 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 1257 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1261 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 1258 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1262 if (params->req_line_speed == SPEED_10000) 1259 if (vars->line_speed == SPEED_10000)
1263 reg_val |= 1260 reg_val |=
1264 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 1261 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
1265 if (params->req_line_speed == SPEED_13000) 1262 if (vars->line_speed == SPEED_13000)
1266 reg_val |= 1263 reg_val |=
1267 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G; 1264 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
1268 CL45_WR_OVER_CL22(bp, params->port, 1265 }
1266
1267 CL45_WR_OVER_CL22(bp, params->port,
1269 params->phy_addr, 1268 params->phy_addr,
1270 MDIO_REG_BANK_SERDES_DIGITAL, 1269 MDIO_REG_BANK_SERDES_DIGITAL,
1271 MDIO_SERDES_DIGITAL_MISC1, reg_val); 1270 MDIO_SERDES_DIGITAL_MISC1, reg_val);
1272 } 1271
1273} 1272}
1274 1273
1275static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params) 1274static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
@@ -1295,48 +1294,49 @@ static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1295 MDIO_OVER_1G_UP3, 0); 1294 MDIO_OVER_1G_UP3, 0);
1296} 1295}
1297 1296
1298static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params, 1297static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc)
1299 u32 *ieee_fc)
1300{ 1298{
1301 struct bnx2x *bp = params->bp; 1299 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1302 /* for AN, we are always publishing full duplex */
1303 u16 an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1304
1305 /* resolve pause mode and advertisement 1300 /* resolve pause mode and advertisement
1306 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */ 1301 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1307 1302
1308 switch (params->req_flow_ctrl) { 1303 switch (params->req_flow_ctrl) {
1309 case FLOW_CTRL_AUTO: 1304 case FLOW_CTRL_AUTO:
1310 if (params->mtu <= MAX_MTU_SIZE) { 1305 if (params->req_fc_auto_adv == FLOW_CTRL_BOTH) {
1311 an_adv |= 1306 *ieee_fc |=
1312 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 1307 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1313 } else { 1308 } else {
1314 an_adv |= 1309 *ieee_fc |=
1315 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 1310 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1316 } 1311 }
1317 break; 1312 break;
1318 case FLOW_CTRL_TX: 1313 case FLOW_CTRL_TX:
1319 an_adv |= 1314 *ieee_fc |=
1320 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 1315 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1321 break; 1316 break;
1322 1317
1323 case FLOW_CTRL_RX: 1318 case FLOW_CTRL_RX:
1324 case FLOW_CTRL_BOTH: 1319 case FLOW_CTRL_BOTH:
1325 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 1320 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1326 break; 1321 break;
1327 1322
1328 case FLOW_CTRL_NONE: 1323 case FLOW_CTRL_NONE:
1329 default: 1324 default:
1330 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 1325 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
1331 break; 1326 break;
1332 } 1327 }
1328}
1333 1329
1334 *ieee_fc = an_adv; 1330static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1331 u32 ieee_fc)
1332{
1333 struct bnx2x *bp = params->bp;
1334 /* for AN, we are always publishing full duplex */
1335 1335
1336 CL45_WR_OVER_CL22(bp, params->port, 1336 CL45_WR_OVER_CL22(bp, params->port,
1337 params->phy_addr, 1337 params->phy_addr,
1338 MDIO_REG_BANK_COMBO_IEEE0, 1338 MDIO_REG_BANK_COMBO_IEEE0,
1339 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, an_adv); 1339 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, (u16)ieee_fc);
1340} 1340}
1341 1341
1342static void bnx2x_restart_autoneg(struct link_params *params) 1342static void bnx2x_restart_autoneg(struct link_params *params)
@@ -1382,7 +1382,8 @@ static void bnx2x_restart_autoneg(struct link_params *params)
1382 } 1382 }
1383} 1383}
1384 1384
1385static void bnx2x_initialize_sgmii_process(struct link_params *params) 1385static void bnx2x_initialize_sgmii_process(struct link_params *params,
1386 struct link_vars *vars)
1386{ 1387{
1387 struct bnx2x *bp = params->bp; 1388 struct bnx2x *bp = params->bp;
1388 u16 control1; 1389 u16 control1;
@@ -1406,7 +1407,7 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params)
1406 control1); 1407 control1);
1407 1408
1408 /* if forced speed */ 1409 /* if forced speed */
1409 if (!(params->req_line_speed == SPEED_AUTO_NEG)) { 1410 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
1410 /* set speed, disable autoneg */ 1411 /* set speed, disable autoneg */
1411 u16 mii_control; 1412 u16 mii_control;
1412 1413
@@ -1419,7 +1420,7 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params)
1419 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 1420 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1420 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 1421 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1421 1422
1422 switch (params->req_line_speed) { 1423 switch (vars->line_speed) {
1423 case SPEED_100: 1424 case SPEED_100:
1424 mii_control |= 1425 mii_control |=
1425 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 1426 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
@@ -1433,8 +1434,8 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params)
1433 break; 1434 break;
1434 default: 1435 default:
1435 /* invalid speed for SGMII */ 1436 /* invalid speed for SGMII */
1436 DP(NETIF_MSG_LINK, "Invalid req_line_speed 0x%x\n", 1437 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1437 params->req_line_speed); 1438 vars->line_speed);
1438 break; 1439 break;
1439 } 1440 }
1440 1441
@@ -1460,20 +1461,20 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params)
1460 */ 1461 */
1461 1462
1462static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) 1463static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
1463{ 1464{ /* LD LP */
1464 switch (pause_result) { /* ASYM P ASYM P */ 1465 switch (pause_result) { /* ASYM P ASYM P */
1465 case 0xb: /* 1 0 1 1 */ 1466 case 0xb: /* 1 0 1 1 */
1466 vars->flow_ctrl = FLOW_CTRL_TX; 1467 vars->flow_ctrl = FLOW_CTRL_TX;
1467 break; 1468 break;
1468 1469
1469 case 0xe: /* 1 1 1 0 */ 1470 case 0xe: /* 1 1 1 0 */
1470 vars->flow_ctrl = FLOW_CTRL_RX; 1471 vars->flow_ctrl = FLOW_CTRL_RX;
1471 break; 1472 break;
1472 1473
1473 case 0x5: /* 0 1 0 1 */ 1474 case 0x5: /* 0 1 0 1 */
1474 case 0x7: /* 0 1 1 1 */ 1475 case 0x7: /* 0 1 1 1 */
1475 case 0xd: /* 1 1 0 1 */ 1476 case 0xd: /* 1 1 0 1 */
1476 case 0xf: /* 1 1 1 1 */ 1477 case 0xf: /* 1 1 1 1 */
1477 vars->flow_ctrl = FLOW_CTRL_BOTH; 1478 vars->flow_ctrl = FLOW_CTRL_BOTH;
1478 break; 1479 break;
1479 1480
@@ -1531,6 +1532,28 @@ static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
1531 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n", 1532 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1532 pause_result); 1533 pause_result);
1533 bnx2x_pause_resolve(vars, pause_result); 1534 bnx2x_pause_resolve(vars, pause_result);
1535 if (vars->flow_ctrl == FLOW_CTRL_NONE &&
1536 ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
1537 bnx2x_cl45_read(bp, port,
1538 ext_phy_type,
1539 ext_phy_addr,
1540 MDIO_AN_DEVAD,
1541 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
1542
1543 bnx2x_cl45_read(bp, port,
1544 ext_phy_type,
1545 ext_phy_addr,
1546 MDIO_AN_DEVAD,
1547 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
1548 pause_result = (ld_pause &
1549 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
1550 pause_result |= (lp_pause &
1551 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
1552
1553 bnx2x_pause_resolve(vars, pause_result);
1554 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x \n",
1555 pause_result);
1556 }
1534 } 1557 }
1535 return ret; 1558 return ret;
1536} 1559}
@@ -1541,8 +1564,8 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1541 u32 gp_status) 1564 u32 gp_status)
1542{ 1565{
1543 struct bnx2x *bp = params->bp; 1566 struct bnx2x *bp = params->bp;
1544 u16 ld_pause; /* local driver */ 1567 u16 ld_pause; /* local driver */
1545 u16 lp_pause; /* link partner */ 1568 u16 lp_pause; /* link partner */
1546 u16 pause_result; 1569 u16 pause_result;
1547 1570
1548 vars->flow_ctrl = FLOW_CTRL_NONE; 1571 vars->flow_ctrl = FLOW_CTRL_NONE;
@@ -1573,13 +1596,10 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1573 (bnx2x_ext_phy_resove_fc(params, vars))) { 1596 (bnx2x_ext_phy_resove_fc(params, vars))) {
1574 return; 1597 return;
1575 } else { 1598 } else {
1576 vars->flow_ctrl = params->req_flow_ctrl; 1599 if (params->req_flow_ctrl == FLOW_CTRL_AUTO)
1577 if (vars->flow_ctrl == FLOW_CTRL_AUTO) { 1600 vars->flow_ctrl = params->req_fc_auto_adv;
1578 if (params->mtu <= MAX_MTU_SIZE) 1601 else
1579 vars->flow_ctrl = FLOW_CTRL_BOTH; 1602 vars->flow_ctrl = params->req_flow_ctrl;
1580 else
1581 vars->flow_ctrl = FLOW_CTRL_TX;
1582 }
1583 } 1603 }
1584 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); 1604 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1585} 1605}
@@ -1590,6 +1610,7 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1590 u32 gp_status) 1610 u32 gp_status)
1591{ 1611{
1592 struct bnx2x *bp = params->bp; 1612 struct bnx2x *bp = params->bp;
1613
1593 u8 rc = 0; 1614 u8 rc = 0;
1594 vars->link_status = 0; 1615 vars->link_status = 0;
1595 1616
@@ -1690,7 +1711,11 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1690 1711
1691 vars->link_status |= LINK_STATUS_SERDES_LINK; 1712 vars->link_status |= LINK_STATUS_SERDES_LINK;
1692 1713
1693 if (params->req_line_speed == SPEED_AUTO_NEG) { 1714 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1715 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1716 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
1717 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1718 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705))) {
1694 vars->autoneg = AUTO_NEG_ENABLED; 1719 vars->autoneg = AUTO_NEG_ENABLED;
1695 1720
1696 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { 1721 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
@@ -1705,18 +1730,18 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
1705 1730
1706 } 1731 }
1707 if (vars->flow_ctrl & FLOW_CTRL_TX) 1732 if (vars->flow_ctrl & FLOW_CTRL_TX)
1708 vars->link_status |= 1733 vars->link_status |=
1709 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 1734 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
1710 1735
1711 if (vars->flow_ctrl & FLOW_CTRL_RX) 1736 if (vars->flow_ctrl & FLOW_CTRL_RX)
1712 vars->link_status |= 1737 vars->link_status |=
1713 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 1738 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1714 1739
1715 } else { /* link_down */ 1740 } else { /* link_down */
1716 DP(NETIF_MSG_LINK, "phy link down\n"); 1741 DP(NETIF_MSG_LINK, "phy link down\n");
1717 1742
1718 vars->phy_link_up = 0; 1743 vars->phy_link_up = 0;
1719 vars->line_speed = 0; 1744
1720 vars->duplex = DUPLEX_FULL; 1745 vars->duplex = DUPLEX_FULL;
1721 vars->flow_ctrl = FLOW_CTRL_NONE; 1746 vars->flow_ctrl = FLOW_CTRL_NONE;
1722 vars->autoneg = AUTO_NEG_DISABLED; 1747 vars->autoneg = AUTO_NEG_DISABLED;
@@ -1817,15 +1842,15 @@ static u8 bnx2x_emac_program(struct link_params *params,
1817} 1842}
1818 1843
1819/*****************************************************************************/ 1844/*****************************************************************************/
1820/* External Phy section */ 1845/* External Phy section */
1821/*****************************************************************************/ 1846/*****************************************************************************/
1822static void bnx2x_hw_reset(struct bnx2x *bp) 1847static void bnx2x_hw_reset(struct bnx2x *bp, u8 port)
1823{ 1848{
1824 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 1849 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1825 MISC_REGISTERS_GPIO_OUTPUT_LOW); 1850 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
1826 msleep(1); 1851 msleep(1);
1827 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 1852 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1828 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1853 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
1829} 1854}
1830 1855
1831static void bnx2x_ext_phy_reset(struct link_params *params, 1856static void bnx2x_ext_phy_reset(struct link_params *params,
@@ -1854,10 +1879,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1854 1879
1855 /* Restore normal power mode*/ 1880 /* Restore normal power mode*/
1856 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1881 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1857 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1882 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1883 params->port);
1858 1884
1859 /* HW reset */ 1885 /* HW reset */
1860 bnx2x_hw_reset(bp); 1886 bnx2x_hw_reset(bp, params->port);
1861 1887
1862 bnx2x_cl45_write(bp, params->port, 1888 bnx2x_cl45_write(bp, params->port,
1863 ext_phy_type, 1889 ext_phy_type,
@@ -1869,7 +1895,8 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1869 /* Unset Low Power Mode and SW reset */ 1895 /* Unset Low Power Mode and SW reset */
1870 /* Restore normal power mode*/ 1896 /* Restore normal power mode*/
1871 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1897 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1872 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1898 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1899 params->port);
1873 1900
1874 DP(NETIF_MSG_LINK, "XGXS 8072\n"); 1901 DP(NETIF_MSG_LINK, "XGXS 8072\n");
1875 bnx2x_cl45_write(bp, params->port, 1902 bnx2x_cl45_write(bp, params->port,
@@ -1887,19 +1914,14 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1887 1914
1888 /* Restore normal power mode*/ 1915 /* Restore normal power mode*/
1889 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1916 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1890 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1917 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1918 params->port);
1891 1919
1892 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 1920 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1893 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1921 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1922 params->port);
1894 1923
1895 DP(NETIF_MSG_LINK, "XGXS 8073\n"); 1924 DP(NETIF_MSG_LINK, "XGXS 8073\n");
1896 bnx2x_cl45_write(bp,
1897 params->port,
1898 ext_phy_type,
1899 ext_phy_addr,
1900 MDIO_PMA_DEVAD,
1901 MDIO_PMA_REG_CTRL,
1902 1<<15);
1903 } 1925 }
1904 break; 1926 break;
1905 1927
@@ -1908,10 +1930,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1908 1930
1909 /* Restore normal power mode*/ 1931 /* Restore normal power mode*/
1910 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1932 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1911 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1933 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1934 params->port);
1912 1935
1913 /* HW reset */ 1936 /* HW reset */
1914 bnx2x_hw_reset(bp); 1937 bnx2x_hw_reset(bp, params->port);
1915 1938
1916 break; 1939 break;
1917 1940
@@ -1934,7 +1957,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1934 1957
1935 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482: 1958 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
1936 DP(NETIF_MSG_LINK, "SerDes 5482\n"); 1959 DP(NETIF_MSG_LINK, "SerDes 5482\n");
1937 bnx2x_hw_reset(bp); 1960 bnx2x_hw_reset(bp, params->port);
1938 break; 1961 break;
1939 1962
1940 default: 1963 default:
@@ -2098,42 +2121,45 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2098 2121
2099} 2122}
2100 2123
2101static void bnx2x_bcm8073_external_rom_boot(struct link_params *params) 2124static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port,
2125 u8 ext_phy_addr)
2102{ 2126{
2103 struct bnx2x *bp = params->bp; 2127 u16 fw_ver1, fw_ver2;
2104 u8 port = params->port; 2128 /* Boot port from external ROM */
2105 u8 ext_phy_addr = ((params->ext_phy_config &
2106 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2107 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2108 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2109 u16 fw_ver1, fw_ver2, val;
2110 /* Need to wait 100ms after reset */
2111 msleep(100);
2112 /* Boot port from external ROM */
2113 /* EDC grst */ 2129 /* EDC grst */
2114 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2130 bnx2x_cl45_write(bp, port,
2131 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2132 ext_phy_addr,
2115 MDIO_PMA_DEVAD, 2133 MDIO_PMA_DEVAD,
2116 MDIO_PMA_REG_GEN_CTRL, 2134 MDIO_PMA_REG_GEN_CTRL,
2117 0x0001); 2135 0x0001);
2118 2136
2119 /* ucode reboot and rst */ 2137 /* ucode reboot and rst */
2120 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2138 bnx2x_cl45_write(bp, port,
2139 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2140 ext_phy_addr,
2121 MDIO_PMA_DEVAD, 2141 MDIO_PMA_DEVAD,
2122 MDIO_PMA_REG_GEN_CTRL, 2142 MDIO_PMA_REG_GEN_CTRL,
2123 0x008c); 2143 0x008c);
2124 2144
2125 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2145 bnx2x_cl45_write(bp, port,
2146 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2147 ext_phy_addr,
2126 MDIO_PMA_DEVAD, 2148 MDIO_PMA_DEVAD,
2127 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 2149 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2128 2150
2129 /* Reset internal microprocessor */ 2151 /* Reset internal microprocessor */
2130 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2152 bnx2x_cl45_write(bp, port,
2153 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2154 ext_phy_addr,
2131 MDIO_PMA_DEVAD, 2155 MDIO_PMA_DEVAD,
2132 MDIO_PMA_REG_GEN_CTRL, 2156 MDIO_PMA_REG_GEN_CTRL,
2133 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 2157 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2134 2158
2135 /* Release srst bit */ 2159 /* Release srst bit */
2136 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2160 bnx2x_cl45_write(bp, port,
2161 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2162 ext_phy_addr,
2137 MDIO_PMA_DEVAD, 2163 MDIO_PMA_DEVAD,
2138 MDIO_PMA_REG_GEN_CTRL, 2164 MDIO_PMA_REG_GEN_CTRL,
2139 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 2165 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
@@ -2142,35 +2168,52 @@ static void bnx2x_bcm8073_external_rom_boot(struct link_params *params)
2142 msleep(100); 2168 msleep(100);
2143 2169
2144 /* Clear ser_boot_ctl bit */ 2170 /* Clear ser_boot_ctl bit */
2145 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2171 bnx2x_cl45_write(bp, port,
2172 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2173 ext_phy_addr,
2146 MDIO_PMA_DEVAD, 2174 MDIO_PMA_DEVAD,
2147 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 2175 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2148 2176
2149 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, 2177 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2150 MDIO_PMA_DEVAD, 2178 ext_phy_addr,
2151 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 2179 MDIO_PMA_DEVAD,
2152 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, 2180 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
2153 MDIO_PMA_DEVAD, 2181 bnx2x_cl45_read(bp, port,
2154 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 2182 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2183 ext_phy_addr,
2184 MDIO_PMA_DEVAD,
2185 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2155 DP(NETIF_MSG_LINK, "8073 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2); 2186 DP(NETIF_MSG_LINK, "8073 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
2156 2187
2157 /* Only set bit 10 = 1 (Tx power down) */ 2188}
2158 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2159 MDIO_PMA_DEVAD,
2160 MDIO_PMA_REG_TX_POWER_DOWN, &val);
2161 2189
2190static void bnx2x_bcm807x_force_10G(struct link_params *params)
2191{
2192 struct bnx2x *bp = params->bp;
2193 u8 port = params->port;
2194 u8 ext_phy_addr = ((params->ext_phy_config &
2195 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2196 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2197 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2198
2199 /* Force KR or KX */
2162 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2200 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2163 MDIO_PMA_DEVAD, 2201 MDIO_PMA_DEVAD,
2164 MDIO_PMA_REG_TX_POWER_DOWN, (val | 1<<10)); 2202 MDIO_PMA_REG_CTRL,
2165 2203 0x2040);
2166 msleep(600);
2167 /* Release bit 10 (Release Tx power down) */
2168 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2204 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2169 MDIO_PMA_DEVAD, 2205 MDIO_PMA_DEVAD,
2170 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 2206 MDIO_PMA_REG_10G_CTRL2,
2171 2207 0x000b);
2208 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2209 MDIO_PMA_DEVAD,
2210 MDIO_PMA_REG_BCM_CTRL,
2211 0x0000);
2212 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2213 MDIO_AN_DEVAD,
2214 MDIO_AN_REG_CTRL,
2215 0x0000);
2172} 2216}
2173
2174static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params) 2217static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
2175{ 2218{
2176 struct bnx2x *bp = params->bp; 2219 struct bnx2x *bp = params->bp;
@@ -2236,32 +2279,51 @@ static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
2236 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2279 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2237 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val); 2280 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
2238} 2281}
2239static void bnx2x_bcm807x_force_10G(struct link_params *params) 2282
2283static void bnx2x_8073_set_pause_cl37(struct link_params *params,
2284 struct link_vars *vars)
2240{ 2285{
2286
2241 struct bnx2x *bp = params->bp; 2287 struct bnx2x *bp = params->bp;
2242 u8 port = params->port; 2288 u16 cl37_val;
2243 u8 ext_phy_addr = ((params->ext_phy_config & 2289 u8 ext_phy_addr = ((params->ext_phy_config &
2244 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> 2290 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2245 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); 2291 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2246 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); 2292 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2247 2293
2248 /* Force KR or KX */ 2294 bnx2x_cl45_read(bp, params->port,
2249 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2295 ext_phy_type,
2250 MDIO_PMA_DEVAD, 2296 ext_phy_addr,
2251 MDIO_PMA_REG_CTRL, 2297 MDIO_AN_DEVAD,
2252 0x2040); 2298 MDIO_AN_REG_CL37_FC_LD, &cl37_val);
2253 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2299
2254 MDIO_PMA_DEVAD, 2300 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2255 MDIO_PMA_REG_10G_CTRL2, 2301 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
2256 0x000b); 2302
2257 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2303 if ((vars->ieee_fc &
2258 MDIO_PMA_DEVAD, 2304 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
2259 MDIO_PMA_REG_BCM_CTRL, 2305 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
2260 0x0000); 2306 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
2261 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, 2307 }
2308 if ((vars->ieee_fc &
2309 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
2310 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
2311 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2312 }
2313 if ((vars->ieee_fc &
2314 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
2315 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
2316 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2317 }
2318 DP(NETIF_MSG_LINK,
2319 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
2320
2321 bnx2x_cl45_write(bp, params->port,
2322 ext_phy_type,
2323 ext_phy_addr,
2262 MDIO_AN_DEVAD, 2324 MDIO_AN_DEVAD,
2263 MDIO_AN_REG_CTRL, 2325 MDIO_AN_REG_CL37_FC_LD, cl37_val);
2264 0x0000); 2326 msleep(500);
2265} 2327}
2266 2328
2267static void bnx2x_ext_phy_set_pause(struct link_params *params, 2329static void bnx2x_ext_phy_set_pause(struct link_params *params,
@@ -2282,13 +2344,16 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
2282 MDIO_AN_REG_ADV_PAUSE, &val); 2344 MDIO_AN_REG_ADV_PAUSE, &val);
2283 2345
2284 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 2346 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
2347
2285 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 2348 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
2286 2349
2287 if (vars->ieee_fc & 2350 if ((vars->ieee_fc &
2351 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
2288 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 2352 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
2289 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 2353 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
2290 } 2354 }
2291 if (vars->ieee_fc & 2355 if ((vars->ieee_fc &
2356 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
2292 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 2357 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
2293 val |= 2358 val |=
2294 MDIO_AN_REG_ADV_PAUSE_PAUSE; 2359 MDIO_AN_REG_ADV_PAUSE_PAUSE;
@@ -2302,6 +2367,65 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
2302 MDIO_AN_REG_ADV_PAUSE, val); 2367 MDIO_AN_REG_ADV_PAUSE, val);
2303} 2368}
2304 2369
2370
2371static void bnx2x_init_internal_phy(struct link_params *params,
2372 struct link_vars *vars)
2373{
2374 struct bnx2x *bp = params->bp;
2375 u8 port = params->port;
2376 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2377 u16 bank, rx_eq;
2378
2379 rx_eq = ((params->serdes_config &
2380 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
2381 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
2382
2383 DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq);
2384 for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
2385 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) {
2386 CL45_WR_OVER_CL22(bp, port,
2387 params->phy_addr,
2388 bank ,
2389 MDIO_RX0_RX_EQ_BOOST,
2390 ((rx_eq &
2391 MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
2392 MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
2393 }
2394
2395 /* forced speed requested? */
2396 if (vars->line_speed != SPEED_AUTO_NEG) {
2397 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2398
2399 /* disable autoneg */
2400 bnx2x_set_autoneg(params, vars);
2401
2402 /* program speed and duplex */
2403 bnx2x_program_serdes(params, vars);
2404
2405 } else { /* AN_mode */
2406 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2407
2408 /* AN enabled */
2409 bnx2x_set_brcm_cl37_advertisment(params);
2410
2411 /* program duplex & pause advertisement (for aneg) */
2412 bnx2x_set_ieee_aneg_advertisment(params,
2413 vars->ieee_fc);
2414
2415 /* enable autoneg */
2416 bnx2x_set_autoneg(params, vars);
2417
2418 /* enable and restart AN */
2419 bnx2x_restart_autoneg(params);
2420 }
2421
2422 } else { /* SGMII mode */
2423 DP(NETIF_MSG_LINK, "SGMII\n");
2424
2425 bnx2x_initialize_sgmii_process(params, vars);
2426 }
2427}
2428
2305static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) 2429static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2306{ 2430{
2307 struct bnx2x *bp = params->bp; 2431 struct bnx2x *bp = params->bp;
@@ -2343,7 +2467,6 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2343 2467
2344 switch (ext_phy_type) { 2468 switch (ext_phy_type) {
2345 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 2469 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2346 DP(NETIF_MSG_LINK, "XGXS Direct\n");
2347 break; 2470 break;
2348 2471
2349 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 2472 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
@@ -2419,7 +2542,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2419 ext_phy_type, 2542 ext_phy_type,
2420 ext_phy_addr, 2543 ext_phy_addr,
2421 MDIO_AN_DEVAD, 2544 MDIO_AN_DEVAD,
2422 MDIO_AN_REG_CL37_FD, 2545 MDIO_AN_REG_CL37_FC_LP,
2423 0x0020); 2546 0x0020);
2424 /* Enable CL37 AN */ 2547 /* Enable CL37 AN */
2425 bnx2x_cl45_write(bp, params->port, 2548 bnx2x_cl45_write(bp, params->port,
@@ -2458,54 +2581,43 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2458 rx_alarm_ctrl_val = 0x400; 2581 rx_alarm_ctrl_val = 0x400;
2459 lasi_ctrl_val = 0x0004; 2582 lasi_ctrl_val = 0x0004;
2460 } else { 2583 } else {
2461 /* In 8073, port1 is directed through emac0 and
2462 * port0 is directed through emac1
2463 */
2464 rx_alarm_ctrl_val = (1<<2); 2584 rx_alarm_ctrl_val = (1<<2);
2465 /*lasi_ctrl_val = 0x0005;*/
2466 lasi_ctrl_val = 0x0004; 2585 lasi_ctrl_val = 0x0004;
2467 } 2586 }
2468 2587
2469 /* Wait for soft reset to get cleared upto 1 sec */ 2588 /* enable LASI */
2470 for (cnt = 0; cnt < 1000; cnt++) { 2589 bnx2x_cl45_write(bp, params->port,
2471 bnx2x_cl45_read(bp, params->port, 2590 ext_phy_type,
2472 ext_phy_type, 2591 ext_phy_addr,
2473 ext_phy_addr, 2592 MDIO_PMA_DEVAD,
2474 MDIO_PMA_DEVAD, 2593 MDIO_PMA_REG_RX_ALARM_CTRL,
2475 MDIO_PMA_REG_CTRL, 2594 rx_alarm_ctrl_val);
2476 &ctrl); 2595
2477 if (!(ctrl & (1<<15))) 2596 bnx2x_cl45_write(bp, params->port,
2478 break; 2597 ext_phy_type,
2479 msleep(1); 2598 ext_phy_addr,
2480 } 2599 MDIO_PMA_DEVAD,
2481 DP(NETIF_MSG_LINK, 2600 MDIO_PMA_REG_LASI_CTRL,
2482 "807x control reg 0x%x (after %d ms)\n", 2601 lasi_ctrl_val);
2483 ctrl, cnt); 2602
2603 bnx2x_8073_set_pause_cl37(params, vars);
2484 2604
2485 if (ext_phy_type == 2605 if (ext_phy_type ==
2486 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){ 2606 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){
2487 bnx2x_bcm8072_external_rom_boot(params); 2607 bnx2x_bcm8072_external_rom_boot(params);
2488 } else { 2608 } else {
2489 bnx2x_bcm8073_external_rom_boot(params); 2609
2490 /* In case of 8073 with long xaui lines, 2610 /* In case of 8073 with long xaui lines,
2491 don't set the 8073 xaui low power*/ 2611 don't set the 8073 xaui low power*/
2492 bnx2x_bcm8073_set_xaui_low_power_mode(params); 2612 bnx2x_bcm8073_set_xaui_low_power_mode(params);
2493 } 2613 }
2494 2614
2495 /* enable LASI */ 2615 bnx2x_cl45_read(bp, params->port,
2496 bnx2x_cl45_write(bp, params->port, 2616 ext_phy_type,
2497 ext_phy_type, 2617 ext_phy_addr,
2498 ext_phy_addr, 2618 MDIO_PMA_DEVAD,
2499 MDIO_PMA_DEVAD, 2619 0xca13,
2500 MDIO_PMA_REG_RX_ALARM_CTRL, 2620 &tmp1);
2501 rx_alarm_ctrl_val);
2502
2503 bnx2x_cl45_write(bp, params->port,
2504 ext_phy_type,
2505 ext_phy_addr,
2506 MDIO_PMA_DEVAD,
2507 MDIO_PMA_REG_LASI_CTRL,
2508 lasi_ctrl_val);
2509 2621
2510 bnx2x_cl45_read(bp, params->port, 2622 bnx2x_cl45_read(bp, params->port,
2511 ext_phy_type, 2623 ext_phy_type,
@@ -2519,12 +2631,21 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2519 /* If this is forced speed, set to KR or KX 2631 /* If this is forced speed, set to KR or KX
2520 * (all other are not supported) 2632 * (all other are not supported)
2521 */ 2633 */
2522 if (!(params->req_line_speed == SPEED_AUTO_NEG)) { 2634 if (params->loopback_mode == LOOPBACK_EXT) {
2523 if (params->req_line_speed == SPEED_10000) { 2635 bnx2x_bcm807x_force_10G(params);
2524 bnx2x_bcm807x_force_10G(params); 2636 DP(NETIF_MSG_LINK,
2525 DP(NETIF_MSG_LINK, 2637 "Forced speed 10G on 807X\n");
2526 "Forced speed 10G on 807X\n"); 2638 break;
2527 break; 2639 } else {
2640 bnx2x_cl45_write(bp, params->port,
2641 ext_phy_type, ext_phy_addr,
2642 MDIO_PMA_DEVAD,
2643 MDIO_PMA_REG_BCM_CTRL,
2644 0x0002);
2645 }
2646 if (params->req_line_speed != SPEED_AUTO_NEG) {
2647 if (params->req_line_speed == SPEED_10000) {
2648 val = (1<<7);
2528 } else if (params->req_line_speed == 2649 } else if (params->req_line_speed ==
2529 SPEED_2500) { 2650 SPEED_2500) {
2530 val = (1<<5); 2651 val = (1<<5);
@@ -2539,11 +2660,14 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2539 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2660 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2540 val |= (1<<7); 2661 val |= (1<<7);
2541 2662
2663 /* Note that 2.5G works only when
2664 used with 1G advertisment */
2542 if (params->speed_cap_mask & 2665 if (params->speed_cap_mask &
2543 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 2666 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
2667 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
2544 val |= (1<<5); 2668 val |= (1<<5);
2545 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); 2669 DP(NETIF_MSG_LINK,
2546 /*val = ((1<<5)|(1<<7));*/ 2670 "807x autoneg val = 0x%x\n", val);
2547 } 2671 }
2548 2672
2549 bnx2x_cl45_write(bp, params->port, 2673 bnx2x_cl45_write(bp, params->port,
@@ -2554,20 +2678,19 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2554 2678
2555 if (ext_phy_type == 2679 if (ext_phy_type ==
2556 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { 2680 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
2557 /* Disable 2.5Ghz */ 2681
2558 bnx2x_cl45_read(bp, params->port, 2682 bnx2x_cl45_read(bp, params->port,
2559 ext_phy_type, 2683 ext_phy_type,
2560 ext_phy_addr, 2684 ext_phy_addr,
2561 MDIO_AN_DEVAD, 2685 MDIO_AN_DEVAD,
2562 0x8329, &tmp1); 2686 0x8329, &tmp1);
2563/* SUPPORT_SPEED_CAPABILITY 2687
2564 (Due to the nature of the link order, its not 2688 if (((params->speed_cap_mask &
2565 possible to enable 2.5G within the autoneg 2689 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
2566 capabilities) 2690 (params->req_line_speed ==
2567 if (params->speed_cap_mask & 2691 SPEED_AUTO_NEG)) ||
2568 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 2692 (params->req_line_speed ==
2569*/ 2693 SPEED_2500)) {
2570 if (params->req_line_speed == SPEED_2500) {
2571 u16 phy_ver; 2694 u16 phy_ver;
2572 /* Allow 2.5G for A1 and above */ 2695 /* Allow 2.5G for A1 and above */
2573 bnx2x_cl45_read(bp, params->port, 2696 bnx2x_cl45_read(bp, params->port,
@@ -2575,49 +2698,53 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2575 ext_phy_addr, 2698 ext_phy_addr,
2576 MDIO_PMA_DEVAD, 2699 MDIO_PMA_DEVAD,
2577 0xc801, &phy_ver); 2700 0xc801, &phy_ver);
2578 2701 DP(NETIF_MSG_LINK, "Add 2.5G\n");
2579 if (phy_ver > 0) 2702 if (phy_ver > 0)
2580 tmp1 |= 1; 2703 tmp1 |= 1;
2581 else 2704 else
2582 tmp1 &= 0xfffe; 2705 tmp1 &= 0xfffe;
2583 } 2706 } else {
2584 else 2707 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
2585 tmp1 &= 0xfffe; 2708 tmp1 &= 0xfffe;
2709 }
2586 2710
2587 bnx2x_cl45_write(bp, params->port, 2711 bnx2x_cl45_write(bp, params->port,
2588 ext_phy_type, 2712 ext_phy_type,
2589 ext_phy_addr, 2713 ext_phy_addr,
2590 MDIO_AN_DEVAD, 2714 MDIO_AN_DEVAD,
2591 0x8329, tmp1); 2715 0x8329, tmp1);
2592 } 2716 }
2593 /* Add support for CL37 (passive mode) I */ 2717
2594 bnx2x_cl45_write(bp, params->port, 2718 /* Add support for CL37 (passive mode) II */
2719
2720 bnx2x_cl45_read(bp, params->port,
2595 ext_phy_type, 2721 ext_phy_type,
2596 ext_phy_addr, 2722 ext_phy_addr,
2597 MDIO_AN_DEVAD, 2723 MDIO_AN_DEVAD,
2598 MDIO_AN_REG_CL37_CL73, 0x040c); 2724 MDIO_AN_REG_CL37_FC_LD,
2599 /* Add support for CL37 (passive mode) II */ 2725 &tmp1);
2726
2600 bnx2x_cl45_write(bp, params->port, 2727 bnx2x_cl45_write(bp, params->port,
2601 ext_phy_type, 2728 ext_phy_type,
2602 ext_phy_addr, 2729 ext_phy_addr,
2603 MDIO_AN_DEVAD, 2730 MDIO_AN_DEVAD,
2604 MDIO_AN_REG_CL37_FD, 0x20); 2731 MDIO_AN_REG_CL37_FC_LD, (tmp1 |
2732 ((params->req_duplex == DUPLEX_FULL) ?
2733 0x20 : 0x40)));
2734
2605 /* Add support for CL37 (passive mode) III */ 2735 /* Add support for CL37 (passive mode) III */
2606 bnx2x_cl45_write(bp, params->port, 2736 bnx2x_cl45_write(bp, params->port,
2607 ext_phy_type, 2737 ext_phy_type,
2608 ext_phy_addr, 2738 ext_phy_addr,
2609 MDIO_AN_DEVAD, 2739 MDIO_AN_DEVAD,
2610 MDIO_AN_REG_CL37_AN, 0x1000); 2740 MDIO_AN_REG_CL37_AN, 0x1000);
2611 /* Restart autoneg */
2612 msleep(500);
2613 2741
2614 if (ext_phy_type == 2742 if (ext_phy_type ==
2615 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { 2743 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
2616 2744 /* The SNR will improve about 2db by changing
2617 /* The SNR will improve about 2db by changing the
2618 BW and FEE main tap. Rest commands are executed 2745 BW and FEE main tap. Rest commands are executed
2619 after link is up*/ 2746 after link is up*/
2620 /* Change FFE main cursor to 5 in EDC register */ 2747 /*Change FFE main cursor to 5 in EDC register*/
2621 if (bnx2x_8073_is_snr_needed(params)) 2748 if (bnx2x_8073_is_snr_needed(params))
2622 bnx2x_cl45_write(bp, params->port, 2749 bnx2x_cl45_write(bp, params->port,
2623 ext_phy_type, 2750 ext_phy_type,
@@ -2626,25 +2753,28 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2626 MDIO_PMA_REG_EDC_FFE_MAIN, 2753 MDIO_PMA_REG_EDC_FFE_MAIN,
2627 0xFB0C); 2754 0xFB0C);
2628 2755
2629 /* Enable FEC (Forware Error Correction) 2756 /* Enable FEC (Forware Error Correction)
2630 Request in the AN */ 2757 Request in the AN */
2631 bnx2x_cl45_read(bp, params->port, 2758 bnx2x_cl45_read(bp, params->port,
2632 ext_phy_type, 2759 ext_phy_type,
2633 ext_phy_addr, 2760 ext_phy_addr,
2634 MDIO_AN_DEVAD, 2761 MDIO_AN_DEVAD,
2635 MDIO_AN_REG_ADV2, &tmp1); 2762 MDIO_AN_REG_ADV2, &tmp1);
2636 2763
2637 tmp1 |= (1<<15); 2764 tmp1 |= (1<<15);
2765
2766 bnx2x_cl45_write(bp, params->port,
2767 ext_phy_type,
2768 ext_phy_addr,
2769 MDIO_AN_DEVAD,
2770 MDIO_AN_REG_ADV2, tmp1);
2638 2771
2639 bnx2x_cl45_write(bp, params->port,
2640 ext_phy_type,
2641 ext_phy_addr,
2642 MDIO_AN_DEVAD,
2643 MDIO_AN_REG_ADV2, tmp1);
2644 } 2772 }
2645 2773
2646 bnx2x_ext_phy_set_pause(params, vars); 2774 bnx2x_ext_phy_set_pause(params, vars);
2647 2775
2776 /* Restart autoneg */
2777 msleep(500);
2648 bnx2x_cl45_write(bp, params->port, 2778 bnx2x_cl45_write(bp, params->port,
2649 ext_phy_type, 2779 ext_phy_type,
2650 ext_phy_addr, 2780 ext_phy_addr,
@@ -2701,10 +2831,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2701 } 2831 }
2702 2832
2703 } else { /* SerDes */ 2833 } else { /* SerDes */
2704/* ext_phy_addr = ((bp->ext_phy_config & 2834
2705 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >>
2706 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT);
2707*/
2708 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config); 2835 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
2709 switch (ext_phy_type) { 2836 switch (ext_phy_type) {
2710 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT: 2837 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
@@ -2726,7 +2853,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2726 2853
2727 2854
2728static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, 2855static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2729 struct link_vars *vars) 2856 struct link_vars *vars)
2730{ 2857{
2731 struct bnx2x *bp = params->bp; 2858 struct bnx2x *bp = params->bp;
2732 u32 ext_phy_type; 2859 u32 ext_phy_type;
@@ -2767,6 +2894,8 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2767 MDIO_PMA_REG_RX_SD, &rx_sd); 2894 MDIO_PMA_REG_RX_SD, &rx_sd);
2768 DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd); 2895 DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd);
2769 ext_phy_link_up = (rx_sd & 0x1); 2896 ext_phy_link_up = (rx_sd & 0x1);
2897 if (ext_phy_link_up)
2898 vars->line_speed = SPEED_10000;
2770 break; 2899 break;
2771 2900
2772 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 2901 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
@@ -2810,6 +2939,13 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2810 */ 2939 */
2811 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) || 2940 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
2812 (val2 & (1<<1))); 2941 (val2 & (1<<1)));
2942 if (ext_phy_link_up) {
2943 if (val2 & (1<<1))
2944 vars->line_speed = SPEED_1000;
2945 else
2946 vars->line_speed = SPEED_10000;
2947 }
2948
2813 /* clear LASI indication*/ 2949 /* clear LASI indication*/
2814 bnx2x_cl45_read(bp, params->port, ext_phy_type, 2950 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2815 ext_phy_addr, 2951 ext_phy_addr,
@@ -2820,6 +2956,8 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2820 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: 2956 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2821 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 2957 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
2822 { 2958 {
2959 u16 link_status = 0;
2960 u16 an1000_status = 0;
2823 if (ext_phy_type == 2961 if (ext_phy_type ==
2824 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) { 2962 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
2825 bnx2x_cl45_read(bp, params->port, 2963 bnx2x_cl45_read(bp, params->port,
@@ -2846,14 +2984,9 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2846 MDIO_PMA_DEVAD, 2984 MDIO_PMA_DEVAD,
2847 MDIO_PMA_REG_LASI_STATUS, &val1); 2985 MDIO_PMA_REG_LASI_STATUS, &val1);
2848 2986
2849 bnx2x_cl45_read(bp, params->port,
2850 ext_phy_type,
2851 ext_phy_addr,
2852 MDIO_PMA_DEVAD,
2853 MDIO_PMA_REG_LASI_STATUS, &val2);
2854 DP(NETIF_MSG_LINK, 2987 DP(NETIF_MSG_LINK,
2855 "8703 LASI status 0x%x->0x%x\n", 2988 "8703 LASI status 0x%x\n",
2856 val1, val2); 2989 val1);
2857 } 2990 }
2858 2991
2859 /* clear the interrupt LASI status register */ 2992 /* clear the interrupt LASI status register */
@@ -2869,20 +3002,23 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2869 MDIO_PCS_REG_STATUS, &val1); 3002 MDIO_PCS_REG_STATUS, &val1);
2870 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", 3003 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n",
2871 val2, val1); 3004 val2, val1);
2872 /* Check the LASI */ 3005 /* Clear MSG-OUT */
2873 bnx2x_cl45_read(bp, params->port, 3006 bnx2x_cl45_read(bp, params->port,
2874 ext_phy_type, 3007 ext_phy_type,
2875 ext_phy_addr, 3008 ext_phy_addr,
2876 MDIO_PMA_DEVAD, 3009 MDIO_PMA_DEVAD,
2877 MDIO_PMA_REG_RX_ALARM, &val2); 3010 0xca13,
3011 &val1);
3012
3013 /* Check the LASI */
2878 bnx2x_cl45_read(bp, params->port, 3014 bnx2x_cl45_read(bp, params->port,
2879 ext_phy_type, 3015 ext_phy_type,
2880 ext_phy_addr, 3016 ext_phy_addr,
2881 MDIO_PMA_DEVAD, 3017 MDIO_PMA_DEVAD,
2882 MDIO_PMA_REG_RX_ALARM, 3018 MDIO_PMA_REG_RX_ALARM, &val2);
2883 &val1); 3019
2884 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x->0x%x\n", 3020 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
2885 val2, val1); 3021
2886 /* Check the link status */ 3022 /* Check the link status */
2887 bnx2x_cl45_read(bp, params->port, 3023 bnx2x_cl45_read(bp, params->port,
2888 ext_phy_type, 3024 ext_phy_type,
@@ -2905,29 +3041,29 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2905 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); 3041 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
2906 if (ext_phy_type == 3042 if (ext_phy_type ==
2907 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { 3043 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
2908 u16 an1000_status = 0; 3044
2909 if (ext_phy_link_up && 3045 if (ext_phy_link_up &&
2910 ( 3046 ((params->req_line_speed !=
2911 (params->req_line_speed != SPEED_10000) 3047 SPEED_10000))) {
2912 )) {
2913 if (bnx2x_bcm8073_xaui_wa(params) 3048 if (bnx2x_bcm8073_xaui_wa(params)
2914 != 0) { 3049 != 0) {
2915 ext_phy_link_up = 0; 3050 ext_phy_link_up = 0;
2916 break; 3051 break;
2917 } 3052 }
2918 bnx2x_cl45_read(bp, params->port, 3053 }
3054 bnx2x_cl45_read(bp, params->port,
2919 ext_phy_type, 3055 ext_phy_type,
2920 ext_phy_addr, 3056 ext_phy_addr,
2921 MDIO_XS_DEVAD, 3057 MDIO_AN_DEVAD,
2922 0x8304, 3058 0x8304,
2923 &an1000_status); 3059 &an1000_status);
2924 bnx2x_cl45_read(bp, params->port, 3060 bnx2x_cl45_read(bp, params->port,
2925 ext_phy_type, 3061 ext_phy_type,
2926 ext_phy_addr, 3062 ext_phy_addr,
2927 MDIO_XS_DEVAD, 3063 MDIO_AN_DEVAD,
2928 0x8304, 3064 0x8304,
2929 &an1000_status); 3065 &an1000_status);
2930 } 3066
2931 /* Check the link status on 1.1.2 */ 3067 /* Check the link status on 1.1.2 */
2932 bnx2x_cl45_read(bp, params->port, 3068 bnx2x_cl45_read(bp, params->port,
2933 ext_phy_type, 3069 ext_phy_type,
@@ -2943,8 +3079,8 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2943 "an_link_status=0x%x\n", 3079 "an_link_status=0x%x\n",
2944 val2, val1, an1000_status); 3080 val2, val1, an1000_status);
2945 3081
2946 ext_phy_link_up = (((val1 & 4) == 4) || 3082 ext_phy_link_up = (((val1 & 4) == 4) ||
2947 (an1000_status & (1<<1))); 3083 (an1000_status & (1<<1)));
2948 if (ext_phy_link_up && 3084 if (ext_phy_link_up &&
2949 bnx2x_8073_is_snr_needed(params)) { 3085 bnx2x_8073_is_snr_needed(params)) {
2950 /* The SNR will improve about 2dbby 3086 /* The SNR will improve about 2dbby
@@ -2968,8 +3104,74 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2968 MDIO_PMA_REG_CDR_BANDWIDTH, 3104 MDIO_PMA_REG_CDR_BANDWIDTH,
2969 0x0333); 3105 0x0333);
2970 3106
3107
3108 }
3109 bnx2x_cl45_read(bp, params->port,
3110 ext_phy_type,
3111 ext_phy_addr,
3112 MDIO_PMA_DEVAD,
3113 0xc820,
3114 &link_status);
3115
3116 /* Bits 0..2 --> speed detected,
3117 bits 13..15--> link is down */
3118 if ((link_status & (1<<2)) &&
3119 (!(link_status & (1<<15)))) {
3120 ext_phy_link_up = 1;
3121 vars->line_speed = SPEED_10000;
3122 DP(NETIF_MSG_LINK,
3123 "port %x: External link"
3124 " up in 10G\n", params->port);
3125 } else if ((link_status & (1<<1)) &&
3126 (!(link_status & (1<<14)))) {
3127 ext_phy_link_up = 1;
3128 vars->line_speed = SPEED_2500;
3129 DP(NETIF_MSG_LINK,
3130 "port %x: External link"
3131 " up in 2.5G\n", params->port);
3132 } else if ((link_status & (1<<0)) &&
3133 (!(link_status & (1<<13)))) {
3134 ext_phy_link_up = 1;
3135 vars->line_speed = SPEED_1000;
3136 DP(NETIF_MSG_LINK,
3137 "port %x: External link"
3138 " up in 1G\n", params->port);
3139 } else {
3140 ext_phy_link_up = 0;
3141 DP(NETIF_MSG_LINK,
3142 "port %x: External link"
3143 " is down\n", params->port);
3144 }
3145 } else {
3146 /* See if 1G link is up for the 8072 */
3147 bnx2x_cl45_read(bp, params->port,
3148 ext_phy_type,
3149 ext_phy_addr,
3150 MDIO_AN_DEVAD,
3151 0x8304,
3152 &an1000_status);
3153 bnx2x_cl45_read(bp, params->port,
3154 ext_phy_type,
3155 ext_phy_addr,
3156 MDIO_AN_DEVAD,
3157 0x8304,
3158 &an1000_status);
3159 if (an1000_status & (1<<1)) {
3160 ext_phy_link_up = 1;
3161 vars->line_speed = SPEED_1000;
3162 DP(NETIF_MSG_LINK,
3163 "port %x: External link"
3164 " up in 1G\n", params->port);
3165 } else if (ext_phy_link_up) {
3166 ext_phy_link_up = 1;
3167 vars->line_speed = SPEED_10000;
3168 DP(NETIF_MSG_LINK,
3169 "port %x: External link"
3170 " up in 10G\n", params->port);
2971 } 3171 }
2972 } 3172 }
3173
3174
2973 break; 3175 break;
2974 } 3176 }
2975 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 3177 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
@@ -3006,6 +3208,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
3006 MDIO_AN_DEVAD, 3208 MDIO_AN_DEVAD,
3007 MDIO_AN_REG_MASTER_STATUS, 3209 MDIO_AN_REG_MASTER_STATUS,
3008 &val2); 3210 &val2);
3211 vars->line_speed = SPEED_10000;
3009 DP(NETIF_MSG_LINK, 3212 DP(NETIF_MSG_LINK,
3010 "SFX7101 AN status 0x%x->Master=%x\n", 3213 "SFX7101 AN status 0x%x->Master=%x\n",
3011 val2, 3214 val2,
@@ -3100,7 +3303,7 @@ static void bnx2x_link_int_enable(struct link_params *params)
3100 * link management 3303 * link management
3101 */ 3304 */
3102static void bnx2x_link_int_ack(struct link_params *params, 3305static void bnx2x_link_int_ack(struct link_params *params,
3103 struct link_vars *vars, u16 is_10g) 3306 struct link_vars *vars, u8 is_10g)
3104{ 3307{
3105 struct bnx2x *bp = params->bp; 3308 struct bnx2x *bp = params->bp;
3106 u8 port = params->port; 3309 u8 port = params->port;
@@ -3181,7 +3384,8 @@ static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
3181} 3384}
3182 3385
3183 3386
3184static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr) 3387static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,
3388 u32 ext_phy_type)
3185{ 3389{
3186 u32 cnt = 0; 3390 u32 cnt = 0;
3187 u16 ctrl = 0; 3391 u16 ctrl = 0;
@@ -3192,12 +3396,14 @@ static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
3192 3396
3193 /* take ext phy out of reset */ 3397 /* take ext phy out of reset */
3194 bnx2x_set_gpio(bp, 3398 bnx2x_set_gpio(bp,
3195 MISC_REGISTERS_GPIO_2, 3399 MISC_REGISTERS_GPIO_2,
3196 MISC_REGISTERS_GPIO_HIGH); 3400 MISC_REGISTERS_GPIO_HIGH,
3401 port);
3197 3402
3198 bnx2x_set_gpio(bp, 3403 bnx2x_set_gpio(bp,
3199 MISC_REGISTERS_GPIO_1, 3404 MISC_REGISTERS_GPIO_1,
3200 MISC_REGISTERS_GPIO_HIGH); 3405 MISC_REGISTERS_GPIO_HIGH,
3406 port);
3201 3407
3202 /* wait for 5ms */ 3408 /* wait for 5ms */
3203 msleep(5); 3409 msleep(5);
@@ -3205,7 +3411,7 @@ static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
3205 for (cnt = 0; cnt < 1000; cnt++) { 3411 for (cnt = 0; cnt < 1000; cnt++) {
3206 msleep(1); 3412 msleep(1);
3207 bnx2x_cl45_read(bp, port, 3413 bnx2x_cl45_read(bp, port,
3208 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 3414 ext_phy_type,
3209 ext_phy_addr, 3415 ext_phy_addr,
3210 MDIO_PMA_DEVAD, 3416 MDIO_PMA_DEVAD,
3211 MDIO_PMA_REG_CTRL, 3417 MDIO_PMA_REG_CTRL,
@@ -3217,13 +3423,17 @@ static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
3217 } 3423 }
3218} 3424}
3219 3425
3220static void bnx2x_turn_off_sf(struct bnx2x *bp) 3426static void bnx2x_turn_off_sf(struct bnx2x *bp, u8 port)
3221{ 3427{
3222 /* put sf to reset */ 3428 /* put sf to reset */
3223 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, MISC_REGISTERS_GPIO_LOW);
3224 bnx2x_set_gpio(bp, 3429 bnx2x_set_gpio(bp,
3225 MISC_REGISTERS_GPIO_2, 3430 MISC_REGISTERS_GPIO_1,
3226 MISC_REGISTERS_GPIO_LOW); 3431 MISC_REGISTERS_GPIO_LOW,
3432 port);
3433 bnx2x_set_gpio(bp,
3434 MISC_REGISTERS_GPIO_2,
3435 MISC_REGISTERS_GPIO_LOW,
3436 port);
3227} 3437}
3228 3438
3229u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, 3439u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
@@ -3253,7 +3463,8 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3253 3463
3254 /* Take ext phy out of reset */ 3464 /* Take ext phy out of reset */
3255 if (!driver_loaded) 3465 if (!driver_loaded)
3256 bnx2x_turn_on_sf(bp, params->port, ext_phy_addr); 3466 bnx2x_turn_on_ef(bp, params->port, ext_phy_addr,
3467 ext_phy_type);
3257 3468
3258 /* wait for 1ms */ 3469 /* wait for 1ms */
3259 msleep(1); 3470 msleep(1);
@@ -3276,11 +3487,16 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3276 version[4] = '\0'; 3487 version[4] = '\0';
3277 3488
3278 if (!driver_loaded) 3489 if (!driver_loaded)
3279 bnx2x_turn_off_sf(bp); 3490 bnx2x_turn_off_sf(bp, params->port);
3280 break; 3491 break;
3281 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: 3492 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3282 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 3493 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
3283 { 3494 {
3495 /* Take ext phy out of reset */
3496 if (!driver_loaded)
3497 bnx2x_turn_on_ef(bp, params->port, ext_phy_addr,
3498 ext_phy_type);
3499
3284 bnx2x_cl45_read(bp, params->port, ext_phy_type, 3500 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3285 ext_phy_addr, 3501 ext_phy_addr,
3286 MDIO_PMA_DEVAD, 3502 MDIO_PMA_DEVAD,
@@ -3333,7 +3549,7 @@ static void bnx2x_set_xgxs_loopback(struct link_params *params,
3333 struct bnx2x *bp = params->bp; 3549 struct bnx2x *bp = params->bp;
3334 3550
3335 if (is_10g) { 3551 if (is_10g) {
3336 u32 md_devad; 3552 u32 md_devad;
3337 3553
3338 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); 3554 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3339 3555
@@ -3553,6 +3769,8 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
3553 u16 hw_led_mode, u32 chip_id) 3769 u16 hw_led_mode, u32 chip_id)
3554{ 3770{
3555 u8 rc = 0; 3771 u8 rc = 0;
3772 u32 tmp;
3773 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3556 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 3774 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3557 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 3775 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3558 speed, hw_led_mode); 3776 speed, hw_led_mode);
@@ -3561,6 +3779,9 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
3561 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); 3779 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3562 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 3780 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3563 SHARED_HW_CFG_LED_MAC1); 3781 SHARED_HW_CFG_LED_MAC1);
3782
3783 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3784 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3564 break; 3785 break;
3565 3786
3566 case LED_MODE_OPER: 3787 case LED_MODE_OPER:
@@ -3572,6 +3793,10 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
3572 LED_BLINK_RATE_VAL); 3793 LED_BLINK_RATE_VAL);
3573 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 3794 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3574 port*4, 1); 3795 port*4, 1);
3796 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3797 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3798 (tmp & (~EMAC_LED_OVERRIDE)));
3799
3575 if (!CHIP_IS_E1H(bp) && 3800 if (!CHIP_IS_E1H(bp) &&
3576 ((speed == SPEED_2500) || 3801 ((speed == SPEED_2500) ||
3577 (speed == SPEED_1000) || 3802 (speed == SPEED_1000) ||
@@ -3622,7 +3847,8 @@ static u8 bnx2x_link_initialize(struct link_params *params,
3622 struct bnx2x *bp = params->bp; 3847 struct bnx2x *bp = params->bp;
3623 u8 port = params->port; 3848 u8 port = params->port;
3624 u8 rc = 0; 3849 u8 rc = 0;
3625 3850 u8 non_ext_phy;
3851 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3626 /* Activate the external PHY */ 3852 /* Activate the external PHY */
3627 bnx2x_ext_phy_reset(params, vars); 3853 bnx2x_ext_phy_reset(params, vars);
3628 3854
@@ -3644,10 +3870,6 @@ static u8 bnx2x_link_initialize(struct link_params *params,
3644 bnx2x_set_swap_lanes(params); 3870 bnx2x_set_swap_lanes(params);
3645 } 3871 }
3646 3872
3647 /* Set Parallel Detect */
3648 if (params->req_line_speed == SPEED_AUTO_NEG)
3649 bnx2x_set_parallel_detection(params, vars->phy_flags);
3650
3651 if (vars->phy_flags & PHY_XGXS_FLAG) { 3873 if (vars->phy_flags & PHY_XGXS_FLAG) {
3652 if (params->req_line_speed && 3874 if (params->req_line_speed &&
3653 ((params->req_line_speed == SPEED_100) || 3875 ((params->req_line_speed == SPEED_100) ||
@@ -3657,68 +3879,33 @@ static u8 bnx2x_link_initialize(struct link_params *params,
3657 vars->phy_flags &= ~PHY_SGMII_FLAG; 3879 vars->phy_flags &= ~PHY_SGMII_FLAG;
3658 } 3880 }
3659 } 3881 }
3882 /* In case of external phy existance, the line speed would be the
3883 line speed linked up by the external phy. In case it is direct only,
3884 then the line_speed during initialization will be equal to the
3885 req_line_speed*/
3886 vars->line_speed = params->req_line_speed;
3660 3887
3661 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 3888 bnx2x_calc_ieee_aneg_adv(params, &vars->ieee_fc);
3662 u16 bank, rx_eq;
3663
3664 rx_eq = ((params->serdes_config &
3665 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
3666 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
3667 3889
3668 DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq); 3890 /* init ext phy and enable link state int */
3669 for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL; 3891 non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
3670 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) { 3892 (params->loopback_mode == LOOPBACK_XGXS_10) ||
3671 CL45_WR_OVER_CL22(bp, port, 3893 (params->loopback_mode == LOOPBACK_EXT_PHY));
3672 params->phy_addr, 3894
3673 bank , 3895 if (non_ext_phy ||
3674 MDIO_RX0_RX_EQ_BOOST, 3896 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705)) {
3675 ((rx_eq & 3897 if (params->req_line_speed == SPEED_AUTO_NEG)
3676 MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) | 3898 bnx2x_set_parallel_detection(params, vars->phy_flags);
3677 MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL)); 3899 bnx2x_init_internal_phy(params, vars);
3678 }
3679
3680 /* forced speed requested? */
3681 if (params->req_line_speed != SPEED_AUTO_NEG) {
3682 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3683
3684 /* disable autoneg */
3685 bnx2x_set_autoneg(params, vars);
3686
3687 /* program speed and duplex */
3688 bnx2x_program_serdes(params);
3689 vars->ieee_fc =
3690 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3691
3692 } else { /* AN_mode */
3693 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3694
3695 /* AN enabled */
3696 bnx2x_set_brcm_cl37_advertisment(params);
3697
3698 /* program duplex & pause advertisement (for aneg) */
3699 bnx2x_set_ieee_aneg_advertisment(params,
3700 &vars->ieee_fc);
3701
3702 /* enable autoneg */
3703 bnx2x_set_autoneg(params, vars);
3704
3705 /* enable and restart AN */
3706 bnx2x_restart_autoneg(params);
3707 }
3708
3709 } else { /* SGMII mode */
3710 DP(NETIF_MSG_LINK, "SGMII\n");
3711
3712 bnx2x_initialize_sgmii_process(params);
3713 } 3900 }
3714 3901
3715 /* init ext phy and enable link state int */ 3902 if (!non_ext_phy)
3716 rc |= bnx2x_ext_phy_init(params, vars); 3903 rc |= bnx2x_ext_phy_init(params, vars);
3717 3904
3718 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 3905 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3719 (NIG_STATUS_XGXS0_LINK10G | 3906 (NIG_STATUS_XGXS0_LINK10G |
3720 NIG_STATUS_XGXS0_LINK_STATUS | 3907 NIG_STATUS_XGXS0_LINK_STATUS |
3721 NIG_STATUS_SERDES0_LINK_STATUS)); 3908 NIG_STATUS_SERDES0_LINK_STATUS));
3722 3909
3723 return rc; 3910 return rc;
3724 3911
@@ -3730,15 +3917,23 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
3730 struct bnx2x *bp = params->bp; 3917 struct bnx2x *bp = params->bp;
3731 3918
3732 u32 val; 3919 u32 val;
3733 DP(NETIF_MSG_LINK, "Phy Initialization started\n"); 3920 DP(NETIF_MSG_LINK, "Phy Initialization started \n");
3734 DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n", 3921 DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n",
3735 params->req_line_speed, params->req_flow_ctrl); 3922 params->req_line_speed, params->req_flow_ctrl);
3736 vars->link_status = 0; 3923 vars->link_status = 0;
3924 vars->phy_link_up = 0;
3925 vars->link_up = 0;
3926 vars->line_speed = 0;
3927 vars->duplex = DUPLEX_FULL;
3928 vars->flow_ctrl = FLOW_CTRL_NONE;
3929 vars->mac_type = MAC_TYPE_NONE;
3930
3737 if (params->switch_cfg == SWITCH_CFG_1G) 3931 if (params->switch_cfg == SWITCH_CFG_1G)
3738 vars->phy_flags = PHY_SERDES_FLAG; 3932 vars->phy_flags = PHY_SERDES_FLAG;
3739 else 3933 else
3740 vars->phy_flags = PHY_XGXS_FLAG; 3934 vars->phy_flags = PHY_XGXS_FLAG;
3741 3935
3936
3742 /* disable attentions */ 3937 /* disable attentions */
3743 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 3938 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
3744 (NIG_MASK_XGXS0_LINK_STATUS | 3939 (NIG_MASK_XGXS0_LINK_STATUS |
@@ -3894,6 +4089,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
3894 } 4089 }
3895 4090
3896 bnx2x_link_initialize(params, vars); 4091 bnx2x_link_initialize(params, vars);
4092 msleep(30);
3897 bnx2x_link_int_enable(params); 4093 bnx2x_link_int_enable(params);
3898 } 4094 }
3899 return 0; 4095 return 0;
@@ -3943,39 +4139,22 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
3943 /* HW reset */ 4139 /* HW reset */
3944 4140
3945 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 4141 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3946 MISC_REGISTERS_GPIO_OUTPUT_LOW); 4142 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4143 port);
3947 4144
3948 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 4145 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3949 MISC_REGISTERS_GPIO_OUTPUT_LOW); 4146 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4147 port);
3950 4148
3951 DP(NETIF_MSG_LINK, "reset external PHY\n"); 4149 DP(NETIF_MSG_LINK, "reset external PHY\n");
3952 } else { 4150 } else if (ext_phy_type ==
3953 4151 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
3954 u8 ext_phy_addr = ((ext_phy_config & 4152 DP(NETIF_MSG_LINK, "Setting 8073 port %d into "
3955 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3956 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3957
3958 /* SW reset */
3959 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3960 MDIO_PMA_DEVAD,
3961 MDIO_PMA_REG_CTRL,
3962 1<<15);
3963
3964 /* Set Low Power Mode */
3965 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3966 MDIO_PMA_DEVAD,
3967 MDIO_PMA_REG_CTRL,
3968 1<<11);
3969
3970
3971 if (ext_phy_type ==
3972 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
3973 DP(NETIF_MSG_LINK, "Setting 8073 port %d into"
3974 "low power mode\n", 4153 "low power mode\n",
3975 port); 4154 port);
3976 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 4155 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3977 MISC_REGISTERS_GPIO_OUTPUT_LOW); 4156 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3978 } 4157 port);
3979 } 4158 }
3980 } 4159 }
3981 /* reset the SerDes/XGXS */ 4160 /* reset the SerDes/XGXS */
@@ -3995,6 +4174,73 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
3995 return 0; 4174 return 0;
3996} 4175}
3997 4176
4177static u8 bnx2x_update_link_down(struct link_params *params,
4178 struct link_vars *vars)
4179{
4180 struct bnx2x *bp = params->bp;
4181 u8 port = params->port;
4182 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
4183 bnx2x_set_led(bp, port, LED_MODE_OFF,
4184 0, params->hw_led_mode,
4185 params->chip_id);
4186
4187 /* indicate no mac active */
4188 vars->mac_type = MAC_TYPE_NONE;
4189
4190 /* update shared memory */
4191 vars->link_status = 0;
4192 vars->line_speed = 0;
4193 bnx2x_update_mng(params, vars->link_status);
4194
4195 /* activate nig drain */
4196 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
4197
4198 /* reset BigMac */
4199 bnx2x_bmac_rx_disable(bp, params->port);
4200 REG_WR(bp, GRCBASE_MISC +
4201 MISC_REGISTERS_RESET_REG_2_CLEAR,
4202 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
4203 return 0;
4204}
4205
4206static u8 bnx2x_update_link_up(struct link_params *params,
4207 struct link_vars *vars,
4208 u8 link_10g, u32 gp_status)
4209{
4210 struct bnx2x *bp = params->bp;
4211 u8 port = params->port;
4212 u8 rc = 0;
4213 vars->link_status |= LINK_STATUS_LINK_UP;
4214 if (link_10g) {
4215 bnx2x_bmac_enable(params, vars, 0);
4216 bnx2x_set_led(bp, port, LED_MODE_OPER,
4217 SPEED_10000, params->hw_led_mode,
4218 params->chip_id);
4219
4220 } else {
4221 bnx2x_emac_enable(params, vars, 0);
4222 rc = bnx2x_emac_program(params, vars->line_speed,
4223 vars->duplex);
4224
4225 /* AN complete? */
4226 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
4227 if (!(vars->phy_flags &
4228 PHY_SGMII_FLAG))
4229 bnx2x_set_sgmii_tx_driver(params);
4230 }
4231 }
4232
4233 /* PBF - link up */
4234 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
4235 vars->line_speed);
4236
4237 /* disable drain */
4238 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
4239
4240 /* update shared memory */
4241 bnx2x_update_mng(params, vars->link_status);
4242 return rc;
4243}
3998/* This function should called upon link interrupt */ 4244/* This function should called upon link interrupt */
3999/* In case vars->link_up, driver needs to 4245/* In case vars->link_up, driver needs to
4000 1. Update the pbf 4246 1. Update the pbf
@@ -4012,10 +4258,10 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4012{ 4258{
4013 struct bnx2x *bp = params->bp; 4259 struct bnx2x *bp = params->bp;
4014 u8 port = params->port; 4260 u8 port = params->port;
4015 u16 i;
4016 u16 gp_status; 4261 u16 gp_status;
4017 u16 link_10g; 4262 u8 link_10g;
4018 u8 rc = 0; 4263 u8 ext_phy_link_up, rc = 0;
4264 u32 ext_phy_type;
4019 4265
4020 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", 4266 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
4021 port, 4267 port,
@@ -4031,15 +4277,16 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4031 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 4277 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
4032 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 4278 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
4033 4279
4280 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4034 4281
4035 /* avoid fast toggling */ 4282 /* Check external link change only for non-direct */
4036 for (i = 0; i < 10; i++) { 4283 ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars);
4037 msleep(10); 4284
4038 CL45_RD_OVER_CL22(bp, port, params->phy_addr, 4285 /* Read gp_status */
4039 MDIO_REG_BANK_GP_STATUS, 4286 CL45_RD_OVER_CL22(bp, port, params->phy_addr,
4040 MDIO_GP_STATUS_TOP_AN_STATUS1, 4287 MDIO_REG_BANK_GP_STATUS,
4041 &gp_status); 4288 MDIO_GP_STATUS_TOP_AN_STATUS1,
4042 } 4289 &gp_status);
4043 4290
4044 rc = bnx2x_link_settings_status(params, vars, gp_status); 4291 rc = bnx2x_link_settings_status(params, vars, gp_status);
4045 if (rc != 0) 4292 if (rc != 0)
@@ -4055,73 +4302,177 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4055 4302
4056 bnx2x_link_int_ack(params, vars, link_10g); 4303 bnx2x_link_int_ack(params, vars, link_10g);
4057 4304
4305 /* In case external phy link is up, and internal link is down
4306 ( not initialized yet probably after link initialization, it needs
4307 to be initialized.
4308 Note that after link down-up as result of cable plug,
4309 the xgxs link would probably become up again without the need to
4310 initialize it*/
4311
4312 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
4313 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
4314 (ext_phy_link_up && !vars->phy_link_up))
4315 bnx2x_init_internal_phy(params, vars);
4316
4058 /* link is up only if both local phy and external phy are up */ 4317 /* link is up only if both local phy and external phy are up */
4059 vars->link_up = (vars->phy_link_up && 4318 vars->link_up = (ext_phy_link_up && vars->phy_link_up);
4060 bnx2x_ext_phy_is_link_up(params, vars));
4061 4319
4062 if (!vars->phy_link_up && 4320 if (vars->link_up)
4063 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18)) { 4321 rc = bnx2x_update_link_up(params, vars, link_10g, gp_status);
4064 bnx2x_ext_phy_is_link_up(params, vars); /* Clear interrupt */ 4322 else
4323 rc = bnx2x_update_link_down(params, vars);
4324
4325 return rc;
4326}
4327
4328static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
4329{
4330 u8 ext_phy_addr[PORT_MAX];
4331 u16 val;
4332 s8 port;
4333
4334 /* PART1 - Reset both phys */
4335 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
4336 /* Extract the ext phy address for the port */
4337 u32 ext_phy_config = REG_RD(bp, shmem_base +
4338 offsetof(struct shmem_region,
4339 dev_info.port_hw_config[port].external_phy_config));
4340
4341 /* disable attentions */
4342 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
4343 (NIG_MASK_XGXS0_LINK_STATUS |
4344 NIG_MASK_XGXS0_LINK10G |
4345 NIG_MASK_SERDES0_LINK_STATUS |
4346 NIG_MASK_MI_INT));
4347
4348 ext_phy_addr[port] =
4349 ((ext_phy_config &
4350 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
4351 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4352
4353 /* Need to take the phy out of low power mode in order
4354 to write to access its registers */
4355 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4356 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
4357
4358 /* Reset the phy */
4359 bnx2x_cl45_write(bp, port,
4360 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4361 ext_phy_addr[port],
4362 MDIO_PMA_DEVAD,
4363 MDIO_PMA_REG_CTRL,
4364 1<<15);
4065 } 4365 }
4066 4366
4067 if (vars->link_up) { 4367 /* Add delay of 150ms after reset */
4068 vars->link_status |= LINK_STATUS_LINK_UP; 4368 msleep(150);
4069 if (link_10g) {
4070 bnx2x_bmac_enable(params, vars, 0);
4071 bnx2x_set_led(bp, port, LED_MODE_OPER,
4072 SPEED_10000, params->hw_led_mode,
4073 params->chip_id);
4074 4369
4075 } else { 4370 /* PART2 - Download firmware to both phys */
4076 bnx2x_emac_enable(params, vars, 0); 4371 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
4077 rc = bnx2x_emac_program(params, vars->line_speed, 4372 u16 fw_ver1;
4078 vars->duplex);
4079 4373
4080 /* AN complete? */ 4374 bnx2x_bcm8073_external_rom_boot(bp, port,
4081 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { 4375 ext_phy_addr[port]);
4082 if (!(vars->phy_flags & 4376
4083 PHY_SGMII_FLAG)) 4377 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4084 bnx2x_set_sgmii_tx_driver(params); 4378 ext_phy_addr[port],
4085 } 4379 MDIO_PMA_DEVAD,
4380 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
4381 if (fw_ver1 == 0) {
4382 DP(NETIF_MSG_LINK,
4383 "bnx2x_8073_common_init_phy port %x "
4384 "fw Download failed\n", port);
4385 return -EINVAL;
4086 } 4386 }
4087 4387
4088 /* PBF - link up */ 4388 /* Only set bit 10 = 1 (Tx power down) */
4089 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, 4389 bnx2x_cl45_read(bp, port,
4090 vars->line_speed); 4390 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4391 ext_phy_addr[port],
4392 MDIO_PMA_DEVAD,
4393 MDIO_PMA_REG_TX_POWER_DOWN, &val);
4091 4394
4092 /* disable drain */ 4395 /* Phase1 of TX_POWER_DOWN reset */
4093 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 4396 bnx2x_cl45_write(bp, port,
4397 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4398 ext_phy_addr[port],
4399 MDIO_PMA_DEVAD,
4400 MDIO_PMA_REG_TX_POWER_DOWN,
4401 (val | 1<<10));
4402 }
4094 4403
4095 /* update shared memory */ 4404 /* Toggle Transmitter: Power down and then up with 600ms
4096 bnx2x_update_mng(params, vars->link_status); 4405 delay between */
4406 msleep(600);
4097 4407
4098 } else { /* link down */ 4408 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
4099 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", params->port); 4409 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
4100 bnx2x_set_led(bp, port, LED_MODE_OFF, 4410 /* Phase2 of POWER_DOWN_RESET*/
4101 0, params->hw_led_mode, 4411 /* Release bit 10 (Release Tx power down) */
4102 params->chip_id); 4412 bnx2x_cl45_read(bp, port,
4413 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4414 ext_phy_addr[port],
4415 MDIO_PMA_DEVAD,
4416 MDIO_PMA_REG_TX_POWER_DOWN, &val);
4103 4417
4104 /* indicate no mac active */ 4418 bnx2x_cl45_write(bp, port,
4105 vars->mac_type = MAC_TYPE_NONE; 4419 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4420 ext_phy_addr[port],
4421 MDIO_PMA_DEVAD,
4422 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
4423 msleep(15);
4106 4424
4107 /* update shared memory */ 4425 /* Read modify write the SPI-ROM version select register */
4108 vars->link_status = 0; 4426 bnx2x_cl45_read(bp, port,
4109 bnx2x_update_mng(params, vars->link_status); 4427 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4428 ext_phy_addr[port],
4429 MDIO_PMA_DEVAD,
4430 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
4431 bnx2x_cl45_write(bp, port,
4432 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4433 ext_phy_addr[port],
4434 MDIO_PMA_DEVAD,
4435 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
4110 4436
4111 /* activate nig drain */ 4437 /* set GPIO2 back to LOW */
4112 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 4438 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4439 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
4440 }
4441 return 0;
4113 4442
4114 /* reset BigMac */ 4443}
4115 bnx2x_bmac_rx_disable(bp, params->port);
4116 REG_WR(bp, GRCBASE_MISC +
4117 MISC_REGISTERS_RESET_REG_2_CLEAR,
4118 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
4119 4444
4445u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
4446{
4447 u8 rc = 0;
4448 u32 ext_phy_type;
4449
4450 DP(NETIF_MSG_LINK, "bnx2x_common_init_phy\n");
4451
4452 /* Read the ext_phy_type for arbitrary port(0) */
4453 ext_phy_type = XGXS_EXT_PHY_TYPE(
4454 REG_RD(bp, shmem_base +
4455 offsetof(struct shmem_region,
4456 dev_info.port_hw_config[0].external_phy_config)));
4457
4458 switch (ext_phy_type) {
4459 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4460 {
4461 rc = bnx2x_8073_common_init_phy(bp, shmem_base);
4462 break;
4463 }
4464 default:
4465 DP(NETIF_MSG_LINK,
4466 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
4467 ext_phy_type);
4468 break;
4120 } 4469 }
4121 4470
4122 return rc; 4471 return rc;
4123} 4472}
4124 4473
4474
4475
4125static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr) 4476static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
4126{ 4477{
4127 u16 val, cnt; 4478 u16 val, cnt;
@@ -4154,7 +4505,7 @@ static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
4154} 4505}
4155#define RESERVED_SIZE 256 4506#define RESERVED_SIZE 256
4156/* max application is 160K bytes - data at end of RAM */ 4507/* max application is 160K bytes - data at end of RAM */
4157#define MAX_APP_SIZE 160*1024 - RESERVED_SIZE 4508#define MAX_APP_SIZE (160*1024 - RESERVED_SIZE)
4158 4509
4159/* Header is 14 bytes */ 4510/* Header is 14 bytes */
4160#define HEADER_SIZE 14 4511#define HEADER_SIZE 14
@@ -4192,12 +4543,12 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4192 size = MAX_APP_SIZE+HEADER_SIZE; 4543 size = MAX_APP_SIZE+HEADER_SIZE;
4193 } 4544 }
4194 DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]); 4545 DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]);
4195 DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]); 4546 DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]);
4196 /* Put the DSP in download mode by setting FLASH_CFG[2] to 1 4547 /* Put the DSP in download mode by setting FLASH_CFG[2] to 1
4197 and issuing a reset.*/ 4548 and issuing a reset.*/
4198 4549
4199 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 4550 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4200 MISC_REGISTERS_GPIO_HIGH); 4551 MISC_REGISTERS_GPIO_HIGH, port);
4201 4552
4202 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr); 4553 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
4203 4554
@@ -4429,7 +4780,8 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4429 } 4780 }
4430 4781
4431 /* DSP Remove Download Mode */ 4782 /* DSP Remove Download Mode */
4432 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, MISC_REGISTERS_GPIO_LOW); 4783 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4784 MISC_REGISTERS_GPIO_LOW, port);
4433 4785
4434 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr); 4786 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
4435 4787
@@ -4437,7 +4789,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4437 for (cnt = 0; cnt < 100; cnt++) 4789 for (cnt = 0; cnt < 100; cnt++)
4438 msleep(5); 4790 msleep(5);
4439 4791
4440 bnx2x_hw_reset(bp); 4792 bnx2x_hw_reset(bp, port);
4441 4793
4442 for (cnt = 0; cnt < 100; cnt++) 4794 for (cnt = 0; cnt < 100; cnt++)
4443 msleep(5); 4795 msleep(5);
@@ -4473,7 +4825,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4473 MDIO_PMA_REG_7101_VER2, 4825 MDIO_PMA_REG_7101_VER2,
4474 &image_revision2); 4826 &image_revision2);
4475 4827
4476 if (data[0x14e] != (image_revision2&0xFF) || 4828 if (data[0x14e] != (image_revision2&0xFF) ||
4477 data[0x14f] != ((image_revision2&0xFF00)>>8) || 4829 data[0x14f] != ((image_revision2&0xFF00)>>8) ||
4478 data[0x150] != (image_revision1&0xFF) || 4830 data[0x150] != (image_revision1&0xFF) ||
4479 data[0x151] != ((image_revision1&0xFF00)>>8)) { 4831 data[0x151] != ((image_revision1&0xFF00)>>8)) {
@@ -4508,11 +4860,11 @@ u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
4508 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 4860 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
4509 /* Take ext phy out of reset */ 4861 /* Take ext phy out of reset */
4510 if (!driver_loaded) 4862 if (!driver_loaded)
4511 bnx2x_turn_on_sf(bp, port, ext_phy_addr); 4863 bnx2x_turn_on_ef(bp, port, ext_phy_addr, ext_phy_type);
4512 rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr, 4864 rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr,
4513 data, size); 4865 data, size);
4514 if (!driver_loaded) 4866 if (!driver_loaded)
4515 bnx2x_turn_off_sf(bp); 4867 bnx2x_turn_off_sf(bp, port);
4516 break; 4868 break;
4517 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 4869 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
4518 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 4870 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
diff --git a/drivers/net/bnx2x_link.h b/drivers/net/bnx2x_link.h
index 714d37ac95de..86d54a17b411 100644
--- a/drivers/net/bnx2x_link.h
+++ b/drivers/net/bnx2x_link.h
@@ -55,14 +55,17 @@ struct link_params {
55#define LOOPBACK_BMAC 2 55#define LOOPBACK_BMAC 2
56#define LOOPBACK_XGXS_10 3 56#define LOOPBACK_XGXS_10 3
57#define LOOPBACK_EXT_PHY 4 57#define LOOPBACK_EXT_PHY 4
58#define LOOPBACK_EXT 5
58 59
59 u16 req_duplex; 60 u16 req_duplex;
60 u16 req_flow_ctrl; 61 u16 req_flow_ctrl;
62 u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
63 req_flow_ctrl is set to AUTO */
61 u16 req_line_speed; /* Also determine AutoNeg */ 64 u16 req_line_speed; /* Also determine AutoNeg */
62 65
63 /* Device parameters */ 66 /* Device parameters */
64 u8 mac_addr[6]; 67 u8 mac_addr[6];
65 u16 mtu; 68
66 69
67 70
68 /* shmem parameters */ 71 /* shmem parameters */
@@ -140,7 +143,7 @@ u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
140 u8 phy_addr, u8 devad, u16 reg, u16 val); 143 u8 phy_addr, u8 devad, u16 reg, u16 val);
141 144
142/* Reads the link_status from the shmem, 145/* Reads the link_status from the shmem,
143 and update the link vars accordinaly */ 146 and update the link vars accordingly */
144void bnx2x_link_status_update(struct link_params *input, 147void bnx2x_link_status_update(struct link_params *input,
145 struct link_vars *output); 148 struct link_vars *output);
146/* returns string representing the fw_version of the external phy */ 149/* returns string representing the fw_version of the external phy */
@@ -149,7 +152,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
149 152
150/* Set/Unset the led 153/* Set/Unset the led
151 Basically, the CLC takes care of the led for the link, but in case one needs 154 Basically, the CLC takes care of the led for the link, but in case one needs
152 to set/unset the led unnatually, set the "mode" to LED_MODE_OPER to 155 to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
153 blink the led, and LED_MODE_OFF to set the led off.*/ 156 blink the led, and LED_MODE_OFF to set the led off.*/
154u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed, 157u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
155 u16 hw_led_mode, u32 chip_id); 158 u16 hw_led_mode, u32 chip_id);
@@ -164,5 +167,7 @@ u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
164 otherwise link is down*/ 167 otherwise link is down*/
165u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars); 168u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars);
166 169
170/* One-time initialization for external phy after power up */
171u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base);
167 172
168#endif /* BNX2X_LINK_H */ 173#endif /* BNX2X_LINK_H */
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 272a4bd25953..3e7dc171cdf1 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -60,8 +60,8 @@
60#include "bnx2x.h" 60#include "bnx2x.h"
61#include "bnx2x_init.h" 61#include "bnx2x_init.h"
62 62
63#define DRV_MODULE_VERSION "1.45.6" 63#define DRV_MODULE_VERSION "1.45.17"
64#define DRV_MODULE_RELDATE "2008/06/23" 64#define DRV_MODULE_RELDATE "2008/08/13"
65#define BNX2X_BC_VER 0x040200 65#define BNX2X_BC_VER 0x040200
66 66
67/* Time in jiffies before concluding the transmitter is hung */ 67/* Time in jiffies before concluding the transmitter is hung */
@@ -76,23 +76,21 @@ MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver");
76MODULE_LICENSE("GPL"); 76MODULE_LICENSE("GPL");
77MODULE_VERSION(DRV_MODULE_VERSION); 77MODULE_VERSION(DRV_MODULE_VERSION);
78 78
79static int disable_tpa;
79static int use_inta; 80static int use_inta;
80static int poll; 81static int poll;
81static int debug; 82static int debug;
82static int disable_tpa;
83static int nomcp;
84static int load_count[3]; /* 0-common, 1-port0, 2-port1 */ 83static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
85static int use_multi; 84static int use_multi;
86 85
86module_param(disable_tpa, int, 0);
87module_param(use_inta, int, 0); 87module_param(use_inta, int, 0);
88module_param(poll, int, 0); 88module_param(poll, int, 0);
89module_param(debug, int, 0); 89module_param(debug, int, 0);
90module_param(disable_tpa, int, 0); 90MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature");
91module_param(nomcp, int, 0);
92MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X"); 91MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
93MODULE_PARM_DESC(poll, "use polling (for debug)"); 92MODULE_PARM_DESC(poll, "use polling (for debug)");
94MODULE_PARM_DESC(debug, "default debug msglevel"); 93MODULE_PARM_DESC(debug, "default debug msglevel");
95MODULE_PARM_DESC(nomcp, "ignore management CPU");
96 94
97#ifdef BNX2X_MULTI 95#ifdef BNX2X_MULTI
98module_param(use_multi, int, 0); 96module_param(use_multi, int, 0);
@@ -237,17 +235,16 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
237 while (*wb_comp != DMAE_COMP_VAL) { 235 while (*wb_comp != DMAE_COMP_VAL) {
238 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 236 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
239 237
240 /* adjust delay for emulation/FPGA */
241 if (CHIP_REV_IS_SLOW(bp))
242 msleep(100);
243 else
244 udelay(5);
245
246 if (!cnt) { 238 if (!cnt) {
247 BNX2X_ERR("dmae timeout!\n"); 239 BNX2X_ERR("dmae timeout!\n");
248 break; 240 break;
249 } 241 }
250 cnt--; 242 cnt--;
243 /* adjust delay for emulation/FPGA */
244 if (CHIP_REV_IS_SLOW(bp))
245 msleep(100);
246 else
247 udelay(5);
251 } 248 }
252 249
253 mutex_unlock(&bp->dmae_mutex); 250 mutex_unlock(&bp->dmae_mutex);
@@ -310,17 +307,16 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
310 307
311 while (*wb_comp != DMAE_COMP_VAL) { 308 while (*wb_comp != DMAE_COMP_VAL) {
312 309
313 /* adjust delay for emulation/FPGA */
314 if (CHIP_REV_IS_SLOW(bp))
315 msleep(100);
316 else
317 udelay(5);
318
319 if (!cnt) { 310 if (!cnt) {
320 BNX2X_ERR("dmae timeout!\n"); 311 BNX2X_ERR("dmae timeout!\n");
321 break; 312 break;
322 } 313 }
323 cnt--; 314 cnt--;
315 /* adjust delay for emulation/FPGA */
316 if (CHIP_REV_IS_SLOW(bp))
317 msleep(100);
318 else
319 udelay(5);
324 } 320 }
325 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n", 321 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
326 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 322 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
@@ -503,6 +499,9 @@ static void bnx2x_panic_dump(struct bnx2x *bp)
503 int i; 499 int i;
504 u16 j, start, end; 500 u16 j, start, end;
505 501
502 bp->stats_state = STATS_STATE_DISABLED;
503 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
504
506 BNX2X_ERR("begin crash dump -----------------\n"); 505 BNX2X_ERR("begin crash dump -----------------\n");
507 506
508 for_each_queue(bp, i) { 507 for_each_queue(bp, i) {
@@ -513,17 +512,20 @@ static void bnx2x_panic_dump(struct bnx2x *bp)
513 " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n", 512 " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n",
514 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod, 513 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
515 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb)); 514 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
516 BNX2X_ERR(" rx_comp_prod(%x) rx_comp_cons(%x)" 515 BNX2X_ERR(" rx_bd_prod(%x) rx_bd_cons(%x)"
517 " *rx_cons_sb(%x) *rx_bd_cons_sb(%x)" 516 " *rx_bd_cons_sb(%x) rx_comp_prod(%x)"
518 " rx_sge_prod(%x) last_max_sge(%x)\n", 517 " rx_comp_cons(%x) *rx_cons_sb(%x)\n",
519 fp->rx_comp_prod, fp->rx_comp_cons, 518 fp->rx_bd_prod, fp->rx_bd_cons,
520 le16_to_cpu(*fp->rx_cons_sb), 519 le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
521 le16_to_cpu(*fp->rx_bd_cons_sb), 520 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
522 fp->rx_sge_prod, fp->last_max_sge); 521 BNX2X_ERR(" rx_sge_prod(%x) last_max_sge(%x)"
523 BNX2X_ERR(" fp_c_idx(%x) fp_u_idx(%x)" 522 " fp_c_idx(%x) *sb_c_idx(%x) fp_u_idx(%x)"
524 " bd data(%x,%x) rx_alloc_failed(%lx)\n", 523 " *sb_u_idx(%x) bd data(%x,%x)\n",
525 fp->fp_c_idx, fp->fp_u_idx, hw_prods->packets_prod, 524 fp->rx_sge_prod, fp->last_max_sge, fp->fp_c_idx,
526 hw_prods->bds_prod, fp->rx_alloc_failed); 525 fp->status_blk->c_status_block.status_block_index,
526 fp->fp_u_idx,
527 fp->status_blk->u_status_block.status_block_index,
528 hw_prods->packets_prod, hw_prods->bds_prod);
527 529
528 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10); 530 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
529 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245); 531 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
@@ -553,8 +555,8 @@ static void bnx2x_panic_dump(struct bnx2x *bp)
553 j, rx_bd[1], rx_bd[0], sw_bd->skb); 555 j, rx_bd[1], rx_bd[0], sw_bd->skb);
554 } 556 }
555 557
556 start = 0; 558 start = RX_SGE(fp->rx_sge_prod);
557 end = RX_SGE_CNT*NUM_RX_SGE_PAGES; 559 end = RX_SGE(fp->last_max_sge);
558 for (j = start; j < end; j++) { 560 for (j = start; j < end; j++) {
559 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 561 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
560 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 562 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
@@ -582,9 +584,6 @@ static void bnx2x_panic_dump(struct bnx2x *bp)
582 bnx2x_fw_dump(bp); 584 bnx2x_fw_dump(bp);
583 bnx2x_mc_assert(bp); 585 bnx2x_mc_assert(bp);
584 BNX2X_ERR("end crash dump -----------------\n"); 586 BNX2X_ERR("end crash dump -----------------\n");
585
586 bp->stats_state = STATS_STATE_DISABLED;
587 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
588} 587}
589 588
590static void bnx2x_int_enable(struct bnx2x *bp) 589static void bnx2x_int_enable(struct bnx2x *bp)
@@ -684,7 +683,8 @@ static void bnx2x_int_disable_sync(struct bnx2x *bp)
684static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id, 683static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
685 u8 storm, u16 index, u8 op, u8 update) 684 u8 storm, u16 index, u8 op, u8 update)
686{ 685{
687 u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; 686 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
687 COMMAND_REG_INT_ACK);
688 struct igu_ack_register igu_ack; 688 struct igu_ack_register igu_ack;
689 689
690 igu_ack.status_block_index = index; 690 igu_ack.status_block_index = index;
@@ -694,9 +694,9 @@ static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
694 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 694 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
695 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 695 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
696 696
697 DP(BNX2X_MSG_OFF, "write 0x%08x to IGU addr 0x%x\n", 697 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
698 (*(u32 *)&igu_ack), BAR_IGU_INTMEM + igu_addr); 698 (*(u32 *)&igu_ack), hc_addr);
699 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, (*(u32 *)&igu_ack)); 699 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
700} 700}
701 701
702static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 702static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
@@ -716,36 +716,15 @@ static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
716 return rc; 716 return rc;
717} 717}
718 718
719static inline int bnx2x_has_work(struct bnx2x_fastpath *fp)
720{
721 u16 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
722
723 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
724 rx_cons_sb++;
725
726 if ((fp->rx_comp_cons != rx_cons_sb) ||
727 (fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) ||
728 (fp->tx_pkt_prod != fp->tx_pkt_cons))
729 return 1;
730
731 return 0;
732}
733
734static u16 bnx2x_ack_int(struct bnx2x *bp) 719static u16 bnx2x_ack_int(struct bnx2x *bp)
735{ 720{
736 u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; 721 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
737 u32 result = REG_RD(bp, BAR_IGU_INTMEM + igu_addr); 722 COMMAND_REG_SIMD_MASK);
723 u32 result = REG_RD(bp, hc_addr);
738 724
739 DP(BNX2X_MSG_OFF, "read 0x%08x from IGU addr 0x%x\n", 725 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
740 result, BAR_IGU_INTMEM + igu_addr); 726 result, hc_addr);
741 727
742#ifdef IGU_DEBUG
743#warning IGU_DEBUG active
744 if (result == 0) {
745 BNX2X_ERR("read %x from IGU\n", result);
746 REG_WR(bp, TM_REG_TIMER_SOFT_RST, 0);
747 }
748#endif
749 return result; 728 return result;
750} 729}
751 730
@@ -898,6 +877,7 @@ static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
898 netif_tx_lock(bp->dev); 877 netif_tx_lock(bp->dev);
899 878
900 if (netif_queue_stopped(bp->dev) && 879 if (netif_queue_stopped(bp->dev) &&
880 (bp->state == BNX2X_STATE_OPEN) &&
901 (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)) 881 (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
902 netif_wake_queue(bp->dev); 882 netif_wake_queue(bp->dev);
903 883
@@ -905,6 +885,7 @@ static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
905 } 885 }
906} 886}
907 887
888
908static void bnx2x_sp_event(struct bnx2x_fastpath *fp, 889static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
909 union eth_rx_cqe *rr_cqe) 890 union eth_rx_cqe *rr_cqe)
910{ 891{
@@ -960,6 +941,7 @@ static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
960 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED; 941 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
961 break; 942 break;
962 943
944
963 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN): 945 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
964 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG): 946 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
965 DP(NETIF_MSG_IFUP, "got set mac ramrod\n"); 947 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
@@ -1169,8 +1151,8 @@ static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
1169 memset(fp->sge_mask, 0xff, 1151 memset(fp->sge_mask, 0xff,
1170 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64)); 1152 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
1171 1153
1172 /* Clear the two last indeces in the page to 1: 1154 /* Clear the two last indices in the page to 1:
1173 these are the indeces that correspond to the "next" element, 1155 these are the indices that correspond to the "next" element,
1174 hence will never be indicated and should be removed from 1156 hence will never be indicated and should be removed from
1175 the calculations. */ 1157 the calculations. */
1176 bnx2x_clear_sge_mask_next_elems(fp); 1158 bnx2x_clear_sge_mask_next_elems(fp);
@@ -1261,7 +1243,7 @@ static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1261 where we are and drop the whole packet */ 1243 where we are and drop the whole packet */
1262 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx); 1244 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
1263 if (unlikely(err)) { 1245 if (unlikely(err)) {
1264 fp->rx_alloc_failed++; 1246 bp->eth_stats.rx_skb_alloc_failed++;
1265 return err; 1247 return err;
1266 } 1248 }
1267 1249
@@ -1297,14 +1279,13 @@ static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1297 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping), 1279 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
1298 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); 1280 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1299 1281
1300 /* if alloc failed drop the packet and keep the buffer in the bin */
1301 if (likely(new_skb)) { 1282 if (likely(new_skb)) {
1283 /* fix ip xsum and give it to the stack */
1284 /* (no need to map the new skb) */
1302 1285
1303 prefetch(skb); 1286 prefetch(skb);
1304 prefetch(((char *)(skb)) + 128); 1287 prefetch(((char *)(skb)) + 128);
1305 1288
1306 /* else fix ip xsum and give it to the stack */
1307 /* (no need to map the new skb) */
1308#ifdef BNX2X_STOP_ON_ERROR 1289#ifdef BNX2X_STOP_ON_ERROR
1309 if (pad + len > bp->rx_buf_size) { 1290 if (pad + len > bp->rx_buf_size) {
1310 BNX2X_ERR("skb_put is about to fail... " 1291 BNX2X_ERR("skb_put is about to fail... "
@@ -1353,9 +1334,10 @@ static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1353 fp->tpa_pool[queue].skb = new_skb; 1334 fp->tpa_pool[queue].skb = new_skb;
1354 1335
1355 } else { 1336 } else {
1337 /* else drop the packet and keep the buffer in the bin */
1356 DP(NETIF_MSG_RX_STATUS, 1338 DP(NETIF_MSG_RX_STATUS,
1357 "Failed to allocate new skb - dropping packet!\n"); 1339 "Failed to allocate new skb - dropping packet!\n");
1358 fp->rx_alloc_failed++; 1340 bp->eth_stats.rx_skb_alloc_failed++;
1359 } 1341 }
1360 1342
1361 fp->tpa_state[queue] = BNX2X_TPA_STOP; 1343 fp->tpa_state[queue] = BNX2X_TPA_STOP;
@@ -1390,7 +1372,6 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1390 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons; 1372 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1391 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod; 1373 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
1392 int rx_pkt = 0; 1374 int rx_pkt = 0;
1393 u16 queue;
1394 1375
1395#ifdef BNX2X_STOP_ON_ERROR 1376#ifdef BNX2X_STOP_ON_ERROR
1396 if (unlikely(bp->panic)) 1377 if (unlikely(bp->panic))
@@ -1456,7 +1437,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1456 if ((!fp->disable_tpa) && 1437 if ((!fp->disable_tpa) &&
1457 (TPA_TYPE(cqe_fp_flags) != 1438 (TPA_TYPE(cqe_fp_flags) !=
1458 (TPA_TYPE_START | TPA_TYPE_END))) { 1439 (TPA_TYPE_START | TPA_TYPE_END))) {
1459 queue = cqe->fast_path_cqe.queue_index; 1440 u16 queue = cqe->fast_path_cqe.queue_index;
1460 1441
1461 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) { 1442 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
1462 DP(NETIF_MSG_RX_STATUS, 1443 DP(NETIF_MSG_RX_STATUS,
@@ -1503,11 +1484,10 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1503 1484
1504 /* is this an error packet? */ 1485 /* is this an error packet? */
1505 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) { 1486 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1506 /* do we sometimes forward error packets anyway? */
1507 DP(NETIF_MSG_RX_ERR, 1487 DP(NETIF_MSG_RX_ERR,
1508 "ERROR flags %x rx packet %u\n", 1488 "ERROR flags %x rx packet %u\n",
1509 cqe_fp_flags, sw_comp_cons); 1489 cqe_fp_flags, sw_comp_cons);
1510 /* TBD make sure MC counts this as a drop */ 1490 bp->eth_stats.rx_err_discard_pkt++;
1511 goto reuse_rx; 1491 goto reuse_rx;
1512 } 1492 }
1513 1493
@@ -1524,7 +1504,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1524 DP(NETIF_MSG_RX_ERR, 1504 DP(NETIF_MSG_RX_ERR,
1525 "ERROR packet dropped " 1505 "ERROR packet dropped "
1526 "because of alloc failure\n"); 1506 "because of alloc failure\n");
1527 fp->rx_alloc_failed++; 1507 bp->eth_stats.rx_skb_alloc_failed++;
1528 goto reuse_rx; 1508 goto reuse_rx;
1529 } 1509 }
1530 1510
@@ -1550,7 +1530,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1550 DP(NETIF_MSG_RX_ERR, 1530 DP(NETIF_MSG_RX_ERR,
1551 "ERROR packet dropped because " 1531 "ERROR packet dropped because "
1552 "of alloc failure\n"); 1532 "of alloc failure\n");
1553 fp->rx_alloc_failed++; 1533 bp->eth_stats.rx_skb_alloc_failed++;
1554reuse_rx: 1534reuse_rx:
1555 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod); 1535 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1556 goto next_rx; 1536 goto next_rx;
@@ -1559,10 +1539,12 @@ reuse_rx:
1559 skb->protocol = eth_type_trans(skb, bp->dev); 1539 skb->protocol = eth_type_trans(skb, bp->dev);
1560 1540
1561 skb->ip_summed = CHECKSUM_NONE; 1541 skb->ip_summed = CHECKSUM_NONE;
1562 if (bp->rx_csum && BNX2X_RX_SUM_OK(cqe)) 1542 if (bp->rx_csum) {
1563 skb->ip_summed = CHECKSUM_UNNECESSARY; 1543 if (likely(BNX2X_RX_CSUM_OK(cqe)))
1564 1544 skb->ip_summed = CHECKSUM_UNNECESSARY;
1565 /* TBD do we pass bad csum packets in promisc */ 1545 else
1546 bp->eth_stats.hw_csum_err++;
1547 }
1566 } 1548 }
1567 1549
1568#ifdef BCM_VLAN 1550#ifdef BCM_VLAN
@@ -1615,6 +1597,12 @@ static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1615 struct net_device *dev = bp->dev; 1597 struct net_device *dev = bp->dev;
1616 int index = FP_IDX(fp); 1598 int index = FP_IDX(fp);
1617 1599
1600 /* Return here if interrupt is disabled */
1601 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1602 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1603 return IRQ_HANDLED;
1604 }
1605
1618 DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n", 1606 DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
1619 index, FP_SB_ID(fp)); 1607 index, FP_SB_ID(fp));
1620 bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0); 1608 bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0);
@@ -1648,17 +1636,17 @@ static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1648 } 1636 }
1649 DP(NETIF_MSG_INTR, "got an interrupt status %u\n", status); 1637 DP(NETIF_MSG_INTR, "got an interrupt status %u\n", status);
1650 1638
1651#ifdef BNX2X_STOP_ON_ERROR
1652 if (unlikely(bp->panic))
1653 return IRQ_HANDLED;
1654#endif
1655
1656 /* Return here if interrupt is disabled */ 1639 /* Return here if interrupt is disabled */
1657 if (unlikely(atomic_read(&bp->intr_sem) != 0)) { 1640 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1658 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n"); 1641 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1659 return IRQ_HANDLED; 1642 return IRQ_HANDLED;
1660 } 1643 }
1661 1644
1645#ifdef BNX2X_STOP_ON_ERROR
1646 if (unlikely(bp->panic))
1647 return IRQ_HANDLED;
1648#endif
1649
1662 mask = 0x2 << bp->fp[0].sb_id; 1650 mask = 0x2 << bp->fp[0].sb_id;
1663 if (status & mask) { 1651 if (status & mask) {
1664 struct bnx2x_fastpath *fp = &bp->fp[0]; 1652 struct bnx2x_fastpath *fp = &bp->fp[0];
@@ -1699,11 +1687,12 @@ static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1699 * General service functions 1687 * General service functions
1700 */ 1688 */
1701 1689
1702static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource) 1690static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1703{ 1691{
1704 u32 lock_status; 1692 u32 lock_status;
1705 u32 resource_bit = (1 << resource); 1693 u32 resource_bit = (1 << resource);
1706 u8 port = BP_PORT(bp); 1694 int func = BP_FUNC(bp);
1695 u32 hw_lock_control_reg;
1707 int cnt; 1696 int cnt;
1708 1697
1709 /* Validating that the resource is within range */ 1698 /* Validating that the resource is within range */
@@ -1714,8 +1703,15 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1714 return -EINVAL; 1703 return -EINVAL;
1715 } 1704 }
1716 1705
1706 if (func <= 5) {
1707 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1708 } else {
1709 hw_lock_control_reg =
1710 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1711 }
1712
1717 /* Validating that the resource is not already taken */ 1713 /* Validating that the resource is not already taken */
1718 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8); 1714 lock_status = REG_RD(bp, hw_lock_control_reg);
1719 if (lock_status & resource_bit) { 1715 if (lock_status & resource_bit) {
1720 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1716 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1721 lock_status, resource_bit); 1717 lock_status, resource_bit);
@@ -1725,9 +1721,8 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1725 /* Try for 1 second every 5ms */ 1721 /* Try for 1 second every 5ms */
1726 for (cnt = 0; cnt < 200; cnt++) { 1722 for (cnt = 0; cnt < 200; cnt++) {
1727 /* Try to acquire the lock */ 1723 /* Try to acquire the lock */
1728 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8 + 4, 1724 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1729 resource_bit); 1725 lock_status = REG_RD(bp, hw_lock_control_reg);
1730 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
1731 if (lock_status & resource_bit) 1726 if (lock_status & resource_bit)
1732 return 0; 1727 return 0;
1733 1728
@@ -1737,11 +1732,12 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1737 return -EAGAIN; 1732 return -EAGAIN;
1738} 1733}
1739 1734
1740static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource) 1735static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1741{ 1736{
1742 u32 lock_status; 1737 u32 lock_status;
1743 u32 resource_bit = (1 << resource); 1738 u32 resource_bit = (1 << resource);
1744 u8 port = BP_PORT(bp); 1739 int func = BP_FUNC(bp);
1740 u32 hw_lock_control_reg;
1745 1741
1746 /* Validating that the resource is within range */ 1742 /* Validating that the resource is within range */
1747 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1743 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
@@ -1751,20 +1747,27 @@ static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
1751 return -EINVAL; 1747 return -EINVAL;
1752 } 1748 }
1753 1749
1750 if (func <= 5) {
1751 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1752 } else {
1753 hw_lock_control_reg =
1754 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1755 }
1756
1754 /* Validating that the resource is currently taken */ 1757 /* Validating that the resource is currently taken */
1755 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8); 1758 lock_status = REG_RD(bp, hw_lock_control_reg);
1756 if (!(lock_status & resource_bit)) { 1759 if (!(lock_status & resource_bit)) {
1757 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1760 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1758 lock_status, resource_bit); 1761 lock_status, resource_bit);
1759 return -EFAULT; 1762 return -EFAULT;
1760 } 1763 }
1761 1764
1762 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8, resource_bit); 1765 REG_WR(bp, hw_lock_control_reg, resource_bit);
1763 return 0; 1766 return 0;
1764} 1767}
1765 1768
1766/* HW Lock for shared dual port PHYs */ 1769/* HW Lock for shared dual port PHYs */
1767static void bnx2x_phy_hw_lock(struct bnx2x *bp) 1770static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1768{ 1771{
1769 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); 1772 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1770 1773
@@ -1772,25 +1775,25 @@ static void bnx2x_phy_hw_lock(struct bnx2x *bp)
1772 1775
1773 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) || 1776 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1774 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) 1777 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1775 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO); 1778 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1776} 1779}
1777 1780
1778static void bnx2x_phy_hw_unlock(struct bnx2x *bp) 1781static void bnx2x_release_phy_lock(struct bnx2x *bp)
1779{ 1782{
1780 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); 1783 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1781 1784
1782 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) || 1785 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1783 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) 1786 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1784 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO); 1787 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1785 1788
1786 mutex_unlock(&bp->port.phy_mutex); 1789 mutex_unlock(&bp->port.phy_mutex);
1787} 1790}
1788 1791
1789int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode) 1792int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1790{ 1793{
1791 /* The GPIO should be swapped if swap register is set and active */ 1794 /* The GPIO should be swapped if swap register is set and active */
1792 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1795 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1793 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ BP_PORT(bp); 1796 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1794 int gpio_shift = gpio_num + 1797 int gpio_shift = gpio_num +
1795 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1798 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1796 u32 gpio_mask = (1 << gpio_shift); 1799 u32 gpio_mask = (1 << gpio_shift);
@@ -1801,7 +1804,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1801 return -EINVAL; 1804 return -EINVAL;
1802 } 1805 }
1803 1806
1804 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1807 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1805 /* read GPIO and mask except the float bits */ 1808 /* read GPIO and mask except the float bits */
1806 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1809 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1807 1810
@@ -1822,7 +1825,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1822 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1825 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1823 break; 1826 break;
1824 1827
1825 case MISC_REGISTERS_GPIO_INPUT_HI_Z : 1828 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1826 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1829 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1827 gpio_num, gpio_shift); 1830 gpio_num, gpio_shift);
1828 /* set FLOAT */ 1831 /* set FLOAT */
@@ -1834,7 +1837,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1834 } 1837 }
1835 1838
1836 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1839 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1837 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_GPIO); 1840 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1838 1841
1839 return 0; 1842 return 0;
1840} 1843}
@@ -1850,19 +1853,19 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1850 return -EINVAL; 1853 return -EINVAL;
1851 } 1854 }
1852 1855
1853 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 1856 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1854 /* read SPIO and mask except the float bits */ 1857 /* read SPIO and mask except the float bits */
1855 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 1858 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1856 1859
1857 switch (mode) { 1860 switch (mode) {
1858 case MISC_REGISTERS_SPIO_OUTPUT_LOW : 1861 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1859 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 1862 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1860 /* clear FLOAT and set CLR */ 1863 /* clear FLOAT and set CLR */
1861 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 1864 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1862 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 1865 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1863 break; 1866 break;
1864 1867
1865 case MISC_REGISTERS_SPIO_OUTPUT_HIGH : 1868 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1866 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 1869 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1867 /* clear FLOAT and set SET */ 1870 /* clear FLOAT and set SET */
1868 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 1871 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
@@ -1880,7 +1883,7 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1880 } 1883 }
1881 1884
1882 REG_WR(bp, MISC_REG_SPIO, spio_reg); 1885 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1883 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_SPIO); 1886 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1884 1887
1885 return 0; 1888 return 0;
1886} 1889}
@@ -1940,46 +1943,63 @@ static void bnx2x_link_report(struct bnx2x *bp)
1940 1943
1941static u8 bnx2x_initial_phy_init(struct bnx2x *bp) 1944static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
1942{ 1945{
1943 u8 rc; 1946 if (!BP_NOMCP(bp)) {
1947 u8 rc;
1944 1948
1945 /* Initialize link parameters structure variables */ 1949 /* Initialize link parameters structure variables */
1946 bp->link_params.mtu = bp->dev->mtu; 1950 /* It is recommended to turn off RX FC for jumbo frames
1951 for better performance */
1952 if (IS_E1HMF(bp))
1953 bp->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH;
1954 else if (bp->dev->mtu > 5000)
1955 bp->link_params.req_fc_auto_adv = FLOW_CTRL_TX;
1956 else
1957 bp->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH;
1947 1958
1948 bnx2x_phy_hw_lock(bp); 1959 bnx2x_acquire_phy_lock(bp);
1949 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 1960 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1950 bnx2x_phy_hw_unlock(bp); 1961 bnx2x_release_phy_lock(bp);
1951 1962
1952 if (bp->link_vars.link_up) 1963 if (bp->link_vars.link_up)
1953 bnx2x_link_report(bp); 1964 bnx2x_link_report(bp);
1954 1965
1955 bnx2x_calc_fc_adv(bp); 1966 bnx2x_calc_fc_adv(bp);
1956 1967
1957 return rc; 1968 return rc;
1969 }
1970 BNX2X_ERR("Bootcode is missing -not initializing link\n");
1971 return -EINVAL;
1958} 1972}
1959 1973
1960static void bnx2x_link_set(struct bnx2x *bp) 1974static void bnx2x_link_set(struct bnx2x *bp)
1961{ 1975{
1962 bnx2x_phy_hw_lock(bp); 1976 if (!BP_NOMCP(bp)) {
1963 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 1977 bnx2x_acquire_phy_lock(bp);
1964 bnx2x_phy_hw_unlock(bp); 1978 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1979 bnx2x_release_phy_lock(bp);
1965 1980
1966 bnx2x_calc_fc_adv(bp); 1981 bnx2x_calc_fc_adv(bp);
1982 } else
1983 BNX2X_ERR("Bootcode is missing -not setting link\n");
1967} 1984}
1968 1985
1969static void bnx2x__link_reset(struct bnx2x *bp) 1986static void bnx2x__link_reset(struct bnx2x *bp)
1970{ 1987{
1971 bnx2x_phy_hw_lock(bp); 1988 if (!BP_NOMCP(bp)) {
1972 bnx2x_link_reset(&bp->link_params, &bp->link_vars); 1989 bnx2x_acquire_phy_lock(bp);
1973 bnx2x_phy_hw_unlock(bp); 1990 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
1991 bnx2x_release_phy_lock(bp);
1992 } else
1993 BNX2X_ERR("Bootcode is missing -not resetting link\n");
1974} 1994}
1975 1995
1976static u8 bnx2x_link_test(struct bnx2x *bp) 1996static u8 bnx2x_link_test(struct bnx2x *bp)
1977{ 1997{
1978 u8 rc; 1998 u8 rc;
1979 1999
1980 bnx2x_phy_hw_lock(bp); 2000 bnx2x_acquire_phy_lock(bp);
1981 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars); 2001 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
1982 bnx2x_phy_hw_unlock(bp); 2002 bnx2x_release_phy_lock(bp);
1983 2003
1984 return rc; 2004 return rc;
1985} 2005}
@@ -1991,7 +2011,7 @@ static u8 bnx2x_link_test(struct bnx2x *bp)
1991 sum of vn_min_rates 2011 sum of vn_min_rates
1992 or 2012 or
1993 0 - if all the min_rates are 0. 2013 0 - if all the min_rates are 0.
1994 In the later case fainess algorithm should be deactivated. 2014 In the later case fairness algorithm should be deactivated.
1995 If not all min_rates are zero then those that are zeroes will 2015 If not all min_rates are zero then those that are zeroes will
1996 be set to 1. 2016 be set to 1.
1997 */ 2017 */
@@ -2114,7 +2134,7 @@ static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func,
2114 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2134 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2115 /* If FAIRNESS is enabled (not all min rates are zeroes) and 2135 /* If FAIRNESS is enabled (not all min rates are zeroes) and
2116 if current min rate is zero - set it to 1. 2136 if current min rate is zero - set it to 1.
2117 This is a requirment of the algorithm. */ 2137 This is a requirement of the algorithm. */
2118 if ((vn_min_rate == 0) && wsum) 2138 if ((vn_min_rate == 0) && wsum)
2119 vn_min_rate = DEF_MIN_RATE; 2139 vn_min_rate = DEF_MIN_RATE;
2120 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 2140 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
@@ -2203,9 +2223,9 @@ static void bnx2x_link_attn(struct bnx2x *bp)
2203 /* Make sure that we are synced with the current statistics */ 2223 /* Make sure that we are synced with the current statistics */
2204 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2224 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2205 2225
2206 bnx2x_phy_hw_lock(bp); 2226 bnx2x_acquire_phy_lock(bp);
2207 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2227 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2208 bnx2x_phy_hw_unlock(bp); 2228 bnx2x_release_phy_lock(bp);
2209 2229
2210 if (bp->link_vars.link_up) { 2230 if (bp->link_vars.link_up) {
2211 2231
@@ -2357,7 +2377,7 @@ static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2357} 2377}
2358 2378
2359/* acquire split MCP access lock register */ 2379/* acquire split MCP access lock register */
2360static int bnx2x_lock_alr(struct bnx2x *bp) 2380static int bnx2x_acquire_alr(struct bnx2x *bp)
2361{ 2381{
2362 u32 i, j, val; 2382 u32 i, j, val;
2363 int rc = 0; 2383 int rc = 0;
@@ -2374,15 +2394,15 @@ static int bnx2x_lock_alr(struct bnx2x *bp)
2374 msleep(5); 2394 msleep(5);
2375 } 2395 }
2376 if (!(val & (1L << 31))) { 2396 if (!(val & (1L << 31))) {
2377 BNX2X_ERR("Cannot acquire nvram interface\n"); 2397 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2378 rc = -EBUSY; 2398 rc = -EBUSY;
2379 } 2399 }
2380 2400
2381 return rc; 2401 return rc;
2382} 2402}
2383 2403
2384/* Release split MCP access lock register */ 2404/* release split MCP access lock register */
2385static void bnx2x_unlock_alr(struct bnx2x *bp) 2405static void bnx2x_release_alr(struct bnx2x *bp)
2386{ 2406{
2387 u32 val = 0; 2407 u32 val = 0;
2388 2408
@@ -2395,7 +2415,6 @@ static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2395 u16 rc = 0; 2415 u16 rc = 0;
2396 2416
2397 barrier(); /* status block is written to by the chip */ 2417 barrier(); /* status block is written to by the chip */
2398
2399 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 2418 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2400 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 2419 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2401 rc |= 1; 2420 rc |= 1;
@@ -2426,26 +2445,31 @@ static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2426static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 2445static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2427{ 2446{
2428 int port = BP_PORT(bp); 2447 int port = BP_PORT(bp);
2429 int func = BP_FUNC(bp); 2448 u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
2430 u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_FUNC_BASE * func) * 8; 2449 COMMAND_REG_ATTN_BITS_SET);
2431 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 2450 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2432 MISC_REG_AEU_MASK_ATTN_FUNC_0; 2451 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2433 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 2452 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2434 NIG_REG_MASK_INTERRUPT_PORT0; 2453 NIG_REG_MASK_INTERRUPT_PORT0;
2454 u32 aeu_mask;
2435 2455
2436 if (~bp->aeu_mask & (asserted & 0xff))
2437 BNX2X_ERR("IGU ERROR\n");
2438 if (bp->attn_state & asserted) 2456 if (bp->attn_state & asserted)
2439 BNX2X_ERR("IGU ERROR\n"); 2457 BNX2X_ERR("IGU ERROR\n");
2440 2458
2459 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2460 aeu_mask = REG_RD(bp, aeu_addr);
2461
2441 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 2462 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
2442 bp->aeu_mask, asserted); 2463 aeu_mask, asserted);
2443 bp->aeu_mask &= ~(asserted & 0xff); 2464 aeu_mask &= ~(asserted & 0xff);
2444 DP(NETIF_MSG_HW, "after masking: aeu_mask %x\n", bp->aeu_mask); 2465 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2445 2466
2446 REG_WR(bp, aeu_addr, bp->aeu_mask); 2467 REG_WR(bp, aeu_addr, aeu_mask);
2468 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2447 2469
2470 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2448 bp->attn_state |= asserted; 2471 bp->attn_state |= asserted;
2472 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2449 2473
2450 if (asserted & ATTN_HARD_WIRED_MASK) { 2474 if (asserted & ATTN_HARD_WIRED_MASK) {
2451 if (asserted & ATTN_NIG_FOR_FUNC) { 2475 if (asserted & ATTN_NIG_FOR_FUNC) {
@@ -2500,9 +2524,9 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2500 2524
2501 } /* if hardwired */ 2525 } /* if hardwired */
2502 2526
2503 DP(NETIF_MSG_HW, "about to mask 0x%08x at IGU addr 0x%x\n", 2527 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2504 asserted, BAR_IGU_INTMEM + igu_addr); 2528 asserted, hc_addr);
2505 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, asserted); 2529 REG_WR(bp, hc_addr, asserted);
2506 2530
2507 /* now set back the mask */ 2531 /* now set back the mask */
2508 if (asserted & ATTN_NIG_FOR_FUNC) 2532 if (asserted & ATTN_NIG_FOR_FUNC)
@@ -2530,12 +2554,12 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2530 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: 2554 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
2531 /* Fan failure attention */ 2555 /* Fan failure attention */
2532 2556
2533 /* The PHY reset is controled by GPIO 1 */ 2557 /* The PHY reset is controlled by GPIO 1 */
2534 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 2558 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2535 MISC_REGISTERS_GPIO_OUTPUT_LOW); 2559 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2536 /* Low power mode is controled by GPIO 2 */ 2560 /* Low power mode is controlled by GPIO 2 */
2537 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 2561 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2538 MISC_REGISTERS_GPIO_OUTPUT_LOW); 2562 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2539 /* mark the failure */ 2563 /* mark the failure */
2540 bp->link_params.ext_phy_config &= 2564 bp->link_params.ext_phy_config &=
2541 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 2565 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
@@ -2699,10 +2723,11 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2699 int index; 2723 int index;
2700 u32 reg_addr; 2724 u32 reg_addr;
2701 u32 val; 2725 u32 val;
2726 u32 aeu_mask;
2702 2727
2703 /* need to take HW lock because MCP or other port might also 2728 /* need to take HW lock because MCP or other port might also
2704 try to handle this event */ 2729 try to handle this event */
2705 bnx2x_lock_alr(bp); 2730 bnx2x_acquire_alr(bp);
2706 2731
2707 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 2732 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
2708 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 2733 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
@@ -2734,32 +2759,35 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2734 HW_PRTY_ASSERT_SET_1) || 2759 HW_PRTY_ASSERT_SET_1) ||
2735 (attn.sig[2] & group_mask.sig[2] & 2760 (attn.sig[2] & group_mask.sig[2] &
2736 HW_PRTY_ASSERT_SET_2)) 2761 HW_PRTY_ASSERT_SET_2))
2737 BNX2X_ERR("FATAL HW block parity attention\n"); 2762 BNX2X_ERR("FATAL HW block parity attention\n");
2738 } 2763 }
2739 } 2764 }
2740 2765
2741 bnx2x_unlock_alr(bp); 2766 bnx2x_release_alr(bp);
2742 2767
2743 reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; 2768 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
2744 2769
2745 val = ~deasserted; 2770 val = ~deasserted;
2746/* DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2771 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2747 val, BAR_IGU_INTMEM + reg_addr); */ 2772 val, reg_addr);
2748 REG_WR(bp, BAR_IGU_INTMEM + reg_addr, val); 2773 REG_WR(bp, reg_addr, val);
2749 2774
2750 if (bp->aeu_mask & (deasserted & 0xff))
2751 BNX2X_ERR("IGU BUG!\n");
2752 if (~bp->attn_state & deasserted) 2775 if (~bp->attn_state & deasserted)
2753 BNX2X_ERR("IGU BUG!\n"); 2776 BNX2X_ERR("IGU ERROR\n");
2754 2777
2755 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 2778 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2756 MISC_REG_AEU_MASK_ATTN_FUNC_0; 2779 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2757 2780
2758 DP(NETIF_MSG_HW, "aeu_mask %x\n", bp->aeu_mask); 2781 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2759 bp->aeu_mask |= (deasserted & 0xff); 2782 aeu_mask = REG_RD(bp, reg_addr);
2783
2784 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
2785 aeu_mask, deasserted);
2786 aeu_mask |= (deasserted & 0xff);
2787 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2760 2788
2761 DP(NETIF_MSG_HW, "new mask %x\n", bp->aeu_mask); 2789 REG_WR(bp, reg_addr, aeu_mask);
2762 REG_WR(bp, reg_addr, bp->aeu_mask); 2790 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2763 2791
2764 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 2792 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2765 bp->attn_state &= ~deasserted; 2793 bp->attn_state &= ~deasserted;
@@ -2800,7 +2828,7 @@ static void bnx2x_sp_task(struct work_struct *work)
2800 2828
2801 /* Return here if interrupt is disabled */ 2829 /* Return here if interrupt is disabled */
2802 if (unlikely(atomic_read(&bp->intr_sem) != 0)) { 2830 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2803 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n"); 2831 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2804 return; 2832 return;
2805 } 2833 }
2806 2834
@@ -2808,7 +2836,7 @@ static void bnx2x_sp_task(struct work_struct *work)
2808/* if (status == 0) */ 2836/* if (status == 0) */
2809/* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 2837/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
2810 2838
2811 DP(BNX2X_MSG_SP, "got a slowpath interrupt (updated %x)\n", status); 2839 DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
2812 2840
2813 /* HW attentions */ 2841 /* HW attentions */
2814 if (status & 0x1) 2842 if (status & 0x1)
@@ -2838,7 +2866,7 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2838 2866
2839 /* Return here if interrupt is disabled */ 2867 /* Return here if interrupt is disabled */
2840 if (unlikely(atomic_read(&bp->intr_sem) != 0)) { 2868 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2841 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n"); 2869 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2842 return IRQ_HANDLED; 2870 return IRQ_HANDLED;
2843 } 2871 }
2844 2872
@@ -2876,11 +2904,11 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2876 /* underflow */ \ 2904 /* underflow */ \
2877 d_hi = m_hi - s_hi; \ 2905 d_hi = m_hi - s_hi; \
2878 if (d_hi > 0) { \ 2906 if (d_hi > 0) { \
2879 /* we can 'loan' 1 */ \ 2907 /* we can 'loan' 1 */ \
2880 d_hi--; \ 2908 d_hi--; \
2881 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \ 2909 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
2882 } else { \ 2910 } else { \
2883 /* m_hi <= s_hi */ \ 2911 /* m_hi <= s_hi */ \
2884 d_hi = 0; \ 2912 d_hi = 0; \
2885 d_lo = 0; \ 2913 d_lo = 0; \
2886 } \ 2914 } \
@@ -2890,7 +2918,7 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2890 d_hi = 0; \ 2918 d_hi = 0; \
2891 d_lo = 0; \ 2919 d_lo = 0; \
2892 } else { \ 2920 } else { \
2893 /* m_hi >= s_hi */ \ 2921 /* m_hi >= s_hi */ \
2894 d_hi = m_hi - s_hi; \ 2922 d_hi = m_hi - s_hi; \
2895 d_lo = m_lo - s_lo; \ 2923 d_lo = m_lo - s_lo; \
2896 } \ 2924 } \
@@ -2963,37 +2991,6 @@ static inline long bnx2x_hilo(u32 *hiref)
2963 * Init service functions 2991 * Init service functions
2964 */ 2992 */
2965 2993
2966static void bnx2x_storm_stats_init(struct bnx2x *bp)
2967{
2968 int func = BP_FUNC(bp);
2969
2970 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func), 1);
2971 REG_WR(bp, BAR_XSTRORM_INTMEM +
2972 XSTORM_STATS_FLAGS_OFFSET(func) + 4, 0);
2973
2974 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func), 1);
2975 REG_WR(bp, BAR_TSTRORM_INTMEM +
2976 TSTORM_STATS_FLAGS_OFFSET(func) + 4, 0);
2977
2978 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func), 0);
2979 REG_WR(bp, BAR_CSTRORM_INTMEM +
2980 CSTORM_STATS_FLAGS_OFFSET(func) + 4, 0);
2981
2982 REG_WR(bp, BAR_XSTRORM_INTMEM +
2983 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
2984 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
2985 REG_WR(bp, BAR_XSTRORM_INTMEM +
2986 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
2987 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
2988
2989 REG_WR(bp, BAR_TSTRORM_INTMEM +
2990 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
2991 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
2992 REG_WR(bp, BAR_TSTRORM_INTMEM +
2993 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
2994 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
2995}
2996
2997static void bnx2x_storm_stats_post(struct bnx2x *bp) 2994static void bnx2x_storm_stats_post(struct bnx2x *bp)
2998{ 2995{
2999 if (!bp->stats_pending) { 2996 if (!bp->stats_pending) {
@@ -3032,6 +3029,8 @@ static void bnx2x_stats_init(struct bnx2x *bp)
3032 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats)); 3029 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
3033 bp->port.old_nig_stats.brb_discard = 3030 bp->port.old_nig_stats.brb_discard =
3034 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38); 3031 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
3032 bp->port.old_nig_stats.brb_truncate =
3033 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
3035 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50, 3034 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
3036 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2); 3035 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
3037 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50, 3036 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
@@ -3101,12 +3100,12 @@ static int bnx2x_stats_comp(struct bnx2x *bp)
3101 3100
3102 might_sleep(); 3101 might_sleep();
3103 while (*stats_comp != DMAE_COMP_VAL) { 3102 while (*stats_comp != DMAE_COMP_VAL) {
3104 msleep(1);
3105 if (!cnt) { 3103 if (!cnt) {
3106 BNX2X_ERR("timeout waiting for stats finished\n"); 3104 BNX2X_ERR("timeout waiting for stats finished\n");
3107 break; 3105 break;
3108 } 3106 }
3109 cnt--; 3107 cnt--;
3108 msleep(1);
3110 } 3109 }
3111 return 1; 3110 return 1;
3112} 3111}
@@ -3451,8 +3450,7 @@ static void bnx2x_bmac_stats_update(struct bnx2x *bp)
3451 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong); 3450 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
3452 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments); 3451 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
3453 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers); 3452 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
3454 UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf); 3453 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
3455 UPDATE_STAT64(rx_stat_grxcf, rx_stat_bmac_xcf);
3456 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered); 3454 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
3457 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffpauseframesreceived); 3455 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffpauseframesreceived);
3458 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent); 3456 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
@@ -3536,6 +3534,8 @@ static int bnx2x_hw_stats_update(struct bnx2x *bp)
3536 3534
3537 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo, 3535 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
3538 new->brb_discard - old->brb_discard); 3536 new->brb_discard - old->brb_discard);
3537 ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
3538 new->brb_truncate - old->brb_truncate);
3539 3539
3540 UPDATE_STAT64_NIG(egress_mac_pkt0, 3540 UPDATE_STAT64_NIG(egress_mac_pkt0,
3541 etherstatspkts1024octetsto1522octets); 3541 etherstatspkts1024octetsto1522octets);
@@ -3713,8 +3713,7 @@ static void bnx2x_net_stats_update(struct bnx2x *bp)
3713 nstats->rx_length_errors = 3713 nstats->rx_length_errors =
3714 estats->rx_stat_etherstatsundersizepkts_lo + 3714 estats->rx_stat_etherstatsundersizepkts_lo +
3715 estats->jabber_packets_received; 3715 estats->jabber_packets_received;
3716 nstats->rx_over_errors = estats->brb_drop_lo + 3716 nstats->rx_over_errors = estats->brb_drop_lo + estats->brb_truncate_lo;
3717 estats->brb_truncate_discard;
3718 nstats->rx_crc_errors = estats->rx_stat_dot3statsfcserrors_lo; 3717 nstats->rx_crc_errors = estats->rx_stat_dot3statsfcserrors_lo;
3719 nstats->rx_frame_errors = estats->rx_stat_dot3statsalignmenterrors_lo; 3718 nstats->rx_frame_errors = estats->rx_stat_dot3statsalignmenterrors_lo;
3720 nstats->rx_fifo_errors = old_tclient->no_buff_discard; 3719 nstats->rx_fifo_errors = old_tclient->no_buff_discard;
@@ -3783,7 +3782,7 @@ static void bnx2x_stats_update(struct bnx2x *bp)
3783 bp->fp->rx_comp_cons), 3782 bp->fp->rx_comp_cons),
3784 le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets); 3783 le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets);
3785 printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u\n", 3784 printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u\n",
3786 netif_queue_stopped(bp->dev)? "Xoff" : "Xon", 3785 netif_queue_stopped(bp->dev) ? "Xoff" : "Xon",
3787 estats->driver_xoff, estats->brb_drop_lo); 3786 estats->driver_xoff, estats->brb_drop_lo);
3788 printk(KERN_DEBUG "tstats: checksum_discard %u " 3787 printk(KERN_DEBUG "tstats: checksum_discard %u "
3789 "packets_too_big_discard %u no_buff_discard %u " 3788 "packets_too_big_discard %u no_buff_discard %u "
@@ -3994,14 +3993,14 @@ static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
3994 3993
3995 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + 3994 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
3996 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, 3995 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
3997 sizeof(struct ustorm_def_status_block)/4); 3996 sizeof(struct ustorm_status_block)/4);
3998 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + 3997 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
3999 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, 3998 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4000 sizeof(struct cstorm_def_status_block)/4); 3999 sizeof(struct cstorm_status_block)/4);
4001} 4000}
4002 4001
4003static void bnx2x_init_sb(struct bnx2x *bp, int sb_id, 4002static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
4004 struct host_status_block *sb, dma_addr_t mapping) 4003 dma_addr_t mapping, int sb_id)
4005{ 4004{
4006 int port = BP_PORT(bp); 4005 int port = BP_PORT(bp);
4007 int func = BP_FUNC(bp); 4006 int func = BP_FUNC(bp);
@@ -4077,7 +4076,6 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4077 atten_status_block); 4076 atten_status_block);
4078 def_sb->atten_status_block.status_block_id = sb_id; 4077 def_sb->atten_status_block.status_block_id = sb_id;
4079 4078
4080 bp->def_att_idx = 0;
4081 bp->attn_state = 0; 4079 bp->attn_state = 0;
4082 4080
4083 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 4081 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
@@ -4094,9 +4092,6 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4094 reg_offset + 0xc + 0x10*index); 4092 reg_offset + 0xc + 0x10*index);
4095 } 4093 }
4096 4094
4097 bp->aeu_mask = REG_RD(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4098 MISC_REG_AEU_MASK_ATTN_FUNC_0));
4099
4100 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 4095 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4101 HC_REG_ATTN_MSG0_ADDR_L); 4096 HC_REG_ATTN_MSG0_ADDR_L);
4102 4097
@@ -4114,17 +4109,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4114 u_def_status_block); 4109 u_def_status_block);
4115 def_sb->u_def_status_block.status_block_id = sb_id; 4110 def_sb->u_def_status_block.status_block_id = sb_id;
4116 4111
4117 bp->def_u_idx = 0;
4118
4119 REG_WR(bp, BAR_USTRORM_INTMEM + 4112 REG_WR(bp, BAR_USTRORM_INTMEM +
4120 USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); 4113 USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4121 REG_WR(bp, BAR_USTRORM_INTMEM + 4114 REG_WR(bp, BAR_USTRORM_INTMEM +
4122 ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), 4115 ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4123 U64_HI(section)); 4116 U64_HI(section));
4124 REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF + 4117 REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
4125 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); 4118 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4126 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(func),
4127 BNX2X_BTR);
4128 4119
4129 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++) 4120 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4130 REG_WR16(bp, BAR_USTRORM_INTMEM + 4121 REG_WR16(bp, BAR_USTRORM_INTMEM +
@@ -4135,17 +4126,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4135 c_def_status_block); 4126 c_def_status_block);
4136 def_sb->c_def_status_block.status_block_id = sb_id; 4127 def_sb->c_def_status_block.status_block_id = sb_id;
4137 4128
4138 bp->def_c_idx = 0;
4139
4140 REG_WR(bp, BAR_CSTRORM_INTMEM + 4129 REG_WR(bp, BAR_CSTRORM_INTMEM +
4141 CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); 4130 CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4142 REG_WR(bp, BAR_CSTRORM_INTMEM + 4131 REG_WR(bp, BAR_CSTRORM_INTMEM +
4143 ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), 4132 ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4144 U64_HI(section)); 4133 U64_HI(section));
4145 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF + 4134 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
4146 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); 4135 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4147 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(func),
4148 BNX2X_BTR);
4149 4136
4150 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++) 4137 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4151 REG_WR16(bp, BAR_CSTRORM_INTMEM + 4138 REG_WR16(bp, BAR_CSTRORM_INTMEM +
@@ -4156,17 +4143,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4156 t_def_status_block); 4143 t_def_status_block);
4157 def_sb->t_def_status_block.status_block_id = sb_id; 4144 def_sb->t_def_status_block.status_block_id = sb_id;
4158 4145
4159 bp->def_t_idx = 0;
4160
4161 REG_WR(bp, BAR_TSTRORM_INTMEM + 4146 REG_WR(bp, BAR_TSTRORM_INTMEM +
4162 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); 4147 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4163 REG_WR(bp, BAR_TSTRORM_INTMEM + 4148 REG_WR(bp, BAR_TSTRORM_INTMEM +
4164 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), 4149 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4165 U64_HI(section)); 4150 U64_HI(section));
4166 REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF + 4151 REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
4167 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); 4152 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4168 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(func),
4169 BNX2X_BTR);
4170 4153
4171 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++) 4154 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4172 REG_WR16(bp, BAR_TSTRORM_INTMEM + 4155 REG_WR16(bp, BAR_TSTRORM_INTMEM +
@@ -4177,23 +4160,20 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4177 x_def_status_block); 4160 x_def_status_block);
4178 def_sb->x_def_status_block.status_block_id = sb_id; 4161 def_sb->x_def_status_block.status_block_id = sb_id;
4179 4162
4180 bp->def_x_idx = 0;
4181
4182 REG_WR(bp, BAR_XSTRORM_INTMEM + 4163 REG_WR(bp, BAR_XSTRORM_INTMEM +
4183 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); 4164 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4184 REG_WR(bp, BAR_XSTRORM_INTMEM + 4165 REG_WR(bp, BAR_XSTRORM_INTMEM +
4185 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), 4166 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4186 U64_HI(section)); 4167 U64_HI(section));
4187 REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF + 4168 REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
4188 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); 4169 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4189 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(func),
4190 BNX2X_BTR);
4191 4170
4192 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++) 4171 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4193 REG_WR16(bp, BAR_XSTRORM_INTMEM + 4172 REG_WR16(bp, BAR_XSTRORM_INTMEM +
4194 XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1); 4173 XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4195 4174
4196 bp->stats_pending = 0; 4175 bp->stats_pending = 0;
4176 bp->set_mac_pending = 0;
4197 4177
4198 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0); 4178 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4199} 4179}
@@ -4209,21 +4189,25 @@ static void bnx2x_update_coalesce(struct bnx2x *bp)
4209 /* HC_INDEX_U_ETH_RX_CQ_CONS */ 4189 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4210 REG_WR8(bp, BAR_USTRORM_INTMEM + 4190 REG_WR8(bp, BAR_USTRORM_INTMEM +
4211 USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id, 4191 USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4212 HC_INDEX_U_ETH_RX_CQ_CONS), 4192 U_SB_ETH_RX_CQ_INDEX),
4213 bp->rx_ticks/12); 4193 bp->rx_ticks/12);
4214 REG_WR16(bp, BAR_USTRORM_INTMEM + 4194 REG_WR16(bp, BAR_USTRORM_INTMEM +
4215 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, 4195 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4216 HC_INDEX_U_ETH_RX_CQ_CONS), 4196 U_SB_ETH_RX_CQ_INDEX),
4197 bp->rx_ticks ? 0 : 1);
4198 REG_WR16(bp, BAR_USTRORM_INTMEM +
4199 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4200 U_SB_ETH_RX_BD_INDEX),
4217 bp->rx_ticks ? 0 : 1); 4201 bp->rx_ticks ? 0 : 1);
4218 4202
4219 /* HC_INDEX_C_ETH_TX_CQ_CONS */ 4203 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4220 REG_WR8(bp, BAR_CSTRORM_INTMEM + 4204 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4221 CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id, 4205 CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4222 HC_INDEX_C_ETH_TX_CQ_CONS), 4206 C_SB_ETH_TX_CQ_INDEX),
4223 bp->tx_ticks/12); 4207 bp->tx_ticks/12);
4224 REG_WR16(bp, BAR_CSTRORM_INTMEM + 4208 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4225 CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, 4209 CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4226 HC_INDEX_C_ETH_TX_CQ_CONS), 4210 C_SB_ETH_TX_CQ_INDEX),
4227 bp->tx_ticks ? 0 : 1); 4211 bp->tx_ticks ? 0 : 1);
4228 } 4212 }
4229} 4213}
@@ -4256,7 +4240,9 @@ static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
4256static void bnx2x_init_rx_rings(struct bnx2x *bp) 4240static void bnx2x_init_rx_rings(struct bnx2x *bp)
4257{ 4241{
4258 int func = BP_FUNC(bp); 4242 int func = BP_FUNC(bp);
4259 u16 ring_prod, cqe_ring_prod = 0; 4243 int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
4244 ETH_MAX_AGGREGATION_QUEUES_E1H;
4245 u16 ring_prod, cqe_ring_prod;
4260 int i, j; 4246 int i, j;
4261 4247
4262 bp->rx_buf_use_size = bp->dev->mtu; 4248 bp->rx_buf_use_size = bp->dev->mtu;
@@ -4270,9 +4256,9 @@ static void bnx2x_init_rx_rings(struct bnx2x *bp)
4270 bp->dev->mtu + ETH_OVREHEAD); 4256 bp->dev->mtu + ETH_OVREHEAD);
4271 4257
4272 for_each_queue(bp, j) { 4258 for_each_queue(bp, j) {
4273 for (i = 0; i < ETH_MAX_AGGREGATION_QUEUES_E1H; i++) { 4259 struct bnx2x_fastpath *fp = &bp->fp[j];
4274 struct bnx2x_fastpath *fp = &bp->fp[j];
4275 4260
4261 for (i = 0; i < max_agg_queues; i++) {
4276 fp->tpa_pool[i].skb = 4262 fp->tpa_pool[i].skb =
4277 netdev_alloc_skb(bp->dev, bp->rx_buf_size); 4263 netdev_alloc_skb(bp->dev, bp->rx_buf_size);
4278 if (!fp->tpa_pool[i].skb) { 4264 if (!fp->tpa_pool[i].skb) {
@@ -4352,8 +4338,7 @@ static void bnx2x_init_rx_rings(struct bnx2x *bp)
4352 BNX2X_ERR("disabling TPA for queue[%d]\n", j); 4338 BNX2X_ERR("disabling TPA for queue[%d]\n", j);
4353 /* Cleanup already allocated elements */ 4339 /* Cleanup already allocated elements */
4354 bnx2x_free_rx_sge_range(bp, fp, ring_prod); 4340 bnx2x_free_rx_sge_range(bp, fp, ring_prod);
4355 bnx2x_free_tpa_pool(bp, fp, 4341 bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
4356 ETH_MAX_AGGREGATION_QUEUES_E1H);
4357 fp->disable_tpa = 1; 4342 fp->disable_tpa = 1;
4358 ring_prod = 0; 4343 ring_prod = 0;
4359 break; 4344 break;
@@ -4363,13 +4348,13 @@ static void bnx2x_init_rx_rings(struct bnx2x *bp)
4363 fp->rx_sge_prod = ring_prod; 4348 fp->rx_sge_prod = ring_prod;
4364 4349
4365 /* Allocate BDs and initialize BD ring */ 4350 /* Allocate BDs and initialize BD ring */
4366 fp->rx_comp_cons = fp->rx_alloc_failed = 0; 4351 fp->rx_comp_cons = 0;
4367 cqe_ring_prod = ring_prod = 0; 4352 cqe_ring_prod = ring_prod = 0;
4368 for (i = 0; i < bp->rx_ring_size; i++) { 4353 for (i = 0; i < bp->rx_ring_size; i++) {
4369 if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) { 4354 if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
4370 BNX2X_ERR("was only able to allocate " 4355 BNX2X_ERR("was only able to allocate "
4371 "%d rx skbs\n", i); 4356 "%d rx skbs\n", i);
4372 fp->rx_alloc_failed++; 4357 bp->eth_stats.rx_skb_alloc_failed++;
4373 break; 4358 break;
4374 } 4359 }
4375 ring_prod = NEXT_RX_IDX(ring_prod); 4360 ring_prod = NEXT_RX_IDX(ring_prod);
@@ -4497,7 +4482,7 @@ static void bnx2x_init_context(struct bnx2x *bp)
4497 } 4482 }
4498 4483
4499 context->cstorm_st_context.sb_index_number = 4484 context->cstorm_st_context.sb_index_number =
4500 HC_INDEX_C_ETH_TX_CQ_CONS; 4485 C_SB_ETH_TX_CQ_INDEX;
4501 context->cstorm_st_context.status_block_id = sb_id; 4486 context->cstorm_st_context.status_block_id = sb_id;
4502 4487
4503 context->xstorm_ag_context.cdu_reserved = 4488 context->xstorm_ag_context.cdu_reserved =
@@ -4535,7 +4520,7 @@ static void bnx2x_set_client_config(struct bnx2x *bp)
4535 int i; 4520 int i;
4536 4521
4537 tstorm_client.mtu = bp->dev->mtu + ETH_OVREHEAD; 4522 tstorm_client.mtu = bp->dev->mtu + ETH_OVREHEAD;
4538 tstorm_client.statistics_counter_id = 0; 4523 tstorm_client.statistics_counter_id = BP_CL_ID(bp);
4539 tstorm_client.config_flags = 4524 tstorm_client.config_flags =
4540 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE; 4525 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
4541#ifdef BCM_VLAN 4526#ifdef BCM_VLAN
@@ -4579,7 +4564,7 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4579 int func = BP_FUNC(bp); 4564 int func = BP_FUNC(bp);
4580 int i; 4565 int i;
4581 4566
4582 DP(NETIF_MSG_RX_STATUS, "rx mode is %d\n", mode); 4567 DP(NETIF_MSG_IFUP, "rx mode %d mask 0x%x\n", mode, mask);
4583 4568
4584 switch (mode) { 4569 switch (mode) {
4585 case BNX2X_RX_MODE_NONE: /* no Rx */ 4570 case BNX2X_RX_MODE_NONE: /* no Rx */
@@ -4617,13 +4602,35 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4617 bnx2x_set_client_config(bp); 4602 bnx2x_set_client_config(bp);
4618} 4603}
4619 4604
4620static void bnx2x_init_internal(struct bnx2x *bp) 4605static void bnx2x_init_internal_common(struct bnx2x *bp)
4606{
4607 int i;
4608
4609 /* Zero this manually as its initialization is
4610 currently missing in the initTool */
4611 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4612 REG_WR(bp, BAR_USTRORM_INTMEM +
4613 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4614}
4615
4616static void bnx2x_init_internal_port(struct bnx2x *bp)
4617{
4618 int port = BP_PORT(bp);
4619
4620 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4621 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4622 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4623 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4624}
4625
4626static void bnx2x_init_internal_func(struct bnx2x *bp)
4621{ 4627{
4622 struct tstorm_eth_function_common_config tstorm_config = {0}; 4628 struct tstorm_eth_function_common_config tstorm_config = {0};
4623 struct stats_indication_flags stats_flags = {0}; 4629 struct stats_indication_flags stats_flags = {0};
4624 int port = BP_PORT(bp); 4630 int port = BP_PORT(bp);
4625 int func = BP_FUNC(bp); 4631 int func = BP_FUNC(bp);
4626 int i; 4632 int i;
4633 u16 max_agg_size;
4627 4634
4628 if (is_multi(bp)) { 4635 if (is_multi(bp)) {
4629 tstorm_config.config_flags = MULTI_FLAGS; 4636 tstorm_config.config_flags = MULTI_FLAGS;
@@ -4636,31 +4643,53 @@ static void bnx2x_init_internal(struct bnx2x *bp)
4636 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func), 4643 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
4637 (*(u32 *)&tstorm_config)); 4644 (*(u32 *)&tstorm_config));
4638 4645
4639/* DP(NETIF_MSG_IFUP, "tstorm_config: 0x%08x\n",
4640 (*(u32 *)&tstorm_config)); */
4641
4642 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */ 4646 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4643 bnx2x_set_storm_rx_mode(bp); 4647 bnx2x_set_storm_rx_mode(bp);
4644 4648
4649 /* reset xstorm per client statistics */
4650 for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++) {
4651 REG_WR(bp, BAR_XSTRORM_INTMEM +
4652 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4653 i*4, 0);
4654 }
4655 /* reset tstorm per client statistics */
4656 for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++) {
4657 REG_WR(bp, BAR_TSTRORM_INTMEM +
4658 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4659 i*4, 0);
4660 }
4661
4662 /* Init statistics related context */
4645 stats_flags.collect_eth = 1; 4663 stats_flags.collect_eth = 1;
4646 4664
4647 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port), 4665 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
4648 ((u32 *)&stats_flags)[0]); 4666 ((u32 *)&stats_flags)[0]);
4649 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port) + 4, 4667 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
4650 ((u32 *)&stats_flags)[1]); 4668 ((u32 *)&stats_flags)[1]);
4651 4669
4652 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port), 4670 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
4653 ((u32 *)&stats_flags)[0]); 4671 ((u32 *)&stats_flags)[0]);
4654 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port) + 4, 4672 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
4655 ((u32 *)&stats_flags)[1]); 4673 ((u32 *)&stats_flags)[1]);
4656 4674
4657 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port), 4675 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
4658 ((u32 *)&stats_flags)[0]); 4676 ((u32 *)&stats_flags)[0]);
4659 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port) + 4, 4677 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
4660 ((u32 *)&stats_flags)[1]); 4678 ((u32 *)&stats_flags)[1]);
4661 4679
4662/* DP(NETIF_MSG_IFUP, "stats_flags: 0x%08x 0x%08x\n", 4680 REG_WR(bp, BAR_XSTRORM_INTMEM +
4663 ((u32 *)&stats_flags)[0], ((u32 *)&stats_flags)[1]); */ 4681 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4682 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4683 REG_WR(bp, BAR_XSTRORM_INTMEM +
4684 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4685 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4686
4687 REG_WR(bp, BAR_TSTRORM_INTMEM +
4688 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4689 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4690 REG_WR(bp, BAR_TSTRORM_INTMEM +
4691 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4692 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4664 4693
4665 if (CHIP_IS_E1H(bp)) { 4694 if (CHIP_IS_E1H(bp)) {
4666 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET, 4695 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
@@ -4676,15 +4705,12 @@ static void bnx2x_init_internal(struct bnx2x *bp)
4676 bp->e1hov); 4705 bp->e1hov);
4677 } 4706 }
4678 4707
4679 /* Zero this manualy as its initialization is 4708 /* Init CQ ring mapping and aggregation size */
4680 currently missing in the initTool */ 4709 max_agg_size = min((u32)(bp->rx_buf_use_size +
4681 for (i = 0; i < USTORM_AGG_DATA_SIZE >> 2; i++) 4710 8*BCM_PAGE_SIZE*PAGES_PER_SGE),
4682 REG_WR(bp, BAR_USTRORM_INTMEM + 4711 (u32)0xffff);
4683 USTORM_AGG_DATA_OFFSET + 4*i, 0);
4684
4685 for_each_queue(bp, i) { 4712 for_each_queue(bp, i) {
4686 struct bnx2x_fastpath *fp = &bp->fp[i]; 4713 struct bnx2x_fastpath *fp = &bp->fp[i];
4687 u16 max_agg_size;
4688 4714
4689 REG_WR(bp, BAR_USTRORM_INTMEM + 4715 REG_WR(bp, BAR_USTRORM_INTMEM +
4690 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)), 4716 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)),
@@ -4693,16 +4719,34 @@ static void bnx2x_init_internal(struct bnx2x *bp)
4693 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4, 4719 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4,
4694 U64_HI(fp->rx_comp_mapping)); 4720 U64_HI(fp->rx_comp_mapping));
4695 4721
4696 max_agg_size = min((u32)(bp->rx_buf_use_size +
4697 8*BCM_PAGE_SIZE*PAGES_PER_SGE),
4698 (u32)0xffff);
4699 REG_WR16(bp, BAR_USTRORM_INTMEM + 4722 REG_WR16(bp, BAR_USTRORM_INTMEM +
4700 USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)), 4723 USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)),
4701 max_agg_size); 4724 max_agg_size);
4702 } 4725 }
4703} 4726}
4704 4727
4705static void bnx2x_nic_init(struct bnx2x *bp) 4728static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4729{
4730 switch (load_code) {
4731 case FW_MSG_CODE_DRV_LOAD_COMMON:
4732 bnx2x_init_internal_common(bp);
4733 /* no break */
4734
4735 case FW_MSG_CODE_DRV_LOAD_PORT:
4736 bnx2x_init_internal_port(bp);
4737 /* no break */
4738
4739 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4740 bnx2x_init_internal_func(bp);
4741 break;
4742
4743 default:
4744 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4745 break;
4746 }
4747}
4748
4749static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4706{ 4750{
4707 int i; 4751 int i;
4708 4752
@@ -4717,19 +4761,20 @@ static void bnx2x_nic_init(struct bnx2x *bp)
4717 DP(NETIF_MSG_IFUP, 4761 DP(NETIF_MSG_IFUP,
4718 "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n", 4762 "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n",
4719 bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp)); 4763 bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
4720 bnx2x_init_sb(bp, FP_SB_ID(fp), fp->status_blk, 4764 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
4721 fp->status_blk_mapping); 4765 FP_SB_ID(fp));
4766 bnx2x_update_fpsb_idx(fp);
4722 } 4767 }
4723 4768
4724 bnx2x_init_def_sb(bp, bp->def_status_blk, 4769 bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
4725 bp->def_status_blk_mapping, DEF_SB_ID); 4770 DEF_SB_ID);
4771 bnx2x_update_dsb_idx(bp);
4726 bnx2x_update_coalesce(bp); 4772 bnx2x_update_coalesce(bp);
4727 bnx2x_init_rx_rings(bp); 4773 bnx2x_init_rx_rings(bp);
4728 bnx2x_init_tx_ring(bp); 4774 bnx2x_init_tx_ring(bp);
4729 bnx2x_init_sp_ring(bp); 4775 bnx2x_init_sp_ring(bp);
4730 bnx2x_init_context(bp); 4776 bnx2x_init_context(bp);
4731 bnx2x_init_internal(bp); 4777 bnx2x_init_internal(bp, load_code);
4732 bnx2x_storm_stats_init(bp);
4733 bnx2x_init_ind_table(bp); 4778 bnx2x_init_ind_table(bp);
4734 bnx2x_int_enable(bp); 4779 bnx2x_int_enable(bp);
4735} 4780}
@@ -4878,7 +4923,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
4878 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 4923 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4879 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 4924 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4880 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 4925 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4881 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0); 4926 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4882 4927
4883 /* Write 0 to parser credits for CFC search request */ 4928 /* Write 0 to parser credits for CFC search request */
4884 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 4929 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
@@ -4933,7 +4978,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
4933 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 4978 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4934 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 4979 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4935 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 4980 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4936 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0); 4981 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4937 4982
4938 /* Write 0 to parser credits for CFC search request */ 4983 /* Write 0 to parser credits for CFC search request */
4939 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 4984 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
@@ -5000,7 +5045,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
5000 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5045 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5001 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5046 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5002 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5047 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5003 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x1); 5048 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5004 5049
5005 DP(NETIF_MSG_HW, "done\n"); 5050 DP(NETIF_MSG_HW, "done\n");
5006 5051
@@ -5089,11 +5134,6 @@ static int bnx2x_init_common(struct bnx2x *bp)
5089 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 5134 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5090#endif 5135#endif
5091 5136
5092#ifndef BCM_ISCSI
5093 /* set NIC mode */
5094 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5095#endif
5096
5097 REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2); 5137 REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
5098#ifdef BCM_ISCSI 5138#ifdef BCM_ISCSI
5099 REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5); 5139 REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
@@ -5163,6 +5203,8 @@ static int bnx2x_init_common(struct bnx2x *bp)
5163 } 5203 }
5164 5204
5165 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END); 5205 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5206 /* set NIC mode */
5207 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5166 if (CHIP_IS_E1H(bp)) 5208 if (CHIP_IS_E1H(bp))
5167 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp)); 5209 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
5168 5210
@@ -5333,6 +5375,13 @@ static int bnx2x_init_common(struct bnx2x *bp)
5333 ((u32 *)&tmp)[1]); 5375 ((u32 *)&tmp)[1]);
5334 } 5376 }
5335 5377
5378 if (!BP_NOMCP(bp)) {
5379 bnx2x_acquire_phy_lock(bp);
5380 bnx2x_common_init_phy(bp, bp->common.shmem_base);
5381 bnx2x_release_phy_lock(bp);
5382 } else
5383 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5384
5336 return 0; 5385 return 0;
5337} 5386}
5338 5387
@@ -5638,18 +5687,23 @@ static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
5638 int func = BP_FUNC(bp); 5687 int func = BP_FUNC(bp);
5639 u32 seq = ++bp->fw_seq; 5688 u32 seq = ++bp->fw_seq;
5640 u32 rc = 0; 5689 u32 rc = 0;
5690 u32 cnt = 1;
5691 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
5641 5692
5642 SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq)); 5693 SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
5643 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq)); 5694 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
5644 5695
5645 /* let the FW do it's magic ... */ 5696 do {
5646 msleep(100); /* TBD */ 5697 /* let the FW do it's magic ... */
5698 msleep(delay);
5647 5699
5648 if (CHIP_REV_IS_SLOW(bp)) 5700 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
5649 msleep(900);
5650 5701
5651 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header); 5702 /* Give the FW up to 2 second (200*10ms) */
5652 DP(BNX2X_MSG_MCP, "read (%x) seq is (%x) from FW MB\n", rc, seq); 5703 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));
5704
5705 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
5706 cnt*delay, rc, seq);
5653 5707
5654 /* is this a reply to our command? */ 5708 /* is this a reply to our command? */
5655 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) { 5709 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
@@ -5713,6 +5767,7 @@ static void bnx2x_free_mem(struct bnx2x *bp)
5713 NUM_RCQ_BD); 5767 NUM_RCQ_BD);
5714 5768
5715 /* SGE ring */ 5769 /* SGE ring */
5770 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
5716 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring), 5771 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
5717 bnx2x_fp(bp, i, rx_sge_mapping), 5772 bnx2x_fp(bp, i, rx_sge_mapping),
5718 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES); 5773 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
@@ -5890,7 +5945,8 @@ static void bnx2x_free_rx_skbs(struct bnx2x *bp)
5890 dev_kfree_skb(skb); 5945 dev_kfree_skb(skb);
5891 } 5946 }
5892 if (!fp->disable_tpa) 5947 if (!fp->disable_tpa)
5893 bnx2x_free_tpa_pool(bp, fp, 5948 bnx2x_free_tpa_pool(bp, fp, CHIP_IS_E1(bp) ?
5949 ETH_MAX_AGGREGATION_QUEUES_E1 :
5894 ETH_MAX_AGGREGATION_QUEUES_E1H); 5950 ETH_MAX_AGGREGATION_QUEUES_E1H);
5895 } 5951 }
5896} 5952}
@@ -5976,8 +6032,8 @@ static int bnx2x_req_msix_irqs(struct bnx2x *bp)
5976 bnx2x_msix_fp_int, 0, 6032 bnx2x_msix_fp_int, 0,
5977 bp->dev->name, &bp->fp[i]); 6033 bp->dev->name, &bp->fp[i]);
5978 if (rc) { 6034 if (rc) {
5979 BNX2X_ERR("request fp #%d irq failed rc %d\n", 6035 BNX2X_ERR("request fp #%d irq failed rc -%d\n",
5980 i + offset, rc); 6036 i + offset, -rc);
5981 bnx2x_free_msix_irqs(bp); 6037 bnx2x_free_msix_irqs(bp);
5982 return -EBUSY; 6038 return -EBUSY;
5983 } 6039 }
@@ -6004,7 +6060,7 @@ static int bnx2x_req_irq(struct bnx2x *bp)
6004 * Init service functions 6060 * Init service functions
6005 */ 6061 */
6006 6062
6007static void bnx2x_set_mac_addr_e1(struct bnx2x *bp) 6063static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set)
6008{ 6064{
6009 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config); 6065 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
6010 int port = BP_PORT(bp); 6066 int port = BP_PORT(bp);
@@ -6026,11 +6082,15 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp)
6026 config->config_table[0].cam_entry.lsb_mac_addr = 6082 config->config_table[0].cam_entry.lsb_mac_addr =
6027 swab16(*(u16 *)&bp->dev->dev_addr[4]); 6083 swab16(*(u16 *)&bp->dev->dev_addr[4]);
6028 config->config_table[0].cam_entry.flags = cpu_to_le16(port); 6084 config->config_table[0].cam_entry.flags = cpu_to_le16(port);
6029 config->config_table[0].target_table_entry.flags = 0; 6085 if (set)
6086 config->config_table[0].target_table_entry.flags = 0;
6087 else
6088 CAM_INVALIDATE(config->config_table[0]);
6030 config->config_table[0].target_table_entry.client_id = 0; 6089 config->config_table[0].target_table_entry.client_id = 0;
6031 config->config_table[0].target_table_entry.vlan_id = 0; 6090 config->config_table[0].target_table_entry.vlan_id = 0;
6032 6091
6033 DP(NETIF_MSG_IFUP, "setting MAC (%04x:%04x:%04x)\n", 6092 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n",
6093 (set ? "setting" : "clearing"),
6034 config->config_table[0].cam_entry.msb_mac_addr, 6094 config->config_table[0].cam_entry.msb_mac_addr,
6035 config->config_table[0].cam_entry.middle_mac_addr, 6095 config->config_table[0].cam_entry.middle_mac_addr,
6036 config->config_table[0].cam_entry.lsb_mac_addr); 6096 config->config_table[0].cam_entry.lsb_mac_addr);
@@ -6040,8 +6100,11 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp)
6040 config->config_table[1].cam_entry.middle_mac_addr = 0xffff; 6100 config->config_table[1].cam_entry.middle_mac_addr = 0xffff;
6041 config->config_table[1].cam_entry.lsb_mac_addr = 0xffff; 6101 config->config_table[1].cam_entry.lsb_mac_addr = 0xffff;
6042 config->config_table[1].cam_entry.flags = cpu_to_le16(port); 6102 config->config_table[1].cam_entry.flags = cpu_to_le16(port);
6043 config->config_table[1].target_table_entry.flags = 6103 if (set)
6104 config->config_table[1].target_table_entry.flags =
6044 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST; 6105 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
6106 else
6107 CAM_INVALIDATE(config->config_table[1]);
6045 config->config_table[1].target_table_entry.client_id = 0; 6108 config->config_table[1].target_table_entry.client_id = 0;
6046 config->config_table[1].target_table_entry.vlan_id = 0; 6109 config->config_table[1].target_table_entry.vlan_id = 0;
6047 6110
@@ -6050,12 +6113,12 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp)
6050 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0); 6113 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
6051} 6114}
6052 6115
6053static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp) 6116static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set)
6054{ 6117{
6055 struct mac_configuration_cmd_e1h *config = 6118 struct mac_configuration_cmd_e1h *config =
6056 (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config); 6119 (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
6057 6120
6058 if (bp->state != BNX2X_STATE_OPEN) { 6121 if (set && (bp->state != BNX2X_STATE_OPEN)) {
6059 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 6122 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
6060 return; 6123 return;
6061 } 6124 }
@@ -6079,9 +6142,14 @@ static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp)
6079 config->config_table[0].client_id = BP_L_ID(bp); 6142 config->config_table[0].client_id = BP_L_ID(bp);
6080 config->config_table[0].vlan_id = 0; 6143 config->config_table[0].vlan_id = 0;
6081 config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov); 6144 config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
6082 config->config_table[0].flags = BP_PORT(bp); 6145 if (set)
6146 config->config_table[0].flags = BP_PORT(bp);
6147 else
6148 config->config_table[0].flags =
6149 MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE;
6083 6150
6084 DP(NETIF_MSG_IFUP, "setting MAC (%04x:%04x:%04x) E1HOV %d CLID %d\n", 6151 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) E1HOV %d CLID %d\n",
6152 (set ? "setting" : "clearing"),
6085 config->config_table[0].msb_mac_addr, 6153 config->config_table[0].msb_mac_addr,
6086 config->config_table[0].middle_mac_addr, 6154 config->config_table[0].middle_mac_addr,
6087 config->config_table[0].lsb_mac_addr, bp->e1hov, BP_L_ID(bp)); 6155 config->config_table[0].lsb_mac_addr, bp->e1hov, BP_L_ID(bp));
@@ -6106,13 +6174,13 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6106 bnx2x_rx_int(bp->fp, 10); 6174 bnx2x_rx_int(bp->fp, 10);
6107 /* if index is different from 0 6175 /* if index is different from 0
6108 * the reply for some commands will 6176 * the reply for some commands will
6109 * be on the none default queue 6177 * be on the non default queue
6110 */ 6178 */
6111 if (idx) 6179 if (idx)
6112 bnx2x_rx_int(&bp->fp[idx], 10); 6180 bnx2x_rx_int(&bp->fp[idx], 10);
6113 } 6181 }
6114 mb(); /* state is changed by bnx2x_sp_event() */
6115 6182
6183 mb(); /* state is changed by bnx2x_sp_event() */
6116 if (*state_p == state) 6184 if (*state_p == state)
6117 return 0; 6185 return 0;
6118 6186
@@ -6167,7 +6235,6 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6167{ 6235{
6168 u32 load_code; 6236 u32 load_code;
6169 int i, rc; 6237 int i, rc;
6170
6171#ifdef BNX2X_STOP_ON_ERROR 6238#ifdef BNX2X_STOP_ON_ERROR
6172 if (unlikely(bp->panic)) 6239 if (unlikely(bp->panic))
6173 return -EPERM; 6240 return -EPERM;
@@ -6183,22 +6250,24 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6183 if (!BP_NOMCP(bp)) { 6250 if (!BP_NOMCP(bp)) {
6184 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ); 6251 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ);
6185 if (!load_code) { 6252 if (!load_code) {
6186 BNX2X_ERR("MCP response failure, unloading\n"); 6253 BNX2X_ERR("MCP response failure, aborting\n");
6187 return -EBUSY; 6254 return -EBUSY;
6188 } 6255 }
6189 if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED) 6256 if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED)
6190 return -EBUSY; /* other port in diagnostic mode */ 6257 return -EBUSY; /* other port in diagnostic mode */
6191 6258
6192 } else { 6259 } else {
6260 int port = BP_PORT(bp);
6261
6193 DP(NETIF_MSG_IFUP, "NO MCP load counts before us %d, %d, %d\n", 6262 DP(NETIF_MSG_IFUP, "NO MCP load counts before us %d, %d, %d\n",
6194 load_count[0], load_count[1], load_count[2]); 6263 load_count[0], load_count[1], load_count[2]);
6195 load_count[0]++; 6264 load_count[0]++;
6196 load_count[1 + BP_PORT(bp)]++; 6265 load_count[1 + port]++;
6197 DP(NETIF_MSG_IFUP, "NO MCP new load counts %d, %d, %d\n", 6266 DP(NETIF_MSG_IFUP, "NO MCP new load counts %d, %d, %d\n",
6198 load_count[0], load_count[1], load_count[2]); 6267 load_count[0], load_count[1], load_count[2]);
6199 if (load_count[0] == 1) 6268 if (load_count[0] == 1)
6200 load_code = FW_MSG_CODE_DRV_LOAD_COMMON; 6269 load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
6201 else if (load_count[1 + BP_PORT(bp)] == 1) 6270 else if (load_count[1 + port] == 1)
6202 load_code = FW_MSG_CODE_DRV_LOAD_PORT; 6271 load_code = FW_MSG_CODE_DRV_LOAD_PORT;
6203 else 6272 else
6204 load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION; 6273 load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION;
@@ -6247,9 +6316,6 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6247 bnx2x_fp(bp, i, disable_tpa) = 6316 bnx2x_fp(bp, i, disable_tpa) =
6248 ((bp->flags & TPA_ENABLE_FLAG) == 0); 6317 ((bp->flags & TPA_ENABLE_FLAG) == 0);
6249 6318
6250 /* Disable interrupt handling until HW is initialized */
6251 atomic_set(&bp->intr_sem, 1);
6252
6253 if (bp->flags & USING_MSIX_FLAG) { 6319 if (bp->flags & USING_MSIX_FLAG) {
6254 rc = bnx2x_req_msix_irqs(bp); 6320 rc = bnx2x_req_msix_irqs(bp);
6255 if (rc) { 6321 if (rc) {
@@ -6276,17 +6342,14 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6276 goto load_error; 6342 goto load_error;
6277 } 6343 }
6278 6344
6279 /* Enable interrupt handling */
6280 atomic_set(&bp->intr_sem, 0);
6281
6282 /* Setup NIC internals and enable interrupts */ 6345 /* Setup NIC internals and enable interrupts */
6283 bnx2x_nic_init(bp); 6346 bnx2x_nic_init(bp, load_code);
6284 6347
6285 /* Send LOAD_DONE command to MCP */ 6348 /* Send LOAD_DONE command to MCP */
6286 if (!BP_NOMCP(bp)) { 6349 if (!BP_NOMCP(bp)) {
6287 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE); 6350 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
6288 if (!load_code) { 6351 if (!load_code) {
6289 BNX2X_ERR("MCP response failure, unloading\n"); 6352 BNX2X_ERR("MCP response failure, aborting\n");
6290 rc = -EBUSY; 6353 rc = -EBUSY;
6291 goto load_int_disable; 6354 goto load_int_disable;
6292 } 6355 }
@@ -6301,11 +6364,12 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6301 for_each_queue(bp, i) 6364 for_each_queue(bp, i)
6302 napi_enable(&bnx2x_fp(bp, i, napi)); 6365 napi_enable(&bnx2x_fp(bp, i, napi));
6303 6366
6367 /* Enable interrupt handling */
6368 atomic_set(&bp->intr_sem, 0);
6369
6304 rc = bnx2x_setup_leading(bp); 6370 rc = bnx2x_setup_leading(bp);
6305 if (rc) { 6371 if (rc) {
6306#ifdef BNX2X_STOP_ON_ERROR 6372 BNX2X_ERR("Setup leading failed!\n");
6307 bp->panic = 1;
6308#endif
6309 goto load_stop_netif; 6373 goto load_stop_netif;
6310 } 6374 }
6311 6375
@@ -6323,9 +6387,9 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6323 } 6387 }
6324 6388
6325 if (CHIP_IS_E1(bp)) 6389 if (CHIP_IS_E1(bp))
6326 bnx2x_set_mac_addr_e1(bp); 6390 bnx2x_set_mac_addr_e1(bp, 1);
6327 else 6391 else
6328 bnx2x_set_mac_addr_e1h(bp); 6392 bnx2x_set_mac_addr_e1h(bp, 1);
6329 6393
6330 if (bp->port.pmf) 6394 if (bp->port.pmf)
6331 bnx2x_initial_phy_init(bp); 6395 bnx2x_initial_phy_init(bp);
@@ -6339,7 +6403,6 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6339 break; 6403 break;
6340 6404
6341 case LOAD_OPEN: 6405 case LOAD_OPEN:
6342 /* IRQ is only requested from bnx2x_open */
6343 netif_start_queue(bp->dev); 6406 netif_start_queue(bp->dev);
6344 bnx2x_set_rx_mode(bp->dev); 6407 bnx2x_set_rx_mode(bp->dev);
6345 if (bp->flags & USING_MSIX_FLAG) 6408 if (bp->flags & USING_MSIX_FLAG)
@@ -6378,8 +6441,7 @@ load_int_disable:
6378 /* Free SKBs, SGEs, TPA pool and driver internals */ 6441 /* Free SKBs, SGEs, TPA pool and driver internals */
6379 bnx2x_free_skbs(bp); 6442 bnx2x_free_skbs(bp);
6380 for_each_queue(bp, i) 6443 for_each_queue(bp, i)
6381 bnx2x_free_rx_sge_range(bp, bp->fp + i, 6444 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
6382 RX_SGE_CNT*NUM_RX_SGE_PAGES);
6383load_error: 6445load_error:
6384 bnx2x_free_mem(bp); 6446 bnx2x_free_mem(bp);
6385 6447
@@ -6411,7 +6473,7 @@ static int bnx2x_stop_multi(struct bnx2x *bp, int index)
6411 return rc; 6473 return rc;
6412} 6474}
6413 6475
6414static void bnx2x_stop_leading(struct bnx2x *bp) 6476static int bnx2x_stop_leading(struct bnx2x *bp)
6415{ 6477{
6416 u16 dsb_sp_prod_idx; 6478 u16 dsb_sp_prod_idx;
6417 /* if the other port is handling traffic, 6479 /* if the other port is handling traffic,
@@ -6429,7 +6491,7 @@ static void bnx2x_stop_leading(struct bnx2x *bp)
6429 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0, 6491 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
6430 &(bp->fp[0].state), 1); 6492 &(bp->fp[0].state), 1);
6431 if (rc) /* timeout */ 6493 if (rc) /* timeout */
6432 return; 6494 return rc;
6433 6495
6434 dsb_sp_prod_idx = *bp->dsb_sp_prod; 6496 dsb_sp_prod_idx = *bp->dsb_sp_prod;
6435 6497
@@ -6441,20 +6503,24 @@ static void bnx2x_stop_leading(struct bnx2x *bp)
6441 so there is not much to do if this times out 6503 so there is not much to do if this times out
6442 */ 6504 */
6443 while (dsb_sp_prod_idx == *bp->dsb_sp_prod) { 6505 while (dsb_sp_prod_idx == *bp->dsb_sp_prod) {
6444 msleep(1);
6445 if (!cnt) { 6506 if (!cnt) {
6446 DP(NETIF_MSG_IFDOWN, "timeout waiting for port del " 6507 DP(NETIF_MSG_IFDOWN, "timeout waiting for port del "
6447 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n", 6508 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
6448 *bp->dsb_sp_prod, dsb_sp_prod_idx); 6509 *bp->dsb_sp_prod, dsb_sp_prod_idx);
6449#ifdef BNX2X_STOP_ON_ERROR 6510#ifdef BNX2X_STOP_ON_ERROR
6450 bnx2x_panic(); 6511 bnx2x_panic();
6512#else
6513 rc = -EBUSY;
6451#endif 6514#endif
6452 break; 6515 break;
6453 } 6516 }
6454 cnt--; 6517 cnt--;
6518 msleep(1);
6455 } 6519 }
6456 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD; 6520 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
6457 bp->fp[0].state = BNX2X_FP_STATE_CLOSED; 6521 bp->fp[0].state = BNX2X_FP_STATE_CLOSED;
6522
6523 return rc;
6458} 6524}
6459 6525
6460static void bnx2x_reset_func(struct bnx2x *bp) 6526static void bnx2x_reset_func(struct bnx2x *bp)
@@ -6496,7 +6562,7 @@ static void bnx2x_reset_port(struct bnx2x *bp)
6496 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 6562 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
6497 if (val) 6563 if (val)
6498 DP(NETIF_MSG_IFDOWN, 6564 DP(NETIF_MSG_IFDOWN,
6499 "BRB1 is not empty %d blooks are occupied\n", val); 6565 "BRB1 is not empty %d blocks are occupied\n", val);
6500 6566
6501 /* TODO: Close Doorbell port? */ 6567 /* TODO: Close Doorbell port? */
6502} 6568}
@@ -6536,11 +6602,12 @@ static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
6536 } 6602 }
6537} 6603}
6538 6604
6539/* msut be called with rtnl_lock */ 6605/* must be called with rtnl_lock */
6540static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode) 6606static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
6541{ 6607{
6608 int port = BP_PORT(bp);
6542 u32 reset_code = 0; 6609 u32 reset_code = 0;
6543 int i, cnt; 6610 int i, cnt, rc;
6544 6611
6545 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; 6612 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
6546 6613
@@ -6557,22 +6624,17 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
6557 (DRV_PULSE_ALWAYS_ALIVE | bp->fw_drv_pulse_wr_seq)); 6624 (DRV_PULSE_ALWAYS_ALIVE | bp->fw_drv_pulse_wr_seq));
6558 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 6625 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
6559 6626
6560 /* Wait until all fast path tasks complete */ 6627 /* Wait until tx fast path tasks complete */
6561 for_each_queue(bp, i) { 6628 for_each_queue(bp, i) {
6562 struct bnx2x_fastpath *fp = &bp->fp[i]; 6629 struct bnx2x_fastpath *fp = &bp->fp[i];
6563 6630
6564#ifdef BNX2X_STOP_ON_ERROR
6565#ifdef __powerpc64__
6566 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
6567#else
6568 DP(NETIF_MSG_IFDOWN, "fp->tpa_queue_used = 0x%llx\n",
6569#endif
6570 fp->tpa_queue_used);
6571#endif
6572 cnt = 1000; 6631 cnt = 1000;
6573 smp_rmb(); 6632 smp_rmb();
6574 while (bnx2x_has_work(fp)) { 6633 while (BNX2X_HAS_TX_WORK(fp)) {
6575 msleep(1); 6634
6635 if (!netif_running(bp->dev))
6636 bnx2x_tx_int(fp, 1000);
6637
6576 if (!cnt) { 6638 if (!cnt) {
6577 BNX2X_ERR("timeout waiting for queue[%d]\n", 6639 BNX2X_ERR("timeout waiting for queue[%d]\n",
6578 i); 6640 i);
@@ -6584,14 +6646,13 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
6584#endif 6646#endif
6585 } 6647 }
6586 cnt--; 6648 cnt--;
6649 msleep(1);
6587 smp_rmb(); 6650 smp_rmb();
6588 } 6651 }
6589 } 6652 }
6590 6653
6591 /* Wait until all slow path tasks complete */ 6654 /* Give HW time to discard old tx messages */
6592 cnt = 1000; 6655 msleep(1);
6593 while ((bp->spq_left != MAX_SPQ_PENDING) && cnt--)
6594 msleep(1);
6595 6656
6596 for_each_queue(bp, i) 6657 for_each_queue(bp, i)
6597 napi_disable(&bnx2x_fp(bp, i, napi)); 6658 napi_disable(&bnx2x_fp(bp, i, napi));
@@ -6601,52 +6662,79 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
6601 /* Release IRQs */ 6662 /* Release IRQs */
6602 bnx2x_free_irq(bp); 6663 bnx2x_free_irq(bp);
6603 6664
6604 if (bp->flags & NO_WOL_FLAG) 6665 if (unload_mode == UNLOAD_NORMAL)
6666 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6667
6668 else if (bp->flags & NO_WOL_FLAG) {
6605 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 6669 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
6670 if (CHIP_IS_E1H(bp))
6671 REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
6606 6672
6607 else if (bp->wol) { 6673 } else if (bp->wol) {
6608 u32 emac_base = BP_PORT(bp) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 6674 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6609 u8 *mac_addr = bp->dev->dev_addr; 6675 u8 *mac_addr = bp->dev->dev_addr;
6610 u32 val; 6676 u32 val;
6611
6612 /* The mac address is written to entries 1-4 to 6677 /* The mac address is written to entries 1-4 to
6613 preserve entry 0 which is used by the PMF */ 6678 preserve entry 0 which is used by the PMF */
6679 u8 entry = (BP_E1HVN(bp) + 1)*8;
6680
6614 val = (mac_addr[0] << 8) | mac_addr[1]; 6681 val = (mac_addr[0] << 8) | mac_addr[1];
6615 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + (BP_E1HVN(bp) + 1)*8, val); 6682 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
6616 6683
6617 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 6684 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
6618 (mac_addr[4] << 8) | mac_addr[5]; 6685 (mac_addr[4] << 8) | mac_addr[5];
6619 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + (BP_E1HVN(bp) + 1)*8 + 4, 6686 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
6620 val);
6621 6687
6622 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 6688 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
6623 6689
6624 } else 6690 } else
6625 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 6691 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6626 6692
6693 if (CHIP_IS_E1(bp)) {
6694 struct mac_configuration_cmd *config =
6695 bnx2x_sp(bp, mcast_config);
6696
6697 bnx2x_set_mac_addr_e1(bp, 0);
6698
6699 for (i = 0; i < config->hdr.length_6b; i++)
6700 CAM_INVALIDATE(config->config_table[i]);
6701
6702 config->hdr.length_6b = i;
6703 if (CHIP_REV_IS_SLOW(bp))
6704 config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
6705 else
6706 config->hdr.offset = BNX2X_MAX_MULTICAST*(1 + port);
6707 config->hdr.client_id = BP_CL_ID(bp);
6708 config->hdr.reserved1 = 0;
6709
6710 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6711 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
6712 U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0);
6713
6714 } else { /* E1H */
6715 bnx2x_set_mac_addr_e1h(bp, 0);
6716
6717 for (i = 0; i < MC_HASH_SIZE; i++)
6718 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
6719 }
6720
6721 if (CHIP_IS_E1H(bp))
6722 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
6723
6627 /* Close multi and leading connections 6724 /* Close multi and leading connections
6628 Completions for ramrods are collected in a synchronous way */ 6725 Completions for ramrods are collected in a synchronous way */
6629 for_each_nondefault_queue(bp, i) 6726 for_each_nondefault_queue(bp, i)
6630 if (bnx2x_stop_multi(bp, i)) 6727 if (bnx2x_stop_multi(bp, i))
6631 goto unload_error; 6728 goto unload_error;
6632 6729
6633 if (CHIP_IS_E1H(bp)) 6730 rc = bnx2x_stop_leading(bp);
6634 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + BP_PORT(bp)*8, 0); 6731 if (rc) {
6635
6636 bnx2x_stop_leading(bp);
6637#ifdef BNX2X_STOP_ON_ERROR
6638 /* If ramrod completion timed out - break here! */
6639 if (bp->panic) {
6640 BNX2X_ERR("Stop leading failed!\n"); 6732 BNX2X_ERR("Stop leading failed!\n");
6733#ifdef BNX2X_STOP_ON_ERROR
6641 return -EBUSY; 6734 return -EBUSY;
6642 } 6735#else
6736 goto unload_error;
6643#endif 6737#endif
6644
6645 if ((bp->state != BNX2X_STATE_CLOSING_WAIT4_UNLOAD) ||
6646 (bp->fp[0].state != BNX2X_FP_STATE_CLOSED)) {
6647 DP(NETIF_MSG_IFDOWN, "failed to close leading properly! "
6648 "state 0x%x fp[0].state 0x%x\n",
6649 bp->state, bp->fp[0].state);
6650 } 6738 }
6651 6739
6652unload_error: 6740unload_error:
@@ -6656,12 +6744,12 @@ unload_error:
6656 DP(NETIF_MSG_IFDOWN, "NO MCP load counts %d, %d, %d\n", 6744 DP(NETIF_MSG_IFDOWN, "NO MCP load counts %d, %d, %d\n",
6657 load_count[0], load_count[1], load_count[2]); 6745 load_count[0], load_count[1], load_count[2]);
6658 load_count[0]--; 6746 load_count[0]--;
6659 load_count[1 + BP_PORT(bp)]--; 6747 load_count[1 + port]--;
6660 DP(NETIF_MSG_IFDOWN, "NO MCP new load counts %d, %d, %d\n", 6748 DP(NETIF_MSG_IFDOWN, "NO MCP new load counts %d, %d, %d\n",
6661 load_count[0], load_count[1], load_count[2]); 6749 load_count[0], load_count[1], load_count[2]);
6662 if (load_count[0] == 0) 6750 if (load_count[0] == 0)
6663 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 6751 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
6664 else if (load_count[1 + BP_PORT(bp)] == 0) 6752 else if (load_count[1 + port] == 0)
6665 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 6753 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
6666 else 6754 else
6667 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 6755 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
@@ -6681,8 +6769,7 @@ unload_error:
6681 /* Free SKBs, SGEs, TPA pool and driver internals */ 6769 /* Free SKBs, SGEs, TPA pool and driver internals */
6682 bnx2x_free_skbs(bp); 6770 bnx2x_free_skbs(bp);
6683 for_each_queue(bp, i) 6771 for_each_queue(bp, i)
6684 bnx2x_free_rx_sge_range(bp, bp->fp + i, 6772 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
6685 RX_SGE_CNT*NUM_RX_SGE_PAGES);
6686 bnx2x_free_mem(bp); 6773 bnx2x_free_mem(bp);
6687 6774
6688 bp->state = BNX2X_STATE_CLOSED; 6775 bp->state = BNX2X_STATE_CLOSED;
@@ -6733,56 +6820,93 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
6733 /* Check if it is the UNDI driver 6820 /* Check if it is the UNDI driver
6734 * UNDI driver initializes CID offset for normal bell to 0x7 6821 * UNDI driver initializes CID offset for normal bell to 0x7
6735 */ 6822 */
6823 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
6736 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 6824 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
6737 if (val == 0x7) { 6825 if (val == 0x7) {
6738 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 6826 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6739 /* save our func and fw_seq */ 6827 /* save our func */
6740 int func = BP_FUNC(bp); 6828 int func = BP_FUNC(bp);
6741 u16 fw_seq = bp->fw_seq; 6829 u32 swap_en;
6830 u32 swap_val;
6742 6831
6743 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 6832 BNX2X_DEV_INFO("UNDI is active! reset device\n");
6744 6833
6745 /* try unload UNDI on port 0 */ 6834 /* try unload UNDI on port 0 */
6746 bp->func = 0; 6835 bp->func = 0;
6747 bp->fw_seq = (SHMEM_RD(bp, 6836 bp->fw_seq =
6748 func_mb[bp->func].drv_mb_header) & 6837 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6749 DRV_MSG_SEQ_NUMBER_MASK); 6838 DRV_MSG_SEQ_NUMBER_MASK);
6750
6751 reset_code = bnx2x_fw_command(bp, reset_code); 6839 reset_code = bnx2x_fw_command(bp, reset_code);
6752 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6753 6840
6754 /* if UNDI is loaded on the other port */ 6841 /* if UNDI is loaded on the other port */
6755 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 6842 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
6756 6843
6844 /* send "DONE" for previous unload */
6845 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6846
6847 /* unload UNDI on port 1 */
6757 bp->func = 1; 6848 bp->func = 1;
6758 bp->fw_seq = (SHMEM_RD(bp, 6849 bp->fw_seq =
6759 func_mb[bp->func].drv_mb_header) & 6850 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6760 DRV_MSG_SEQ_NUMBER_MASK); 6851 DRV_MSG_SEQ_NUMBER_MASK);
6761 6852 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6762 bnx2x_fw_command(bp, 6853
6763 DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS); 6854 bnx2x_fw_command(bp, reset_code);
6764 bnx2x_fw_command(bp,
6765 DRV_MSG_CODE_UNLOAD_DONE);
6766
6767 /* restore our func and fw_seq */
6768 bp->func = func;
6769 bp->fw_seq = fw_seq;
6770 } 6855 }
6771 6856
6857 REG_WR(bp, (BP_PORT(bp) ? HC_REG_CONFIG_1 :
6858 HC_REG_CONFIG_0), 0x1000);
6859
6860 /* close input traffic and wait for it */
6861 /* Do not rcv packets to BRB */
6862 REG_WR(bp,
6863 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
6864 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
6865 /* Do not direct rcv packets that are not for MCP to
6866 * the BRB */
6867 REG_WR(bp,
6868 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
6869 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6870 /* clear AEU */
6871 REG_WR(bp,
6872 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
6873 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
6874 msleep(10);
6875
6876 /* save NIG port swap info */
6877 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6878 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6772 /* reset device */ 6879 /* reset device */
6773 REG_WR(bp, 6880 REG_WR(bp,
6774 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6881 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6775 0xd3ffff7f); 6882 0xd3ffffff);
6776 REG_WR(bp, 6883 REG_WR(bp,
6777 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 6884 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6778 0x1403); 6885 0x1403);
6886 /* take the NIG out of reset and restore swap values */
6887 REG_WR(bp,
6888 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6889 MISC_REGISTERS_RESET_REG_1_RST_NIG);
6890 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
6891 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
6892
6893 /* send unload done to the MCP */
6894 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6895
6896 /* restore our func and fw_seq */
6897 bp->func = func;
6898 bp->fw_seq =
6899 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6900 DRV_MSG_SEQ_NUMBER_MASK);
6779 } 6901 }
6902 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
6780 } 6903 }
6781} 6904}
6782 6905
6783static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 6906static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
6784{ 6907{
6785 u32 val, val2, val3, val4, id; 6908 u32 val, val2, val3, val4, id;
6909 u16 pmc;
6786 6910
6787 /* Get the chip revision id and number. */ 6911 /* Get the chip revision id and number. */
6788 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 6912 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
@@ -6840,8 +6964,16 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
6840 BNX2X_ERR("This driver needs bc_ver %X but found %X," 6964 BNX2X_ERR("This driver needs bc_ver %X but found %X,"
6841 " please upgrade BC\n", BNX2X_BC_VER, val); 6965 " please upgrade BC\n", BNX2X_BC_VER, val);
6842 } 6966 }
6843 BNX2X_DEV_INFO("%sWoL Capable\n", 6967
6844 (bp->flags & NO_WOL_FLAG)? "Not " : ""); 6968 if (BP_E1HVN(bp) == 0) {
6969 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
6970 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
6971 } else {
6972 /* no WOL capability for E1HVN != 0 */
6973 bp->flags |= NO_WOL_FLAG;
6974 }
6975 BNX2X_DEV_INFO("%sWoL capable\n",
6976 (bp->flags & NO_WOL_FLAG) ? "Not " : "");
6845 6977
6846 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 6978 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
6847 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 6979 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
@@ -7274,9 +7406,8 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
7274 bp->mf_config = 7406 bp->mf_config =
7275 SHMEM_RD(bp, mf_cfg.func_mf_config[func].config); 7407 SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
7276 7408
7277 val = 7409 val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) &
7278 (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) & 7410 FUNC_MF_CFG_E1HOV_TAG_MASK);
7279 FUNC_MF_CFG_E1HOV_TAG_MASK);
7280 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 7411 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7281 7412
7282 bp->e1hov = val; 7413 bp->e1hov = val;
@@ -7324,7 +7455,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
7324 7455
7325 if (BP_NOMCP(bp)) { 7456 if (BP_NOMCP(bp)) {
7326 /* only supposed to happen on emulation/FPGA */ 7457 /* only supposed to happen on emulation/FPGA */
7327 BNX2X_ERR("warning rendom MAC workaround active\n"); 7458 BNX2X_ERR("warning random MAC workaround active\n");
7328 random_ether_addr(bp->dev->dev_addr); 7459 random_ether_addr(bp->dev->dev_addr);
7329 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 7460 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
7330 } 7461 }
@@ -7337,8 +7468,8 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
7337 int func = BP_FUNC(bp); 7468 int func = BP_FUNC(bp);
7338 int rc; 7469 int rc;
7339 7470
7340 if (nomcp) 7471 /* Disable interrupt handling until HW is initialized */
7341 bp->flags |= NO_MCP_FLAG; 7472 atomic_set(&bp->intr_sem, 1);
7342 7473
7343 mutex_init(&bp->port.phy_mutex); 7474 mutex_init(&bp->port.phy_mutex);
7344 7475
@@ -7377,8 +7508,6 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
7377 bp->tx_ticks = 50; 7508 bp->tx_ticks = 50;
7378 bp->rx_ticks = 25; 7509 bp->rx_ticks = 25;
7379 7510
7380 bp->stats_ticks = 1000000 & 0xffff00;
7381
7382 bp->timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); 7511 bp->timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
7383 bp->current_interval = (poll ? poll : bp->timer_interval); 7512 bp->current_interval = (poll ? poll : bp->timer_interval);
7384 7513
@@ -7628,25 +7757,25 @@ static void bnx2x_get_drvinfo(struct net_device *dev,
7628 struct ethtool_drvinfo *info) 7757 struct ethtool_drvinfo *info)
7629{ 7758{
7630 struct bnx2x *bp = netdev_priv(dev); 7759 struct bnx2x *bp = netdev_priv(dev);
7631 char phy_fw_ver[PHY_FW_VER_LEN]; 7760 u8 phy_fw_ver[PHY_FW_VER_LEN];
7632 7761
7633 strcpy(info->driver, DRV_MODULE_NAME); 7762 strcpy(info->driver, DRV_MODULE_NAME);
7634 strcpy(info->version, DRV_MODULE_VERSION); 7763 strcpy(info->version, DRV_MODULE_VERSION);
7635 7764
7636 phy_fw_ver[0] = '\0'; 7765 phy_fw_ver[0] = '\0';
7637 if (bp->port.pmf) { 7766 if (bp->port.pmf) {
7638 bnx2x_phy_hw_lock(bp); 7767 bnx2x_acquire_phy_lock(bp);
7639 bnx2x_get_ext_phy_fw_version(&bp->link_params, 7768 bnx2x_get_ext_phy_fw_version(&bp->link_params,
7640 (bp->state != BNX2X_STATE_CLOSED), 7769 (bp->state != BNX2X_STATE_CLOSED),
7641 phy_fw_ver, PHY_FW_VER_LEN); 7770 phy_fw_ver, PHY_FW_VER_LEN);
7642 bnx2x_phy_hw_unlock(bp); 7771 bnx2x_release_phy_lock(bp);
7643 } 7772 }
7644 7773
7645 snprintf(info->fw_version, 32, "%d.%d.%d:%d BC:%x%s%s", 7774 snprintf(info->fw_version, 32, "BC:%d.%d.%d%s%s",
7646 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION, 7775 (bp->common.bc_ver & 0xff0000) >> 16,
7647 BCM_5710_FW_REVISION_VERSION, 7776 (bp->common.bc_ver & 0xff00) >> 8,
7648 BCM_5710_FW_COMPILE_FLAGS, bp->common.bc_ver, 7777 (bp->common.bc_ver & 0xff),
7649 ((phy_fw_ver[0] != '\0')? " PHY:":""), phy_fw_ver); 7778 ((phy_fw_ver[0] != '\0') ? " PHY:" : ""), phy_fw_ver);
7650 strcpy(info->bus_info, pci_name(bp->pdev)); 7779 strcpy(info->bus_info, pci_name(bp->pdev));
7651 info->n_stats = BNX2X_NUM_STATS; 7780 info->n_stats = BNX2X_NUM_STATS;
7652 info->testinfo_len = BNX2X_NUM_TESTS; 7781 info->testinfo_len = BNX2X_NUM_TESTS;
@@ -8097,7 +8226,7 @@ static int bnx2x_set_eeprom(struct net_device *dev,
8097 if (eeprom->magic == 0x00504859) 8226 if (eeprom->magic == 0x00504859)
8098 if (bp->port.pmf) { 8227 if (bp->port.pmf) {
8099 8228
8100 bnx2x_phy_hw_lock(bp); 8229 bnx2x_acquire_phy_lock(bp);
8101 rc = bnx2x_flash_download(bp, BP_PORT(bp), 8230 rc = bnx2x_flash_download(bp, BP_PORT(bp),
8102 bp->link_params.ext_phy_config, 8231 bp->link_params.ext_phy_config,
8103 (bp->state != BNX2X_STATE_CLOSED), 8232 (bp->state != BNX2X_STATE_CLOSED),
@@ -8109,7 +8238,7 @@ static int bnx2x_set_eeprom(struct net_device *dev,
8109 rc |= bnx2x_phy_init(&bp->link_params, 8238 rc |= bnx2x_phy_init(&bp->link_params,
8110 &bp->link_vars); 8239 &bp->link_vars);
8111 } 8240 }
8112 bnx2x_phy_hw_unlock(bp); 8241 bnx2x_release_phy_lock(bp);
8113 8242
8114 } else /* Only the PMF can access the PHY */ 8243 } else /* Only the PMF can access the PHY */
8115 return -EINVAL; 8244 return -EINVAL;
@@ -8128,7 +8257,6 @@ static int bnx2x_get_coalesce(struct net_device *dev,
8128 8257
8129 coal->rx_coalesce_usecs = bp->rx_ticks; 8258 coal->rx_coalesce_usecs = bp->rx_ticks;
8130 coal->tx_coalesce_usecs = bp->tx_ticks; 8259 coal->tx_coalesce_usecs = bp->tx_ticks;
8131 coal->stats_block_coalesce_usecs = bp->stats_ticks;
8132 8260
8133 return 0; 8261 return 0;
8134} 8262}
@@ -8146,44 +8274,12 @@ static int bnx2x_set_coalesce(struct net_device *dev,
8146 if (bp->tx_ticks > 0x3000) 8274 if (bp->tx_ticks > 0x3000)
8147 bp->tx_ticks = 0x3000; 8275 bp->tx_ticks = 0x3000;
8148 8276
8149 bp->stats_ticks = coal->stats_block_coalesce_usecs;
8150 if (bp->stats_ticks > 0xffff00)
8151 bp->stats_ticks = 0xffff00;
8152 bp->stats_ticks &= 0xffff00;
8153
8154 if (netif_running(dev)) 8277 if (netif_running(dev))
8155 bnx2x_update_coalesce(bp); 8278 bnx2x_update_coalesce(bp);
8156 8279
8157 return 0; 8280 return 0;
8158} 8281}
8159 8282
8160static int bnx2x_set_flags(struct net_device *dev, u32 data)
8161{
8162 struct bnx2x *bp = netdev_priv(dev);
8163 int changed = 0;
8164 int rc = 0;
8165
8166 if (data & ETH_FLAG_LRO) {
8167 if (!(dev->features & NETIF_F_LRO)) {
8168 dev->features |= NETIF_F_LRO;
8169 bp->flags |= TPA_ENABLE_FLAG;
8170 changed = 1;
8171 }
8172
8173 } else if (dev->features & NETIF_F_LRO) {
8174 dev->features &= ~NETIF_F_LRO;
8175 bp->flags &= ~TPA_ENABLE_FLAG;
8176 changed = 1;
8177 }
8178
8179 if (changed && netif_running(dev)) {
8180 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8181 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
8182 }
8183
8184 return rc;
8185}
8186
8187static void bnx2x_get_ringparam(struct net_device *dev, 8283static void bnx2x_get_ringparam(struct net_device *dev,
8188 struct ethtool_ringparam *ering) 8284 struct ethtool_ringparam *ering)
8189{ 8285{
@@ -8266,7 +8362,7 @@ static int bnx2x_set_pauseparam(struct net_device *dev,
8266 8362
8267 if (epause->autoneg) { 8363 if (epause->autoneg) {
8268 if (!(bp->port.supported & SUPPORTED_Autoneg)) { 8364 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
8269 DP(NETIF_MSG_LINK, "Autoneg not supported\n"); 8365 DP(NETIF_MSG_LINK, "autoneg not supported\n");
8270 return -EINVAL; 8366 return -EINVAL;
8271 } 8367 }
8272 8368
@@ -8285,6 +8381,34 @@ static int bnx2x_set_pauseparam(struct net_device *dev,
8285 return 0; 8381 return 0;
8286} 8382}
8287 8383
8384static int bnx2x_set_flags(struct net_device *dev, u32 data)
8385{
8386 struct bnx2x *bp = netdev_priv(dev);
8387 int changed = 0;
8388 int rc = 0;
8389
8390 /* TPA requires Rx CSUM offloading */
8391 if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
8392 if (!(dev->features & NETIF_F_LRO)) {
8393 dev->features |= NETIF_F_LRO;
8394 bp->flags |= TPA_ENABLE_FLAG;
8395 changed = 1;
8396 }
8397
8398 } else if (dev->features & NETIF_F_LRO) {
8399 dev->features &= ~NETIF_F_LRO;
8400 bp->flags &= ~TPA_ENABLE_FLAG;
8401 changed = 1;
8402 }
8403
8404 if (changed && netif_running(dev)) {
8405 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8406 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
8407 }
8408
8409 return rc;
8410}
8411
8288static u32 bnx2x_get_rx_csum(struct net_device *dev) 8412static u32 bnx2x_get_rx_csum(struct net_device *dev)
8289{ 8413{
8290 struct bnx2x *bp = netdev_priv(dev); 8414 struct bnx2x *bp = netdev_priv(dev);
@@ -8295,9 +8419,19 @@ static u32 bnx2x_get_rx_csum(struct net_device *dev)
8295static int bnx2x_set_rx_csum(struct net_device *dev, u32 data) 8419static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
8296{ 8420{
8297 struct bnx2x *bp = netdev_priv(dev); 8421 struct bnx2x *bp = netdev_priv(dev);
8422 int rc = 0;
8298 8423
8299 bp->rx_csum = data; 8424 bp->rx_csum = data;
8300 return 0; 8425
8426 /* Disable TPA, when Rx CSUM is disabled. Otherwise all
8427 TPA'ed packets will be discarded due to wrong TCP CSUM */
8428 if (!data) {
8429 u32 flags = ethtool_op_get_flags(dev);
8430
8431 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
8432 }
8433
8434 return rc;
8301} 8435}
8302 8436
8303static int bnx2x_set_tso(struct net_device *dev, u32 data) 8437static int bnx2x_set_tso(struct net_device *dev, u32 data)
@@ -8335,6 +8469,7 @@ static int bnx2x_test_registers(struct bnx2x *bp)
8335{ 8469{
8336 int idx, i, rc = -ENODEV; 8470 int idx, i, rc = -ENODEV;
8337 u32 wr_val = 0; 8471 u32 wr_val = 0;
8472 int port = BP_PORT(bp);
8338 static const struct { 8473 static const struct {
8339 u32 offset0; 8474 u32 offset0;
8340 u32 offset1; 8475 u32 offset1;
@@ -8400,7 +8535,6 @@ static int bnx2x_test_registers(struct bnx2x *bp)
8400 8535
8401 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 8536 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
8402 u32 offset, mask, save_val, val; 8537 u32 offset, mask, save_val, val;
8403 int port = BP_PORT(bp);
8404 8538
8405 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 8539 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
8406 mask = reg_tbl[i].mask; 8540 mask = reg_tbl[i].mask;
@@ -8446,16 +8580,17 @@ static int bnx2x_test_memory(struct bnx2x *bp)
8446 static const struct { 8580 static const struct {
8447 char *name; 8581 char *name;
8448 u32 offset; 8582 u32 offset;
8449 u32 mask; 8583 u32 e1_mask;
8584 u32 e1h_mask;
8450 } prty_tbl[] = { 8585 } prty_tbl[] = {
8451 { "CCM_REG_CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0 }, 8586 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0 },
8452 { "CFC_REG_CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0 }, 8587 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2 },
8453 { "DMAE_REG_DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0 }, 8588 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0 },
8454 { "TCM_REG_TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0 }, 8589 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0 },
8455 { "UCM_REG_UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0 }, 8590 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0 },
8456 { "XCM_REG_XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x1 }, 8591 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0 },
8457 8592
8458 { NULL, 0xffffffff, 0 } 8593 { NULL, 0xffffffff, 0, 0 }
8459 }; 8594 };
8460 8595
8461 if (!netif_running(bp->dev)) 8596 if (!netif_running(bp->dev))
@@ -8469,7 +8604,8 @@ static int bnx2x_test_memory(struct bnx2x *bp)
8469 /* Check the parity status */ 8604 /* Check the parity status */
8470 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 8605 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
8471 val = REG_RD(bp, prty_tbl[i].offset); 8606 val = REG_RD(bp, prty_tbl[i].offset);
8472 if (val & ~(prty_tbl[i].mask)) { 8607 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
8608 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask)))) {
8473 DP(NETIF_MSG_HW, 8609 DP(NETIF_MSG_HW,
8474 "%s is 0x%x\n", prty_tbl[i].name, val); 8610 "%s is 0x%x\n", prty_tbl[i].name, val);
8475 goto test_mem_exit; 8611 goto test_mem_exit;
@@ -8539,15 +8675,15 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
8539 8675
8540 if (loopback_mode == BNX2X_MAC_LOOPBACK) { 8676 if (loopback_mode == BNX2X_MAC_LOOPBACK) {
8541 bp->link_params.loopback_mode = LOOPBACK_BMAC; 8677 bp->link_params.loopback_mode = LOOPBACK_BMAC;
8542 bnx2x_phy_hw_lock(bp); 8678 bnx2x_acquire_phy_lock(bp);
8543 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 8679 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
8544 bnx2x_phy_hw_unlock(bp); 8680 bnx2x_release_phy_lock(bp);
8545 8681
8546 } else if (loopback_mode == BNX2X_PHY_LOOPBACK) { 8682 } else if (loopback_mode == BNX2X_PHY_LOOPBACK) {
8547 bp->link_params.loopback_mode = LOOPBACK_XGXS_10; 8683 bp->link_params.loopback_mode = LOOPBACK_XGXS_10;
8548 bnx2x_phy_hw_lock(bp); 8684 bnx2x_acquire_phy_lock(bp);
8549 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 8685 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
8550 bnx2x_phy_hw_unlock(bp); 8686 bnx2x_release_phy_lock(bp);
8551 /* wait until link state is restored */ 8687 /* wait until link state is restored */
8552 bnx2x_wait_for_link(bp, link_up); 8688 bnx2x_wait_for_link(bp, link_up);
8553 8689
@@ -8771,7 +8907,7 @@ static void bnx2x_self_test(struct net_device *dev,
8771 if (!netif_running(dev)) 8907 if (!netif_running(dev))
8772 return; 8908 return;
8773 8909
8774 /* offline tests are not suppoerted in MF mode */ 8910 /* offline tests are not supported in MF mode */
8775 if (IS_E1HMF(bp)) 8911 if (IS_E1HMF(bp))
8776 etest->flags &= ~ETH_TEST_FL_OFFLINE; 8912 etest->flags &= ~ETH_TEST_FL_OFFLINE;
8777 8913
@@ -8827,76 +8963,99 @@ static const struct {
8827 long offset; 8963 long offset;
8828 int size; 8964 int size;
8829 u32 flags; 8965 u32 flags;
8830 char string[ETH_GSTRING_LEN]; 8966#define STATS_FLAGS_PORT 1
8967#define STATS_FLAGS_FUNC 2
8968 u8 string[ETH_GSTRING_LEN];
8831} bnx2x_stats_arr[BNX2X_NUM_STATS] = { 8969} bnx2x_stats_arr[BNX2X_NUM_STATS] = {
8832/* 1 */ { STATS_OFFSET32(valid_bytes_received_hi), 8, 1, "rx_bytes" }, 8970/* 1 */ { STATS_OFFSET32(valid_bytes_received_hi),
8833 { STATS_OFFSET32(error_bytes_received_hi), 8, 1, "rx_error_bytes" }, 8971 8, STATS_FLAGS_FUNC, "rx_bytes" },
8834 { STATS_OFFSET32(total_bytes_transmitted_hi), 8, 1, "tx_bytes" }, 8972 { STATS_OFFSET32(error_bytes_received_hi),
8835 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 8, 0, "tx_error_bytes" }, 8973 8, STATS_FLAGS_FUNC, "rx_error_bytes" },
8974 { STATS_OFFSET32(total_bytes_transmitted_hi),
8975 8, STATS_FLAGS_FUNC, "tx_bytes" },
8976 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
8977 8, STATS_FLAGS_PORT, "tx_error_bytes" },
8836 { STATS_OFFSET32(total_unicast_packets_received_hi), 8978 { STATS_OFFSET32(total_unicast_packets_received_hi),
8837 8, 1, "rx_ucast_packets" }, 8979 8, STATS_FLAGS_FUNC, "rx_ucast_packets" },
8838 { STATS_OFFSET32(total_multicast_packets_received_hi), 8980 { STATS_OFFSET32(total_multicast_packets_received_hi),
8839 8, 1, "rx_mcast_packets" }, 8981 8, STATS_FLAGS_FUNC, "rx_mcast_packets" },
8840 { STATS_OFFSET32(total_broadcast_packets_received_hi), 8982 { STATS_OFFSET32(total_broadcast_packets_received_hi),
8841 8, 1, "rx_bcast_packets" }, 8983 8, STATS_FLAGS_FUNC, "rx_bcast_packets" },
8842 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 8984 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
8843 8, 1, "tx_packets" }, 8985 8, STATS_FLAGS_FUNC, "tx_packets" },
8844 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 8986 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
8845 8, 0, "tx_mac_errors" }, 8987 8, STATS_FLAGS_PORT, "tx_mac_errors" },
8846/* 10 */{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 8988/* 10 */{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
8847 8, 0, "tx_carrier_errors" }, 8989 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
8848 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 8990 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
8849 8, 0, "rx_crc_errors" }, 8991 8, STATS_FLAGS_PORT, "rx_crc_errors" },
8850 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 8992 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
8851 8, 0, "rx_align_errors" }, 8993 8, STATS_FLAGS_PORT, "rx_align_errors" },
8852 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 8994 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
8853 8, 0, "tx_single_collisions" }, 8995 8, STATS_FLAGS_PORT, "tx_single_collisions" },
8854 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 8996 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
8855 8, 0, "tx_multi_collisions" }, 8997 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
8856 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 8998 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
8857 8, 0, "tx_deferred" }, 8999 8, STATS_FLAGS_PORT, "tx_deferred" },
8858 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 9000 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
8859 8, 0, "tx_excess_collisions" }, 9001 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
8860 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 9002 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
8861 8, 0, "tx_late_collisions" }, 9003 8, STATS_FLAGS_PORT, "tx_late_collisions" },
8862 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 9004 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
8863 8, 0, "tx_total_collisions" }, 9005 8, STATS_FLAGS_PORT, "tx_total_collisions" },
8864 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 9006 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
8865 8, 0, "rx_fragments" }, 9007 8, STATS_FLAGS_PORT, "rx_fragments" },
8866/* 20 */{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 8, 0, "rx_jabbers" }, 9008/* 20 */{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
9009 8, STATS_FLAGS_PORT, "rx_jabbers" },
8867 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 9010 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
8868 8, 0, "rx_undersize_packets" }, 9011 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
8869 { STATS_OFFSET32(jabber_packets_received), 9012 { STATS_OFFSET32(jabber_packets_received),
8870 4, 1, "rx_oversize_packets" }, 9013 4, STATS_FLAGS_FUNC, "rx_oversize_packets" },
8871 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 9014 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
8872 8, 0, "tx_64_byte_packets" }, 9015 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
8873 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 9016 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
8874 8, 0, "tx_65_to_127_byte_packets" }, 9017 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
8875 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 9018 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
8876 8, 0, "tx_128_to_255_byte_packets" }, 9019 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
8877 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 9020 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
8878 8, 0, "tx_256_to_511_byte_packets" }, 9021 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
8879 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 9022 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
8880 8, 0, "tx_512_to_1023_byte_packets" }, 9023 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
8881 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 9024 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
8882 8, 0, "tx_1024_to_1522_byte_packets" }, 9025 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
8883 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 9026 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
8884 8, 0, "tx_1523_to_9022_byte_packets" }, 9027 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
8885/* 30 */{ STATS_OFFSET32(rx_stat_xonpauseframesreceived_hi), 9028/* 30 */{ STATS_OFFSET32(rx_stat_xonpauseframesreceived_hi),
8886 8, 0, "rx_xon_frames" }, 9029 8, STATS_FLAGS_PORT, "rx_xon_frames" },
8887 { STATS_OFFSET32(rx_stat_xoffpauseframesreceived_hi), 9030 { STATS_OFFSET32(rx_stat_xoffpauseframesreceived_hi),
8888 8, 0, "rx_xoff_frames" }, 9031 8, STATS_FLAGS_PORT, "rx_xoff_frames" },
8889 { STATS_OFFSET32(tx_stat_outxonsent_hi), 8, 0, "tx_xon_frames" }, 9032 { STATS_OFFSET32(tx_stat_outxonsent_hi),
8890 { STATS_OFFSET32(tx_stat_outxoffsent_hi), 8, 0, "tx_xoff_frames" }, 9033 8, STATS_FLAGS_PORT, "tx_xon_frames" },
9034 { STATS_OFFSET32(tx_stat_outxoffsent_hi),
9035 8, STATS_FLAGS_PORT, "tx_xoff_frames" },
8891 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 9036 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
8892 8, 0, "rx_mac_ctrl_frames" }, 9037 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
8893 { STATS_OFFSET32(mac_filter_discard), 4, 1, "rx_filtered_packets" }, 9038 { STATS_OFFSET32(mac_filter_discard),
8894 { STATS_OFFSET32(no_buff_discard), 4, 1, "rx_discards" }, 9039 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
8895 { STATS_OFFSET32(xxoverflow_discard), 4, 1, "rx_fw_discards" }, 9040 { STATS_OFFSET32(no_buff_discard),
8896 { STATS_OFFSET32(brb_drop_hi), 8, 1, "brb_discard" }, 9041 4, STATS_FLAGS_FUNC, "rx_discards" },
8897/* 39 */{ STATS_OFFSET32(brb_truncate_discard), 8, 1, "brb_truncate" } 9042 { STATS_OFFSET32(xxoverflow_discard),
9043 4, STATS_FLAGS_PORT, "rx_fw_discards" },
9044 { STATS_OFFSET32(brb_drop_hi),
9045 8, STATS_FLAGS_PORT, "brb_discard" },
9046 { STATS_OFFSET32(brb_truncate_hi),
9047 8, STATS_FLAGS_PORT, "brb_truncate" },
9048/* 40 */{ STATS_OFFSET32(rx_err_discard_pkt),
9049 4, STATS_FLAGS_FUNC, "rx_phy_ip_err_discards"},
9050 { STATS_OFFSET32(rx_skb_alloc_failed),
9051 4, STATS_FLAGS_FUNC, "rx_skb_alloc_discard" },
9052/* 42 */{ STATS_OFFSET32(hw_csum_err),
9053 4, STATS_FLAGS_FUNC, "rx_csum_offload_errors" }
8898}; 9054};
8899 9055
9056#define IS_NOT_E1HMF_STAT(bp, i) \
9057 (IS_E1HMF(bp) && (bnx2x_stats_arr[i].flags & STATS_FLAGS_PORT))
9058
8900static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 9059static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
8901{ 9060{
8902 struct bnx2x *bp = netdev_priv(dev); 9061 struct bnx2x *bp = netdev_priv(dev);
@@ -8905,7 +9064,7 @@ static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
8905 switch (stringset) { 9064 switch (stringset) {
8906 case ETH_SS_STATS: 9065 case ETH_SS_STATS:
8907 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 9066 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
8908 if (IS_E1HMF(bp) && (!bnx2x_stats_arr[i].flags)) 9067 if (IS_NOT_E1HMF_STAT(bp, i))
8909 continue; 9068 continue;
8910 strcpy(buf + j*ETH_GSTRING_LEN, 9069 strcpy(buf + j*ETH_GSTRING_LEN,
8911 bnx2x_stats_arr[i].string); 9070 bnx2x_stats_arr[i].string);
@@ -8925,7 +9084,7 @@ static int bnx2x_get_stats_count(struct net_device *dev)
8925 int i, num_stats = 0; 9084 int i, num_stats = 0;
8926 9085
8927 for (i = 0; i < BNX2X_NUM_STATS; i++) { 9086 for (i = 0; i < BNX2X_NUM_STATS; i++) {
8928 if (IS_E1HMF(bp) && (!bnx2x_stats_arr[i].flags)) 9087 if (IS_NOT_E1HMF_STAT(bp, i))
8929 continue; 9088 continue;
8930 num_stats++; 9089 num_stats++;
8931 } 9090 }
@@ -8940,7 +9099,7 @@ static void bnx2x_get_ethtool_stats(struct net_device *dev,
8940 int i, j; 9099 int i, j;
8941 9100
8942 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 9101 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
8943 if (IS_E1HMF(bp) && (!bnx2x_stats_arr[i].flags)) 9102 if (IS_NOT_E1HMF_STAT(bp, i))
8944 continue; 9103 continue;
8945 9104
8946 if (bnx2x_stats_arr[i].size == 0) { 9105 if (bnx2x_stats_arr[i].size == 0) {
@@ -9057,7 +9216,7 @@ static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
9057 PCI_PM_CTRL_PME_STATUS)); 9216 PCI_PM_CTRL_PME_STATUS));
9058 9217
9059 if (pmcsr & PCI_PM_CTRL_STATE_MASK) 9218 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
9060 /* delay required during transition out of D3hot */ 9219 /* delay required during transition out of D3hot */
9061 msleep(20); 9220 msleep(20);
9062 break; 9221 break;
9063 9222
@@ -9104,17 +9263,16 @@ static int bnx2x_poll(struct napi_struct *napi, int budget)
9104 9263
9105 bnx2x_update_fpsb_idx(fp); 9264 bnx2x_update_fpsb_idx(fp);
9106 9265
9107 if ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || 9266 if (BNX2X_HAS_TX_WORK(fp))
9108 (fp->tx_pkt_prod != fp->tx_pkt_cons))
9109 bnx2x_tx_int(fp, budget); 9267 bnx2x_tx_int(fp, budget);
9110 9268
9111 if (le16_to_cpu(*fp->rx_cons_sb) != fp->rx_comp_cons) 9269 if (BNX2X_HAS_RX_WORK(fp))
9112 work_done = bnx2x_rx_int(fp, budget); 9270 work_done = bnx2x_rx_int(fp, budget);
9113 9271
9114 rmb(); /* bnx2x_has_work() reads the status block */ 9272 rmb(); /* BNX2X_HAS_WORK() reads the status block */
9115 9273
9116 /* must not complete if we consumed full budget */ 9274 /* must not complete if we consumed full budget */
9117 if ((work_done < budget) && !bnx2x_has_work(fp)) { 9275 if ((work_done < budget) && !BNX2X_HAS_WORK(fp)) {
9118 9276
9119#ifdef BNX2X_STOP_ON_ERROR 9277#ifdef BNX2X_STOP_ON_ERROR
9120poll_panic: 9278poll_panic:
@@ -9131,7 +9289,7 @@ poll_panic:
9131 9289
9132 9290
9133/* we split the first BD into headers and data BDs 9291/* we split the first BD into headers and data BDs
9134 * to ease the pain of our fellow micocode engineers 9292 * to ease the pain of our fellow microcode engineers
9135 * we use one mapping for both BDs 9293 * we use one mapping for both BDs
9136 * So far this has only been observed to happen 9294 * So far this has only been observed to happen
9137 * in Other Operating Systems(TM) 9295 * in Other Operating Systems(TM)
@@ -9238,7 +9396,7 @@ static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
9238 /* Check if LSO packet needs to be copied: 9396 /* Check if LSO packet needs to be copied:
9239 3 = 1 (for headers BD) + 2 (for PBD and last BD) */ 9397 3 = 1 (for headers BD) + 2 (for PBD and last BD) */
9240 int wnd_size = MAX_FETCH_BD - 3; 9398 int wnd_size = MAX_FETCH_BD - 3;
9241 /* Number of widnows to check */ 9399 /* Number of windows to check */
9242 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size; 9400 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
9243 int wnd_idx = 0; 9401 int wnd_idx = 0;
9244 int frag_idx = 0; 9402 int frag_idx = 0;
@@ -9340,7 +9498,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
9340 skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr, 9498 skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
9341 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type); 9499 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);
9342 9500
9343 /* First, check if we need to linearaize the skb 9501 /* First, check if we need to linearize the skb
9344 (due to FW restrictions) */ 9502 (due to FW restrictions) */
9345 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) { 9503 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
9346 /* Statistics of linearization */ 9504 /* Statistics of linearization */
@@ -9349,7 +9507,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
9349 DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - " 9507 DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - "
9350 "silently dropping this SKB\n"); 9508 "silently dropping this SKB\n");
9351 dev_kfree_skb_any(skb); 9509 dev_kfree_skb_any(skb);
9352 return 0; 9510 return NETDEV_TX_OK;
9353 } 9511 }
9354 } 9512 }
9355 9513
@@ -9372,7 +9530,8 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
9372 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 9530 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
9373 tx_bd->general_data = (UNICAST_ADDRESS << 9531 tx_bd->general_data = (UNICAST_ADDRESS <<
9374 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT); 9532 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT);
9375 tx_bd->general_data |= 1; /* header nbd */ 9533 /* header nbd */
9534 tx_bd->general_data |= (1 << ETH_TX_BD_HDR_NBDS_SHIFT);
9376 9535
9377 /* remember the first BD of the packet */ 9536 /* remember the first BD of the packet */
9378 tx_buf->first_bd = fp->tx_bd_prod; 9537 tx_buf->first_bd = fp->tx_bd_prod;
@@ -9451,7 +9610,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
9451 9610
9452 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 9611 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9453 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 9612 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9454 nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL)? 1 : 2); 9613 nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL) ? 1 : 2);
9455 tx_bd->nbd = cpu_to_le16(nbd); 9614 tx_bd->nbd = cpu_to_le16(nbd);
9456 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 9615 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
9457 9616
@@ -9721,9 +9880,9 @@ static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
9721 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 9880 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9722 if (netif_running(dev)) { 9881 if (netif_running(dev)) {
9723 if (CHIP_IS_E1(bp)) 9882 if (CHIP_IS_E1(bp))
9724 bnx2x_set_mac_addr_e1(bp); 9883 bnx2x_set_mac_addr_e1(bp, 1);
9725 else 9884 else
9726 bnx2x_set_mac_addr_e1h(bp); 9885 bnx2x_set_mac_addr_e1h(bp, 1);
9727 } 9886 }
9728 9887
9729 return 0; 9888 return 0;
@@ -9734,6 +9893,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9734{ 9893{
9735 struct mii_ioctl_data *data = if_mii(ifr); 9894 struct mii_ioctl_data *data = if_mii(ifr);
9736 struct bnx2x *bp = netdev_priv(dev); 9895 struct bnx2x *bp = netdev_priv(dev);
9896 int port = BP_PORT(bp);
9737 int err; 9897 int err;
9738 9898
9739 switch (cmd) { 9899 switch (cmd) {
@@ -9749,7 +9909,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9749 return -EAGAIN; 9909 return -EAGAIN;
9750 9910
9751 mutex_lock(&bp->port.phy_mutex); 9911 mutex_lock(&bp->port.phy_mutex);
9752 err = bnx2x_cl45_read(bp, BP_PORT(bp), 0, bp->port.phy_addr, 9912 err = bnx2x_cl45_read(bp, port, 0, bp->port.phy_addr,
9753 DEFAULT_PHY_DEV_ADDR, 9913 DEFAULT_PHY_DEV_ADDR,
9754 (data->reg_num & 0x1f), &mii_regval); 9914 (data->reg_num & 0x1f), &mii_regval);
9755 data->val_out = mii_regval; 9915 data->val_out = mii_regval;
@@ -9765,7 +9925,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9765 return -EAGAIN; 9925 return -EAGAIN;
9766 9926
9767 mutex_lock(&bp->port.phy_mutex); 9927 mutex_lock(&bp->port.phy_mutex);
9768 err = bnx2x_cl45_write(bp, BP_PORT(bp), 0, bp->port.phy_addr, 9928 err = bnx2x_cl45_write(bp, port, 0, bp->port.phy_addr,
9769 DEFAULT_PHY_DEV_ADDR, 9929 DEFAULT_PHY_DEV_ADDR,
9770 (data->reg_num & 0x1f), data->val_in); 9930 (data->reg_num & 0x1f), data->val_in);
9771 mutex_unlock(&bp->port.phy_mutex); 9931 mutex_unlock(&bp->port.phy_mutex);
@@ -10141,7 +10301,7 @@ static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
10141 10301
10142 netif_device_detach(dev); 10302 netif_device_detach(dev);
10143 10303
10144 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 10304 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
10145 10305
10146 bnx2x_set_power_state(bp, pci_choose_state(pdev, state)); 10306 bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
10147 10307
@@ -10174,7 +10334,7 @@ static int bnx2x_resume(struct pci_dev *pdev)
10174 bnx2x_set_power_state(bp, PCI_D0); 10334 bnx2x_set_power_state(bp, PCI_D0);
10175 netif_device_attach(dev); 10335 netif_device_attach(dev);
10176 10336
10177 rc = bnx2x_nic_load(bp, LOAD_NORMAL); 10337 rc = bnx2x_nic_load(bp, LOAD_OPEN);
10178 10338
10179 rtnl_unlock(); 10339 rtnl_unlock();
10180 10340
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index 15c9a9946724..a67b0c358ae4 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -6,7 +6,7 @@
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation. 7 * the Free Software Foundation.
8 * 8 *
9 * The registers description starts with the regsister Access type followed 9 * The registers description starts with the register Access type followed
10 * by size in bits. For example [RW 32]. The access types are: 10 * by size in bits. For example [RW 32]. The access types are:
11 * R - Read only 11 * R - Read only
12 * RC - Clear on read 12 * RC - Clear on read
@@ -49,7 +49,7 @@
49/* [RW 10] Write client 0: Assert pause threshold. */ 49/* [RW 10] Write client 0: Assert pause threshold. */
50#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 50#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
51#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c 51#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
52/* [R 24] The number of full blocks occpied by port. */ 52/* [R 24] The number of full blocks occupied by port. */
53#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 53#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
54/* [RW 1] Reset the design by software. */ 54/* [RW 1] Reset the design by software. */
55#define BRB1_REG_SOFT_RESET 0x600dc 55#define BRB1_REG_SOFT_RESET 0x600dc
@@ -740,6 +740,7 @@
740#define HC_REG_ATTN_MSG1_ADDR_L 0x108020 740#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
741#define HC_REG_ATTN_NUM_P0 0x108038 741#define HC_REG_ATTN_NUM_P0 0x108038
742#define HC_REG_ATTN_NUM_P1 0x10803c 742#define HC_REG_ATTN_NUM_P1 0x10803c
743#define HC_REG_COMMAND_REG 0x108180
743#define HC_REG_CONFIG_0 0x108000 744#define HC_REG_CONFIG_0 0x108000
744#define HC_REG_CONFIG_1 0x108004 745#define HC_REG_CONFIG_1 0x108004
745#define HC_REG_FUNC_NUM_P0 0x1080ac 746#define HC_REG_FUNC_NUM_P0 0x1080ac
@@ -1372,6 +1373,23 @@
1372 be asserted). */ 1373 be asserted). */
1373#define MISC_REG_DRIVER_CONTROL_16 0xa5f0 1374#define MISC_REG_DRIVER_CONTROL_16 0xa5f0
1374#define MISC_REG_DRIVER_CONTROL_16_SIZE 2 1375#define MISC_REG_DRIVER_CONTROL_16_SIZE 2
1376/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1377 32 clients. Each client can be controlled by one driver only. One in each
1378 bit represent that this driver control the appropriate client (Ex: bit 5
1379 is set means this driver control client number 5). addr1 = set; addr0 =
1380 clear; read from both addresses will give the same result = status. write
1381 to address 1 will set a request to control all the clients that their
1382 appropriate bit (in the write command) is set. if the client is free (the
1383 appropriate bit in all the other drivers is clear) one will be written to
1384 that driver register; if the client isn't free the bit will remain zero.
1385 if the appropriate bit is set (the driver request to gain control on a
1386 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1387 interrupt will be asserted). write to address 0 will set a request to
1388 free all the clients that their appropriate bit (in the write command) is
1389 set. if the appropriate bit is clear (the driver request to free a client
1390 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1391 be asserted). */
1392#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1375/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 1393/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1376 only. */ 1394 only. */
1377#define MISC_REG_E1HMF_MODE 0xa5f8 1395#define MISC_REG_E1HMF_MODE 0xa5f8
@@ -1394,13 +1412,13 @@
1394#define MISC_REG_GPIO 0xa490 1412#define MISC_REG_GPIO 0xa490
1395/* [R 28] this field hold the last information that caused reserved 1413/* [R 28] this field hold the last information that caused reserved
1396 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1414 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1397 [27:24] the master thatcaused the attention - according to the following 1415 [27:24] the master that caused the attention - according to the following
1398 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1416 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1399 dbu; 8 = dmae */ 1417 dbu; 8 = dmae */
1400#define MISC_REG_GRC_RSV_ATTN 0xa3c0 1418#define MISC_REG_GRC_RSV_ATTN 0xa3c0
1401/* [R 28] this field hold the last information that caused timeout 1419/* [R 28] this field hold the last information that caused timeout
1402 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1420 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1403 [27:24] the master thatcaused the attention - according to the following 1421 [27:24] the master that caused the attention - according to the following
1404 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1422 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1405 dbu; 8 = dmae */ 1423 dbu; 8 = dmae */
1406#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4 1424#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
@@ -1677,6 +1695,7 @@
1677/* [RW 8] init credit counter for port0 in LLH */ 1695/* [RW 8] init credit counter for port0 in LLH */
1678#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 1696#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1679#define NIG_REG_LLH0_XCM_MASK 0x10130 1697#define NIG_REG_LLH0_XCM_MASK 0x10130
1698#define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
1680/* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1699/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1681#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc 1700#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1682/* [RW 2] Determine the classification participants. 0: no classification.1: 1701/* [RW 2] Determine the classification participants. 0: no classification.1:
@@ -1727,6 +1746,9 @@
1727/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 1746/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1728 for port0 */ 1747 for port0 */
1729#define NIG_REG_STAT0_BRB_DISCARD 0x105f0 1748#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1749/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
1750 for port0 */
1751#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
1730/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 1752/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1731 between 1024 and 1522 bytes for port0 */ 1753 between 1024 and 1522 bytes for port0 */
1732#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750 1754#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
@@ -2298,7 +2320,7 @@
2298/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; 2320/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2299 -128k */ 2321 -128k */
2300#define PXP2_REG_RQ_QM_P_SIZE 0x120050 2322#define PXP2_REG_RQ_QM_P_SIZE 0x120050
2301/* [RW 1] 1' indicates that the RBC has finished configurating the PSWRQ */ 2323/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
2302#define PXP2_REG_RQ_RBC_DONE 0x1201b0 2324#define PXP2_REG_RQ_RBC_DONE 0x1201b0
2303/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; 2325/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
2304 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 2326 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
@@ -2406,7 +2428,7 @@
2406/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2428/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2407 buffer reaches this number has_payload will be asserted */ 2429 buffer reaches this number has_payload will be asserted */
2408#define PXP2_REG_WR_DMAE_MPS 0x1205ec 2430#define PXP2_REG_WR_DMAE_MPS 0x1205ec
2409/* [RW 10] if Number of entries in dmae fifo will be higer than this 2431/* [RW 10] if Number of entries in dmae fifo will be higher than this
2410 threshold then has_payload indication will be asserted; the default value 2432 threshold then has_payload indication will be asserted; the default value
2411 should be equal to &gt; write MBS size! */ 2433 should be equal to &gt; write MBS size! */
2412#define PXP2_REG_WR_DMAE_TH 0x120368 2434#define PXP2_REG_WR_DMAE_TH 0x120368
@@ -2427,7 +2449,7 @@
2427/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2449/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2428 buffer reaches this number has_payload will be asserted */ 2450 buffer reaches this number has_payload will be asserted */
2429#define PXP2_REG_WR_TSDM_MPS 0x1205d4 2451#define PXP2_REG_WR_TSDM_MPS 0x1205d4
2430/* [RW 10] if Number of entries in usdmdp fifo will be higer than this 2452/* [RW 10] if Number of entries in usdmdp fifo will be higher than this
2431 threshold then has_payload indication will be asserted; the default value 2453 threshold then has_payload indication will be asserted; the default value
2432 should be equal to &gt; write MBS size! */ 2454 should be equal to &gt; write MBS size! */
2433#define PXP2_REG_WR_USDMDP_TH 0x120348 2455#define PXP2_REG_WR_USDMDP_TH 0x120348
@@ -3294,12 +3316,12 @@
3294#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3316#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3295#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4) 3317#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
3296#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4 3318#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
3297/* [R 1] debug only: This bit indicates wheter indicates that external 3319/* [R 1] debug only: This bit indicates whether indicates that external
3298 buffer was wrapped (oldest data was thrown); Relevant only when 3320 buffer was wrapped (oldest data was thrown); Relevant only when
3299 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */ 3321 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
3300#define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124 3322#define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
3301#define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1 3323#define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
3302/* [R 1] debug only: This bit indicates wheter the internal buffer was 3324/* [R 1] debug only: This bit indicates whether the internal buffer was
3303 wrapped (oldest data was thrown) Relevant only when 3325 wrapped (oldest data was thrown) Relevant only when
3304 ~dbg_registers_debug_target=0 (internal buffer) */ 3326 ~dbg_registers_debug_target=0 (internal buffer) */
3305#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128 3327#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
@@ -4944,6 +4966,7 @@
4944#define EMAC_RX_MODE_PROMISCUOUS (1L<<8) 4966#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
4945#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 4967#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
4946#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 4968#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
4969#define EMAC_TX_MODE_FLOW_EN (1L<<4)
4947#define MISC_REGISTERS_GPIO_0 0 4970#define MISC_REGISTERS_GPIO_0 0
4948#define MISC_REGISTERS_GPIO_1 1 4971#define MISC_REGISTERS_GPIO_1 1
4949#define MISC_REGISTERS_GPIO_2 2 4972#define MISC_REGISTERS_GPIO_2 2
@@ -4959,6 +4982,7 @@
4959#define MISC_REGISTERS_GPIO_PORT_SHIFT 4 4982#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
4960#define MISC_REGISTERS_GPIO_SET_POS 8 4983#define MISC_REGISTERS_GPIO_SET_POS 8
4961#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 4984#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
4985#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
4962#define MISC_REGISTERS_RESET_REG_1_SET 0x584 4986#define MISC_REGISTERS_RESET_REG_1_SET 0x584
4963#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 4987#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
4964#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) 4988#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
@@ -4993,7 +5017,9 @@
4993#define HW_LOCK_MAX_RESOURCE_VALUE 31 5017#define HW_LOCK_MAX_RESOURCE_VALUE 31
4994#define HW_LOCK_RESOURCE_8072_MDIO 0 5018#define HW_LOCK_RESOURCE_8072_MDIO 0
4995#define HW_LOCK_RESOURCE_GPIO 1 5019#define HW_LOCK_RESOURCE_GPIO 1
5020#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
4996#define HW_LOCK_RESOURCE_SPIO 2 5021#define HW_LOCK_RESOURCE_SPIO 2
5022#define HW_LOCK_RESOURCE_UNDI 5
4997#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) 5023#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
4998#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) 5024#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
4999#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) 5025#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
@@ -5144,59 +5170,73 @@
5144#define GRCBASE_MISC_AEU GRCBASE_MISC 5170#define GRCBASE_MISC_AEU GRCBASE_MISC
5145 5171
5146 5172
5147/*the offset of the configuration space in the pci core register*/ 5173/* offset of configuration space in the pci core register */
5148#define PCICFG_OFFSET 0x2000 5174#define PCICFG_OFFSET 0x2000
5149#define PCICFG_VENDOR_ID_OFFSET 0x00 5175#define PCICFG_VENDOR_ID_OFFSET 0x00
5150#define PCICFG_DEVICE_ID_OFFSET 0x02 5176#define PCICFG_DEVICE_ID_OFFSET 0x02
5151#define PCICFG_COMMAND_OFFSET 0x04 5177#define PCICFG_COMMAND_OFFSET 0x04
5178#define PCICFG_COMMAND_IO_SPACE (1<<0)
5179#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5180#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5181#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5182#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5183#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5184#define PCICFG_COMMAND_PERR_ENA (1<<6)
5185#define PCICFG_COMMAND_STEPPING (1<<7)
5186#define PCICFG_COMMAND_SERR_ENA (1<<8)
5187#define PCICFG_COMMAND_FAST_B2B (1<<9)
5188#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5189#define PCICFG_COMMAND_RESERVED (0x1f<<11)
5152#define PCICFG_STATUS_OFFSET 0x06 5190#define PCICFG_STATUS_OFFSET 0x06
5153#define PCICFG_REVESION_ID 0x08 5191#define PCICFG_REVESION_ID 0x08
5154#define PCICFG_CACHE_LINE_SIZE 0x0c 5192#define PCICFG_CACHE_LINE_SIZE 0x0c
5155#define PCICFG_LATENCY_TIMER 0x0d 5193#define PCICFG_LATENCY_TIMER 0x0d
5156#define PCICFG_BAR_1_LOW 0x10 5194#define PCICFG_BAR_1_LOW 0x10
5157#define PCICFG_BAR_1_HIGH 0x14 5195#define PCICFG_BAR_1_HIGH 0x14
5158#define PCICFG_BAR_2_LOW 0x18 5196#define PCICFG_BAR_2_LOW 0x18
5159#define PCICFG_BAR_2_HIGH 0x1c 5197#define PCICFG_BAR_2_HIGH 0x1c
5160#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 5198#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
5161#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 5199#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5162#define PCICFG_INT_LINE 0x3c 5200#define PCICFG_INT_LINE 0x3c
5163#define PCICFG_INT_PIN 0x3d 5201#define PCICFG_INT_PIN 0x3d
5164#define PCICFG_PM_CSR_OFFSET 0x4c 5202#define PCICFG_PM_CAPABILITY 0x48
5165#define PCICFG_GRC_ADDRESS 0x78 5203#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5166#define PCICFG_GRC_DATA 0x80 5204#define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5205#define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5206#define PCICFG_PM_CAPABILITY_DSI (1<<21)
5207#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5208#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5209#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5210#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5211#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5212#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5213#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5214#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5215#define PCICFG_PM_CSR_OFFSET 0x4c
5216#define PCICFG_PM_CSR_STATE (0x3<<0)
5217#define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5218#define PCICFG_PM_CSR_PME_STATUS (1<<15)
5219#define PCICFG_GRC_ADDRESS 0x78
5220#define PCICFG_GRC_DATA 0x80
5167#define PCICFG_DEVICE_CONTROL 0xb4 5221#define PCICFG_DEVICE_CONTROL 0xb4
5168#define PCICFG_LINK_CONTROL 0xbc 5222#define PCICFG_LINK_CONTROL 0xbc
5169 5223
5170#define PCICFG_COMMAND_IO_SPACE (1<<0)
5171#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5172#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5173#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5174#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5175#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5176#define PCICFG_COMMAND_PERR_ENA (1<<6)
5177#define PCICFG_COMMAND_STEPPING (1<<7)
5178#define PCICFG_COMMAND_SERR_ENA (1<<8)
5179#define PCICFG_COMMAND_FAST_B2B (1<<9)
5180#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5181#define PCICFG_COMMAND_RESERVED (0x1f<<11)
5182
5183#define PCICFG_PM_CSR_STATE (0x3<<0)
5184#define PCICFG_PM_CSR_PME_STATUS (1<<15)
5185 5224
5186#define BAR_USTRORM_INTMEM 0x400000 5225#define BAR_USTRORM_INTMEM 0x400000
5187#define BAR_CSTRORM_INTMEM 0x410000 5226#define BAR_CSTRORM_INTMEM 0x410000
5188#define BAR_XSTRORM_INTMEM 0x420000 5227#define BAR_XSTRORM_INTMEM 0x420000
5189#define BAR_TSTRORM_INTMEM 0x430000 5228#define BAR_TSTRORM_INTMEM 0x430000
5190 5229
5230/* for accessing the IGU in case of status block ACK */
5191#define BAR_IGU_INTMEM 0x440000 5231#define BAR_IGU_INTMEM 0x440000
5192 5232
5193#define BAR_DOORBELL_OFFSET 0x800000 5233#define BAR_DOORBELL_OFFSET 0x800000
5194 5234
5195#define BAR_ME_REGISTER 0x450000 5235#define BAR_ME_REGISTER 0x450000
5196 5236
5197 5237/* config_2 offset */
5198#define GRC_CONFIG_2_SIZE_REG 0x408 /* config_2 offset */ 5238#define GRC_CONFIG_2_SIZE_REG 0x408
5199#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 5239#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
5200#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 5240#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
5201#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 5241#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
5202#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 5242#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
@@ -5213,11 +5253,11 @@
5213#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 5253#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
5214#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 5254#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
5215#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 5255#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
5216#define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 5256#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
5217#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 5257#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
5218#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 5258#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
5219#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 5259#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
5220#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 5260#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
5221#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 5261#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
5222#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 5262#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
5223#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 5263#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
@@ -5234,46 +5274,44 @@
5234#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 5274#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
5235#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 5275#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
5236#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 5276#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
5237#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 5277#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
5238#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 5278#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
5239 5279
5240/* config_3 offset */ 5280/* config_3 offset */
5241#define GRC_CONFIG_3_SIZE_REG (0x40c) 5281#define GRC_CONFIG_3_SIZE_REG 0x40c
5242#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 5282#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
5243#define PCI_CONFIG_3_FORCE_PME (1L<<24) 5283#define PCI_CONFIG_3_FORCE_PME (1L<<24)
5244#define PCI_CONFIG_3_PME_STATUS (1L<<25) 5284#define PCI_CONFIG_3_PME_STATUS (1L<<25)
5245#define PCI_CONFIG_3_PME_ENABLE (1L<<26) 5285#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
5246#define PCI_CONFIG_3_PM_STATE (0x3L<<27) 5286#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
5247#define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 5287#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
5248#define PCI_CONFIG_3_PCI_POWER (1L<<31) 5288#define PCI_CONFIG_3_PCI_POWER (1L<<31)
5249
5250/* config_2 offset */
5251#define GRC_CONFIG_2_SIZE_REG 0x408
5252 5289
5253#define GRC_BAR2_CONFIG 0x4e0 5290#define GRC_BAR2_CONFIG 0x4e0
5254#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 5291#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
5255#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 5292#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
5256#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 5293#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
5257#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 5294#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
5258#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 5295#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
5259#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 5296#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
5260#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 5297#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
5261#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 5298#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
5262#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 5299#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
5263#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 5300#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
5264#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 5301#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
5265#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 5302#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
5266#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 5303#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
5267#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 5304#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
5268#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 5305#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
5269#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 5306#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
5270#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 5307#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
5271#define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 5308#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
5309
5310#define PCI_PM_DATA_A 0x410
5311#define PCI_PM_DATA_B 0x414
5312#define PCI_ID_VAL1 0x434
5313#define PCI_ID_VAL2 0x438
5272 5314
5273#define PCI_PM_DATA_A (0x410)
5274#define PCI_PM_DATA_B (0x414)
5275#define PCI_ID_VAL1 (0x434)
5276#define PCI_ID_VAL2 (0x438)
5277 5315
5278#define MDIO_REG_BANK_CL73_IEEEB0 0x0 5316#define MDIO_REG_BANK_CL73_IEEEB0 0x0
5279#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 5317#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
@@ -5522,6 +5560,8 @@ Theotherbitsarereservedandshouldbezero*/
5522#define MDIO_PMA_REG_GEN_CTRL 0xca10 5560#define MDIO_PMA_REG_GEN_CTRL 0xca10
5523#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 5561#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
5524#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a 5562#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
5563#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
5564#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
5525#define MDIO_PMA_REG_ROM_VER1 0xca19 5565#define MDIO_PMA_REG_ROM_VER1 0xca19
5526#define MDIO_PMA_REG_ROM_VER2 0xca1a 5566#define MDIO_PMA_REG_ROM_VER2 0xca1a
5527#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b 5567#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
@@ -5576,7 +5616,8 @@ Theotherbitsarereservedandshouldbezero*/
5576#define MDIO_AN_REG_LINK_STATUS 0x8304 5616#define MDIO_AN_REG_LINK_STATUS 0x8304
5577#define MDIO_AN_REG_CL37_CL73 0x8370 5617#define MDIO_AN_REG_CL37_CL73 0x8370
5578#define MDIO_AN_REG_CL37_AN 0xffe0 5618#define MDIO_AN_REG_CL37_AN 0xffe0
5579#define MDIO_AN_REG_CL37_FD 0xffe4 5619#define MDIO_AN_REG_CL37_FC_LD 0xffe4
5620#define MDIO_AN_REG_CL37_FC_LP 0xffe5
5580 5621
5581 5622
5582#define IGU_FUNC_BASE 0x0400 5623#define IGU_FUNC_BASE 0x0400
@@ -5600,4 +5641,13 @@ Theotherbitsarereservedandshouldbezero*/
5600#define IGU_INT_NOP 2 5641#define IGU_INT_NOP 2
5601#define IGU_INT_NOP2 3 5642#define IGU_INT_NOP2 3
5602 5643
5644#define COMMAND_REG_INT_ACK 0x0
5645#define COMMAND_REG_PROD_UPD 0x4
5646#define COMMAND_REG_ATTN_BITS_UPD 0x8
5647#define COMMAND_REG_ATTN_BITS_SET 0xc
5648#define COMMAND_REG_ATTN_BITS_CLR 0x10
5649#define COMMAND_REG_COALESCE_NOW 0x14
5650#define COMMAND_REG_SIMD_MASK 0x18
5651#define COMMAND_REG_SIMD_NOMASK 0x1c
5652
5603 5653
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 02:49:00 -0400