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authorAlex Deucher <alex@botchco.com>2008-06-18 22:38:29 -0400
committerDave Airlie <airlied@redhat.com>2008-06-18 22:38:29 -0400
commit5cfb6956073a9e42d44a26790b7800980634d037 (patch)
tree10f6deb2880e6e0c72e2ddfe175724d05fc68a48 /drivers
parent7ecabc53a29bb31689fa1852a926e021179a64a6 (diff)
drm/radeon: switch IGP gart to use radeon_write_agp_base()
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/char/drm/radeon_cp.c12
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index d4feccbe46d5..441645ea8b87 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -127,6 +127,9 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
127 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { 127 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
128 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); 128 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
129 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); 129 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
130 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
131 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
132 RADEON_WRITE(RS480_AGP_BASE_2, 0);
130 } else { 133 } else {
131 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 134 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
132 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) 135 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
@@ -741,14 +744,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
741 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | 744 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
742 RS480_REQ_TYPE_SNOOP_DIS)); 745 RS480_REQ_TYPE_SNOOP_DIS));
743 746
744 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { 747 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
745 IGP_WRITE_MCIND(RS690_MC_AGP_BASE,
746 (unsigned int)dev_priv->gart_vm_start);
747 IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
748 } else {
749 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
750 RADEON_WRITE(RS480_AGP_BASE_2, 0);
751 }
752 748
753 dev_priv->gart_size = 32*1024*1024; 749 dev_priv->gart_size = 32*1024*1024;
754 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & 750 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &