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authorAlex Deucher <alexdeucher@gmail.com>2010-03-24 13:55:51 -0400
committerDave Airlie <airlied@redhat.com>2010-04-08 20:16:09 -0400
commit45f9a39bedc3afab3fc85567792efc0103f34a55 (patch)
tree57a16fa09b3c31ee56d9c4803de00a477d7396ff /drivers
parentfe251e2fffa1ebc17c8e6e895b0374ae4e732fa5 (diff)
drm/radeon/kms/evergreen: implement irq support
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c8
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c549
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h148
-rw-r--r--drivers/gpu/drm/radeon/r600.c40
-rw-r--r--drivers/gpu/drm/radeon/radeon.h5
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h4
7 files changed, 719 insertions, 41 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index fd4ef6d18849..6300675dd488 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -249,17 +249,13 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
249 if (ASIC_IS_DCE3(rdev)) 249 if (ASIC_IS_DCE3(rdev))
250 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 250 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
251 atombios_blank_crtc(crtc, ATOM_DISABLE); 251 atombios_blank_crtc(crtc, ATOM_DISABLE);
252 /* XXX re-enable when interrupt support is added */ 252 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
253 if (!ASIC_IS_DCE4(rdev))
254 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
255 radeon_crtc_load_lut(crtc); 253 radeon_crtc_load_lut(crtc);
256 break; 254 break;
257 case DRM_MODE_DPMS_STANDBY: 255 case DRM_MODE_DPMS_STANDBY:
258 case DRM_MODE_DPMS_SUSPEND: 256 case DRM_MODE_DPMS_SUSPEND:
259 case DRM_MODE_DPMS_OFF: 257 case DRM_MODE_DPMS_OFF:
260 /* XXX re-enable when interrupt support is added */ 258 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
261 if (!ASIC_IS_DCE4(rdev))
262 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
263 atombios_blank_crtc(crtc, ATOM_ENABLE); 259 atombios_blank_crtc(crtc, ATOM_ENABLE);
264 if (ASIC_IS_DCE3(rdev)) 260 if (ASIC_IS_DCE3(rdev))
265 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 261 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 57fe569682df..5c34349058c1 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1205,12 +1205,532 @@ int evergreen_asic_reset(struct radeon_device *rdev)
1205 return evergreen_gpu_soft_reset(rdev); 1205 return evergreen_gpu_soft_reset(rdev);
1206} 1206}
1207 1207
1208/* Interrupts */
1209
1210u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
1211{
1212 switch (crtc) {
1213 case 0:
1214 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
1215 case 1:
1216 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
1217 case 2:
1218 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
1219 case 3:
1220 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
1221 case 4:
1222 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
1223 case 5:
1224 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
1225 default:
1226 return 0;
1227 }
1228}
1229
1230void evergreen_disable_interrupt_state(struct radeon_device *rdev)
1231{
1232 u32 tmp;
1233
1234 WREG32(CP_INT_CNTL, 0);
1235 WREG32(GRBM_INT_CNTL, 0);
1236 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1237 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1238 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1239 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1240 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1241 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1242
1243 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1244 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1245 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1246 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1247 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1248 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1249
1250 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
1251 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
1252
1253 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1254 WREG32(DC_HPD1_INT_CONTROL, tmp);
1255 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1256 WREG32(DC_HPD2_INT_CONTROL, tmp);
1257 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1258 WREG32(DC_HPD3_INT_CONTROL, tmp);
1259 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1260 WREG32(DC_HPD4_INT_CONTROL, tmp);
1261 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1262 WREG32(DC_HPD5_INT_CONTROL, tmp);
1263 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1264 WREG32(DC_HPD6_INT_CONTROL, tmp);
1265
1266}
1267
1268int evergreen_irq_set(struct radeon_device *rdev)
1269{
1270 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1271 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
1272 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
1273
1274 if (!rdev->irq.installed) {
1275 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
1276 return -EINVAL;
1277 }
1278 /* don't enable anything if the ih is disabled */
1279 if (!rdev->ih.enabled) {
1280 r600_disable_interrupts(rdev);
1281 /* force the active interrupt state to all disabled */
1282 evergreen_disable_interrupt_state(rdev);
1283 return 0;
1284 }
1285
1286 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
1287 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
1288 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
1289 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
1290 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
1291 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
1292
1293 if (rdev->irq.sw_int) {
1294 DRM_DEBUG("evergreen_irq_set: sw int\n");
1295 cp_int_cntl |= RB_INT_ENABLE;
1296 }
1297 if (rdev->irq.crtc_vblank_int[0]) {
1298 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
1299 crtc1 |= VBLANK_INT_MASK;
1300 }
1301 if (rdev->irq.crtc_vblank_int[1]) {
1302 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
1303 crtc2 |= VBLANK_INT_MASK;
1304 }
1305 if (rdev->irq.crtc_vblank_int[2]) {
1306 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
1307 crtc3 |= VBLANK_INT_MASK;
1308 }
1309 if (rdev->irq.crtc_vblank_int[3]) {
1310 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
1311 crtc4 |= VBLANK_INT_MASK;
1312 }
1313 if (rdev->irq.crtc_vblank_int[4]) {
1314 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
1315 crtc5 |= VBLANK_INT_MASK;
1316 }
1317 if (rdev->irq.crtc_vblank_int[5]) {
1318 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
1319 crtc6 |= VBLANK_INT_MASK;
1320 }
1321 if (rdev->irq.hpd[0]) {
1322 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
1323 hpd1 |= DC_HPDx_INT_EN;
1324 }
1325 if (rdev->irq.hpd[1]) {
1326 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
1327 hpd2 |= DC_HPDx_INT_EN;
1328 }
1329 if (rdev->irq.hpd[2]) {
1330 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
1331 hpd3 |= DC_HPDx_INT_EN;
1332 }
1333 if (rdev->irq.hpd[3]) {
1334 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
1335 hpd4 |= DC_HPDx_INT_EN;
1336 }
1337 if (rdev->irq.hpd[4]) {
1338 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
1339 hpd5 |= DC_HPDx_INT_EN;
1340 }
1341 if (rdev->irq.hpd[5]) {
1342 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
1343 hpd6 |= DC_HPDx_INT_EN;
1344 }
1345
1346 WREG32(CP_INT_CNTL, cp_int_cntl);
1347
1348 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
1349 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
1350 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
1351 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
1352 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
1353 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
1354
1355 WREG32(DC_HPD1_INT_CONTROL, hpd1);
1356 WREG32(DC_HPD2_INT_CONTROL, hpd2);
1357 WREG32(DC_HPD3_INT_CONTROL, hpd3);
1358 WREG32(DC_HPD4_INT_CONTROL, hpd4);
1359 WREG32(DC_HPD5_INT_CONTROL, hpd5);
1360 WREG32(DC_HPD6_INT_CONTROL, hpd6);
1361
1362 return 0;
1363}
1364
1365static inline void evergreen_irq_ack(struct radeon_device *rdev,
1366 u32 *disp_int,
1367 u32 *disp_int_cont,
1368 u32 *disp_int_cont2,
1369 u32 *disp_int_cont3,
1370 u32 *disp_int_cont4,
1371 u32 *disp_int_cont5)
1372{
1373 u32 tmp;
1374
1375 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
1376 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
1377 *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
1378 *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
1379 *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
1380 *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
1381
1382 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
1383 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
1384 if (*disp_int & LB_D1_VLINE_INTERRUPT)
1385 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
1386
1387 if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT)
1388 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
1389 if (*disp_int_cont & LB_D2_VLINE_INTERRUPT)
1390 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
1391
1392 if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
1393 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
1394 if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
1395 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
1396
1397 if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
1398 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
1399 if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
1400 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
1401
1402 if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
1403 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
1404 if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
1405 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
1406
1407 if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
1408 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
1409 if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
1410 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
1411
1412 if (*disp_int & DC_HPD1_INTERRUPT) {
1413 tmp = RREG32(DC_HPD1_INT_CONTROL);
1414 tmp |= DC_HPDx_INT_ACK;
1415 WREG32(DC_HPD1_INT_CONTROL, tmp);
1416 }
1417 if (*disp_int_cont & DC_HPD2_INTERRUPT) {
1418 tmp = RREG32(DC_HPD2_INT_CONTROL);
1419 tmp |= DC_HPDx_INT_ACK;
1420 WREG32(DC_HPD2_INT_CONTROL, tmp);
1421 }
1422 if (*disp_int_cont2 & DC_HPD3_INTERRUPT) {
1423 tmp = RREG32(DC_HPD3_INT_CONTROL);
1424 tmp |= DC_HPDx_INT_ACK;
1425 WREG32(DC_HPD3_INT_CONTROL, tmp);
1426 }
1427 if (*disp_int_cont3 & DC_HPD4_INTERRUPT) {
1428 tmp = RREG32(DC_HPD4_INT_CONTROL);
1429 tmp |= DC_HPDx_INT_ACK;
1430 WREG32(DC_HPD4_INT_CONTROL, tmp);
1431 }
1432 if (*disp_int_cont4 & DC_HPD5_INTERRUPT) {
1433 tmp = RREG32(DC_HPD5_INT_CONTROL);
1434 tmp |= DC_HPDx_INT_ACK;
1435 WREG32(DC_HPD5_INT_CONTROL, tmp);
1436 }
1437 if (*disp_int_cont5 & DC_HPD6_INTERRUPT) {
1438 tmp = RREG32(DC_HPD5_INT_CONTROL);
1439 tmp |= DC_HPDx_INT_ACK;
1440 WREG32(DC_HPD6_INT_CONTROL, tmp);
1441 }
1442}
1443
1444void evergreen_irq_disable(struct radeon_device *rdev)
1445{
1446 u32 disp_int, disp_int_cont, disp_int_cont2;
1447 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
1448
1449 r600_disable_interrupts(rdev);
1450 /* Wait and acknowledge irq */
1451 mdelay(1);
1452 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
1453 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
1454 evergreen_disable_interrupt_state(rdev);
1455}
1456
1457static void evergreen_irq_suspend(struct radeon_device *rdev)
1458{
1459 evergreen_irq_disable(rdev);
1460 r600_rlc_stop(rdev);
1461}
1462
1463static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
1464{
1465 u32 wptr, tmp;
1466
1467 /* XXX use writeback */
1468 wptr = RREG32(IH_RB_WPTR);
1469
1470 if (wptr & RB_OVERFLOW) {
1471 /* When a ring buffer overflow happen start parsing interrupt
1472 * from the last not overwritten vector (wptr + 16). Hopefully
1473 * this should allow us to catchup.
1474 */
1475 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
1476 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
1477 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
1478 tmp = RREG32(IH_RB_CNTL);
1479 tmp |= IH_WPTR_OVERFLOW_CLEAR;
1480 WREG32(IH_RB_CNTL, tmp);
1481 }
1482 return (wptr & rdev->ih.ptr_mask);
1483}
1484
1485int evergreen_irq_process(struct radeon_device *rdev)
1486{
1487 u32 wptr = evergreen_get_ih_wptr(rdev);
1488 u32 rptr = rdev->ih.rptr;
1489 u32 src_id, src_data;
1490 u32 ring_index;
1491 u32 disp_int, disp_int_cont, disp_int_cont2;
1492 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
1493 unsigned long flags;
1494 bool queue_hotplug = false;
1495
1496 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
1497 if (!rdev->ih.enabled)
1498 return IRQ_NONE;
1499
1500 spin_lock_irqsave(&rdev->ih.lock, flags);
1501
1502 if (rptr == wptr) {
1503 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1504 return IRQ_NONE;
1505 }
1506 if (rdev->shutdown) {
1507 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1508 return IRQ_NONE;
1509 }
1510
1511restart_ih:
1512 /* display interrupts */
1513 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
1514 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
1515
1516 rdev->ih.wptr = wptr;
1517 while (rptr != wptr) {
1518 /* wptr/rptr are in bytes! */
1519 ring_index = rptr / 4;
1520 src_id = rdev->ih.ring[ring_index] & 0xff;
1521 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
1522
1523 switch (src_id) {
1524 case 1: /* D1 vblank/vline */
1525 switch (src_data) {
1526 case 0: /* D1 vblank */
1527 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
1528 drm_handle_vblank(rdev->ddev, 0);
1529 wake_up(&rdev->irq.vblank_queue);
1530 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
1531 DRM_DEBUG("IH: D1 vblank\n");
1532 }
1533 break;
1534 case 1: /* D1 vline */
1535 if (disp_int & LB_D1_VLINE_INTERRUPT) {
1536 disp_int &= ~LB_D1_VLINE_INTERRUPT;
1537 DRM_DEBUG("IH: D1 vline\n");
1538 }
1539 break;
1540 default:
1541 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1542 break;
1543 }
1544 break;
1545 case 2: /* D2 vblank/vline */
1546 switch (src_data) {
1547 case 0: /* D2 vblank */
1548 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
1549 drm_handle_vblank(rdev->ddev, 1);
1550 wake_up(&rdev->irq.vblank_queue);
1551 disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
1552 DRM_DEBUG("IH: D2 vblank\n");
1553 }
1554 break;
1555 case 1: /* D2 vline */
1556 if (disp_int_cont & LB_D2_VLINE_INTERRUPT) {
1557 disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
1558 DRM_DEBUG("IH: D2 vline\n");
1559 }
1560 break;
1561 default:
1562 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1563 break;
1564 }
1565 break;
1566 case 3: /* D3 vblank/vline */
1567 switch (src_data) {
1568 case 0: /* D3 vblank */
1569 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
1570 drm_handle_vblank(rdev->ddev, 2);
1571 wake_up(&rdev->irq.vblank_queue);
1572 disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
1573 DRM_DEBUG("IH: D3 vblank\n");
1574 }
1575 break;
1576 case 1: /* D3 vline */
1577 if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
1578 disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
1579 DRM_DEBUG("IH: D3 vline\n");
1580 }
1581 break;
1582 default:
1583 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1584 break;
1585 }
1586 break;
1587 case 4: /* D4 vblank/vline */
1588 switch (src_data) {
1589 case 0: /* D4 vblank */
1590 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
1591 drm_handle_vblank(rdev->ddev, 3);
1592 wake_up(&rdev->irq.vblank_queue);
1593 disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
1594 DRM_DEBUG("IH: D4 vblank\n");
1595 }
1596 break;
1597 case 1: /* D4 vline */
1598 if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
1599 disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
1600 DRM_DEBUG("IH: D4 vline\n");
1601 }
1602 break;
1603 default:
1604 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1605 break;
1606 }
1607 break;
1608 case 5: /* D5 vblank/vline */
1609 switch (src_data) {
1610 case 0: /* D5 vblank */
1611 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
1612 drm_handle_vblank(rdev->ddev, 4);
1613 wake_up(&rdev->irq.vblank_queue);
1614 disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
1615 DRM_DEBUG("IH: D5 vblank\n");
1616 }
1617 break;
1618 case 1: /* D5 vline */
1619 if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
1620 disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
1621 DRM_DEBUG("IH: D5 vline\n");
1622 }
1623 break;
1624 default:
1625 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1626 break;
1627 }
1628 break;
1629 case 6: /* D6 vblank/vline */
1630 switch (src_data) {
1631 case 0: /* D6 vblank */
1632 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
1633 drm_handle_vblank(rdev->ddev, 5);
1634 wake_up(&rdev->irq.vblank_queue);
1635 disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
1636 DRM_DEBUG("IH: D6 vblank\n");
1637 }
1638 break;
1639 case 1: /* D6 vline */
1640 if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
1641 disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
1642 DRM_DEBUG("IH: D6 vline\n");
1643 }
1644 break;
1645 default:
1646 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1647 break;
1648 }
1649 break;
1650 case 42: /* HPD hotplug */
1651 switch (src_data) {
1652 case 0:
1653 if (disp_int & DC_HPD1_INTERRUPT) {
1654 disp_int &= ~DC_HPD1_INTERRUPT;
1655 queue_hotplug = true;
1656 DRM_DEBUG("IH: HPD1\n");
1657 }
1658 break;
1659 case 1:
1660 if (disp_int_cont & DC_HPD2_INTERRUPT) {
1661 disp_int_cont &= ~DC_HPD2_INTERRUPT;
1662 queue_hotplug = true;
1663 DRM_DEBUG("IH: HPD2\n");
1664 }
1665 break;
1666 case 2:
1667 if (disp_int_cont2 & DC_HPD3_INTERRUPT) {
1668 disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
1669 queue_hotplug = true;
1670 DRM_DEBUG("IH: HPD3\n");
1671 }
1672 break;
1673 case 3:
1674 if (disp_int_cont3 & DC_HPD4_INTERRUPT) {
1675 disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
1676 queue_hotplug = true;
1677 DRM_DEBUG("IH: HPD4\n");
1678 }
1679 break;
1680 case 4:
1681 if (disp_int_cont4 & DC_HPD5_INTERRUPT) {
1682 disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
1683 queue_hotplug = true;
1684 DRM_DEBUG("IH: HPD5\n");
1685 }
1686 break;
1687 case 5:
1688 if (disp_int_cont5 & DC_HPD6_INTERRUPT) {
1689 disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
1690 queue_hotplug = true;
1691 DRM_DEBUG("IH: HPD6\n");
1692 }
1693 break;
1694 default:
1695 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1696 break;
1697 }
1698 break;
1699 case 176: /* CP_INT in ring buffer */
1700 case 177: /* CP_INT in IB1 */
1701 case 178: /* CP_INT in IB2 */
1702 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
1703 radeon_fence_process(rdev);
1704 break;
1705 case 181: /* CP EOP event */
1706 DRM_DEBUG("IH: CP EOP\n");
1707 break;
1708 default:
1709 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1710 break;
1711 }
1712
1713 /* wptr/rptr are in bytes! */
1714 rptr += 16;
1715 rptr &= rdev->ih.ptr_mask;
1716 }
1717 /* make sure wptr hasn't changed while processing */
1718 wptr = evergreen_get_ih_wptr(rdev);
1719 if (wptr != rdev->ih.wptr)
1720 goto restart_ih;
1721 if (queue_hotplug)
1722 queue_work(rdev->wq, &rdev->hotplug_work);
1723 rdev->ih.rptr = rptr;
1724 WREG32(IH_RB_RPTR, rdev->ih.rptr);
1725 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1726 return IRQ_HANDLED;
1727}
1728
1208static int evergreen_startup(struct radeon_device *rdev) 1729static int evergreen_startup(struct radeon_device *rdev)
1209{ 1730{
1210 int r; 1731 int r;
1211 1732
1212 /* XXX until interrupts are supported */ 1733 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1213 if (!rdev->me_fw || !rdev->pfp_fw /*|| !rdev->rlc_fw*/) {
1214 r = r600_init_microcode(rdev); 1734 r = r600_init_microcode(rdev);
1215 if (r) { 1735 if (r) {
1216 DRM_ERROR("Failed to load firmware!\n"); 1736 DRM_ERROR("Failed to load firmware!\n");
@@ -1246,6 +1766,7 @@ static int evergreen_startup(struct radeon_device *rdev)
1246 DRM_ERROR("failed to pin blit object %d\n", r); 1766 DRM_ERROR("failed to pin blit object %d\n", r);
1247 return r; 1767 return r;
1248 } 1768 }
1769#endif
1249 1770
1250 /* Enable IRQ */ 1771 /* Enable IRQ */
1251 r = r600_irq_init(rdev); 1772 r = r600_irq_init(rdev);
@@ -1254,8 +1775,7 @@ static int evergreen_startup(struct radeon_device *rdev)
1254 radeon_irq_kms_fini(rdev); 1775 radeon_irq_kms_fini(rdev);
1255 return r; 1776 return r;
1256 } 1777 }
1257 r600_irq_set(rdev); 1778 evergreen_irq_set(rdev);
1258#endif
1259 1779
1260 r = radeon_ring_init(rdev, rdev->cp.ring_size); 1780 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1261 if (r) 1781 if (r)
@@ -1312,8 +1832,8 @@ int evergreen_suspend(struct radeon_device *rdev)
1312 /* FIXME: we should wait for ring to be empty */ 1832 /* FIXME: we should wait for ring to be empty */
1313 r700_cp_stop(rdev); 1833 r700_cp_stop(rdev);
1314 rdev->cp.ready = false; 1834 rdev->cp.ready = false;
1835 evergreen_irq_suspend(rdev);
1315 r600_wb_disable(rdev); 1836 r600_wb_disable(rdev);
1316
1317 evergreen_pcie_gart_disable(rdev); 1837 evergreen_pcie_gart_disable(rdev);
1318#if 0 1838#if 0
1319 /* unpin shaders bo */ 1839 /* unpin shaders bo */
@@ -1415,17 +1935,17 @@ int evergreen_init(struct radeon_device *rdev)
1415 r = radeon_bo_init(rdev); 1935 r = radeon_bo_init(rdev);
1416 if (r) 1936 if (r)
1417 return r; 1937 return r;
1418#if 0 1938
1419 r = radeon_irq_kms_init(rdev); 1939 r = radeon_irq_kms_init(rdev);
1420 if (r) 1940 if (r)
1421 return r; 1941 return r;
1422#endif 1942
1423 rdev->cp.ring_obj = NULL; 1943 rdev->cp.ring_obj = NULL;
1424 r600_ring_init(rdev, 1024 * 1024); 1944 r600_ring_init(rdev, 1024 * 1024);
1425#if 0 1945
1426 rdev->ih.ring_obj = NULL; 1946 rdev->ih.ring_obj = NULL;
1427 r600_ih_ring_init(rdev, 64 * 1024); 1947 r600_ih_ring_init(rdev, 64 * 1024);
1428#endif 1948
1429 r = r600_pcie_gart_init(rdev); 1949 r = r600_pcie_gart_init(rdev);
1430 if (r) 1950 if (r)
1431 return r; 1951 return r;
@@ -1436,10 +1956,8 @@ int evergreen_init(struct radeon_device *rdev)
1436 dev_err(rdev->dev, "disabling GPU acceleration\n"); 1956 dev_err(rdev->dev, "disabling GPU acceleration\n");
1437 r700_cp_fini(rdev); 1957 r700_cp_fini(rdev);
1438 r600_wb_fini(rdev); 1958 r600_wb_fini(rdev);
1439#if 0
1440 r600_irq_fini(rdev); 1959 r600_irq_fini(rdev);
1441 radeon_irq_kms_fini(rdev); 1960 radeon_irq_kms_fini(rdev);
1442#endif
1443 evergreen_pcie_gart_fini(rdev); 1961 evergreen_pcie_gart_fini(rdev);
1444 rdev->accel_working = false; 1962 rdev->accel_working = false;
1445 } 1963 }
@@ -1461,14 +1979,11 @@ int evergreen_init(struct radeon_device *rdev)
1461void evergreen_fini(struct radeon_device *rdev) 1979void evergreen_fini(struct radeon_device *rdev)
1462{ 1980{
1463 radeon_pm_fini(rdev); 1981 radeon_pm_fini(rdev);
1464 evergreen_suspend(rdev); 1982 /*r600_blit_fini(rdev);*/
1465#if 0 1983 r700_cp_fini(rdev);
1466 r600_blit_fini(rdev); 1984 r600_wb_fini(rdev);
1467 r600_irq_fini(rdev); 1985 r600_irq_fini(rdev);
1468 radeon_irq_kms_fini(rdev); 1986 radeon_irq_kms_fini(rdev);
1469 radeon_ring_fini(rdev);
1470 r600_wb_fini(rdev);
1471#endif
1472 evergreen_pcie_gart_fini(rdev); 1987 evergreen_pcie_gart_fini(rdev);
1473 radeon_gem_fini(rdev); 1988 radeon_gem_fini(rdev);
1474 radeon_fence_driver_fini(rdev); 1989 radeon_fence_driver_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 10e9768534da..93e9e17ad54a 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -405,4 +405,152 @@
405#define SOFT_RESET_REGBB (1 << 22) 405#define SOFT_RESET_REGBB (1 << 22)
406#define SOFT_RESET_ORB (1 << 23) 406#define SOFT_RESET_ORB (1 << 23)
407 407
408#define IH_RB_CNTL 0x3e00
409# define IH_RB_ENABLE (1 << 0)
410# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
411# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
412# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
413# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
414# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
415# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
416#define IH_RB_BASE 0x3e04
417#define IH_RB_RPTR 0x3e08
418#define IH_RB_WPTR 0x3e0c
419# define RB_OVERFLOW (1 << 0)
420# define WPTR_OFFSET_MASK 0x3fffc
421#define IH_RB_WPTR_ADDR_HI 0x3e10
422#define IH_RB_WPTR_ADDR_LO 0x3e14
423#define IH_CNTL 0x3e18
424# define ENABLE_INTR (1 << 0)
425# define IH_MC_SWAP(x) ((x) << 2)
426# define IH_MC_SWAP_NONE 0
427# define IH_MC_SWAP_16BIT 1
428# define IH_MC_SWAP_32BIT 2
429# define IH_MC_SWAP_64BIT 3
430# define RPTR_REARM (1 << 4)
431# define MC_WRREQ_CREDIT(x) ((x) << 15)
432# define MC_WR_CLEAN_CNT(x) ((x) << 20)
433
434#define CP_INT_CNTL 0xc124
435# define CNTX_BUSY_INT_ENABLE (1 << 19)
436# define CNTX_EMPTY_INT_ENABLE (1 << 20)
437# define SCRATCH_INT_ENABLE (1 << 25)
438# define TIME_STAMP_INT_ENABLE (1 << 26)
439# define IB2_INT_ENABLE (1 << 29)
440# define IB1_INT_ENABLE (1 << 30)
441# define RB_INT_ENABLE (1 << 31)
442#define CP_INT_STATUS 0xc128
443# define SCRATCH_INT_STAT (1 << 25)
444# define TIME_STAMP_INT_STAT (1 << 26)
445# define IB2_INT_STAT (1 << 29)
446# define IB1_INT_STAT (1 << 30)
447# define RB_INT_STAT (1 << 31)
448
449#define GRBM_INT_CNTL 0x8060
450# define RDERR_INT_ENABLE (1 << 0)
451# define GUI_IDLE_INT_ENABLE (1 << 19)
452
453/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
454#define CRTC_STATUS_FRAME_COUNT 0x6e98
455
456/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
457#define VLINE_STATUS 0x6bb8
458# define VLINE_OCCURRED (1 << 0)
459# define VLINE_ACK (1 << 4)
460# define VLINE_STAT (1 << 12)
461# define VLINE_INTERRUPT (1 << 16)
462# define VLINE_INTERRUPT_TYPE (1 << 17)
463/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
464#define VBLANK_STATUS 0x6bbc
465# define VBLANK_OCCURRED (1 << 0)
466# define VBLANK_ACK (1 << 4)
467# define VBLANK_STAT (1 << 12)
468# define VBLANK_INTERRUPT (1 << 16)
469# define VBLANK_INTERRUPT_TYPE (1 << 17)
470
471/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
472#define INT_MASK 0x6b40
473# define VBLANK_INT_MASK (1 << 0)
474# define VLINE_INT_MASK (1 << 4)
475
476#define DISP_INTERRUPT_STATUS 0x60f4
477# define LB_D1_VLINE_INTERRUPT (1 << 2)
478# define LB_D1_VBLANK_INTERRUPT (1 << 3)
479# define DC_HPD1_INTERRUPT (1 << 17)
480# define DC_HPD1_RX_INTERRUPT (1 << 18)
481# define DACA_AUTODETECT_INTERRUPT (1 << 22)
482# define DACB_AUTODETECT_INTERRUPT (1 << 23)
483# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
484# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
485#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
486# define LB_D2_VLINE_INTERRUPT (1 << 2)
487# define LB_D2_VBLANK_INTERRUPT (1 << 3)
488# define DC_HPD2_INTERRUPT (1 << 17)
489# define DC_HPD2_RX_INTERRUPT (1 << 18)
490# define DISP_TIMER_INTERRUPT (1 << 24)
491#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
492# define LB_D3_VLINE_INTERRUPT (1 << 2)
493# define LB_D3_VBLANK_INTERRUPT (1 << 3)
494# define DC_HPD3_INTERRUPT (1 << 17)
495# define DC_HPD3_RX_INTERRUPT (1 << 18)
496#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
497# define LB_D4_VLINE_INTERRUPT (1 << 2)
498# define LB_D4_VBLANK_INTERRUPT (1 << 3)
499# define DC_HPD4_INTERRUPT (1 << 17)
500# define DC_HPD4_RX_INTERRUPT (1 << 18)
501#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
502# define LB_D5_VLINE_INTERRUPT (1 << 2)
503# define LB_D5_VBLANK_INTERRUPT (1 << 3)
504# define DC_HPD5_INTERRUPT (1 << 17)
505# define DC_HPD5_RX_INTERRUPT (1 << 18)
506#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050
507# define LB_D6_VLINE_INTERRUPT (1 << 2)
508# define LB_D6_VBLANK_INTERRUPT (1 << 3)
509# define DC_HPD6_INTERRUPT (1 << 17)
510# define DC_HPD6_RX_INTERRUPT (1 << 18)
511
512/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
513#define GRPH_INT_STATUS 0x6858
514# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
515# define GRPH_PFLIP_INT_CLEAR (1 << 8)
516/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
517#define GRPH_INT_CONTROL 0x685c
518# define GRPH_PFLIP_INT_MASK (1 << 0)
519# define GRPH_PFLIP_INT_TYPE (1 << 8)
520
521#define DACA_AUTODETECT_INT_CONTROL 0x66c8
522#define DACB_AUTODETECT_INT_CONTROL 0x67c8
523
524#define DC_HPD1_INT_STATUS 0x601c
525#define DC_HPD2_INT_STATUS 0x6028
526#define DC_HPD3_INT_STATUS 0x6034
527#define DC_HPD4_INT_STATUS 0x6040
528#define DC_HPD5_INT_STATUS 0x604c
529#define DC_HPD6_INT_STATUS 0x6058
530# define DC_HPDx_INT_STATUS (1 << 0)
531# define DC_HPDx_SENSE (1 << 1)
532# define DC_HPDx_RX_INT_STATUS (1 << 8)
533
534#define DC_HPD1_INT_CONTROL 0x6020
535#define DC_HPD2_INT_CONTROL 0x602c
536#define DC_HPD3_INT_CONTROL 0x6038
537#define DC_HPD4_INT_CONTROL 0x6044
538#define DC_HPD5_INT_CONTROL 0x6050
539#define DC_HPD6_INT_CONTROL 0x605c
540# define DC_HPDx_INT_ACK (1 << 0)
541# define DC_HPDx_INT_POLARITY (1 << 8)
542# define DC_HPDx_INT_EN (1 << 16)
543# define DC_HPDx_RX_INT_ACK (1 << 20)
544# define DC_HPDx_RX_INT_EN (1 << 24)
545
546#define DC_HPD1_CONTROL 0x6024
547#define DC_HPD2_CONTROL 0x6030
548#define DC_HPD3_CONTROL 0x603c
549#define DC_HPD4_CONTROL 0x6048
550#define DC_HPD5_CONTROL 0x6054
551#define DC_HPD6_CONTROL 0x6060
552# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
553# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
554# define DC_HPDx_EN (1 << 28)
555
408#endif 556#endif
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 4b0225715b93..d178fa826eec 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -45,6 +45,7 @@
45#define R700_RLC_UCODE_SIZE 1024 45#define R700_RLC_UCODE_SIZE 1024
46#define EVERGREEN_PFP_UCODE_SIZE 1120 46#define EVERGREEN_PFP_UCODE_SIZE 1120
47#define EVERGREEN_PM4_UCODE_SIZE 1376 47#define EVERGREEN_PM4_UCODE_SIZE 1376
48#define EVERGREEN_RLC_UCODE_SIZE 768
48 49
49/* Firmware Names */ 50/* Firmware Names */
50MODULE_FIRMWARE("radeon/R600_pfp.bin"); 51MODULE_FIRMWARE("radeon/R600_pfp.bin");
@@ -71,12 +72,16 @@ MODULE_FIRMWARE("radeon/R600_rlc.bin");
71MODULE_FIRMWARE("radeon/R700_rlc.bin"); 72MODULE_FIRMWARE("radeon/R700_rlc.bin");
72MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 73MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
73MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 74MODULE_FIRMWARE("radeon/CEDAR_me.bin");
75MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
74MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 76MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
75MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 77MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
78MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
76MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 79MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
77MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 80MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
81MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
78MODULE_FIRMWARE("radeon/CYRPESS_pfp.bin"); 82MODULE_FIRMWARE("radeon/CYRPESS_pfp.bin");
79MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 83MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
84MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
80 85
81int r600_debugfs_mc_info_init(struct radeon_device *rdev); 86int r600_debugfs_mc_info_init(struct radeon_device *rdev);
82 87
@@ -84,6 +89,7 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev);
84int r600_mc_wait_for_idle(struct radeon_device *rdev); 89int r600_mc_wait_for_idle(struct radeon_device *rdev);
85void r600_gpu_init(struct radeon_device *rdev); 90void r600_gpu_init(struct radeon_device *rdev);
86void r600_fini(struct radeon_device *rdev); 91void r600_fini(struct radeon_device *rdev);
92void r600_irq_disable(struct radeon_device *rdev);
87 93
88/* hpd for digital panel detect/disconnect */ 94/* hpd for digital panel detect/disconnect */
89bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 95bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
@@ -1461,20 +1467,20 @@ int r600_init_microcode(struct radeon_device *rdev)
1461 break; 1467 break;
1462 case CHIP_CEDAR: 1468 case CHIP_CEDAR:
1463 chip_name = "CEDAR"; 1469 chip_name = "CEDAR";
1464 rlc_chip_name = ""; 1470 rlc_chip_name = "CEDAR";
1465 break; 1471 break;
1466 case CHIP_REDWOOD: 1472 case CHIP_REDWOOD:
1467 chip_name = "REDWOOD"; 1473 chip_name = "REDWOOD";
1468 rlc_chip_name = ""; 1474 rlc_chip_name = "REDWOOD";
1469 break; 1475 break;
1470 case CHIP_JUNIPER: 1476 case CHIP_JUNIPER:
1471 chip_name = "JUNIPER"; 1477 chip_name = "JUNIPER";
1472 rlc_chip_name = ""; 1478 rlc_chip_name = "JUNIPER";
1473 break; 1479 break;
1474 case CHIP_CYPRESS: 1480 case CHIP_CYPRESS:
1475 case CHIP_HEMLOCK: 1481 case CHIP_HEMLOCK:
1476 chip_name = "CYPRESS"; 1482 chip_name = "CYPRESS";
1477 rlc_chip_name = ""; 1483 rlc_chip_name = "CYPRESS";
1478 break; 1484 break;
1479 default: BUG(); 1485 default: BUG();
1480 } 1486 }
@@ -1482,7 +1488,7 @@ int r600_init_microcode(struct radeon_device *rdev)
1482 if (rdev->family >= CHIP_CEDAR) { 1488 if (rdev->family >= CHIP_CEDAR) {
1483 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 1489 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1484 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 1490 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
1485 rlc_req_size = 0; 1491 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
1486 } else if (rdev->family >= CHIP_RV770) { 1492 } else if (rdev->family >= CHIP_RV770) {
1487 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 1493 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1488 me_req_size = R700_PM4_UCODE_SIZE * 4; 1494 me_req_size = R700_PM4_UCODE_SIZE * 4;
@@ -1518,8 +1524,6 @@ int r600_init_microcode(struct radeon_device *rdev)
1518 err = -EINVAL; 1524 err = -EINVAL;
1519 } 1525 }
1520 1526
1521 /* XXX until evergreen interrupts are supported */
1522 if (rdev->family < CHIP_CEDAR) {
1523 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 1527 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1524 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); 1528 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1525 if (err) 1529 if (err)
@@ -1530,7 +1534,6 @@ int r600_init_microcode(struct radeon_device *rdev)
1530 rdev->rlc_fw->size, fw_name); 1534 rdev->rlc_fw->size, fw_name);
1531 err = -EINVAL; 1535 err = -EINVAL;
1532 } 1536 }
1533 }
1534 1537
1535out: 1538out:
1536 platform_device_unregister(pdev); 1539 platform_device_unregister(pdev);
@@ -2309,10 +2312,11 @@ static void r600_ih_ring_fini(struct radeon_device *rdev)
2309 } 2312 }
2310} 2313}
2311 2314
2312static void r600_rlc_stop(struct radeon_device *rdev) 2315void r600_rlc_stop(struct radeon_device *rdev)
2313{ 2316{
2314 2317
2315 if (rdev->family >= CHIP_RV770) { 2318 if ((rdev->family >= CHIP_RV770) &&
2319 (rdev->family <= CHIP_RV740)) {
2316 /* r7xx asics need to soft reset RLC before halting */ 2320 /* r7xx asics need to soft reset RLC before halting */
2317 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 2321 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2318 RREG32(SRBM_SOFT_RESET); 2322 RREG32(SRBM_SOFT_RESET);
@@ -2349,7 +2353,12 @@ static int r600_rlc_init(struct radeon_device *rdev)
2349 WREG32(RLC_UCODE_CNTL, 0); 2353 WREG32(RLC_UCODE_CNTL, 0);
2350 2354
2351 fw_data = (const __be32 *)rdev->rlc_fw->data; 2355 fw_data = (const __be32 *)rdev->rlc_fw->data;
2352 if (rdev->family >= CHIP_RV770) { 2356 if (rdev->family >= CHIP_CEDAR) {
2357 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2358 WREG32(RLC_UCODE_ADDR, i);
2359 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2360 }
2361 } else if (rdev->family >= CHIP_RV770) {
2353 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 2362 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2354 WREG32(RLC_UCODE_ADDR, i); 2363 WREG32(RLC_UCODE_ADDR, i);
2355 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 2364 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
@@ -2379,7 +2388,7 @@ static void r600_enable_interrupts(struct radeon_device *rdev)
2379 rdev->ih.enabled = true; 2388 rdev->ih.enabled = true;
2380} 2389}
2381 2390
2382static void r600_disable_interrupts(struct radeon_device *rdev) 2391void r600_disable_interrupts(struct radeon_device *rdev)
2383{ 2392{
2384 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 2393 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2385 u32 ih_cntl = RREG32(IH_CNTL); 2394 u32 ih_cntl = RREG32(IH_CNTL);
@@ -2494,7 +2503,10 @@ int r600_irq_init(struct radeon_device *rdev)
2494 WREG32(IH_CNTL, ih_cntl); 2503 WREG32(IH_CNTL, ih_cntl);
2495 2504
2496 /* force the active interrupt state to all disabled */ 2505 /* force the active interrupt state to all disabled */
2497 r600_disable_interrupt_state(rdev); 2506 if (rdev->family >= CHIP_CEDAR)
2507 evergreen_disable_interrupt_state(rdev);
2508 else
2509 r600_disable_interrupt_state(rdev);
2498 2510
2499 /* enable irqs */ 2511 /* enable irqs */
2500 r600_enable_interrupts(rdev); 2512 r600_enable_interrupts(rdev);
@@ -2504,7 +2516,7 @@ int r600_irq_init(struct radeon_device *rdev)
2504 2516
2505void r600_irq_suspend(struct radeon_device *rdev) 2517void r600_irq_suspend(struct radeon_device *rdev)
2506{ 2518{
2507 r600_disable_interrupts(rdev); 2519 r600_irq_disable(rdev);
2508 r600_rlc_stop(rdev); 2520 r600_rlc_stop(rdev);
2509} 2521}
2510 2522
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index acf21d7e3cb2..e0132ef093b4 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -372,7 +372,7 @@ struct radeon_irq {
372 bool installed; 372 bool installed;
373 bool sw_int; 373 bool sw_int;
374 /* FIXME: use a define max crtc rather than hardcode it */ 374 /* FIXME: use a define max crtc rather than hardcode it */
375 bool crtc_vblank_int[2]; 375 bool crtc_vblank_int[6];
376 wait_queue_head_t vblank_queue; 376 wait_queue_head_t vblank_queue;
377 /* FIXME: use defines for max hpd/dacs */ 377 /* FIXME: use defines for max hpd/dacs */
378 bool hpd[6]; 378 bool hpd[6];
@@ -1324,6 +1324,8 @@ extern void r600_irq_fini(struct radeon_device *rdev);
1324extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 1324extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1325extern int r600_irq_set(struct radeon_device *rdev); 1325extern int r600_irq_set(struct radeon_device *rdev);
1326extern void r600_irq_suspend(struct radeon_device *rdev); 1326extern void r600_irq_suspend(struct radeon_device *rdev);
1327extern void r600_disable_interrupts(struct radeon_device *rdev);
1328extern void r600_rlc_stop(struct radeon_device *rdev);
1327/* r600 audio */ 1329/* r600 audio */
1328extern int r600_audio_init(struct radeon_device *rdev); 1330extern int r600_audio_init(struct radeon_device *rdev);
1329extern int r600_audio_tmds_index(struct drm_encoder *encoder); 1331extern int r600_audio_tmds_index(struct drm_encoder *encoder);
@@ -1343,6 +1345,7 @@ extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1343 1345
1344extern void r700_cp_stop(struct radeon_device *rdev); 1346extern void r700_cp_stop(struct radeon_device *rdev);
1345extern void r700_cp_fini(struct radeon_device *rdev); 1347extern void r700_cp_fini(struct radeon_device *rdev);
1348void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1346 1349
1347/* evergreen */ 1350/* evergreen */
1348struct evergreen_mc_save { 1351struct evergreen_mc_save {
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 3a576ab805cf..f835333c1b69 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -643,9 +643,9 @@ static struct radeon_asic evergreen_asic = {
643 .gart_set_page = &rs600_gart_set_page, 643 .gart_set_page = &rs600_gart_set_page,
644 .ring_test = &r600_ring_test, 644 .ring_test = &r600_ring_test,
645 .ring_ib_execute = &r600_ring_ib_execute, 645 .ring_ib_execute = &r600_ring_ib_execute,
646 .irq_set = NULL, 646 .irq_set = &evergreen_irq_set,
647 .irq_process = NULL, 647 .irq_process = &evergreen_irq_process,
648 .get_vblank_counter = NULL, 648 .get_vblank_counter = &evergreen_get_vblank_counter,
649 .fence_ring_emit = NULL, 649 .fence_ring_emit = NULL,
650 .cs_parse = NULL, 650 .cs_parse = NULL,
651 .copy_blit = NULL, 651 .copy_blit = NULL,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 1d451ff03676..ef2c7ba1bdc9 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -294,4 +294,8 @@ void evergreen_hpd_fini(struct radeon_device *rdev);
294bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 294bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
295void evergreen_hpd_set_polarity(struct radeon_device *rdev, 295void evergreen_hpd_set_polarity(struct radeon_device *rdev,
296 enum radeon_hpd_id hpd); 296 enum radeon_hpd_id hpd);
297u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
298int evergreen_irq_set(struct radeon_device *rdev);
299int evergreen_irq_process(struct radeon_device *rdev);
300
297#endif 301#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-11 13:02:51 -0400