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authorBorislav Petkov <borislav.petkov@amd.com>2009-12-15 10:03:53 -0500
committerBorislav Petkov <borislav.petkov@amd.com>2009-12-16 11:48:39 -0500
commit256f7276af20c88b492353710d5d6640b09c3d63 (patch)
tree9d2a4a26da9d79b3d19dafa9cf44149a1cee7a28 /drivers
parent35d8069234bacfab608d2d7571c2cb71a23c3fae (diff)
edac, mce, amd: silence GART TLB errors
Although reporting of benign GART TLB errors is disabled in __mcheck_cpu_apply_quirks, those are still being logged, and, as a result, trip up amd64_edac. Pull up reporting check so that machines with loaded edac module bail out early and don't spit fragments into dmesg. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/edac/edac_mce_amd.c21
1 files changed, 6 insertions, 15 deletions
diff --git a/drivers/edac/edac_mce_amd.c b/drivers/edac/edac_mce_amd.c
index 9965b8daca74..8fc91a019620 100644
--- a/drivers/edac/edac_mce_amd.c
+++ b/drivers/edac/edac_mce_amd.c
@@ -299,6 +299,12 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
299 if (!handle_errors) 299 if (!handle_errors)
300 return; 300 return;
301 301
302 /*
303 * GART TLB error reporting is disabled by default. Bail out early.
304 */
305 if (TLB_ERROR(ec) && !report_gart_errors)
306 return;
307
302 pr_emerg(" Northbridge Error, node %d", node_id); 308 pr_emerg(" Northbridge Error, node %d", node_id);
303 309
304 /* 310 /*
@@ -332,21 +338,6 @@ static void amd_decode_fr_mce(u64 mc5_status)
332static inline void amd_decode_err_code(unsigned int ec) 338static inline void amd_decode_err_code(unsigned int ec)
333{ 339{
334 if (TLB_ERROR(ec)) { 340 if (TLB_ERROR(ec)) {
335 /*
336 * GART errors are intended to help graphics driver developers
337 * to detect bad GART PTEs. It is recommended by AMD to disable
338 * GART table walk error reporting by default[1] (currently
339 * being disabled in mce_cpu_quirks()) and according to the
340 * comment in mce_cpu_quirks(), such GART errors can be
341 * incorrectly triggered. We may see these errors anyway and
342 * unless requested by the user, they won't be reported.
343 *
344 * [1] section 13.10.1 on BIOS and Kernel Developers Guide for
345 * AMD NPT family 0Fh processors
346 */
347 if (!report_gart_errors)
348 return;
349
350 pr_emerg(" Transaction: %s, Cache Level %s\n", 341 pr_emerg(" Transaction: %s, Cache Level %s\n",
351 TT_MSG(ec), LL_MSG(ec)); 342 TT_MSG(ec), LL_MSG(ec));
352 } else if (MEM_ERROR(ec)) { 343 } else if (MEM_ERROR(ec)) {