drm/i915: enable parity error interrupts

The previous patch put all the code, and handlers in place. It should
now be safe to enable the parity error interrupt. The parity error must
be unmasked in both the GTIMR, and the CS IMR. Unfortunately, the docs
aren't clear about this; nevertheless it's the truth.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 14 insertions, 4 deletions

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c5266355973b..4a457521d76e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1889,13 +1889,13 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
                    DE_PIPEA_VBLANK_IVB);
         POSTING_READ(DEIER);
 
-        dev_priv->gt_irq_mask = ~0;
+        dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 
         I915_WRITE(GTIIR, I915_READ(GTIIR));
         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 
         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
-                GEN6_BLITTER_USER_INTERRUPT;
+                GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
         I915_WRITE(GTIER, render_irqs);
         POSTING_READ(GTIER);
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1df1694835a1..89a5e7f89d7a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -427,6 +427,9 @@ static int init_render_ring(struct intel_ring_buffer *ring)
         if (INTEL_INFO(dev)->gen >= 6)
                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
+        if (IS_IVYBRIDGE(dev))
+                I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
+
         return ret;
 }
 
@@ -814,7 +817,11 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
         if (ring->irq_refcount++ == 0) {
-                I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
+                if (IS_IVYBRIDGE(dev) && ring->id == RCS)
+                        I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
+                                                GEN6_RENDER_L3_PARITY_ERROR));
+                else
+                        I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
                 POSTING_READ(GTIMR);
@@ -833,7 +840,10 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
         if (--ring->irq_refcount == 0) {
-                I915_WRITE_IMR(ring, ~0);
+                if (IS_IVYBRIDGE(dev) && ring->id == RCS)
+                        I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
+                else
+                        I915_WRITE_IMR(ring, ~0);
                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
                 POSTING_READ(GTIMR);