Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (106 commits)
  powerpc/p3060qds: Add support for P3060QDS board
  powerpc/83xx: Add shutdown request support to MCU handling on MPC8349 MITX
  powerpc/85xx: Make kexec to interate over online cpus
  powerpc/fsl_booke: Fix comment in head_fsl_booke.S
  powerpc/85xx: issue 15 EOI after core reset for FSL CoreNet devices
  powerpc/8xxx: Fix interrupt handling in MPC8xxx GPIO driver
  powerpc/85xx: Add 'fsl,pq3-gpio' compatiable for GPIO driver
  powerpc/86xx: Correct Gianfar support for GE boards
  powerpc/cpm: Clear muram before it is in use.
  drivers/virt: add ioctl for 32-bit compat on 64-bit to fsl-hv-manager
  powerpc/fsl_msi: add support for "msi-address-64" property
  powerpc/85xx: Setup secondary cores PIR with hard SMP id
  powerpc/fsl-booke: Fix settlbcam for 64-bit
  powerpc/85xx: Adding DCSR node to dtsi device trees
  powerpc/85xx: clean up FPGA device tree nodes for Freecsale QorIQ boards
  powerpc/85xx: fix PHYS_64BIT selection for P1022DS
  powerpc/fsl-booke: Fix setup_initial_memory_limit to not blindly map
  powerpc: respect mem= setting for early memory limit setup
  powerpc: Update corenet64_smp_defconfig
  powerpc: Update mpc85xx/corenet 32-bit defconfigs
  ...

Fix up trivial conflicts in:
 - arch/powerpc/configs/40x/hcu4_defconfig
	removed stale file, edited elsewhere
 - arch/powerpc/include/asm/udbg.h, arch/powerpc/kernel/udbg.c:
	added opal and gelic drivers vs added ePAPR driver
 - drivers/tty/serial/8250.c
	moved UPIO_TSI to powerpc vs removed UPIO_DWAPB support

15 files changed, 927 insertions, 33 deletions

diff --git a/drivers/edac/cpc925_edac.c b/drivers/edac/cpc925_edac.c
index a687a0d16962..a774c0ddaf5b 100644
--- a/drivers/edac/cpc925_edac.c
+++ b/drivers/edac/cpc925_edac.c
@@ -90,6 +90,7 @@ enum apimask_bits {
         ECC_MASK_ENABLE = (APIMASK_ECC_UE_H | APIMASK_ECC_CE_H |
                            APIMASK_ECC_UE_L | APIMASK_ECC_CE_L),
 };
+#define APIMASK_ADI(n)          CPC925_BIT(((n)+1))
 
 /************************************************************
  *      Processor Interface Exception Register (APIEXCP)
@@ -581,16 +582,73 @@ static void cpc925_mc_check(struct mem_ctl_info *mci)
 }
 
 /******************** CPU err device********************************/
+static u32 cpc925_cpu_mask_disabled(void)
+{
+        struct device_node *cpus;
+        struct device_node *cpunode = NULL;
+        static u32 mask = 0;
+
+        /* use cached value if available */
+        if (mask != 0)
+                return mask;
+
+        mask = APIMASK_ADI0 | APIMASK_ADI1;
+
+        cpus = of_find_node_by_path("/cpus");
+        if (cpus == NULL) {
+                cpc925_printk(KERN_DEBUG, "No /cpus node !\n");
+                return 0;
+        }
+
+        while ((cpunode = of_get_next_child(cpus, cpunode)) != NULL) {
+                const u32 *reg = of_get_property(cpunode, "reg", NULL);
+
+                if (strcmp(cpunode->type, "cpu")) {
+                        cpc925_printk(KERN_ERR, "Not a cpu node in /cpus: %s\n", cpunode->name);
+                        continue;
+                }
+
+                if (reg == NULL || *reg > 2) {
+                        cpc925_printk(KERN_ERR, "Bad reg value at %s\n", cpunode->full_name);
+                        continue;
+                }
+
+                mask &= ~APIMASK_ADI(*reg);
+        }
+
+        if (mask != (APIMASK_ADI0 | APIMASK_ADI1)) {
+                /* We assume that each CPU sits on it's own PI and that
+                 * for present CPUs the reg property equals to the PI
+                 * interface id */
+                cpc925_printk(KERN_WARNING,
+                                "Assuming PI id is equal to CPU MPIC id!\n");
+        }
+
+        of_node_put(cpunode);
+        of_node_put(cpus);
+
+        return mask;
+}
+
 /* Enable CPU Errors detection */
 static void cpc925_cpu_init(struct cpc925_dev_info *dev_info)
 {
         u32 apimask;
+        u32 cpumask;
 
         apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
-        if ((apimask & CPU_MASK_ENABLE) == 0) {
-                apimask |= CPU_MASK_ENABLE;
-                __raw_writel(apimask, dev_info->vbase + REG_APIMASK_OFFSET);
+
+        cpumask = cpc925_cpu_mask_disabled();
+        if (apimask & cpumask) {
+                cpc925_printk(KERN_WARNING, "CPU(s) not present, "
+                                "but enabled in APIMASK, disabling\n");
+                apimask &= ~cpumask;
         }
+
+        if ((apimask & CPU_MASK_ENABLE) == 0)
+                apimask |= CPU_MASK_ENABLE;
+
+        __raw_writel(apimask, dev_info->vbase + REG_APIMASK_OFFSET);
 }
 
 /* Disable CPU Errors detection */
@@ -622,6 +680,9 @@ static void cpc925_cpu_check(struct edac_device_ctl_info *edac_dev)
         if ((apiexcp & CPU_EXCP_DETECTED) == 0)
                 return;
 
+        if ((apiexcp & ~cpc925_cpu_mask_disabled()) == 0)
+                return;
+
         apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
         cpc925_printk(KERN_INFO, "Processor Interface Fault\n"
                                  "Processor Interface register dump:\n");
diff --git a/drivers/edac/ppc4xx_edac.c b/drivers/edac/ppc4xx_edac.c
index 0de7d8770891..38400963e245 100644
--- a/drivers/edac/ppc4xx_edac.c
+++ b/drivers/edac/ppc4xx_edac.c
@@ -205,7 +205,7 @@ static struct platform_driver ppc4xx_edac_driver = {
         .remove                 = ppc4xx_edac_remove,
         .driver = {
                 .owner = THIS_MODULE,
-                .name = PPC4XX_EDAC_MODULE_NAME
+                .name = PPC4XX_EDAC_MODULE_NAME,
                 .of_match_table = ppc4xx_edac_match,
         },
 };
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 74603ca06e34..8482a23887dc 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -99,6 +99,14 @@ config GPIO_MPC5200
         def_bool y
         depends on PPC_MPC52xx
 
+config GPIO_MPC8XXX
+        bool "MPC512x/MPC8xxx GPIO support"
+        depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \
+                   FSL_SOC_BOOKE || PPC_86xx
+        help
+          Say Y here if you're going to use hardware that connects to the
+          MPC512x/831x/834x/837x/8572/8610 GPIOs.
+
 config GPIO_MSM_V1
         tristate "Qualcomm MSM GPIO v1"
         depends on GPIOLIB && ARCH_MSM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4a9ad2f99ada..dbcb0bcfd8da 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_MC33880)	+= gpio-mc33880.o
 obj-$(CONFIG_GPIO_MCP23S08)     += gpio-mcp23s08.o
 obj-$(CONFIG_GPIO_ML_IOH)       += gpio-ml-ioh.o
 obj-$(CONFIG_GPIO_MPC5200)      += gpio-mpc5200.o
+obj-$(CONFIG_GPIO_MPC8XXX)      += gpio-mpc8xxx.o
 obj-$(CONFIG_GPIO_MSM_V1)       += gpio-msm-v1.o
 obj-$(CONFIG_GPIO_MSM_V2)       += gpio-msm-v2.o
 obj-$(CONFIG_GPIO_MXC)          += gpio-mxc.o
diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
new file mode 100644
index 000000000000..ec3fcf0a7e12
--- /dev/null
+++ b/drivers/gpio/gpio-mpc8xxx.c
@@ -0,0 +1,398 @@
+/*
+ * GPIOs on MPC512x/8349/8572/8610 and compatible
+ *
+ * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+#include <linux/irq.h>
+
+#define MPC8XXX_GPIO_PINS       32
+
+#define GPIO_DIR                0x00
+#define GPIO_ODR                0x04
+#define GPIO_DAT                0x08
+#define GPIO_IER                0x0c
+#define GPIO_IMR                0x10
+#define GPIO_ICR                0x14
+#define GPIO_ICR2               0x18
+
+struct mpc8xxx_gpio_chip {
+        struct of_mm_gpio_chip mm_gc;
+        spinlock_t lock;
+
+        /*
+         * shadowed data register to be able to clear/set output pins in
+         * open drain mode safely
+         */
+        u32 data;
+        struct irq_host *irq;
+        void *of_dev_id_data;
+};
+
+static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
+{
+        return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
+}
+
+static inline struct mpc8xxx_gpio_chip *
+to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
+{
+        return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
+}
+
+static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
+{
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
+
+        mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
+}
+
+/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
+ * defined as output cannot be determined by reading GPDAT register,
+ * so we use shadow data register instead. The status of input pins
+ * is determined by reading GPDAT register.
+ */
+static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+        u32 val;
+        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
+
+        val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
+
+        return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
+}
+
+static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
+
+        return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
+}
+
+static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
+        unsigned long flags;
+
+        spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+
+        if (val)
+                mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
+        else
+                mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
+
+        out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
+
+        spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+}
+
+static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
+        unsigned long flags;
+
+        spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+
+        clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
+
+        spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+
+        return 0;
+}
+
+static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
+        unsigned long flags;
+
+        mpc8xxx_gpio_set(gc, gpio, val);
+
+        spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+
+        setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
+
+        spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+
+        return 0;
+}
+
+static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+{
+        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
+
+        if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
+                return irq_create_mapping(mpc8xxx_gc->irq, offset);
+        else
+                return -ENXIO;
+}
+
+static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
+{
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+        unsigned int mask;
+
+        mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
+        if (mask)
+                generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
+                                                     32 - ffs(mask)));
+        chip->irq_eoi(&desc->irq_data);
+}
+
+static void mpc8xxx_irq_unmask(struct irq_data *d)
+{
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
+        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+        unsigned long flags;
+
+        spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+
+        setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+
+        spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+}
+
+static void mpc8xxx_irq_mask(struct irq_data *d)
+{
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
+        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+        unsigned long flags;
+
+        spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+
+        clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+
+        spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+}
+
+static void mpc8xxx_irq_ack(struct irq_data *d)
+{
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
+        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+
+        out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+}
+
+static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
+{
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
+        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+        unsigned long flags;
+
+        switch (flow_type) {
+        case IRQ_TYPE_EDGE_FALLING:
+                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+                setbits32(mm->regs + GPIO_ICR,
+                          mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+                break;
+
+        case IRQ_TYPE_EDGE_BOTH:
+                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+                clrbits32(mm->regs + GPIO_ICR,
+                          mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
+{
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
+        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+        unsigned long gpio = irqd_to_hwirq(d);
+        void __iomem *reg;
+        unsigned int shift;
+        unsigned long flags;
+
+        if (gpio < 16) {
+                reg = mm->regs + GPIO_ICR;
+                shift = (15 - gpio) * 2;
+        } else {
+                reg = mm->regs + GPIO_ICR2;
+                shift = (15 - (gpio % 16)) * 2;
+        }
+
+        switch (flow_type) {
+        case IRQ_TYPE_EDGE_FALLING:
+        case IRQ_TYPE_LEVEL_LOW:
+                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+                clrsetbits_be32(reg, 3 << shift, 2 << shift);
+                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+                break;
+
+        case IRQ_TYPE_EDGE_RISING:
+        case IRQ_TYPE_LEVEL_HIGH:
+                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+                clrsetbits_be32(reg, 3 << shift, 1 << shift);
+                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+                break;
+
+        case IRQ_TYPE_EDGE_BOTH:
+                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+                clrbits32(reg, 3 << shift);
+                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct irq_chip mpc8xxx_irq_chip = {
+        .name           = "mpc8xxx-gpio",
+        .irq_unmask     = mpc8xxx_irq_unmask,
+        .irq_mask       = mpc8xxx_irq_mask,
+        .irq_ack        = mpc8xxx_irq_ack,
+        .irq_set_type   = mpc8xxx_irq_set_type,
+};
+
+static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
+                                irq_hw_number_t hw)
+{
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
+
+        if (mpc8xxx_gc->of_dev_id_data)
+                mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
+
+        irq_set_chip_data(virq, h->host_data);
+        irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
+        irq_set_irq_type(virq, IRQ_TYPE_NONE);
+
+        return 0;
+}
+
+static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct,
+                                  const u32 *intspec, unsigned int intsize,
+                                  irq_hw_number_t *out_hwirq,
+                                  unsigned int *out_flags)
+
+{
+        /* interrupt sense values coming from the device tree equal either
+         * EDGE_FALLING or EDGE_BOTH
+         */
+        *out_hwirq = intspec[0];
+        *out_flags = intspec[1];
+
+        return 0;
+}
+
+static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
+        .map    = mpc8xxx_gpio_irq_map,
+        .xlate  = mpc8xxx_gpio_irq_xlate,
+};
+
+static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
+        { .compatible = "fsl,mpc8349-gpio", },
+        { .compatible = "fsl,mpc8572-gpio", },
+        { .compatible = "fsl,mpc8610-gpio", },
+        { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
+        { .compatible = "fsl,pq3-gpio",     },
+        { .compatible = "fsl,qoriq-gpio",   },
+        {}
+};
+
+static void __init mpc8xxx_add_controller(struct device_node *np)
+{
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc;
+        struct of_mm_gpio_chip *mm_gc;
+        struct gpio_chip *gc;
+        const struct of_device_id *id;
+        unsigned hwirq;
+        int ret;
+
+        mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
+        if (!mpc8xxx_gc) {
+                ret = -ENOMEM;
+                goto err;
+        }
+
+        spin_lock_init(&mpc8xxx_gc->lock);
+
+        mm_gc = &mpc8xxx_gc->mm_gc;
+        gc = &mm_gc->gc;
+
+        mm_gc->save_regs = mpc8xxx_gpio_save_regs;
+        gc->ngpio = MPC8XXX_GPIO_PINS;
+        gc->direction_input = mpc8xxx_gpio_dir_in;
+        gc->direction_output = mpc8xxx_gpio_dir_out;
+        if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
+                gc->get = mpc8572_gpio_get;
+        else
+                gc->get = mpc8xxx_gpio_get;
+        gc->set = mpc8xxx_gpio_set;
+        gc->to_irq = mpc8xxx_gpio_to_irq;
+
+        ret = of_mm_gpiochip_add(np, mm_gc);
+        if (ret)
+                goto err;
+
+        hwirq = irq_of_parse_and_map(np, 0);
+        if (hwirq == NO_IRQ)
+                goto skip_irq;
+
+        mpc8xxx_gc->irq =
+                irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS,
+                               &mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS);
+        if (!mpc8xxx_gc->irq)
+                goto skip_irq;
+
+        id = of_match_node(mpc8xxx_gpio_ids, np);
+        if (id)
+                mpc8xxx_gc->of_dev_id_data = id->data;
+
+        mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
+
+        /* ack and mask all irqs */
+        out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
+        out_be32(mm_gc->regs + GPIO_IMR, 0);
+
+        irq_set_handler_data(hwirq, mpc8xxx_gc);
+        irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
+
+skip_irq:
+        return;
+
+err:
+        pr_err("%s: registration failed with status %d\n",
+               np->full_name, ret);
+        kfree(mpc8xxx_gc);
+
+        return;
+}
+
+static int __init mpc8xxx_add_gpiochips(void)
+{
+        struct device_node *np;
+
+        for_each_matching_node(np, mpc8xxx_gpio_ids)
+                mpc8xxx_add_controller(np);
+
+        return 0;
+}
+arch_initcall(mpc8xxx_add_gpiochips);
diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.c b/drivers/net/ethernet/toshiba/ps3_gelic_net.c
index ddb33cfd3543..7bf1e2015784 100644
--- a/drivers/net/ethernet/toshiba/ps3_gelic_net.c
+++ b/drivers/net/ethernet/toshiba/ps3_gelic_net.c
@@ -1674,6 +1674,9 @@ static int __devinit ps3_gelic_driver_probe(struct ps3_system_bus_device *dev)
         int result;
 
         pr_debug("%s: called\n", __func__);
+
+        udbg_shutdown_ps3gelic();
+
         result = ps3_open_hv_device(dev);
 
         if (result) {
diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.h b/drivers/net/ethernet/toshiba/ps3_gelic_net.h
index d3fadfbc3bcc..a93df6ac1909 100644
--- a/drivers/net/ethernet/toshiba/ps3_gelic_net.h
+++ b/drivers/net/ethernet/toshiba/ps3_gelic_net.h
@@ -359,6 +359,12 @@ static inline void *port_priv(struct gelic_port *port)
         return port->priv;
 }
 
+#ifdef CONFIG_PPC_EARLY_DEBUG_PS3GELIC
+extern void udbg_shutdown_ps3gelic(void);
+#else
+static inline void udbg_shutdown_ps3gelic(void) {}
+#endif
+
 extern int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask);
 /* shared netdev ops */
 extern void gelic_card_up(struct gelic_card *card);
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index aeec35bc3789..fd85fa298e0f 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -681,9 +681,14 @@ int __init early_init_dt_scan_chosen(unsigned long node, const char *uname,
         if (p != NULL && l > 0)
                 strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
 
+        /*
+         * CONFIG_CMDLINE is meant to be a default in case nothing else
+         * managed to set the command line, unless CONFIG_CMDLINE_FORCE
+         * is set in which case we override whatever was found earlier.
+         */
 #ifdef CONFIG_CMDLINE
 #ifndef CONFIG_CMDLINE_FORCE
-        if (p == NULL || l == 0 || (l == 1 && (*p) == 0))
+        if (!((char *)data)[0])
 #endif
                 strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
 #endif /* CONFIG_CMDLINE */
diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig
index e371753ba921..4222035acfb7 100644
--- a/drivers/tty/hvc/Kconfig
+++ b/drivers/tty/hvc/Kconfig
@@ -34,6 +34,15 @@ config HVC_ISERIES
         help
           iSeries machines support a hypervisor virtual console.
 
+config HVC_OPAL
+        bool "OPAL Console support"
+        depends on PPC_POWERNV
+        select HVC_DRIVER
+        select HVC_IRQ
+        default y
+        help
+          PowerNV machines running under OPAL need that driver to get a console
+
 config HVC_RTAS
         bool "IBM RTAS Console support"
         depends on PPC_RTAS
diff --git a/drivers/tty/hvc/Makefile b/drivers/tty/hvc/Makefile
index e29205316376..89abf40bc73d 100644
--- a/drivers/tty/hvc/Makefile
+++ b/drivers/tty/hvc/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_HVC_CONSOLE)       += hvc_vio.o hvsi_lib.o
+obj-$(CONFIG_HVC_OPAL)          += hvc_opal.o hvsi_lib.o
 obj-$(CONFIG_HVC_OLD_HVSI)      += hvsi.o
 obj-$(CONFIG_HVC_ISERIES)       += hvc_iseries.o
 obj-$(CONFIG_HVC_RTAS)          += hvc_rtas.o
diff --git a/drivers/tty/hvc/hvc_opal.c b/drivers/tty/hvc/hvc_opal.c
new file mode 100644
index 000000000000..7b38512d6c41
--- /dev/null
+++ b/drivers/tty/hvc/hvc_opal.c
@@ -0,0 +1,424 @@
+/*
+ * opal driver interface to hvc_console.c
+ *
+ * Copyright 2011 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#undef DEBUG
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/console.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+#include <asm/hvconsole.h>
+#include <asm/prom.h>
+#include <asm/firmware.h>
+#include <asm/hvsi.h>
+#include <asm/udbg.h>
+#include <asm/opal.h>
+
+#include "hvc_console.h"
+
+static const char hvc_opal_name[] = "hvc_opal";
+
+static struct of_device_id hvc_opal_match[] __devinitdata = {
+        { .name = "serial", .compatible = "ibm,opal-console-raw" },
+        { .name = "serial", .compatible = "ibm,opal-console-hvsi" },
+        { },
+};
+
+typedef enum hv_protocol {
+        HV_PROTOCOL_RAW,
+        HV_PROTOCOL_HVSI
+} hv_protocol_t;
+
+struct hvc_opal_priv {
+        hv_protocol_t           proto;  /* Raw data or HVSI packets */
+        struct hvsi_priv        hvsi;   /* HVSI specific data */
+};
+static struct hvc_opal_priv *hvc_opal_privs[MAX_NR_HVC_CONSOLES];
+
+/* For early boot console */
+static struct hvc_opal_priv hvc_opal_boot_priv;
+static u32 hvc_opal_boot_termno;
+
+static const struct hv_ops hvc_opal_raw_ops = {
+        .get_chars = opal_get_chars,
+        .put_chars = opal_put_chars,
+        .notifier_add = notifier_add_irq,
+        .notifier_del = notifier_del_irq,
+        .notifier_hangup = notifier_hangup_irq,
+};
+
+static int hvc_opal_hvsi_get_chars(uint32_t vtermno, char *buf, int count)
+{
+        struct hvc_opal_priv *pv = hvc_opal_privs[vtermno];
+
+        if (WARN_ON(!pv))
+                return -ENODEV;
+
+        return hvsilib_get_chars(&pv->hvsi, buf, count);
+}
+
+static int hvc_opal_hvsi_put_chars(uint32_t vtermno, const char *buf, int count)
+{
+        struct hvc_opal_priv *pv = hvc_opal_privs[vtermno];
+
+        if (WARN_ON(!pv))
+                return -ENODEV;
+
+        return hvsilib_put_chars(&pv->hvsi, buf, count);
+}
+
+static int hvc_opal_hvsi_open(struct hvc_struct *hp, int data)
+{
+        struct hvc_opal_priv *pv = hvc_opal_privs[hp->vtermno];
+        int rc;
+
+        pr_devel("HVSI@%x: do open !\n", hp->vtermno);
+
+        rc = notifier_add_irq(hp, data);
+        if (rc)
+                return rc;
+
+        return hvsilib_open(&pv->hvsi, hp);
+}
+
+static void hvc_opal_hvsi_close(struct hvc_struct *hp, int data)
+{
+        struct hvc_opal_priv *pv = hvc_opal_privs[hp->vtermno];
+
+        pr_devel("HVSI@%x: do close !\n", hp->vtermno);
+
+        hvsilib_close(&pv->hvsi, hp);
+
+        notifier_del_irq(hp, data);
+}
+
+void hvc_opal_hvsi_hangup(struct hvc_struct *hp, int data)
+{
+        struct hvc_opal_priv *pv = hvc_opal_privs[hp->vtermno];
+
+        pr_devel("HVSI@%x: do hangup !\n", hp->vtermno);
+
+        hvsilib_close(&pv->hvsi, hp);
+
+        notifier_hangup_irq(hp, data);
+}
+
+static int hvc_opal_hvsi_tiocmget(struct hvc_struct *hp)
+{
+        struct hvc_opal_priv *pv = hvc_opal_privs[hp->vtermno];
+
+        if (!pv)
+                return -EINVAL;
+        return pv->hvsi.mctrl;
+}
+
+static int hvc_opal_hvsi_tiocmset(struct hvc_struct *hp, unsigned int set,
+                                unsigned int clear)
+{
+        struct hvc_opal_priv *pv = hvc_opal_privs[hp->vtermno];
+
+        pr_devel("HVSI@%x: Set modem control, set=%x,clr=%x\n",
+                 hp->vtermno, set, clear);
+
+        if (set & TIOCM_DTR)
+                hvsilib_write_mctrl(&pv->hvsi, 1);
+        else if (clear & TIOCM_DTR)
+                hvsilib_write_mctrl(&pv->hvsi, 0);
+
+        return 0;
+}
+
+static const struct hv_ops hvc_opal_hvsi_ops = {
+        .get_chars = hvc_opal_hvsi_get_chars,
+        .put_chars = hvc_opal_hvsi_put_chars,
+        .notifier_add = hvc_opal_hvsi_open,
+        .notifier_del = hvc_opal_hvsi_close,
+        .notifier_hangup = hvc_opal_hvsi_hangup,
+        .tiocmget = hvc_opal_hvsi_tiocmget,
+        .tiocmset = hvc_opal_hvsi_tiocmset,
+};
+
+static int __devinit hvc_opal_probe(struct platform_device *dev)
+{
+        const struct hv_ops *ops;
+        struct hvc_struct *hp;
+        struct hvc_opal_priv *pv;
+        hv_protocol_t proto;
+        unsigned int termno, boot = 0;
+        const __be32 *reg;
+
+        if (of_device_is_compatible(dev->dev.of_node, "ibm,opal-console-raw")) {
+                proto = HV_PROTOCOL_RAW;
+                ops = &hvc_opal_raw_ops;
+        } else if (of_device_is_compatible(dev->dev.of_node,
+                                           "ibm,opal-console-hvsi")) {
+                proto = HV_PROTOCOL_HVSI;
+                ops = &hvc_opal_hvsi_ops;
+        } else {
+                pr_err("hvc_opal: Unkown protocol for %s\n",
+                       dev->dev.of_node->full_name);
+                return -ENXIO;
+        }
+
+        reg = of_get_property(dev->dev.of_node, "reg", NULL);
+        termno = reg ? be32_to_cpup(reg) : 0;
+
+        /* Is it our boot one ? */
+        if (hvc_opal_privs[termno] == &hvc_opal_boot_priv) {
+                pv = hvc_opal_privs[termno];
+                boot = 1;
+        } else if (hvc_opal_privs[termno] == NULL) {
+                pv = kzalloc(sizeof(struct hvc_opal_priv), GFP_KERNEL);
+                if (!pv)
+                        return -ENOMEM;
+                pv->proto = proto;
+                hvc_opal_privs[termno] = pv;
+                if (proto == HV_PROTOCOL_HVSI)
+                        hvsilib_init(&pv->hvsi, opal_get_chars, opal_put_chars,
+                                     termno, 0);
+
+                /* Instanciate now to establish a mapping index==vtermno */
+                hvc_instantiate(termno, termno, ops);
+        } else {
+                pr_err("hvc_opal: Device %s has duplicate terminal number #%d\n",
+                       dev->dev.of_node->full_name, termno);
+                return -ENXIO;
+        }
+
+        pr_info("hvc%d: %s protocol on %s%s\n", termno,
+                proto == HV_PROTOCOL_RAW ? "raw" : "hvsi",
+                dev->dev.of_node->full_name,
+                boot ? " (boot console)" : "");
+
+        /* We don't do IRQ yet */
+        hp = hvc_alloc(termno, 0, ops, MAX_VIO_PUT_CHARS);
+        if (IS_ERR(hp))
+                return PTR_ERR(hp);
+        dev_set_drvdata(&dev->dev, hp);
+
+        return 0;
+}
+
+static int __devexit hvc_opal_remove(struct platform_device *dev)
+{
+        struct hvc_struct *hp = dev_get_drvdata(&dev->dev);
+        int rc, termno;
+
+        termno = hp->vtermno;
+        rc = hvc_remove(hp);
+        if (rc == 0) {
+                if (hvc_opal_privs[termno] != &hvc_opal_boot_priv)
+                        kfree(hvc_opal_privs[termno]);
+                hvc_opal_privs[termno] = NULL;
+        }
+        return rc;
+}
+
+static struct platform_driver hvc_opal_driver = {
+        .probe          = hvc_opal_probe,
+        .remove         = __devexit_p(hvc_opal_remove),
+        .driver         = {
+                .name   = hvc_opal_name,
+                .owner  = THIS_MODULE,
+                .of_match_table = hvc_opal_match,
+        }
+};
+
+static int __init hvc_opal_init(void)
+{
+        if (!firmware_has_feature(FW_FEATURE_OPAL))
+                return -ENODEV;
+
+        /* Register as a vio device to receive callbacks */
+        return platform_driver_register(&hvc_opal_driver);
+}
+module_init(hvc_opal_init);
+
+static void __exit hvc_opal_exit(void)
+{
+        platform_driver_unregister(&hvc_opal_driver);
+}
+module_exit(hvc_opal_exit);
+
+static void udbg_opal_putc(char c)
+{
+        unsigned int termno = hvc_opal_boot_termno;
+        int count = -1;
+
+        if (c == '\n')
+                udbg_opal_putc('\r');
+
+        do {
+                switch(hvc_opal_boot_priv.proto) {
+                case HV_PROTOCOL_RAW:
+                        count = opal_put_chars(termno, &c, 1);
+                        break;
+                case HV_PROTOCOL_HVSI:
+                        count = hvc_opal_hvsi_put_chars(termno, &c, 1);
+                        break;
+                }
+        } while(count == 0 || count == -EAGAIN);
+}
+
+static int udbg_opal_getc_poll(void)
+{
+        unsigned int termno = hvc_opal_boot_termno;
+        int rc = 0;
+        char c;
+
+        switch(hvc_opal_boot_priv.proto) {
+        case HV_PROTOCOL_RAW:
+                rc = opal_get_chars(termno, &c, 1);
+                break;
+        case HV_PROTOCOL_HVSI:
+                rc = hvc_opal_hvsi_get_chars(termno, &c, 1);
+                break;
+        }
+        if (!rc)
+                return -1;
+        return c;
+}
+
+static int udbg_opal_getc(void)
+{
+        int ch;
+        for (;;) {
+                ch = udbg_opal_getc_poll();
+                if (ch == -1) {
+                        /* This shouldn't be needed...but... */
+                        volatile unsigned long delay;
+                        for (delay=0; delay < 2000000; delay++)
+                                ;
+                } else {
+                        return ch;
+                }
+        }
+}
+
+static void udbg_init_opal_common(void)
+{
+        udbg_putc = udbg_opal_putc;
+        udbg_getc = udbg_opal_getc;
+        udbg_getc_poll = udbg_opal_getc_poll;
+        tb_ticks_per_usec = 0x200; /* Make udelay not suck */
+}
+
+void __init hvc_opal_init_early(void)
+{
+        struct device_node *stdout_node = NULL;
+        const u32 *termno;
+        const char *name = NULL;
+        const struct hv_ops *ops;
+        u32 index;
+
+        /* find the boot console from /chosen/stdout */
+        if (of_chosen)
+                name = of_get_property(of_chosen, "linux,stdout-path", NULL);
+        if (name) {
+                stdout_node = of_find_node_by_path(name);
+                if (!stdout_node) {
+                        pr_err("hvc_opal: Failed to locate default console!\n");
+                        return;
+                }
+        } else {
+                struct device_node *opal, *np;
+
+                /* Current OPAL takeover doesn't provide the stdout
+                 * path, so we hard wire it
+                 */
+                opal = of_find_node_by_path("/ibm,opal/consoles");
+                if (opal)
+                        pr_devel("hvc_opal: Found consoles in new location\n");
+                if (!opal) {
+                        opal = of_find_node_by_path("/ibm,opal");
+                        if (opal)
+                                pr_devel("hvc_opal: "
+                                         "Found consoles in old location\n");
+                }
+                if (!opal)
+                        return;
+                for_each_child_of_node(opal, np) {
+                        if (!strcmp(np->name, "serial")) {
+                                stdout_node = np;
+                                break;
+                        }
+                }
+                of_node_put(opal);
+        }
+        if (!stdout_node)
+                return;
+        termno = of_get_property(stdout_node, "reg", NULL);
+        index = termno ? *termno : 0;
+        if (index >= MAX_NR_HVC_CONSOLES)
+                return;
+        hvc_opal_privs[index] = &hvc_opal_boot_priv;
+
+        /* Check the protocol */
+        if (of_device_is_compatible(stdout_node, "ibm,opal-console-raw")) {
+                hvc_opal_boot_priv.proto = HV_PROTOCOL_RAW;
+                ops = &hvc_opal_raw_ops;
+                pr_devel("hvc_opal: Found RAW console\n");
+        }
+        else if (of_device_is_compatible(stdout_node,"ibm,opal-console-hvsi")) {
+                hvc_opal_boot_priv.proto = HV_PROTOCOL_HVSI;
+                ops = &hvc_opal_hvsi_ops;
+                hvsilib_init(&hvc_opal_boot_priv.hvsi, opal_get_chars,
+                             opal_put_chars, index, 1);
+                /* HVSI, perform the handshake now */
+                hvsilib_establish(&hvc_opal_boot_priv.hvsi);
+                pr_devel("hvc_opal: Found HVSI console\n");
+        } else
+                goto out;
+        hvc_opal_boot_termno = index;
+        udbg_init_opal_common();
+        add_preferred_console("hvc", index, NULL);
+        hvc_instantiate(index, index, ops);
+out:
+        of_node_put(stdout_node);
+}
+
+#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL_RAW
+void __init udbg_init_debug_opal(void)
+{
+        u32 index = CONFIG_PPC_EARLY_DEBUG_OPAL_VTERMNO;
+        hvc_opal_privs[index] = &hvc_opal_boot_priv;
+        hvc_opal_boot_priv.proto = HV_PROTOCOL_RAW;
+        hvc_opal_boot_termno = index;
+        udbg_init_opal_common();
+}
+#endif /* CONFIG_PPC_EARLY_DEBUG_OPAL_RAW */
+
+#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL_HVSI
+void __init udbg_init_debug_opal_hvsi(void)
+{
+        u32 index = CONFIG_PPC_EARLY_DEBUG_OPAL_VTERMNO;
+        hvc_opal_privs[index] = &hvc_opal_boot_priv;
+        hvc_opal_boot_termno = index;
+        udbg_init_opal_common();
+        hvsilib_init(&hvc_opal_boot_priv.hvsi, opal_get_chars, opal_put_chars,
+                     index, 1);
+        hvsilib_establish(&hvc_opal_boot_priv.hvsi);
+}
+#endif /* CONFIG_PPC_EARLY_DEBUG_OPAL_HVSI */
diff --git a/drivers/tty/hvc/hvcs.c b/drivers/tty/hvc/hvcs.c
index 55882b5930a6..b9040bec36bd 100644
--- a/drivers/tty/hvc/hvcs.c
+++ b/drivers/tty/hvc/hvcs.c
@@ -1532,7 +1532,7 @@ static int __devinit hvcs_initialize(void)
                 goto register_fail;
         }
 
-        hvcs_pi_buff = kmalloc(PAGE_SIZE, GFP_KERNEL);
+        hvcs_pi_buff = (unsigned long *) __get_free_page(GFP_KERNEL);
         if (!hvcs_pi_buff) {
                 rc = -ENOMEM;
                 goto buff_alloc_fail;
@@ -1548,7 +1548,7 @@ static int __devinit hvcs_initialize(void)
         return 0;
 
 kthread_fail:
-        kfree(hvcs_pi_buff);
+        free_page((unsigned long)hvcs_pi_buff);
 buff_alloc_fail:
         tty_unregister_driver(hvcs_tty_driver);
 register_fail:
@@ -1597,7 +1597,7 @@ static void __exit hvcs_module_exit(void)
         kthread_stop(hvcs_task);
 
         spin_lock(&hvcs_pi_lock);
-        kfree(hvcs_pi_buff);
+        free_page((unsigned long)hvcs_pi_buff);
         hvcs_pi_buff = NULL;
         spin_unlock(&hvcs_pi_lock);
 
diff --git a/drivers/tty/hvc/hvsi_lib.c b/drivers/tty/hvc/hvsi_lib.c
index bd9b09827b24..6f4dd83d8695 100644
--- a/drivers/tty/hvc/hvsi_lib.c
+++ b/drivers/tty/hvc/hvsi_lib.c
@@ -183,7 +183,7 @@ int hvsilib_get_chars(struct hvsi_priv *pv, char *buf, int count)
         unsigned int tries, read = 0;
 
         if (WARN_ON(!pv))
-                return 0;
+                return -ENXIO;
 
         /* If we aren't open, don't do anything in order to avoid races
          * with connection establishment. The hvc core will call this
@@ -234,7 +234,7 @@ int hvsilib_put_chars(struct hvsi_priv *pv, const char *buf, int count)
         int rc, adjcount = min(count, HVSI_MAX_OUTGOING_DATA);
 
         if (WARN_ON(!pv))
-                return 0;
+                return -ENODEV;
 
         dp.hdr.type = VS_DATA_PACKET_HEADER;
         dp.hdr.len = adjcount + sizeof(struct hvsi_header);
diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
index a87a56cb5417..eeadf1b8e093 100644
--- a/drivers/tty/serial/8250.c
+++ b/drivers/tty/serial/8250.c
@@ -450,24 +450,6 @@ static void au_serial_out(struct uart_port *p, int offset, int value)
         __raw_writel(value, p->membase + offset);
 }
 
-static unsigned int tsi_serial_in(struct uart_port *p, int offset)
-{
-        unsigned int tmp;
-        offset = map_8250_in_reg(p, offset) << p->regshift;
-        if (offset == UART_IIR) {
-                tmp = readl(p->membase + (UART_IIR & ~3));
-                return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
-        } else
-                return readb(p->membase + offset);
-}
-
-static void tsi_serial_out(struct uart_port *p, int offset, int value)
-{
-        offset = map_8250_out_reg(p, offset) << p->regshift;
-        if (!((offset == UART_IER) && (value & UART_IER_UUE)))
-                writeb(value, p->membase + offset);
-}
-
 static unsigned int io_serial_in(struct uart_port *p, int offset)
 {
         offset = map_8250_in_reg(p, offset) << p->regshift;
@@ -508,11 +490,6 @@ static void set_io_from_upio(struct uart_port *p)
                 p->serial_out = au_serial_out;
                 break;
 
-        case UPIO_TSI:
-                p->serial_in = tsi_serial_in;
-                p->serial_out = tsi_serial_out;
-                break;
-
         default:
                 p->serial_in = io_serial_in;
                 p->serial_out = io_serial_out;
diff --git a/drivers/virt/fsl_hypervisor.c b/drivers/virt/fsl_hypervisor.c
index 3d9162151fd2..4939e0ccc4e5 100644
--- a/drivers/virt/fsl_hypervisor.c
+++ b/drivers/virt/fsl_hypervisor.c
@@ -706,6 +706,7 @@ static const struct file_operations fsl_hv_fops = {
         .poll = fsl_hv_poll,
         .read = fsl_hv_read,
         .unlocked_ioctl = fsl_hv_ioctl,
+        .compat_ioctl = fsl_hv_ioctl,
 };
 
 static struct miscdevice fsl_hv_misc_dev = {