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authorNick Kossifidis <mick@madwifi.org>2008-07-30 06:18:59 -0400
committerJohn W. Linville <linville@tuxdriver.com>2008-08-01 15:31:31 -0400
commit0bacdf303f72a3ed34252934114bc04e79222687 (patch)
tree59f6144374b22822a0db710e8f6061d7982cd1b3 /drivers
parent00b1304c4ca81dd893973cc620b87a5c3ff3f660 (diff)
ath5k: Update register list
* Update list of registers * Use updated register macros inside hw.c, initvals.c and debug.c Changes-licensed-under: ISC Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/ath5k/debug.c2
-rw-r--r--drivers/net/wireless/ath5k/hw.c43
-rw-r--r--drivers/net/wireless/ath5k/initvals.c4
-rw-r--r--drivers/net/wireless/ath5k/reg.h934
4 files changed, 720 insertions, 263 deletions
diff --git a/drivers/net/wireless/ath5k/debug.c b/drivers/net/wireless/ath5k/debug.c
index 41d5fa34b544..6fa6c8e04ff0 100644
--- a/drivers/net/wireless/ath5k/debug.c
+++ b/drivers/net/wireless/ath5k/debug.c
@@ -129,7 +129,7 @@ static struct reg regs[] = {
129 REG_STRUCT_INIT(AR5K_CPC1), 129 REG_STRUCT_INIT(AR5K_CPC1),
130 REG_STRUCT_INIT(AR5K_CPC2), 130 REG_STRUCT_INIT(AR5K_CPC2),
131 REG_STRUCT_INIT(AR5K_CPC3), 131 REG_STRUCT_INIT(AR5K_CPC3),
132 REG_STRUCT_INIT(AR5K_CPCORN), 132 REG_STRUCT_INIT(AR5K_CPCOVF),
133 REG_STRUCT_INIT(AR5K_RESET_CTL), 133 REG_STRUCT_INIT(AR5K_RESET_CTL),
134 REG_STRUCT_INIT(AR5K_SLEEP_CTL), 134 REG_STRUCT_INIT(AR5K_SLEEP_CTL),
135 REG_STRUCT_INIT(AR5K_INTPEND), 135 REG_STRUCT_INIT(AR5K_INTPEND),
diff --git a/drivers/net/wireless/ath5k/hw.c b/drivers/net/wireless/ath5k/hw.c
index 7ca87a557312..42ef41ed5d18 100644
--- a/drivers/net/wireless/ath5k/hw.c
+++ b/drivers/net/wireless/ath5k/hw.c
@@ -843,27 +843,26 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
843 * Write some more initial register settings 843 * Write some more initial register settings
844 */ 844 */
845 if (ah->ah_version == AR5K_AR5212) { 845 if (ah->ah_version == AR5K_AR5212) {
846 ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11)); 846 ath5k_hw_reg_write(ah, 0x0002a002, 0x982c);
847 847
848 if (channel->hw_value == CHANNEL_G) 848 if (channel->hw_value == CHANNEL_G)
849 if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413) 849 if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413)
850 ath5k_hw_reg_write(ah, 0x00f80d80, 850 ath5k_hw_reg_write(ah, 0x00f80d80,
851 AR5K_PHY(83)); 851 0x994c);
852 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424) 852 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424)
853 ath5k_hw_reg_write(ah, 0x00380140, 853 ath5k_hw_reg_write(ah, 0x00380140,
854 AR5K_PHY(83)); 854 0x994c);
855 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425) 855 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425)
856 ath5k_hw_reg_write(ah, 0x00fc0ec0, 856 ath5k_hw_reg_write(ah, 0x00fc0ec0,
857 AR5K_PHY(83)); 857 0x994c);
858 else /* 2425 */ 858 else /* 2425 */
859 ath5k_hw_reg_write(ah, 0x00fc0fc0, 859 ath5k_hw_reg_write(ah, 0x00fc0fc0,
860 AR5K_PHY(83)); 860 0x994c);
861 else 861 else
862 ath5k_hw_reg_write(ah, 0x00000000, 862 ath5k_hw_reg_write(ah, 0x00000000, 0x994c);
863 AR5K_PHY(83));
864 863
865 ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); 864 ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);
866 ath5k_hw_reg_write(ah, 0x0000000f, 0x8060); 865 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
867 ath5k_hw_reg_write(ah, 0x00000000, 0xa254); 866 ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
868 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL); 867 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
869 } 868 }
@@ -935,7 +934,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
935 return ret; 934 return ret;
936 935
937 /* Set antenna mode */ 936 /* Set antenna mode */
938 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x44), 937 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_ANT_CTL,
939 ah->ah_antenna[ee_mode][0], 0xfffffc06); 938 ah->ah_antenna[ee_mode][0], 0xfffffc06);
940 939
941 /* 940 /*
@@ -965,15 +964,15 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
965 964
966 ath5k_hw_reg_write(ah, 965 ath5k_hw_reg_write(ah,
967 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), 966 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
968 AR5K_PHY(0x5a)); 967 AR5K_PHY_NFTHRES);
969 968
970 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x11), 969 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_SETTLING,
971 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 970 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
972 0xffffc07f); 971 0xffffc07f);
973 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x12), 972 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_GAIN,
974 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 973 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
975 0xfffc0fff); 974 0xfffc0fff);
976 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x14), 975 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_DESIRED_SIZE,
977 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | 976 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
978 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 977 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
979 0xffff0000); 978 0xffff0000);
@@ -982,13 +981,13 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
982 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | 981 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
983 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | 982 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
984 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | 983 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
985 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d)); 984 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
986 985
987 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x0a), 986 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_RF_CTL3,
988 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); 987 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
989 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x19), 988 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_NF,
990 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); 989 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
991 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x49), 4, 0xffffff01); 990 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 4, 0xffffff01);
992 991
993 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 992 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
994 AR5K_PHY_IQ_CORR_ENABLE | 993 AR5K_PHY_IQ_CORR_ENABLE |
@@ -3363,11 +3362,13 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3363 ath5k_hw_reg_write(ah, ah->ah_turbo ? 3362 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3364 AR5K_INIT_PROTO_TIME_CNTRL_TURBO : 3363 AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
3365 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); 3364 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
3366 /* Set PHY register 0x9844 (??) */ 3365 /* Set AR5K_PHY_SETTLING */
3367 ath5k_hw_reg_write(ah, ah->ah_turbo ? 3366 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3368 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 : 3367 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
3369 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C, 3368 | 0x38 :
3370 AR5K_PHY(17)); 3369 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
3370 | 0x1C,
3371 AR5K_PHY_SETTLING);
3371 /* Set Frame Control Register */ 3372 /* Set Frame Control Register */
3372 ath5k_hw_reg_write(ah, ah->ah_turbo ? 3373 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3373 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | 3374 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
diff --git a/drivers/net/wireless/ath5k/initvals.c b/drivers/net/wireless/ath5k/initvals.c
index 04c84e9da89d..2806b21bf90b 100644
--- a/drivers/net/wireless/ath5k/initvals.c
+++ b/drivers/net/wireless/ath5k/initvals.c
@@ -489,7 +489,7 @@ static const struct ath5k_ini ar5212_ini[] = {
489 { AR5K_QUEUE_TXDP(9), 0x00000000 }, 489 { AR5K_QUEUE_TXDP(9), 0x00000000 },
490 { AR5K_DCU_FP, 0x00000000 }, 490 { AR5K_DCU_FP, 0x00000000 },
491 { AR5K_DCU_TXP, 0x00000000 }, 491 { AR5K_DCU_TXP, 0x00000000 },
492 { AR5K_DCU_TX_FILTER, 0x00000000 }, 492 { AR5K_DCU_TX_FILTER_0_BASE, 0x00000000 },
493 /* Unknown table */ 493 /* Unknown table */
494 { 0x1078, 0x00000000 }, 494 { 0x1078, 0x00000000 },
495 { 0x10b8, 0x00000000 }, 495 { 0x10b8, 0x00000000 },
@@ -679,7 +679,7 @@ static const struct ath5k_ini ar5212_ini[] = {
679 { AR5K_PHY(645), 0x00106c10 }, 679 { AR5K_PHY(645), 0x00106c10 },
680 { AR5K_PHY(646), 0x009c4060 }, 680 { AR5K_PHY(646), 0x009c4060 },
681 { AR5K_PHY(647), 0x1483800a }, 681 { AR5K_PHY(647), 0x1483800a },
682 /* { AR5K_PHY(648), 0x018830c6 },*/ /* 2413 */ 682 /* { AR5K_PHY(648), 0x018830c6 },*/ /* 2413/2425 */
683 { AR5K_PHY(648), 0x01831061 }, 683 { AR5K_PHY(648), 0x01831061 },
684 { AR5K_PHY(649), 0x00000400 }, 684 { AR5K_PHY(649), 0x00000400 },
685 /*{ AR5K_PHY(650), 0x000001b5 },*/ 685 /*{ AR5K_PHY(650), 0x000001b5 },*/
diff --git a/drivers/net/wireless/ath5k/reg.h b/drivers/net/wireless/ath5k/reg.h
index 30629b3e37c2..7562bf173d3e 100644
--- a/drivers/net/wireless/ath5k/reg.h
+++ b/drivers/net/wireless/ath5k/reg.h
@@ -53,7 +53,7 @@
53#define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ 53#define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
54#define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ 54#define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
55#define AR5K_CR_RXD 0x00000020 /* RX Disable */ 55#define AR5K_CR_RXD 0x00000020 /* RX Disable */
56#define AR5K_CR_SWI 0x00000040 56#define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
57 57
58/* 58/*
59 * RX Descriptor Pointer register 59 * RX Descriptor Pointer register
@@ -65,19 +65,19 @@
65 */ 65 */
66#define AR5K_CFG 0x0014 /* Register Address */ 66#define AR5K_CFG 0x0014 /* Register Address */
67#define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */ 67#define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */
68#define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer (?) */ 68#define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */
69#define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ 69#define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */
70#define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer (?) */ 70#define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */
71#define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register values (?) */ 71#define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */
72#define AR5K_CFG_ADHOC 0x00000020 /* [5211+] */ 72#define AR5K_CFG_ADHOC 0x00000020 /* AP/Adhoc indication [5211+] */
73#define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ 73#define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */
74#define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ 74#define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */
75#define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (?) */ 75#define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */
76#define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */ 76#define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */
77#define AR5K_CFG_TXCNT_S 11 77#define AR5K_CFG_TXCNT_S 11
78#define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ 78#define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */
79#define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ 79#define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */
80#define AR5K_CFG_PCI_THRES 0x00060000 /* [5211+] */ 80#define AR5K_CFG_PCI_THRES 0x00060000 /* PCI Master req q threshold [5211+] */
81#define AR5K_CFG_PCI_THRES_S 17 81#define AR5K_CFG_PCI_THRES_S 17
82 82
83/* 83/*
@@ -162,35 +162,40 @@
162/* 162/*
163 * Transmit configuration register 163 * Transmit configuration register
164 */ 164 */
165#define AR5K_TXCFG 0x0030 /* Register Address */ 165#define AR5K_TXCFG 0x0030 /* Register Address */
166#define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size */ 166#define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size (read) */
167#define AR5K_TXCFG_SDMAMR_S 0 167#define AR5K_TXCFG_SDMAMR_S 0
168#define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */ 168#define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */
169#define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */ 169#define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */
170#define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */ 170#define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */
171#define AR5K_TXCFG_TXFULL_S 4 171#define AR5K_TXCFG_TXFULL_S 4
172#define AR5K_TXCFG_TXFULL_0B 0x00000000 172#define AR5K_TXCFG_TXFULL_0B 0x00000000
173#define AR5K_TXCFG_TXFULL_64B 0x00000010 173#define AR5K_TXCFG_TXFULL_64B 0x00000010
174#define AR5K_TXCFG_TXFULL_128B 0x00000020 174#define AR5K_TXCFG_TXFULL_128B 0x00000020
175#define AR5K_TXCFG_TXFULL_192B 0x00000030 175#define AR5K_TXCFG_TXFULL_192B 0x00000030
176#define AR5K_TXCFG_TXFULL_256B 0x00000040 176#define AR5K_TXCFG_TXFULL_256B 0x00000040
177#define AR5K_TXCFG_TXCONT_EN 0x00000080 177#define AR5K_TXCFG_TXCONT_EN 0x00000080
178#define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ 178#define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */
179#define AR5K_TXCFG_JUMBO_TXE 0x00000400 /* Enable jumbo frames transmition (?) [5211+] */ 179#define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400 /* Enable jumbo tx descriptors [5211+] */
180#define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ 180#define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 /* Adhoc Beacon ATIM Policy */
181#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */ 181#define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 /* Disable ATIM window defer [5211+] */
182#define AR5K_TXCFG_RDY_DIS 0x00004000 /* [5211+] */ 182#define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */
183#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */
184#define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */
185#define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */
186#define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */
183 187
184/* 188/*
185 * Receive configuration register 189 * Receive configuration register
186 */ 190 */
187#define AR5K_RXCFG 0x0034 /* Register Address */ 191#define AR5K_RXCFG 0x0034 /* Register Address */
188#define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size */ 192#define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size (write) */
189#define AR5K_RXCFG_SDMAMW_S 0 193#define AR5K_RXCFG_SDMAMW_S 0
190#define AR5K_RXCFG_DEF_ANTENNA 0x00000008 /* Default antenna */ 194#define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */
191#define AR5K_RXCFG_ZLFDMA 0x00000010 /* Zero-length DMA */ 195#define AR5K_RXCFG_DEF_ANTENNA 0x00000010 /* Default antenna (?) */
192#define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo frames reception (?) [5211+] */ 196#define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo rx descriptors [5211+] */
193#define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames (?) [5211+] */ 197#define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames [5211+] */
198#define AR5K_RXCFG_SLE_ENTRY 0x00000080 /* Sleep entry policy */
194 199
195/* 200/*
196 * Receive jumbo descriptor last address register 201 * Receive jumbo descriptor last address register
@@ -202,35 +207,35 @@
202 * MIB control register 207 * MIB control register
203 */ 208 */
204#define AR5K_MIBC 0x0040 /* Register Address */ 209#define AR5K_MIBC 0x0040 /* Register Address */
205#define AR5K_MIBC_COW 0x00000001 210#define AR5K_MIBC_COW 0x00000001 /* Warn test indicator */
206#define AR5K_MIBC_FMC 0x00000002 /* Freeze Mib Counters (?) */ 211#define AR5K_MIBC_FMC 0x00000002 /* Freeze MIB Counters */
207#define AR5K_MIBC_CMC 0x00000004 /* Clean Mib Counters (?) */ 212#define AR5K_MIBC_CMC 0x00000004 /* Clean MIB Counters */
208#define AR5K_MIBC_MCS 0x00000008 213#define AR5K_MIBC_MCS 0x00000008 /* MIB counter strobe */
209 214
210/* 215/*
211 * Timeout prescale register 216 * Timeout prescale register
212 */ 217 */
213#define AR5K_TOPS 0x0044 218#define AR5K_TOPS 0x0044
214#define AR5K_TOPS_M 0x0000ffff /* [5211+] (?) */ 219#define AR5K_TOPS_M 0x0000ffff
215 220
216/* 221/*
217 * Receive timeout register (no frame received) 222 * Receive timeout register (no frame received)
218 */ 223 */
219#define AR5K_RXNOFRM 0x0048 224#define AR5K_RXNOFRM 0x0048
220#define AR5K_RXNOFRM_M 0x000003ff /* [5211+] (?) */ 225#define AR5K_RXNOFRM_M 0x000003ff
221 226
222/* 227/*
223 * Transmit timeout register (no frame sent) 228 * Transmit timeout register (no frame sent)
224 */ 229 */
225#define AR5K_TXNOFRM 0x004c 230#define AR5K_TXNOFRM 0x004c
226#define AR5K_TXNOFRM_M 0x000003ff /* [5211+] (?) */ 231#define AR5K_TXNOFRM_M 0x000003ff
227#define AR5K_TXNOFRM_QCU 0x000ffc00 /* [5211+] (?) */ 232#define AR5K_TXNOFRM_QCU 0x000ffc00
228 233
229/* 234/*
230 * Receive frame gap timeout register 235 * Receive frame gap timeout register
231 */ 236 */
232#define AR5K_RPGTO 0x0050 237#define AR5K_RPGTO 0x0050
233#define AR5K_RPGTO_M 0x000003ff /* [5211+] (?) */ 238#define AR5K_RPGTO_M 0x000003ff
234 239
235/* 240/*
236 * Receive frame count limit register 241 * Receive frame count limit register
@@ -241,6 +246,7 @@
241 246
242/* 247/*
243 * Misc settings register 248 * Misc settings register
249 * (reserved0-3)
244 */ 250 */
245#define AR5K_MISC 0x0058 /* Register Address */ 251#define AR5K_MISC 0x0058 /* Register Address */
246#define AR5K_MISC_DMA_OBS_M 0x000001e0 252#define AR5K_MISC_DMA_OBS_M 0x000001e0
@@ -256,6 +262,7 @@
256 262
257/* 263/*
258 * QCU/DCU clock gating register (5311) 264 * QCU/DCU clock gating register (5311)
265 * (reserved4-5)
259 */ 266 */
260#define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */ 267#define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */
261#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */ 268#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */
@@ -284,18 +291,18 @@
284#define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ 291#define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */
285#define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ 292#define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */
286#define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ 293#define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */
287#define AR5K_ISR_SWI 0x00002000 /* Software interrupt (?) */ 294#define AR5K_ISR_SWI 0x00002000 /* Software interrupt */
288#define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ 295#define AR5K_ISR_RXPHY 0x00004000 /* PHY error */
289#define AR5K_ISR_RXKCM 0x00008000 296#define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */
290#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ 297#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */
291#define AR5K_ISR_BRSSI 0x00020000 298#define AR5K_ISR_BRSSI 0x00020000
292#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ 299#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */
293#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 300#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
294#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ 301#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */
295#define AR5K_ISR_MCABT 0x00100000 /* [5210] */ 302#define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */
296#define AR5K_ISR_RXCHIRP 0x00200000 /* [5212+] */ 303#define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */
297#define AR5K_ISR_SSERR 0x00200000 /* [5210] */ 304#define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */
298#define AR5K_ISR_DPERR 0x00400000 /* [5210] */ 305#define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */
299#define AR5K_ISR_TIM 0x00800000 /* [5210] */ 306#define AR5K_ISR_TIM 0x00800000 /* [5210] */
300#define AR5K_ISR_BCNMISC 0x00800000 /* [5212+] */ 307#define AR5K_ISR_BCNMISC 0x00800000 /* [5212+] */
301#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill)*/ 308#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill)*/
@@ -320,14 +327,14 @@
320 327
321#define AR5K_SISR2 0x008c /* Register Address [5211+] */ 328#define AR5K_SISR2 0x008c /* Register Address [5211+] */
322#define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ 329#define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */
323#define AR5K_SISR2_MCABT 0x00100000 330#define AR5K_SISR2_MCABT 0x00100000 /* Master Cycle Abort */
324#define AR5K_SISR2_SSERR 0x00200000 331#define AR5K_SISR2_SSERR 0x00200000 /* Signaled System Error */
325#define AR5K_SISR2_DPERR 0x00400000 332#define AR5K_SISR2_DPERR 0x00400000 /* Det par Error (?) */
326#define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ 333#define AR5K_SISR2_TIM 0x01000000 /* [5212+] */
327#define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ 334#define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */
328#define AR5K_SISR2_DTIM_SYNC 0x04000000 /* [5212+] */ 335#define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */
329#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* [5212+] */ 336#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
330#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* [5212+] */ 337#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
331#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ 338#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */
332 339
333#define AR5K_SISR3 0x0090 /* Register Address [5211+] */ 340#define AR5K_SISR3 0x0090 /* Register Address [5211+] */
@@ -368,18 +375,18 @@
368#define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ 375#define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/
369#define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ 376#define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/
370#define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ 377#define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/
371#define AR5K_IMR_SWI 0x00002000 378#define AR5K_IMR_SWI 0x00002000 /* Software interrupt */
372#define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ 379#define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/
373#define AR5K_IMR_RXKCM 0x00008000 380#define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */
374#define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ 381#define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/
375#define AR5K_IMR_BRSSI 0x00020000 382#define AR5K_IMR_BRSSI 0x00020000
376#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ 383#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/
377#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 384#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
378#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ 385#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */
379#define AR5K_IMR_MCABT 0x00100000 /* [5210] */ 386#define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */
380#define AR5K_IMR_RXCHIRP 0x00200000 /* [5212+]*/ 387#define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/
381#define AR5K_IMR_SSERR 0x00200000 /* [5210] */ 388#define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */
382#define AR5K_IMR_DPERR 0x00400000 /* [5210] */ 389#define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */
383#define AR5K_IMR_TIM 0x00800000 /* [5211+] */ 390#define AR5K_IMR_TIM 0x00800000 /* [5211+] */
384#define AR5K_IMR_BCNMISC 0x00800000 /* [5212+] */ 391#define AR5K_IMR_BCNMISC 0x00800000 /* [5212+] */
385#define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ 392#define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/
@@ -405,14 +412,14 @@
405#define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ 412#define AR5K_SIMR2 0x00ac /* Register Address [5211+] */
406#define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ 413#define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */
407#define AR5K_SIMR2_QCU_TXURN_S 0 414#define AR5K_SIMR2_QCU_TXURN_S 0
408#define AR5K_SIMR2_MCABT 0x00100000 415#define AR5K_SIMR2_MCABT 0x00100000 /* Master Cycle Abort */
409#define AR5K_SIMR2_SSERR 0x00200000 416#define AR5K_SIMR2_SSERR 0x00200000 /* Signaled System Error */
410#define AR5K_SIMR2_DPERR 0x00400000 417#define AR5K_SIMR2_DPERR 0x00400000 /* Det par Error (?) */
411#define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ 418#define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */
412#define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ 419#define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */
413#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* [5212+] */ 420#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */
414#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* [5212+] */ 421#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
415#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* [5212+] */ 422#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
416#define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ 423#define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */
417 424
418#define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ 425#define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */
@@ -425,23 +432,69 @@
425#define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */ 432#define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */
426#define AR5K_SIMR4_QTRIG_S 0 433#define AR5K_SIMR4_QTRIG_S 0
427 434
435/*
436 * DMA Debug registers 0-7
437 * 0xe0 - 0xfc
438 */
428 439
429/* 440/*
430 * Decompression mask registers [5212+] 441 * Decompression mask registers [5212+]
431 */ 442 */
432#define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (?)*/ 443#define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (index) */
433#define AR5K_DCM_DATA 0x0404 /*Decompression mask data (?)*/ 444#define AR5K_DCM_DATA 0x0404 /*Decompression mask data */
445
446/*
447 * Wake On Wireless pattern control register [5212+]
448 */
449#define AR5K_WOW_PCFG 0x0410 /* Register Address */
450#define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 /* Pattern match enable */
451#define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 /* Long frame policy */
452#define AR5K_WOW_PCFG_WOBMISS 0x00000004 /* Wake on bea(con) miss (?) */
453#define AR5K_WOW_PCFG_PAT_0_EN 0x00000100 /* Enable pattern 0 */
454#define AR5K_WOW_PCFG_PAT_1_EN 0x00000200 /* Enable pattern 1 */
455#define AR5K_WOW_PCFG_PAT_2_EN 0x00000400 /* Enable pattern 2 */
456#define AR5K_WOW_PCFG_PAT_3_EN 0x00000800 /* Enable pattern 3 */
457#define AR5K_WOW_PCFG_PAT_4_EN 0x00001000 /* Enable pattern 4 */
458#define AR5K_WOW_PCFG_PAT_5_EN 0x00002000 /* Enable pattern 5 */
459
460/*
461 * Wake On Wireless pattern index register (?) [5212+]
462 */
463#define AR5K_WOW_PAT_IDX 0x0414
464
465/*
466 * Wake On Wireless pattern data register [5212+]
467 */
468#define AR5K_WOW_PAT_DATA 0x0418 /* Register Address */
469#define AR5K_WOW_PAT_DATA_0_3_V 0x00000001 /* Pattern 0, 3 value */
470#define AR5K_WOW_PAT_DATA_1_4_V 0x00000100 /* Pattern 1, 4 value */
471#define AR5K_WOW_PAT_DATA_2_5_V 0x00010000 /* Pattern 2, 5 value */
472#define AR5K_WOW_PAT_DATA_0_3_M 0x01000000 /* Pattern 0, 3 mask */
473#define AR5K_WOW_PAT_DATA_1_4_M 0x04000000 /* Pattern 1, 4 mask */
474#define AR5K_WOW_PAT_DATA_2_5_M 0x10000000 /* Pattern 2, 5 mask */
434 475
435/* 476/*
436 * Decompression configuration registers [5212+] 477 * Decompression configuration registers [5212+]
437 */ 478 */
438#define AR5K_DCCFG 0x0420 479#define AR5K_DCCFG 0x0420 /* Register Address */
480#define AR5K_DCCFG_GLOBAL_EN 0x00000001 /* Enable decompression on all queues */
481#define AR5K_DCCFG_BYPASS_EN 0x00000002 /* Bypass decompression */
482#define AR5K_DCCFG_BCAST_EN 0x00000004 /* Enable decompression for bcast frames */
483#define AR5K_DCCFG_MCAST_EN 0x00000008 /* Enable decompression for mcast frames */
439 484
440/* 485/*
441 * Compression configuration registers [5212+] 486 * Compression configuration registers [5212+]
442 */ 487 */
443#define AR5K_CCFG 0x0600 488#define AR5K_CCFG 0x0600 /* Register Address */
444#define AR5K_CCFG_CUP 0x0604 489#define AR5K_CCFG_WINDOW_SIZE 0x00000007 /* Compression window size */
490#define AR5K_CCFG_CPC_EN 0x00000008 /* Enable performance counters */
491
492#define AR5K_CCFG_CCU 0x0604 /* Register Address */
493#define AR5K_CCFG_CCU_CUP_EN 0x00000001 /* CCU Catchup enable */
494#define AR5K_CCFG_CCU_CREDIT 0x00000002 /* CCU Credit (field) */
495#define AR5K_CCFG_CCU_CD_THRES 0x00000080 /* CCU Cyc(lic?) debt threshold (field) */
496#define AR5K_CCFG_CCU_CUP_LCNT 0x00010000 /* CCU Catchup lit(?) count */
497#define AR5K_CCFG_CCU_INIT 0x00100200 /* Initial value during reset */
445 498
446/* 499/*
447 * Compression performance counter registers [5212+] 500 * Compression performance counter registers [5212+]
@@ -450,7 +503,7 @@
450#define AR5K_CPC1 0x0614 /* Compression performance counter 1*/ 503#define AR5K_CPC1 0x0614 /* Compression performance counter 1*/
451#define AR5K_CPC2 0x0618 /* Compression performance counter 2 */ 504#define AR5K_CPC2 0x0618 /* Compression performance counter 2 */
452#define AR5K_CPC3 0x061c /* Compression performance counter 3 */ 505#define AR5K_CPC3 0x061c /* Compression performance counter 3 */
453#define AR5K_CPCORN 0x0620 /* Compression performance overrun (?) */ 506#define AR5K_CPCOVF 0x0620 /* Compression performance overflow */
454 507
455 508
456/* 509/*
@@ -466,8 +519,6 @@
466 * set/clear, which contain status for all queues (we shift by 1 for each 519 * set/clear, which contain status for all queues (we shift by 1 for each
467 * queue). To access these registers easily we define some macros here 520 * queue). To access these registers easily we define some macros here
468 * that are used inside HAL. For more infos check out *_tx_queue functs. 521 * that are used inside HAL. For more infos check out *_tx_queue functs.
469 *
470 * TODO: Boundary checking on macros (here?)
471 */ 522 */
472 523
473/* 524/*
@@ -513,7 +564,6 @@
513#define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */ 564#define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */
514#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */ 565#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */
515#define AR5K_QCU_RDYTIMECFG_INTVAL_S 0 566#define AR5K_QCU_RDYTIMECFG_INTVAL_S 0
516#define AR5K_QCU_RDYTIMECFG_DURATION 0x00ffffff /* Ready time duration mask */
517#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */ 567#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */
518#define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q) 568#define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)
519 569
@@ -534,19 +584,20 @@
534 */ 584 */
535#define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */ 585#define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */
536#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ 586#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */
537#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ 587#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */
538#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ 588#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */
539#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated (?) */ 589#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated (?) */
540#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* Time gated (?) */ 590#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* Time gated (?) */
541#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated (?) */ 591#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated (?) */
542#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ 592#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */
543#define AR5K_QCU_MISC_CBREXP 0x00000020 /* CBR expired (normal queue) */ 593#define AR5K_QCU_MISC_CBREXP 0x00000020 /* CBR expired (normal queue) */
544#define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /* CBR expired (beacon queue) */ 594#define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /* CBR expired (beacon queue) */
545#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Beacons enabled */ 595#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */
546#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR threshold enabled (?) */ 596#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR threshold enabled */
547#define AR5K_QCU_MISC_TXE 0x00000200 /* TXE reset when RDYTIME enalbed (?) */ 597#define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME enalbed */
548#define AR5K_QCU_MISC_CBR 0x00000400 /* CBR threshold reset (?) */ 598#define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */
549#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU reset (?) */ 599#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */
600#define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */
550#define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q) 601#define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)
551 602
552 603
@@ -555,7 +606,7 @@
555 */ 606 */
556#define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */ 607#define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */
557#define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */ 608#define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */
558#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter (?) */ 609#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter */
559#define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q) 610#define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)
560 611
561/* 612/*
@@ -569,9 +620,11 @@
569 */ 620 */
570#define AR5K_QCU_CBB_SELECT 0x0b00 621#define AR5K_QCU_CBB_SELECT 0x0b00
571#define AR5K_QCU_CBB_ADDR 0x0b04 622#define AR5K_QCU_CBB_ADDR 0x0b04
623#define AR5K_QCU_CBB_ADDR_S 9
572 624
573/* 625/*
574 * QCU compression buffer configuration register [5212+] 626 * QCU compression buffer configuration register [5212+]
627 * (buffer size)
575 */ 628 */
576#define AR5K_QCU_CBCFG 0x0b08 629#define AR5K_QCU_CBCFG 0x0b08
577 630
@@ -652,80 +705,100 @@
652 * No lockout means there is no special handling. 705 * No lockout means there is no special handling.
653 */ 706 */
654#define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ 707#define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */
655#define AR5K_DCU_MISC_BACKOFF 0x000007ff /* Mask for backoff setting (?) */ 708#define AR5K_DCU_MISC_BACKOFF 0x000007ff /* Mask for backoff threshold */
656#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ 709#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */
657#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll (?) */ 710#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */
658#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff (?) */ 711#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */
659#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch (?) */ 712#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */
660#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ 713#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */
661#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 714#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0
662#define AR5K_DCU_MISC_VIRTCOL_MODIFIED 1 715#define AR5K_DCU_MISC_VIRTCOL_MODIFIED 1
663#define AR5K_DCU_MISC_VIRTCOL_IGNORE 2 716#define AR5K_DCU_MISC_VIRTCOL_IGNORE 2
664#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Beacon enable (?) */ 717#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */
665#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ 718#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */
666#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 719#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17
667#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ 720#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */
668#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ 721#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */
669#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ 722#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */
670#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 723#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 /* Ignore Arbiter lockout */
671#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment (?) */ 724#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment */
672#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff (?) */ 725#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */
673#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision policy (?) */ 726#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision cw policy */
674#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 727#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS policy (?) */
675#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ 728#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */
676#define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) 729#define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)
677 730
678/* 731/*
679 * DCU frame sequence number registers 732 * DCU frame sequence number registers
680 */ 733 */
681#define AR5K_DCU_SEQNUM_BASE 0x1140 734#define AR5K_DCU_SEQNUM_BASE 0x1140
682#define AR5K_DCU_SEQNUM_M 0x00000fff 735#define AR5K_DCU_SEQNUM_M 0x00000fff
683#define AR5K_QUEUE_DFS_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q) 736#define AR5K_QUEUE_DFS_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
684 737
685/* 738/*
686 * DCU global IFS SIFS registers 739 * DCU global IFS SIFS register
687 */ 740 */
688#define AR5K_DCU_GBL_IFS_SIFS 0x1030 741#define AR5K_DCU_GBL_IFS_SIFS 0x1030
689#define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff 742#define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff
690 743
691/* 744/*
692 * DCU global IFS slot interval registers 745 * DCU global IFS slot interval register
693 */ 746 */
694#define AR5K_DCU_GBL_IFS_SLOT 0x1070 747#define AR5K_DCU_GBL_IFS_SLOT 0x1070
695#define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff 748#define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff
696 749
697/* 750/*
698 * DCU global IFS EIFS registers 751 * DCU global IFS EIFS register
699 */ 752 */
700#define AR5K_DCU_GBL_IFS_EIFS 0x10b0 753#define AR5K_DCU_GBL_IFS_EIFS 0x10b0
701#define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff 754#define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff
702 755
703/* 756/*
704 * DCU global IFS misc registers 757 * DCU global IFS misc register
758 *
759 * LFSR stands for Linear Feedback Shift Register
760 * and it's used for generating pseudo-random
761 * number sequences.
762 *
763 * (If i understand corectly, random numbers are
764 * used for idle sensing -multiplied with cwmin/max etc-)
705 */ 765 */
706#define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ 766#define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */
707#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 767#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 /* LFSR Slice Select */
708#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode (?) */ 768#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */
709#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask (?) */ 769#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */
710#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 770#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */
711#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 771#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */
772#define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFC cnt reset policy (?) */
773#define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */
774#define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */
712 775
713/* 776/*
714 * DCU frame prefetch control register 777 * DCU frame prefetch control register
715 */ 778 */
716#define AR5K_DCU_FP 0x1230 779#define AR5K_DCU_FP 0x1230 /* Register Address */
780#define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */
781#define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */
782#define AR5K_DCU_FP_BURST_DCU_EN 0x00000020 /* Enable burst prefetch on DCU (?) */
717 783
718/* 784/*
719 * DCU transmit pause control/status register 785 * DCU transmit pause control/status register
720 */ 786 */
721#define AR5K_DCU_TXP 0x1270 /* Register Address */ 787#define AR5K_DCU_TXP 0x1270 /* Register Address */
722#define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask (?) */ 788#define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask */
723#define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status (?) */ 789#define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status */
790
791/*
792 * DCU transmit filter table 0 (32 entries)
793 */
794#define AR5K_DCU_TX_FILTER_0_BASE 0x1038
795#define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
724 796
725/* 797/*
726 * DCU transmit filter register 798 * DCU transmit filter table 1 (16 entries)
727 */ 799 */
728#define AR5K_DCU_TX_FILTER 0x1038 800#define AR5K_DCU_TX_FILTER_1_BASE 0x103c
801#define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + ((_n - 32) * 64))
729 802
730/* 803/*
731 * DCU clear transmit filter register 804 * DCU clear transmit filter register
@@ -739,9 +812,6 @@
739 812
740/* 813/*
741 * Reset control register 814 * Reset control register
742 *
743 * 4 and 8 are not used in 5211/5212 and
744 * 2 means "baseband reset" on 5211/5212.
745 */ 815 */
746#define AR5K_RESET_CTL 0x4000 /* Register Address */ 816#define AR5K_RESET_CTL 0x4000 /* Register Address */
747#define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */ 817#define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */
@@ -765,6 +835,7 @@
765#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ 835#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */
766#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 836#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000
767#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ 837#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */
838/* more bits */
768 839
769/* 840/*
770 * Interrupt pending register 841 * Interrupt pending register
@@ -776,13 +847,14 @@
776 * Sleep force register 847 * Sleep force register
777 */ 848 */
778#define AR5K_SFR 0x400c 849#define AR5K_SFR 0x400c
779#define AR5K_SFR_M 0x00000001 850#define AR5K_SFR_EN 0x00000001
780 851
781/* 852/*
782 * PCI configuration register 853 * PCI configuration register
783 */ 854 */
784#define AR5K_PCICFG 0x4010 /* Register Address */ 855#define AR5K_PCICFG 0x4010 /* Register Address */
785#define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ 856#define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */
857#define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock (?) */
786#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ 858#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */
787#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ 859#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */
788#define AR5K_PCICFG_EESIZE_S 3 860#define AR5K_PCICFG_EESIZE_S 3
@@ -798,19 +870,21 @@
798#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix (?) */ 870#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix (?) */
799#define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep (?) */ 871#define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep (?) */
800#define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ 872#define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */
801#define AR5K_PCICFG_SL_INPEN 0x00002800 /* Sleep even whith pending interrupts (?) */ 873#define AR5K_PCICFG_UNK 0x00001000 /* Passed on some parts durring attach (?) */
874#define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even whith pending interrupts (?) */
802#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ 875#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */
803#define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ 876#define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */
804#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ 877#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */
805#define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ 878#define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */
806#define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ 879#define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */
807#define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ 880#define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */
808#define AR5K_PCICFG_LEDBLINK 0x00700000 881#define AR5K_PCICFG_LEDBLINK 0x00700000 /* Led blink rate */
809#define AR5K_PCICFG_LEDBLINK_S 20 882#define AR5K_PCICFG_LEDBLINK_S 20
810#define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slow led blink rate (?) [5211+] */ 883#define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slowest led blink rate [5211+] */
811#define AR5K_PCICFG_LEDSTATE \ 884#define AR5K_PCICFG_LEDSTATE \
812 (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ 885 (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \
813 AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) 886 AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
887#define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate (field) */
814 888
815/* 889/*
816 * "General Purpose Input/Output" (GPIO) control register 890 * "General Purpose Input/Output" (GPIO) control register
@@ -947,7 +1021,7 @@
947#define AR5K_EEPROM_VERSION_4_4 0x4004 1021#define AR5K_EEPROM_VERSION_4_4 0x4004
948#define AR5K_EEPROM_VERSION_4_5 0x4005 1022#define AR5K_EEPROM_VERSION_4_5 0x4005
949#define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */ 1023#define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */
950#define AR5K_EEPROM_VERSION_4_7 0x3007 1024#define AR5K_EEPROM_VERSION_4_7 0x4007
951 1025
952#define AR5K_EEPROM_MODE_11A 0 1026#define AR5K_EEPROM_MODE_11A 0
953#define AR5K_EEPROM_MODE_11B 1 1027#define AR5K_EEPROM_MODE_11B 1
@@ -1023,10 +1097,14 @@
1023#define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */ 1097#define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */
1024 1098
1025/* 1099/*
1026 * EEPROM config register (?) 1100 * EEPROM config register
1027 */ 1101 */
1028#define AR5K_EEPROM_CFG 0x6010 1102#define AR5K_EEPROM_CFG 0x6010 /* Register Addres */
1029 1103#define AR5K_EEPROM_CFG_SIZE_OVR 0x00000001
1104#define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */
1105#define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */
1106#define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protectio key */
1107#define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */
1030 1108
1031 1109
1032/* 1110/*
@@ -1050,7 +1128,7 @@
1050#define AR5K_STA_ID1 0x8004 /* Register Address */ 1128#define AR5K_STA_ID1 0x8004 /* Register Address */
1051#define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */ 1129#define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */
1052#define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */ 1130#define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */
1053#define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting (?) */ 1131#define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting */
1054#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */ 1132#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */
1055#define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */ 1133#define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */
1056#define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */ 1134#define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */
@@ -1059,9 +1137,13 @@
1059 AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) 1137 AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)
1060#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */ 1138#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */
1061#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ 1139#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */
1062#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS (?) */ 1140#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */
1063#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS (?) */ 1141#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS */
1064#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate (for ACK/CTS ?) [5211+] */ 1142#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate (for ACK/CTS ?) [5211+] */
1143#define AR5K_STA_ID1_SELF_GEN_SECTORE 0x04000000 /* Self generate sectore (?) */
1144#define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */
1145#define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Keysearch mode (?) */
1146#define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */
1065 1147
1066/* 1148/*
1067 * First BSSID register (MAC address, lower 32bits) 1149 * First BSSID register (MAC address, lower 32bits)
@@ -1117,7 +1199,7 @@
1117 * 1199 *
1118 * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) 1200 * Retry limit register for 5210 (no QCU/DCU so it's done in PCU)
1119 */ 1201 */
1120#define AR5K_NODCU_RETRY_LMT 0x801c /*Register Address */ 1202#define AR5K_NODCU_RETRY_LMT 0x801c /* Register Address */
1121#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ 1203#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */
1122#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 1204#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0
1123#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */ 1205#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */
@@ -1136,9 +1218,9 @@
1136#define AR5K_USEC_5211 0x801c /* Register Address [5211+] */ 1218#define AR5K_USEC_5211 0x801c /* Register Address [5211+] */
1137#define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \ 1219#define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \
1138 AR5K_USEC_5210 : AR5K_USEC_5211) 1220 AR5K_USEC_5210 : AR5K_USEC_5211)
1139#define AR5K_USEC_1 0x0000007f 1221#define AR5K_USEC_1 0x0000007f /* clock cycles for 1us */
1140#define AR5K_USEC_1_S 0 1222#define AR5K_USEC_1_S 0
1141#define AR5K_USEC_32 0x00003f80 1223#define AR5K_USEC_32 0x00003f80 /* clock cycles for 1us while on 32Mhz clock */
1142#define AR5K_USEC_32_S 7 1224#define AR5K_USEC_32_S 7
1143#define AR5K_USEC_TX_LATENCY_5211 0x007fc000 1225#define AR5K_USEC_TX_LATENCY_5211 0x007fc000
1144#define AR5K_USEC_TX_LATENCY_5211_S 14 1226#define AR5K_USEC_TX_LATENCY_5211_S 14
@@ -1152,16 +1234,16 @@
1152/* 1234/*
1153 * PCU beacon control register 1235 * PCU beacon control register
1154 */ 1236 */
1155#define AR5K_BEACON_5210 0x8024 1237#define AR5K_BEACON_5210 0x8024 /*Register Address [5210] */
1156#define AR5K_BEACON_5211 0x8020 1238#define AR5K_BEACON_5211 0x8020 /*Register Address [5211+] */
1157#define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \ 1239#define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \
1158 AR5K_BEACON_5210 : AR5K_BEACON_5211) 1240 AR5K_BEACON_5210 : AR5K_BEACON_5211)
1159#define AR5K_BEACON_PERIOD 0x0000ffff 1241#define AR5K_BEACON_PERIOD 0x0000ffff /* Mask for beacon period */
1160#define AR5K_BEACON_PERIOD_S 0 1242#define AR5K_BEACON_PERIOD_S 0
1161#define AR5K_BEACON_TIM 0x007f0000 1243#define AR5K_BEACON_TIM 0x007f0000 /* Mask for TIM offset */
1162#define AR5K_BEACON_TIM_S 16 1244#define AR5K_BEACON_TIM_S 16
1163#define AR5K_BEACON_ENABLE 0x00800000 1245#define AR5K_BEACON_ENABLE 0x00800000 /* Enable beacons */
1164#define AR5K_BEACON_RESET_TSF 0x01000000 1246#define AR5K_BEACON_RESET_TSF 0x01000000 /* Force TSF reset */
1165 1247
1166/* 1248/*
1167 * CFP period register 1249 * CFP period register
@@ -1234,7 +1316,6 @@
1234 1316
1235/* 1317/*
1236 * Receive filter register 1318 * Receive filter register
1237 * TODO: Get these out of ar5xxx.h on ath5k
1238 */ 1319 */
1239#define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */ 1320#define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */
1240#define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ 1321#define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */
@@ -1307,11 +1388,11 @@
1307#define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ 1388#define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */
1308#define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \ 1389#define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \
1309 AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) 1390 AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211)
1310#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 1391#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 /* Disable ACKs if WEP key is invalid */
1311#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs (?) */ 1392#define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs */
1312#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs (?) */ 1393#define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs */
1313#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption (?) */ 1394#define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption */
1314#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption (?) */ 1395#define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption */
1315#define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */ 1396#define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */
1316#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */ 1397#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */
1317#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 1398#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020
@@ -1329,13 +1410,13 @@
1329#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 1410#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100
1330#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ 1411#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \
1331 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) 1412 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
1332#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /* Scrambler seed (?) */ 1413#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /* Enable scrambler seed */
1333#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 1414#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400
1334#define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ 1415#define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \
1335 AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) 1416 AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211)
1336#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ 1417#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */
1337#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */ 1418#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */
1338#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask (?) */ 1419#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask */
1339#define AR5K_DIAG_SW_SCRAM_SEED_S 10 1420#define AR5K_DIAG_SW_SCRAM_SEED_S 10
1340#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ 1421#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */
1341#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 1422#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000
@@ -1344,6 +1425,7 @@
1344 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) 1425 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
1345#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 1426#define AR5K_DIAG_SW_OBSPT_M 0x000c0000
1346#define AR5K_DIAG_SW_OBSPT_S 18 1427#define AR5K_DIAG_SW_OBSPT_S 18
1428/* more bits */
1347 1429
1348/* 1430/*
1349 * TSF (clock) register (lower 32 bits) 1431 * TSF (clock) register (lower 32 bits)
@@ -1369,15 +1451,34 @@
1369/* 1451/*
1370 * ADDAC test register [5211+] 1452 * ADDAC test register [5211+]
1371 */ 1453 */
1372#define AR5K_ADDAC_TEST 0x8054 1454#define AR5K_ADDAC_TEST 0x8054 /* Register Address */
1373#define AR5K_ADDAC_TEST_TXCONT 0x00000001 1455#define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */
1456#define AR5K_ADDAC_TEST_TST_MODE 0x00000002 /* Test mode */
1457#define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */
1458#define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008 /* Loop length (field) */
1459#define AR5K_ADDAC_TEST_USE_U8 0x00004000 /* Use upper 8 bits */
1460#define AR5K_ADDAC_TEST_MSB 0x00008000 /* State of MSB */
1461#define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000 /* Trigger select */
1462#define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000 /* Trigger polarity */
1463#define AR5K_ADDAC_TEST_RXCONT 0x00040000 /* Continuous capture */
1464#define AR5K_ADDAC_TEST_CAPTURE 0x00080000 /* Begin capture */
1465#define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* Test ARM (Adaptive Radio Mode ?) */
1374 1466
1375/* 1467/*
1376 * Default antenna register [5211+] 1468 * Default antenna register [5211+]
1377 */ 1469 */
1378#define AR5K_DEFAULT_ANTENNA 0x8058 1470#define AR5K_DEFAULT_ANTENNA 0x8058
1379 1471
1472/*
1473 * Frame control QoS mask register (?) [5211+]
1474 * (FC_QOS_MASK)
1475 */
1476#define AR5K_FRAME_CTL_QOSM 0x805c
1380 1477
1478/*
1479 * Seq mask register (?) [5211+]
1480 */
1481#define AR5K_SEQ_MASK 0x8060
1381 1482
1382/* 1483/*
1383 * Retry count register [5210] 1484 * Retry count register [5210]
@@ -1449,124 +1550,242 @@
1449/* 1550/*
1450 * XR (eXtended Range) mode register 1551 * XR (eXtended Range) mode register
1451 */ 1552 */
1452#define AR5K_XRMODE 0x80c0 1553#define AR5K_XRMODE 0x80c0 /* Register Address */
1453#define AR5K_XRMODE_POLL_TYPE_M 0x0000003f 1554#define AR5K_XRMODE_POLL_TYPE_M 0x0000003f /* Mask for Poll type (?) */
1454#define AR5K_XRMODE_POLL_TYPE_S 0 1555#define AR5K_XRMODE_POLL_TYPE_S 0
1455#define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c 1556#define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c /* Mask for Poll subtype (?) */
1456#define AR5K_XRMODE_POLL_SUBTYPE_S 2 1557#define AR5K_XRMODE_POLL_SUBTYPE_S 2
1457#define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 1558#define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 /* Wait for poll */
1458#define AR5K_XRMODE_SIFS_DELAY 0x000fff00 1559#define AR5K_XRMODE_SIFS_DELAY 0x000fff00 /* Mask for SIFS delay */
1459#define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 1560#define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 /* Mask for frame hold (?) */
1460#define AR5K_XRMODE_FRAME_HOLD_S 20 1561#define AR5K_XRMODE_FRAME_HOLD_S 20
1461 1562
1462/* 1563/*
1463 * XR delay register 1564 * XR delay register
1464 */ 1565 */
1465#define AR5K_XRDELAY 0x80c4 1566#define AR5K_XRDELAY 0x80c4 /* Register Address */
1466#define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff 1567#define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff /* Mask for slot delay */
1467#define AR5K_XRDELAY_SLOT_DELAY_S 0 1568#define AR5K_XRDELAY_SLOT_DELAY_S 0
1468#define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 1569#define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 /* Mask for CHIRP data delay */
1469#define AR5K_XRDELAY_CHIRP_DELAY_S 16 1570#define AR5K_XRDELAY_CHIRP_DELAY_S 16
1470 1571
1471/* 1572/*
1472 * XR timeout register 1573 * XR timeout register
1473 */ 1574 */
1474#define AR5K_XRTIMEOUT 0x80c8 1575#define AR5K_XRTIMEOUT 0x80c8 /* Register Address */
1475#define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff 1576#define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff /* Mask for CHIRP timeout */
1476#define AR5K_XRTIMEOUT_CHIRP_S 0 1577#define AR5K_XRTIMEOUT_CHIRP_S 0
1477#define AR5K_XRTIMEOUT_POLL_M 0xffff0000 1578#define AR5K_XRTIMEOUT_POLL_M 0xffff0000 /* Mask for Poll timeout */
1478#define AR5K_XRTIMEOUT_POLL_S 16 1579#define AR5K_XRTIMEOUT_POLL_S 16
1479 1580
1480/* 1581/*
1481 * XR chirp register 1582 * XR chirp register
1482 */ 1583 */
1483#define AR5K_XRCHIRP 0x80cc 1584#define AR5K_XRCHIRP 0x80cc /* Register Address */
1484#define AR5K_XRCHIRP_SEND 0x00000001 1585#define AR5K_XRCHIRP_SEND 0x00000001 /* Send CHIRP */
1485#define AR5K_XRCHIRP_GAP 0xffff0000 1586#define AR5K_XRCHIRP_GAP 0xffff0000 /* Mask for CHIRP gap (?) */
1486 1587
1487/* 1588/*
1488 * XR stomp register 1589 * XR stomp register
1489 */ 1590 */
1490#define AR5K_XRSTOMP 0x80d0 1591#define AR5K_XRSTOMP 0x80d0 /* Register Address */
1491#define AR5K_XRSTOMP_TX 0x00000001 1592#define AR5K_XRSTOMP_TX 0x00000001 /* Stomp Tx (?) */
1492#define AR5K_XRSTOMP_RX_ABORT 0x00000002 1593#define AR5K_XRSTOMP_RX 0x00000002 /* Stomp Rx (?) */
1493#define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 1594#define AR5K_XRSTOMP_TX_RSSI 0x00000004 /* Stomp Tx RSSI (?) */
1595#define AR5K_XRSTOMP_TX_BSSID 0x00000008 /* Stomp Tx BSSID (?) */
1596#define AR5K_XRSTOMP_DATA 0x00000010 /* Stomp data (?)*/
1597#define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 /* Mask for XR RSSI threshold */
1494 1598
1495/* 1599/*
1496 * First enhanced sleep register 1600 * First enhanced sleep register
1497 */ 1601 */
1498#define AR5K_SLEEP0 0x80d4 1602#define AR5K_SLEEP0 0x80d4 /* Register Address */
1499#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff 1603#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff /* Mask for next DTIM (?) */
1500#define AR5K_SLEEP0_NEXT_DTIM_S 0 1604#define AR5K_SLEEP0_NEXT_DTIM_S 0
1501#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 1605#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 /* Assume DTIM */
1502#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 1606#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 /* Enable enchanced sleep control */
1503#define AR5K_SLEEP0_CABTO 0xff000000 1607#define AR5K_SLEEP0_CABTO 0xff000000 /* Mask for CAB Time Out */
1504#define AR5K_SLEEP0_CABTO_S 24 1608#define AR5K_SLEEP0_CABTO_S 24
1505 1609
1506/* 1610/*
1507 * Second enhanced sleep register 1611 * Second enhanced sleep register
1508 */ 1612 */
1509#define AR5K_SLEEP1 0x80d8 1613#define AR5K_SLEEP1 0x80d8 /* Register Address */
1510#define AR5K_SLEEP1_NEXT_TIM 0x0007ffff 1614#define AR5K_SLEEP1_NEXT_TIM 0x0007ffff /* Mask for next TIM (?) */
1511#define AR5K_SLEEP1_NEXT_TIM_S 0 1615#define AR5K_SLEEP1_NEXT_TIM_S 0
1512#define AR5K_SLEEP1_BEACON_TO 0xff000000 1616#define AR5K_SLEEP1_BEACON_TO 0xff000000 /* Mask for Beacon Time Out */
1513#define AR5K_SLEEP1_BEACON_TO_S 24 1617#define AR5K_SLEEP1_BEACON_TO_S 24
1514 1618
1515/* 1619/*
1516 * Third enhanced sleep register 1620 * Third enhanced sleep register
1517 */ 1621 */
1518#define AR5K_SLEEP2 0x80dc 1622#define AR5K_SLEEP2 0x80dc /* Register Address */
1519#define AR5K_SLEEP2_TIM_PER 0x0000ffff 1623#define AR5K_SLEEP2_TIM_PER 0x0000ffff /* Mask for TIM period (?) */
1520#define AR5K_SLEEP2_TIM_PER_S 0 1624#define AR5K_SLEEP2_TIM_PER_S 0
1521#define AR5K_SLEEP2_DTIM_PER 0xffff0000 1625#define AR5K_SLEEP2_DTIM_PER 0xffff0000 /* Mask for DTIM period (?) */
1522#define AR5K_SLEEP2_DTIM_PER_S 16 1626#define AR5K_SLEEP2_DTIM_PER_S 16
1523 1627
1524/* 1628/*
1525 * BSSID mask registers 1629 * BSSID mask registers
1526 */ 1630 */
1527#define AR5K_BSS_IDM0 0x80e0 1631#define AR5K_BSS_IDM0 0x80e0 /* Upper bits */
1528#define AR5K_BSS_IDM1 0x80e4 1632#define AR5K_BSS_IDM1 0x80e4 /* Lower bits */
1529 1633
1530/* 1634/*
1531 * TX power control (TPC) register 1635 * TX power control (TPC) register
1636 *
1637 * XXX: PCDAC steps (0.5dbm) or DBM ?
1638 *
1639 * XXX: Mask changes for newer chips to 7f
1640 * like tx power table ?
1532 */ 1641 */
1533#define AR5K_TXPC 0x80e8 1642#define AR5K_TXPC 0x80e8 /* Register Address */
1534#define AR5K_TXPC_ACK_M 0x0000003f 1643#define AR5K_TXPC_ACK_M 0x0000003f /* Mask for ACK tx power */
1535#define AR5K_TXPC_ACK_S 0 1644#define AR5K_TXPC_ACK_S 0
1536#define AR5K_TXPC_CTS_M 0x00003f00 1645#define AR5K_TXPC_CTS_M 0x00003f00 /* Mask for CTS tx power */
1537#define AR5K_TXPC_CTS_S 8 1646#define AR5K_TXPC_CTS_S 8
1538#define AR5K_TXPC_CHIRP_M 0x003f0000 1647#define AR5K_TXPC_CHIRP_M 0x003f0000 /* Mask for CHIRP tx power */
1539#define AR5K_TXPC_CHIRP_S 22 1648#define AR5K_TXPC_CHIRP_S 22
1540 1649
1541/* 1650/*
1542 * Profile count registers 1651 * Profile count registers
1543 */ 1652 */
1544#define AR5K_PROFCNT_TX 0x80ec 1653#define AR5K_PROFCNT_TX 0x80ec /* Tx count */
1545#define AR5K_PROFCNT_RX 0x80f0 1654#define AR5K_PROFCNT_RX 0x80f0 /* Rx count */
1546#define AR5K_PROFCNT_RXCLR 0x80f4 1655#define AR5K_PROFCNT_RXCLR 0x80f4 /* Clear Rx count */
1547#define AR5K_PROFCNT_CYCLE 0x80f8 1656#define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle count (?) */
1657
1658/*
1659 * Quiet (period) control registers (?)
1660 */
1661#define AR5K_QUIET_CTL1 0x80fc /* Register Address */
1662#define AR5K_QUIET_CTL1_NEXT_QT 0x0000ffff /* Mask for next quiet (period?) (?) */
1663#define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet (period?) */
1664#define AR5K_QUIET_CTL2 0x8100 /* Register Address */
1665#define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period (?) */
1666#define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet duration (?) */
1548 1667
1549/* 1668/*
1550 * TSF parameter register 1669 * TSF parameter register
1551 */ 1670 */
1552#define AR5K_TSF_PARM 0x8104 1671#define AR5K_TSF_PARM 0x8104 /* Register Address */
1553#define AR5K_TSF_PARM_INC_M 0x000000ff 1672#define AR5K_TSF_PARM_INC_M 0x000000ff /* Mask for TSF increment */
1554#define AR5K_TSF_PARM_INC_S 0 1673#define AR5K_TSF_PARM_INC_S 0
1555 1674
1556/* 1675/*
1676 * QoS register (?)
1677 */
1678#define AR5K_QOS 0x8108 /* Register Address */
1679#define AR5K_QOS_NOACK_2BIT_VALUES 0x00000000 /* (field) */
1680#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000020 /* (field) */
1681#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000080 /* (field) */
1682
1683/*
1557 * PHY error filter register 1684 * PHY error filter register
1558 */ 1685 */
1559#define AR5K_PHY_ERR_FIL 0x810c 1686#define AR5K_PHY_ERR_FIL 0x810c
1560#define AR5K_PHY_ERR_FIL_RADAR 0x00000020 1687#define AR5K_PHY_ERR_FIL_RADAR 0x00000020 /* Radar signal */
1561#define AR5K_PHY_ERR_FIL_OFDM 0x00020000 1688#define AR5K_PHY_ERR_FIL_OFDM 0x00020000 /* OFDM false detect (ANI) */
1562#define AR5K_PHY_ERR_FIL_CCK 0x02000000 1689#define AR5K_PHY_ERR_FIL_CCK 0x02000000 /* CCK false detect (ANI) */
1690
1691/*
1692 * XR latency register
1693 */
1694#define AR5K_XRLAT_TX 0x8110
1563 1695
1564/* 1696/*
1565 * Rate duration register 1697 * ACK SIFS register
1698 */
1699#define AR5K_ACKSIFS 0x8114 /* Register Address */
1700#define AR5K_ACKSIFS_INC 0x00000000 /* ACK SIFS Increment (field) */
1701
1702/*
1703 * MIC QoS control register (?)
1704 */
1705#define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */
1706#define AR5K_MIC_QOS_CTL_0 0x00000001 /* MIC QoS control 0 (?) */
1707#define AR5K_MIC_QOS_CTL_1 0x00000004 /* MIC QoS control 1 (?) */
1708#define AR5K_MIC_QOS_CTL_2 0x00000010 /* MIC QoS control 2 (?) */
1709#define AR5K_MIC_QOS_CTL_3 0x00000040 /* MIC QoS control 3 (?) */
1710#define AR5K_MIC_QOS_CTL_4 0x00000100 /* MIC QoS control 4 (?) */
1711#define AR5K_MIC_QOS_CTL_5 0x00000400 /* MIC QoS control 5 (?) */
1712#define AR5K_MIC_QOS_CTL_6 0x00001000 /* MIC QoS control 6 (?) */
1713#define AR5K_MIC_QOS_CTL_7 0x00004000 /* MIC QoS control 7 (?) */
1714#define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */
1715
1716/*
1717 * MIC QoS select register (?)
1718 */
1719#define AR5K_MIC_QOS_SEL 0x811c
1720#define AR5K_MIC_QOS_SEL_0 0x00000001
1721#define AR5K_MIC_QOS_SEL_1 0x00000010
1722#define AR5K_MIC_QOS_SEL_2 0x00000100
1723#define AR5K_MIC_QOS_SEL_3 0x00001000
1724#define AR5K_MIC_QOS_SEL_4 0x00010000
1725#define AR5K_MIC_QOS_SEL_5 0x00100000
1726#define AR5K_MIC_QOS_SEL_6 0x01000000
1727#define AR5K_MIC_QOS_SEL_7 0x10000000
1728
1729/*
1730 * Misc mode control register (?)
1731 */
1732#define AR5K_MISC_MODE 0x8120 /* Register Address */
1733#define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001 /* Force BSSID match */
1734#define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002 /* ACK SIFS memory (?) */
1735/* more bits */
1736
1737/*
1738 * OFDM Filter counter
1739 */
1740#define AR5K_OFDM_FIL_CNT 0x8124
1741
1742/*
1743 * CCK Filter counter
1744 */
1745#define AR5K_CCK_FIL_CNT 0x8128
1746
1747/*
1748 * PHY Error Counters (?)
1749 */
1750#define AR5K_PHYERR_CNT1 0x812c
1751#define AR5K_PHYERR_CNT1_MASK 0x8130
1752
1753#define AR5K_PHYERR_CNT2 0x8134
1754#define AR5K_PHYERR_CNT2_MASK 0x8138
1755
1756/*
1757 * TSF Threshold register (?)
1758 */
1759#define AR5K_TSF_THRES 0x813c
1760
1761/*
1762 * Rate -> ACK SIFS mapping table (32 entries)
1763 */
1764#define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */
1765#define AR5K_RATE_ACKSIFS(_n) (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2))
1766#define AR5K_RATE_ACKSIFS_NORMAL 0x00000001 /* Normal SIFS (field) */
1767#define AR5K_RATE_ACKSIFS_TURBO 0x00000400 /* Turbo SIFS (field) */
1768
1769/*
1770 * Rate -> duration mapping table (32 entries)
1566 */ 1771 */
1567#define AR5K_RATE_DUR_BASE 0x8700 1772#define AR5K_RATE_DUR_BASE 0x8700
1568#define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2)) 1773#define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2))
1569 1774
1775/*
1776 * Rate -> db mapping table
1777 * (8 entries, each one has 4 8bit fields)
1778 */
1779#define AR5K_RATE2DB_BASE 0x87c0
1780#define AR5K_RATE2DB(_n) (AR5K_RATE2DB_BASE + ((_n) << 2))
1781
1782/*
1783 * db -> Rate mapping table
1784 * (8 entries, each one has 4 8bit fields)
1785 */
1786#define AR5K_DB2RATE_BASE 0x87e0
1787#define AR5K_DB2RATE(_n) (AR5K_DB2RATE_BASE + ((_n) << 2))
1788
1570/*===5212 end===*/ 1789/*===5212 end===*/
1571 1790
1572/* 1791/*
@@ -1613,12 +1832,34 @@
1613/*===PHY REGISTERS===*/ 1832/*===PHY REGISTERS===*/
1614 1833
1615/* 1834/*
1616 * PHY register 1835 * PHY registers start
1617 */ 1836 */
1618#define AR5K_PHY_BASE 0x9800 1837#define AR5K_PHY_BASE 0x9800
1619#define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2)) 1838#define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2))
1620#define AR5K_PHY_SHIFT_2GHZ 0x00004007 1839
1621#define AR5K_PHY_SHIFT_5GHZ 0x00000007 1840/*
1841 * TST_2 (Misc config parameters)
1842 */
1843#define AR5K_PHY_TST2 0x9800 /* Register Address */
1844#define AR5K_PHY_TST2_TRIG_SEL 0x00000001 /* Trigger select (?) (field ?) */
1845#define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) (field ?) */
1846#define AR5K_PHY_TST2_CBUS_MODE 0x00000100 /* Cardbus mode (?) */
1847/* bit reserved */
1848#define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32Khz external) */
1849#define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */
1850#define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */
1851#define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */
1852#define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch) */
1853#define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */
1854#define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 /* 2GHz rx path is the 5GHz path inverted (?) */
1855#define AR5K_PHY_TST2_SLOW_CLK160 0x00020000 /* Slow CLK160 (?) */
1856#define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000 /* AGC OBS Select 3 (?) */
1857#define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000 /* BB OBS Select (field ?) */
1858#define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000 /* ADC OBS Select (field ?) */
1859#define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000 /* RX Clear Select (?) */
1860#define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000 /* Force AGC clear (?) */
1861#define AR5K_PHY_SHIFT_2GHZ 0x00004007 /* Used to access 2GHz radios */
1862#define AR5K_PHY_SHIFT_5GHZ 0x00000007 /* Used to access 5GHz radios (default) */
1622 1863
1623/* 1864/*
1624 * PHY frame control register [5110] /turbo mode register [5111+] 1865 * PHY frame control register [5110] /turbo mode register [5111+]
@@ -1630,18 +1871,21 @@
1630 * a "turbo mode register" for 5110. We treat this one as 1871 * a "turbo mode register" for 5110. We treat this one as
1631 * a frame control register for 5110 below. 1872 * a frame control register for 5110 below.
1632 */ 1873 */
1633#define AR5K_PHY_TURBO 0x9804 1874#define AR5K_PHY_TURBO 0x9804 /* Register Address */
1634#define AR5K_PHY_TURBO_MODE 0x00000001 1875#define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */
1635#define AR5K_PHY_TURBO_SHORT 0x00000002 1876#define AR5K_PHY_TURBO_SHORT 0x00000002 /* Short mode (20Mhz channels) (?) */
1636 1877
1637/* 1878/*
1638 * PHY agility command register 1879 * PHY agility command register
1880 * (aka TST_1)
1639 */ 1881 */
1640#define AR5K_PHY_AGC 0x9808 1882#define AR5K_PHY_AGC 0x9808 /* Register Address */
1641#define AR5K_PHY_AGC_DISABLE 0x08000000 1883#define AR5K_PHY_TST1 0x9808
1884#define AR5K_PHY_AGC_DISABLE 0x08000000 /* Disable AGC to A2 (?)*/
1885#define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */
1642 1886
1643/* 1887/*
1644 * PHY timing register [5112+] 1888 * PHY timing register 3 [5112+]
1645 */ 1889 */
1646#define AR5K_PHY_TIMING_3 0x9814 1890#define AR5K_PHY_TIMING_3 0x9814
1647#define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 1891#define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000
@@ -1657,26 +1901,81 @@
1657/* 1901/*
1658 * PHY activation register 1902 * PHY activation register
1659 */ 1903 */
1660#define AR5K_PHY_ACT 0x981c 1904#define AR5K_PHY_ACT 0x981c /* Register Address */
1661#define AR5K_PHY_ACT_ENABLE 0x00000001 1905#define AR5K_PHY_ACT_ENABLE 0x00000001 /* Activate PHY */
1662#define AR5K_PHY_ACT_DISABLE 0x00000002 1906#define AR5K_PHY_ACT_DISABLE 0x00000002 /* Deactivate PHY */
1907
1908/*
1909 * PHY RF control registers
1910 * (i think these are delay times,
1911 * these calibration values exist
1912 * in EEPROM)
1913 */
1914#define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */
1915#define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* Mask for TX frame to TX d(esc?) start */
1916
1917#define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */
1918#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000000f /* Mask for TX end to XLNA on */
1919
1920#define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */
1921#define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */
1922#define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100 /* TX frame to XPA B on (field) */
1923#define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000 /* TX end to XPA A off (field) */
1924#define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000 /* TX end to XPA B off (field) */
1925
1926/*
1927 * Pre-Amplifier control register
1928 * (XPA -> external pre-amplifier)
1929 */
1930#define AR5K_PHY_PA_CTL 0x9838 /* Register Address */
1931#define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001 /* XPA A high (?) */
1932#define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002 /* XPA B high (?) */
1933#define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004 /* Enable XPA A */
1934#define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 /* Enable XPA B */
1935
1936/*
1937 * PHY settling register
1938 */
1939#define AR5K_PHY_SETTLING 0x9844 /* Register Address */
1940#define AR5K_PHY_SETTLING_AGC 0x0000007f /* Mask for AGC settling time */
1941#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Mask for Switch settlig time */
1942
1943/*
1944 * PHY Gain registers
1945 */
1946#define AR5K_PHY_GAIN 0x9848 /* Register Address */
1947#define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* Mask for TX-RX Attenuation */
1948
1949#define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */
1950#define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */
1951
1952/*
1953 * Desired size register
1954 * (for more infos read ANI patent)
1955 */
1956#define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */
1957#define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* Mask for ADC desired size */
1958#define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* Mask for PGA desired size */
1959#define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Mask for Total desired size (?) */
1663 1960
1664/* 1961/*
1665 * PHY signal register 1962 * PHY signal register
1963 * (for more infos read ANI patent)
1666 */ 1964 */
1667#define AR5K_PHY_SIG 0x9858 1965#define AR5K_PHY_SIG 0x9858 /* Register Address */
1668#define AR5K_PHY_SIG_FIRSTEP 0x0003f000 1966#define AR5K_PHY_SIG_FIRSTEP 0x0003f000 /* Mask for FIRSTEP */
1669#define AR5K_PHY_SIG_FIRSTEP_S 12 1967#define AR5K_PHY_SIG_FIRSTEP_S 12
1670#define AR5K_PHY_SIG_FIRPWR 0x03fc0000 1968#define AR5K_PHY_SIG_FIRPWR 0x03fc0000 /* Mask for FIPWR */
1671#define AR5K_PHY_SIG_FIRPWR_S 18 1969#define AR5K_PHY_SIG_FIRPWR_S 18
1672 1970
1673/* 1971/*
1674 * PHY coarse agility control register 1972 * PHY coarse agility control register
1973 * (for more infos read ANI patent)
1675 */ 1974 */
1676#define AR5K_PHY_AGCCOARSE 0x985c 1975#define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */
1677#define AR5K_PHY_AGCCOARSE_LO 0x00007f80 1976#define AR5K_PHY_AGCCOARSE_LO 0x00007f80 /* Mask for AGC Coarse low */
1678#define AR5K_PHY_AGCCOARSE_LO_S 7 1977#define AR5K_PHY_AGCCOARSE_LO_S 7
1679#define AR5K_PHY_AGCCOARSE_HI 0x003f8000 1978#define AR5K_PHY_AGCCOARSE_HI 0x003f8000 /* Mask for AGC Coarse high */
1680#define AR5K_PHY_AGCCOARSE_HI_S 15 1979#define AR5K_PHY_AGCCOARSE_HI_S 15
1681 1980
1682/* 1981/*
@@ -1689,12 +1988,13 @@
1689/* 1988/*
1690 * PHY noise floor status register 1989 * PHY noise floor status register
1691 */ 1990 */
1692#define AR5K_PHY_NF 0x9864 1991#define AR5K_PHY_NF 0x9864 /* Register address */
1693#define AR5K_PHY_NF_M 0x000001ff 1992#define AR5K_PHY_NF_M 0x000001ff /* Noise floor mask */
1694#define AR5K_PHY_NF_ACTIVE 0x00000100 1993#define AR5K_PHY_NF_ACTIVE 0x00000100 /* Noise floor calibration still active */
1695#define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M) 1994#define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M)
1696#define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1) 1995#define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1)
1697#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) 1996#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9))
1997#define AR5K_PHY_NF_THRESH62 0x00001000 /* Thresh62 -check ANI patent- (field) */
1698 1998
1699/* 1999/*
1700 * PHY ADC saturation register [5110] 2000 * PHY ADC saturation register [5110]
@@ -1706,6 +2006,30 @@
1706#define AR5K_PHY_ADCSAT_THR_S 5 2006#define AR5K_PHY_ADCSAT_THR_S 5
1707 2007
1708/* 2008/*
2009 * PHY Weak ofdm signal detection threshold registers (ANI) [5212+]
2010 */
2011
2012/* High thresholds */
2013#define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868
2014#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f
2015#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 0
2016#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000
2017#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S 17
2018#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000
2019#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24
2020
2021/* Low thresholds */
2022#define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c
2023#define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001
2024#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00
2025#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8
2026#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000
2027#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14
2028#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000
2029#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21
2030
2031
2032/*
1709 * PHY sleep registers [5112+] 2033 * PHY sleep registers [5112+]
1710 */ 2034 */
1711#define AR5K_PHY_SCR 0x9870 2035#define AR5K_PHY_SCR 0x9870
@@ -1730,6 +2054,8 @@
1730 AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) 2054 AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212)
1731#define AR5K_PHY_PLL_RF5111 0x00000000 2055#define AR5K_PHY_PLL_RF5111 0x00000000
1732#define AR5K_PHY_PLL_RF5112 0x00000040 2056#define AR5K_PHY_PLL_RF5112 0x00000040
2057#define AR5K_PHY_PLL_HALF_RATE 0x00000100
2058#define AR5K_PHY_PLL_QUARTER_RATE 0x00000200
1733 2059
1734/* 2060/*
1735 * RF Buffer register 2061 * RF Buffer register
@@ -1792,23 +2118,74 @@
1792#define AR5K_PHY_RFSTG_DISABLE 0x00000021 2118#define AR5K_PHY_RFSTG_DISABLE 0x00000021
1793 2119
1794/* 2120/*
2121 * PHY Antenna control register
2122 */
2123#define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */
2124#define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */
2125#define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 /* Sectored Antenna */
2126#define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 /* Hitune5 (?) */
2127#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x00000010 /* Switch table idle (?) */
2128
2129/*
1795 * PHY receiver delay register [5111+] 2130 * PHY receiver delay register [5111+]
1796 */ 2131 */
1797#define AR5K_PHY_RX_DELAY 0x9914 2132#define AR5K_PHY_RX_DELAY 0x9914 /* Register Address */
1798#define AR5K_PHY_RX_DELAY_M 0x00003fff 2133#define AR5K_PHY_RX_DELAY_M 0x00003fff /* Mask for RX activate to receive delay (/100ns) */
2134
2135/*
2136 * PHY max rx length register (?) [5111]
2137 */
2138#define AR5K_PHY_MAX_RX_LEN 0x991c
1799 2139
1800/* 2140/*
1801 * PHY timing I(nphase) Q(adrature) control register [5111+] 2141 * PHY timing register 4
2142 * I(nphase)/Q(adrature) calibration register [5111+]
1802 */ 2143 */
1803#define AR5K_PHY_IQ 0x9920 /* Register address */ 2144#define AR5K_PHY_IQ 0x9920 /* Register Address */
1804#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ 2145#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */
1805#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ 2146#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */
1806#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 2147#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5
1807#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ 2148#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */
1808#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 2149#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 /* Mask for max number of samples in log scale */
1809#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 2150#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12
1810#define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */ 2151#define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */
2152#define AR5K_PHY_IQ_USE_PT_DF 0x00020000 /* Use pilot track df (?) */
2153#define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 /* Early trigger threshold (?) (field) */
2154#define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000 /* Enable pilot mask (?) */
2155#define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000 /* Enable channel mask (?) */
2156#define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000 /* Enable spur filter */
2157#define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000 /* Enable spur rssi */
1811 2158
2159/*
2160 * PHY timing register 5
2161 * OFDM Self-correlator Cyclic RSSI threshold params
2162 * (Check out bb_cycpwr_thr1 on ANI patent)
2163 */
2164#define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */
2165#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */
2166#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */
2167#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */
2168#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */
2169#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */
2170#define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000 /* Long sc threshold hi rssi (?) */
2171
2172/*
2173 * PHY-only warm reset register
2174 */
2175#define AR5K_PHY_WARM_RESET 0x9928
2176
2177/*
2178 * PHY-only control register
2179 */
2180#define AR5K_PHY_CTL 0x992c /* Register Address */
2181#define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001 /* RX drain rate (?) */
2182#define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002 /* Late tx signal symbol (?) */
2183#define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004 /* Generate scrambler */
2184#define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008 /* TX antenna select */
2185#define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010 /* Static TX antenna */
2186#define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020 /* RX antenna select */
2187#define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040 /* Static RX antenna */
2188#define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */
1812 2189
1813/* 2190/*
1814 * PHY PAPD probe register [5111+ (?)] 2191 * PHY PAPD probe register [5111+ (?)]
@@ -1816,9 +2193,13 @@
1816 * Because it's always 0 in 5211 initialization code 2193 * Because it's always 0 in 5211 initialization code
1817 */ 2194 */
1818#define AR5K_PHY_PAPD_PROBE 0x9930 2195#define AR5K_PHY_PAPD_PROBE 0x9930
2196#define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001
2197#define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002
2198#define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040
1819#define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 2199#define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00
1820#define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9 2200#define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9
1821#define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 2201#define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000
2202#define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000
1822#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */ 2203#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */
1823#define AR5K_PHY_PAPD_PROBE_TYPE_S 23 2204#define AR5K_PHY_PAPD_PROBE_TYPE_S 23
1824#define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 2205#define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0
@@ -1848,15 +2229,16 @@
1848#define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \ 2229#define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \
1849 AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) 2230 AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)
1850/*---[5111+]---*/ 2231/*---[5111+]---*/
1851#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 2232#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */
1852#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 2233#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3
2234#define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */
1853/*---[5110/5111]---*/ 2235/*---[5110/5111]---*/
1854#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 2236#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */
1855#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 2237#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 /* Parity error */
1856#define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 /* illegal rate */ 2238#define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 /* Illegal rate */
1857#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* illegal length */ 2239#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* Illegal length */
1858#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 2240#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000
1859#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* tx underrun */ 2241#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* TX underrun */
1860#define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ 2242#define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \
1861 AR5K_PHY_FRAME_CTL_TXURN_ERR | \ 2243 AR5K_PHY_FRAME_CTL_TXURN_ERR | \
1862 AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ 2244 AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \
@@ -1915,6 +2297,11 @@ after DFS is enabled */
1915#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 2297#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964
1916 2298
1917/* 2299/*
2300 * PHY Noise floor threshold
2301 */
2302#define AR5K_PHY_NFTHRES 0x9968
2303
2304/*
1918 * PHY clock sleep registers [5112+] 2305 * PHY clock sleep registers [5112+]
1919 */ 2306 */
1920#define AR5K_PHY_SCLOCK 0x99f0 2307#define AR5K_PHY_SCLOCK 0x99f0
@@ -1922,56 +2309,116 @@ after DFS is enabled */
1922#define AR5K_PHY_SDELAY 0x99f4 2309#define AR5K_PHY_SDELAY 0x99f4
1923#define AR5K_PHY_SDELAY_32MHZ 0x000000ff 2310#define AR5K_PHY_SDELAY_32MHZ 0x000000ff
1924#define AR5K_PHY_SPENDING 0x99f8 2311#define AR5K_PHY_SPENDING 0x99f8
2312#define AR5K_PHY_SPENDING_14 0x00000014
2313#define AR5K_PHY_SPENDING_18 0x00000018
1925#define AR5K_PHY_SPENDING_RF5111 0x00000018 2314#define AR5K_PHY_SPENDING_RF5111 0x00000018
1926#define AR5K_PHY_SPENDING_RF5112 0x00000014 /* <- i 've only seen this on 2425 dumps ! */ 2315#define AR5K_PHY_SPENDING_RF5112 0x00000014
1927#define AR5K_PHY_SPENDING_RF5112A 0x0000000e /* but since i only have 5112A-based chips */ 2316/* #define AR5K_PHY_SPENDING_RF5112A 0x0000000e */
1928#define AR5K_PHY_SPENDING_RF5424 0x00000012 /* to test it might be also for old 5112. */ 2317/* #define AR5K_PHY_SPENDING_RF5424 0x00000012 */
2318#define AR5K_PHY_SPENDING_RF5413 0x00000014
2319#define AR5K_PHY_SPENDING_RF2413 0x00000014
2320#define AR5K_PHY_SPENDING_RF2425 0x00000018
1929 2321
1930/* 2322/*
1931 * Misc PHY/radio registers [5110 - 5111] 2323 * Misc PHY/radio registers [5110 - 5111]
1932 */ 2324 */
1933#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ 2325#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */
1934#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) 2326#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2))
1935#define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplrifier Gain table base address */ 2327#define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplrifier Gain table base address */
1936#define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) 2328#define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2))
1937 2329
1938/* 2330/*
1939 * PHY timing IQ calibration result register [5111+] 2331 * PHY timing IQ calibration result register [5111+]
1940 */ 2332 */
1941#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */ 2333#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */
1942#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */ 2334#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */
1943#define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* I/Q Correlation */ 2335#define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* I/Q Correlation */
1944 2336
1945/* 2337/*
1946 * PHY current RSSI register [5111+] 2338 * PHY current RSSI register [5111+]
1947 */ 2339 */
1948#define AR5K_PHY_CURRENT_RSSI 0x9c1c 2340#define AR5K_PHY_CURRENT_RSSI 0x9c1c
2341
2342/*
2343 * PHY RF Bus grant register (?)
2344 */
2345#define AR5K_PHY_RFBUS_GRANT 0x9c20
2346
2347/*
2348 * PHY ADC test register
2349 */
2350#define AR5K_PHY_ADC_TEST 0x9c24
2351#define AR5K_PHY_ADC_TEST_I 0x00000001
2352#define AR5K_PHY_ADC_TEST_Q 0x00000200
2353
2354/*
2355 * PHY DAC test register
2356 */
2357#define AR5K_PHY_DAC_TEST 0x9c28
2358#define AR5K_PHY_DAC_TEST_I 0x00000001
2359#define AR5K_PHY_DAC_TEST_Q 0x00000200
2360
2361/*
2362 * PHY PTAT register (?)
2363 */
2364#define AR5K_PHY_PTAT 0x9c2c
2365
2366/*
2367 * PHY Illegal TX rate register [5112+]
2368 */
2369#define AR5K_PHY_BAD_TX_RATE 0x9c30
2370
2371/*
2372 * PHY SPUR Power register [5112+]
2373 */
2374#define AR5K_PHY_SPUR_PWR 0x9c34 /* Register Address */
2375#define AR5K_PHY_SPUR_PWR_I 0x00000001 /* SPUR Power estimate for I (field) */
2376#define AR5K_PHY_SPUR_PWR_Q 0x00000100 /* SPUR Power estimate for Q (field) */
2377#define AR5K_PHY_SPUR_PWR_FILT 0x00010000 /* Power with SPUR removed (field) */
2378
2379/*
2380 * PHY Channel status register [5112+] (?)
2381 */
2382#define AR5K_PHY_CHAN_STATUS 0x9c38
2383#define AR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001
2384#define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002
2385#define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004
2386#define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008
2387
2388/*
2389 * PHY PAPD I (power?) table (?)
2390 * (92! entries)
2391 */
2392#define AR5K_PHY_PAPD_I_BASE 0xa000
2393#define AR5K_PHY_PAPD_I(_n) (AR5K_PHY_PAPD_I_BASE + ((_n) << 2))
1949 2394
1950/* 2395/*
1951 * PHY PCDAC TX power table 2396 * PHY PCDAC TX power table
1952 */ 2397 */
1953#define AR5K_PHY_PCDAC_TXPOWER_BASE_5211 0xa180 2398#define AR5K_PHY_PCDAC_TXPOWER_BASE_5211 0xa180
1954#define AR5K_PHY_PCDAC_TXPOWER_BASE_5413 0xa280 2399#define AR5K_PHY_PCDAC_TXPOWER_BASE_2413 0xa280
1955#define AR5K_PHY_PCDAC_TXPOWER_BASE (ah->ah_radio >= AR5K_RF5413 ? \ 2400#define AR5K_PHY_PCDAC_TXPOWER_BASE (ah->ah_radio >= AR5K_RF2413 ? \
1956 AR5K_PHY_PCDAC_TXPOWER_BASE_5413 :\ 2401 AR5K_PHY_PCDAC_TXPOWER_BASE_2413 :\
1957 AR5K_PHY_PCDAC_TXPOWER_BASE_5211) 2402 AR5K_PHY_PCDAC_TXPOWER_BASE_5211)
1958#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) 2403#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))
1959 2404
1960/* 2405/*
1961 * PHY mode register [5111+] 2406 * PHY mode register [5111+]
1962 */ 2407 */
1963#define AR5K_PHY_MODE 0x0a200 /* Register address */ 2408#define AR5K_PHY_MODE 0x0a200 /* Register Address */
1964#define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation mask*/ 2409#define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation bit */
1965#define AR5K_PHY_MODE_MOD_OFDM 0 2410#define AR5K_PHY_MODE_MOD_OFDM 0
1966#define AR5K_PHY_MODE_MOD_CCK 1 2411#define AR5K_PHY_MODE_MOD_CCK 1
1967#define AR5K_PHY_MODE_FREQ 0x00000002 /* Freq mode mask */ 2412#define AR5K_PHY_MODE_FREQ 0x00000002 /* Freq mode bit */
1968#define AR5K_PHY_MODE_FREQ_5GHZ 0 2413#define AR5K_PHY_MODE_FREQ_5GHZ 0
1969#define AR5K_PHY_MODE_FREQ_2GHZ 2 2414#define AR5K_PHY_MODE_FREQ_2GHZ 2
1970#define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Dynamic OFDM/CCK mode mask [5112+] */ 2415#define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Enable Dynamic OFDM/CCK mode [5112+] */
1971#define AR5K_PHY_MODE_RAD 0x00000008 /* [5212+] */ 2416#define AR5K_PHY_MODE_RAD 0x00000008 /* [5212+] */
1972#define AR5K_PHY_MODE_RAD_RF5111 0 2417#define AR5K_PHY_MODE_RAD_RF5111 0
1973#define AR5K_PHY_MODE_RAD_RF5112 8 2418#define AR5K_PHY_MODE_RAD_RF5112 8
1974#define AR5K_PHY_MODE_XR 0x00000010 /* [5112+] */ 2419#define AR5K_PHY_MODE_XR 0x00000010 /* Enable XR mode [5112+] */
2420#define AR5K_PHY_MODE_HALF_RATE 0x00000020 /* Enable Half rate (test) */
2421#define AR5K_PHY_MODE_QUARTER_RATE 0x00000040 /* Enable Quarter rat (test) */
1975 2422
1976/* 2423/*
1977 * PHY CCK transmit control register [5111+ (?)] 2424 * PHY CCK transmit control register [5111+ (?)]
@@ -1979,6 +2426,15 @@ after DFS is enabled */
1979#define AR5K_PHY_CCKTXCTL 0xa204 2426#define AR5K_PHY_CCKTXCTL 0xa204
1980#define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 2427#define AR5K_PHY_CCKTXCTL_WORLD 0x00000000
1981#define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 2428#define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010
2429#define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001
2430#define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004
2431
2432/*
2433 * PHY CCK Cross-correlator Barker RSSI threshold register [5212+]
2434 */
2435#define AR5K_PHY_CCK_CROSSCORR 0xa208
2436#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000000f
2437#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0
1982 2438
1983/* 2439/*
1984 * PHY 2GHz gain register [5111+] 2440 * PHY 2GHz gain register [5111+]
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 17:24:46 -0400