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authorEilon Greenstein <eilong@broadcom.com>2009-02-12 03:37:16 -0500
committerDavid S. Miller <davem@davemloft.net>2009-02-16 02:31:42 -0500
commit052a38e096dece43e38a19a896ae7ad019415bc1 (patch)
tree127b34c6948872a535bfc13e102d852515c44679 /drivers
parentc2c8b03e200bdda3ba23d27f5c33bac784dced01 (diff)
bnx2x: Using registers name
Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2x.h9
-rw-r--r--drivers/net/bnx2x_link.c71
-rw-r--r--drivers/net/bnx2x_reg.h7
3 files changed, 49 insertions, 38 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 12d2d0bd9a42..9834a86d8139 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -446,10 +446,13 @@ struct bnx2x_fastpath {
446#define BNX2X_RX_CSUM_OK(cqe) \ 446#define BNX2X_RX_CSUM_OK(cqe) \
447 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) 447 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
448 448
449#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
450 (((le16_to_cpu(flags) & \
451 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
452 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
453 == PRS_FLAG_OVERETH_IPV4)
449#define BNX2X_RX_SUM_FIX(cqe) \ 454#define BNX2X_RX_SUM_FIX(cqe) \
450 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \ 455 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
451 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
452 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
453 456
454 457
455#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES) 458#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index 4a594b84ba20..39db995c6985 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -2094,7 +2094,7 @@ static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
2094 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 2094 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2095 ext_phy_addr, 2095 ext_phy_addr,
2096 MDIO_PMA_DEVAD, 2096 MDIO_PMA_DEVAD,
2097 0xc801, &val); 2097 MDIO_PMA_REG_8073_CHIP_REV, &val);
2098 2098
2099 if (val != 1) { 2099 if (val != 1) {
2100 /* No need to workaround in 8073 A1 */ 2100 /* No need to workaround in 8073 A1 */
@@ -2126,7 +2126,7 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2126 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 2126 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2127 ext_phy_addr, 2127 ext_phy_addr,
2128 MDIO_PMA_DEVAD, 2128 MDIO_PMA_DEVAD,
2129 0xc801, &val); 2129 MDIO_PMA_REG_8073_CHIP_REV, &val);
2130 2130
2131 if (val > 0) { 2131 if (val > 0) {
2132 /* No need to workaround in 8073 A1 */ 2132 /* No need to workaround in 8073 A1 */
@@ -2142,7 +2142,8 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2142 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 2142 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2143 ext_phy_addr, 2143 ext_phy_addr,
2144 MDIO_PMA_DEVAD, 2144 MDIO_PMA_DEVAD,
2145 0xc820, &val); 2145 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
2146 &val);
2146 /* If bit [14] = 0 or bit [13] = 0, continue on with 2147 /* If bit [14] = 0 or bit [13] = 0, continue on with
2147 system initialization (XAUI work-around not required, 2148 system initialization (XAUI work-around not required,
2148 as these bits indicate 2.5G or 1G link up). */ 2149 as these bits indicate 2.5G or 1G link up). */
@@ -2160,7 +2161,7 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2160 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 2161 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2161 ext_phy_addr, 2162 ext_phy_addr,
2162 MDIO_PMA_DEVAD, 2163 MDIO_PMA_DEVAD,
2163 0xc841, &val); 2164 MDIO_PMA_REG_8073_XAUI_WA, &val);
2164 if (val & (1<<15)) { 2165 if (val & (1<<15)) {
2165 DP(NETIF_MSG_LINK, 2166 DP(NETIF_MSG_LINK,
2166 "XAUI workaround has completed\n"); 2167 "XAUI workaround has completed\n");
@@ -2758,7 +2759,7 @@ static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
2758 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 2759 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2759 ext_phy_addr, 2760 ext_phy_addr,
2760 MDIO_PMA_DEVAD, 2761 MDIO_PMA_DEVAD,
2761 0xc801, &val); 2762 MDIO_PMA_REG_8073_CHIP_REV, &val);
2762 2763
2763 if (val == 0) { 2764 if (val == 0) {
2764 /* Mustn't set low power mode in 8073 A0 */ 2765 /* Mustn't set low power mode in 8073 A0 */
@@ -3283,7 +3284,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3283 ext_phy_type, 3284 ext_phy_type,
3284 ext_phy_addr, 3285 ext_phy_addr,
3285 MDIO_PMA_DEVAD, 3286 MDIO_PMA_DEVAD,
3286 0xca13, 3287 MDIO_PMA_REG_M8051_MSGOUT_REG,
3287 &tmp1); 3288 &tmp1);
3288 3289
3289 bnx2x_cl45_read(bp, params->port, 3290 bnx2x_cl45_read(bp, params->port,
@@ -3350,7 +3351,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3350 ext_phy_type, 3351 ext_phy_type,
3351 ext_phy_addr, 3352 ext_phy_addr,
3352 MDIO_AN_DEVAD, 3353 MDIO_AN_DEVAD,
3353 0x8329, &tmp1); 3354 MDIO_AN_REG_8073_2_5G, &tmp1);
3354 3355
3355 if (((params->speed_cap_mask & 3356 if (((params->speed_cap_mask &
3356 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 3357 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
@@ -3364,7 +3365,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3364 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 3365 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
3365 ext_phy_addr, 3366 ext_phy_addr,
3366 MDIO_PMA_DEVAD, 3367 MDIO_PMA_DEVAD,
3367 0xc801, &phy_ver); 3368 MDIO_PMA_REG_8073_CHIP_REV, &phy_ver);
3368 DP(NETIF_MSG_LINK, "Add 2.5G\n"); 3369 DP(NETIF_MSG_LINK, "Add 2.5G\n");
3369 if (phy_ver > 0) 3370 if (phy_ver > 0)
3370 tmp1 |= 1; 3371 tmp1 |= 1;
@@ -3379,7 +3380,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3379 ext_phy_type, 3380 ext_phy_type,
3380 ext_phy_addr, 3381 ext_phy_addr,
3381 MDIO_AN_DEVAD, 3382 MDIO_AN_DEVAD,
3382 0x8329, tmp1); 3383 MDIO_AN_REG_8073_2_5G, tmp1);
3383 } 3384 }
3384 3385
3385 /* Add support for CL37 (passive mode) II */ 3386 /* Add support for CL37 (passive mode) II */
@@ -3737,7 +3738,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
3737 ext_phy_type, 3738 ext_phy_type,
3738 ext_phy_addr, 3739 ext_phy_addr,
3739 MDIO_PMA_DEVAD, 3740 MDIO_PMA_DEVAD,
3740 0xca13, 3741 MDIO_PMA_REG_M8051_MSGOUT_REG,
3741 &val1); 3742 &val1);
3742 3743
3743 /* Check the LASI */ 3744 /* Check the LASI */
@@ -3782,17 +3783,17 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
3782 } 3783 }
3783 } 3784 }
3784 bnx2x_cl45_read(bp, params->port, 3785 bnx2x_cl45_read(bp, params->port,
3785 ext_phy_type, 3786 ext_phy_type,
3786 ext_phy_addr, 3787 ext_phy_addr,
3787 MDIO_AN_DEVAD, 3788 MDIO_AN_DEVAD,
3788 0x8304, 3789 MDIO_AN_REG_LINK_STATUS,
3789 &an1000_status); 3790 &an1000_status);
3790 bnx2x_cl45_read(bp, params->port, 3791 bnx2x_cl45_read(bp, params->port,
3791 ext_phy_type, 3792 ext_phy_type,
3792 ext_phy_addr, 3793 ext_phy_addr,
3793 MDIO_AN_DEVAD, 3794 MDIO_AN_DEVAD,
3794 0x8304, 3795 MDIO_AN_REG_LINK_STATUS,
3795 &an1000_status); 3796 &an1000_status);
3796 3797
3797 /* Check the link status on 1.1.2 */ 3798 /* Check the link status on 1.1.2 */
3798 bnx2x_cl45_read(bp, params->port, 3799 bnx2x_cl45_read(bp, params->port,
@@ -3837,11 +3838,11 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
3837 3838
3838 } 3839 }
3839 bnx2x_cl45_read(bp, params->port, 3840 bnx2x_cl45_read(bp, params->port,
3840 ext_phy_type, 3841 ext_phy_type,
3841 ext_phy_addr, 3842 ext_phy_addr,
3842 MDIO_PMA_DEVAD, 3843 MDIO_PMA_DEVAD,
3843 0xc820, 3844 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
3844 &link_status); 3845 &link_status);
3845 3846
3846 /* Bits 0..2 --> speed detected, 3847 /* Bits 0..2 --> speed detected,
3847 bits 13..15--> link is down */ 3848 bits 13..15--> link is down */
@@ -3875,17 +3876,17 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
3875 } else { 3876 } else {
3876 /* See if 1G link is up for the 8072 */ 3877 /* See if 1G link is up for the 8072 */
3877 bnx2x_cl45_read(bp, params->port, 3878 bnx2x_cl45_read(bp, params->port,
3878 ext_phy_type, 3879 ext_phy_type,
3879 ext_phy_addr, 3880 ext_phy_addr,
3880 MDIO_AN_DEVAD, 3881 MDIO_AN_DEVAD,
3881 0x8304, 3882 MDIO_AN_REG_LINK_STATUS,
3882 &an1000_status); 3883 &an1000_status);
3883 bnx2x_cl45_read(bp, params->port, 3884 bnx2x_cl45_read(bp, params->port,
3884 ext_phy_type, 3885 ext_phy_type,
3885 ext_phy_addr, 3886 ext_phy_addr,
3886 MDIO_AN_DEVAD, 3887 MDIO_AN_DEVAD,
3887 0x8304, 3888 MDIO_AN_REG_LINK_STATUS,
3888 &an1000_status); 3889 &an1000_status);
3889 if (an1000_status & (1<<1)) { 3890 if (an1000_status & (1<<1)) {
3890 ext_phy_link_up = 1; 3891 ext_phy_link_up = 1;
3891 vars->line_speed = SPEED_1000; 3892 vars->line_speed = SPEED_1000;
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index 08e703dc2b46..360a2564aa98 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -5239,6 +5239,7 @@
5239#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 5239#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5240#define HW_LOCK_RESOURCE_SPIO 2 5240#define HW_LOCK_RESOURCE_SPIO 2
5241#define HW_LOCK_RESOURCE_UNDI 5 5241#define HW_LOCK_RESOURCE_UNDI 5
5242#define PRS_FLAG_OVERETH_IPV4 1
5242#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) 5243#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
5243#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) 5244#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
5244#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) 5245#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
@@ -5861,6 +5862,10 @@ Theotherbitsarereservedandshouldbezero*/
5861#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 5862#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
5862 5863
5863 5864
5865#define MDIO_PMA_REG_8073_CHIP_REV 0xc801
5866#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
5867#define MDIO_PMA_REG_8073_XAUI_WA 0xc841
5868
5864#define MDIO_PMA_REG_7101_RESET 0xc000 5869#define MDIO_PMA_REG_7101_RESET 0xc000
5865#define MDIO_PMA_REG_7107_LED_CNTL 0xc007 5870#define MDIO_PMA_REG_7107_LED_CNTL 0xc007
5866#define MDIO_PMA_REG_7101_VER1 0xc026 5871#define MDIO_PMA_REG_7101_VER1 0xc026
@@ -5917,6 +5922,8 @@ Theotherbitsarereservedandshouldbezero*/
5917#define MDIO_AN_REG_CL37_FC_LD 0xffe4 5922#define MDIO_AN_REG_CL37_FC_LD 0xffe4
5918#define MDIO_AN_REG_CL37_FC_LP 0xffe5 5923#define MDIO_AN_REG_CL37_FC_LP 0xffe5
5919 5924
5925#define MDIO_AN_REG_8073_2_5G 0x8329
5926
5920 5927
5921#define IGU_FUNC_BASE 0x0400 5928#define IGU_FUNC_BASE 0x0400
5922 5929
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 11:58:11 -0500