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authorDave Airlie <airlied@redhat.com>2009-12-22 20:18:33 -0500
committerDave Airlie <airlied@redhat.com>2009-12-22 20:18:33 -0500
commitd94a5108f716bbd524358eb5a440d63991744a62 (patch)
tree221988e3e87c26bf0cdf16cc411b3e3220c8637e /drivers
parent44f9e6c6bc508b202755d9e9e48a8ba96a5f0fa4 (diff)
parent0786201d8cd0730e72b0e087484dd47cc5f58409 (diff)
Merge remote branch 'korg/drm-radeon-next' into drm-linus
* korg/drm-radeon-next: drm/radeon/kms: add definitions for v4 power tables drm/radeon/kms: never combine LVDS with another encoder drm/radeon/kms: Check module arguments to be valid V2 drm/radeon/kms: Avoid crash when trying to cleanup uninitialized structure drm/radeon/kms: add cvt mode if we only have lvds w/h and no edid (v4) drm/radeon/kms: add 3DC compression support drm/radeon/kms: allow rendering while no colorbuffer is set on r300 drm/radeon/kms: enable memory clock reading on legacy (V2) drm/radeon/kms: prevent parallel AtomBIOS calls drm/radeon/kms: set proper default tv standard drm/radeon/kms: fix legacy rmx drm/radeon/kms/atom: fill in proper defines for digital setup
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/radeon/atom.c12
-rw-r--r--drivers/gpu/drm/radeon/atom.h1
-rw-r--r--drivers/gpu/drm/radeon/atombios.h199
-rw-r--r--drivers/gpu/drm/radeon/r100.c4
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h4
-rw-r--r--drivers/gpu/drm/radeon/r300.c30
-rw-r--r--drivers/gpu/drm/radeon/r300_reg.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon.h4
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h7
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c105
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c16
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c80
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c18
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h6
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c4
21 files changed, 459 insertions, 61 deletions
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 6578d19dff93..388140a7e651 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -58,6 +58,7 @@ typedef struct {
58} atom_exec_context; 58} atom_exec_context;
59 59
60int atom_debug = 0; 60int atom_debug = 0;
61static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
61void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); 62void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
62 63
63static uint32_t atom_arg_mask[8] = 64static uint32_t atom_arg_mask[8] =
@@ -573,7 +574,7 @@ static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
573 else 574 else
574 SDEBUG(" table: %d\n", idx); 575 SDEBUG(" table: %d\n", idx);
575 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) 576 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
576 atom_execute_table(ctx->ctx, idx, ctx->ps + ctx->ps_shift); 577 atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
577} 578}
578 579
579static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) 580static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
@@ -1040,7 +1041,7 @@ static struct {
1040 atom_op_shr, ATOM_ARG_MC}, { 1041 atom_op_shr, ATOM_ARG_MC}, {
1041atom_op_debug, 0},}; 1042atom_op_debug, 0},};
1042 1043
1043void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1044static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
1044{ 1045{
1045 int base = CU16(ctx->cmd_table + 4 + 2 * index); 1046 int base = CU16(ctx->cmd_table + 4 + 2 * index);
1046 int len, ws, ps, ptr; 1047 int len, ws, ps, ptr;
@@ -1092,6 +1093,13 @@ void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
1092 kfree(ectx.ws); 1093 kfree(ectx.ws);
1093} 1094}
1094 1095
1096void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
1097{
1098 mutex_lock(&ctx->mutex);
1099 atom_execute_table_locked(ctx, index, params);
1100 mutex_unlock(&ctx->mutex);
1101}
1102
1095static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 }; 1103static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
1096 1104
1097static void atom_index_iio(struct atom_context *ctx, int base) 1105static void atom_index_iio(struct atom_context *ctx, int base)
diff --git a/drivers/gpu/drm/radeon/atom.h b/drivers/gpu/drm/radeon/atom.h
index 6671848e5ea1..47fd943f6d14 100644
--- a/drivers/gpu/drm/radeon/atom.h
+++ b/drivers/gpu/drm/radeon/atom.h
@@ -120,6 +120,7 @@ struct card_info {
120 120
121struct atom_context { 121struct atom_context {
122 struct card_info *card; 122 struct card_info *card;
123 struct mutex mutex;
123 void *bios; 124 void *bios;
124 uint32_t cmd_table, data_table; 125 uint32_t cmd_table, data_table;
125 uint16_t *iio; 126 uint16_t *iio;
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index e83927644de4..8e28842080df 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -4690,6 +4690,205 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 {
4690 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 4690 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
4691} ATOM_POWERPLAY_INFO_V3; 4691} ATOM_POWERPLAY_INFO_V3;
4692 4692
4693/* New PPlib */
4694/**************************************************************************/
4695typedef struct _ATOM_PPLIB_THERMALCONTROLLER
4696
4697{
4698 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_*
4699 UCHAR ucI2cLine; // as interpreted by DAL I2C
4700 UCHAR ucI2cAddress;
4701 UCHAR ucFanParameters; // Fan Control Parameters.
4702 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only.
4703 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only.
4704 UCHAR ucReserved; // ----
4705 UCHAR ucFlags; // to be defined
4706} ATOM_PPLIB_THERMALCONTROLLER;
4707
4708#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
4709#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller.
4710
4711#define ATOM_PP_THERMALCONTROLLER_NONE 0
4712#define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib
4713#define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib
4714#define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib
4715#define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib
4716#define ATOM_PP_THERMALCONTROLLER_LM64 5
4717#define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib
4718#define ATOM_PP_THERMALCONTROLLER_RV6xx 7
4719#define ATOM_PP_THERMALCONTROLLER_RV770 8
4720#define ATOM_PP_THERMALCONTROLLER_ADT7473 9
4721
4722typedef struct _ATOM_PPLIB_STATE
4723{
4724 UCHAR ucNonClockStateIndex;
4725 UCHAR ucClockStateIndices[1]; // variable-sized
4726} ATOM_PPLIB_STATE;
4727
4728//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
4729#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
4730#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
4731#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4
4732#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8
4733#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16
4734#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32
4735#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64
4736#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128
4737#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256
4738#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
4739#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
4740#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
4741
4742typedef struct _ATOM_PPLIB_POWERPLAYTABLE
4743{
4744 ATOM_COMMON_TABLE_HEADER sHeader;
4745
4746 UCHAR ucDataRevision;
4747
4748 UCHAR ucNumStates;
4749 UCHAR ucStateEntrySize;
4750 UCHAR ucClockInfoSize;
4751 UCHAR ucNonClockSize;
4752
4753 // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
4754 USHORT usStateArrayOffset;
4755
4756 // offset from start of this table to array of ASIC-specific structures,
4757 // currently ATOM_PPLIB_CLOCK_INFO.
4758 USHORT usClockInfoArrayOffset;
4759
4760 // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO
4761 USHORT usNonClockInfoArrayOffset;
4762
4763 USHORT usBackbiasTime; // in microseconds
4764 USHORT usVoltageTime; // in microseconds
4765 USHORT usTableSize; //the size of this structure, or the extended structure
4766
4767 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_*
4768
4769 ATOM_PPLIB_THERMALCONTROLLER sThermalController;
4770
4771 USHORT usBootClockInfoOffset;
4772 USHORT usBootNonClockInfoOffset;
4773
4774} ATOM_PPLIB_POWERPLAYTABLE;
4775
4776//// ATOM_PPLIB_NONCLOCK_INFO::usClassification
4777#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007
4778#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0
4779#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0
4780#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1
4781#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3
4782#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5
4783// 2, 4, 6, 7 are reserved
4784
4785#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008
4786#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010
4787#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020
4788#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040
4789#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080
4790#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100
4791#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200
4792#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400
4793#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800
4794#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000
4795// remaining 3 bits are reserved
4796
4797//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
4798#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001
4799#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002
4800
4801// 0 is 2.5Gb/s, 1 is 5Gb/s
4802#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004
4803#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2
4804
4805// lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec
4806#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8
4807#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3
4808
4809// lookup into reduced refresh-rate table
4810#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00
4811#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
4812
4813#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0
4814#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1
4815// 2-15 TBD as needed.
4816
4817#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000
4818#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000
4819#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000
4820
4821#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000
4822
4823// Contained in an array starting at the offset
4824// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
4825// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex
4826typedef struct _ATOM_PPLIB_NONCLOCK_INFO
4827{
4828 USHORT usClassification;
4829 UCHAR ucMinTemperature;
4830 UCHAR ucMaxTemperature;
4831 ULONG ulCapsAndSettings;
4832 UCHAR ucRequiredPower;
4833 UCHAR ucUnused1[3];
4834} ATOM_PPLIB_NONCLOCK_INFO;
4835
4836// Contained in an array starting at the offset
4837// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
4838// referenced from ATOM_PPLIB_STATE::ucClockStateIndices
4839typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
4840{
4841 USHORT usEngineClockLow;
4842 UCHAR ucEngineClockHigh;
4843
4844 USHORT usMemoryClockLow;
4845 UCHAR ucMemoryClockHigh;
4846
4847 USHORT usVDDC;
4848 USHORT usUnused1;
4849 USHORT usUnused2;
4850
4851 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
4852
4853} ATOM_PPLIB_R600_CLOCK_INFO;
4854
4855// ulFlags in ATOM_PPLIB_R600_CLOCK_INFO
4856#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1
4857#define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2
4858#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4
4859#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8
4860#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16
4861
4862typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
4863
4864{
4865 USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600).
4866 UCHAR ucLowEngineClockHigh;
4867 USHORT usHighEngineClockLow; // High Engine clock in MHz.
4868 UCHAR ucHighEngineClockHigh;
4869 USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants.
4870 UCHAR ucMemoryClockHigh; // Currentyl unused.
4871 UCHAR ucPadding; // For proper alignment and size.
4872 USHORT usVDDC; // For the 780, use: None, Low, High, Variable
4873 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
4874 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement.
4875 USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
4876 ULONG ulFlags;
4877} ATOM_PPLIB_RS780_CLOCK_INFO;
4878
4879#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
4880#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
4881#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
4882#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
4883
4884#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
4885#define ATOM_PPLIB_RS780_SPMCLK_LOW 1
4886#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
4887
4888#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
4889#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
4890#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
4891
4693/**************************************************************************/ 4892/**************************************************************************/
4694 4893
4695/* Following definitions are for compatiblity issue in different SW components. */ 4894/* Following definitions are for compatiblity issue in different SW components. */
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 84e5df766d3f..71727460968f 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2881,6 +2881,10 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2881 2881
2882 for (i = 0; i < track->num_cb; i++) { 2882 for (i = 0; i < track->num_cb; i++) {
2883 if (track->cb[i].robj == NULL) { 2883 if (track->cb[i].robj == NULL) {
2884 if (!(track->fastfill || track->color_channel_mask ||
2885 track->blend_read_enable)) {
2886 continue;
2887 }
2884 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2888 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2885 return -EINVAL; 2889 return -EINVAL;
2886 } 2890 }
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index 7188c3778ee2..b27a6999d219 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -67,13 +67,15 @@ struct r100_cs_track {
67 unsigned immd_dwords; 67 unsigned immd_dwords;
68 unsigned num_arrays; 68 unsigned num_arrays;
69 unsigned max_indx; 69 unsigned max_indx;
70 unsigned color_channel_mask;
70 struct r100_cs_track_array arrays[11]; 71 struct r100_cs_track_array arrays[11];
71 struct r100_cs_track_cb cb[R300_MAX_CB]; 72 struct r100_cs_track_cb cb[R300_MAX_CB];
72 struct r100_cs_track_cb zb; 73 struct r100_cs_track_cb zb;
73 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 74 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
74 bool z_enabled; 75 bool z_enabled;
75 bool separate_cube; 76 bool separate_cube;
76 77 bool fastfill;
78 bool blend_read_enable;
77}; 79};
78 80
79int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 81int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 83490c2b5061..3f2cc9e2e8d9 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -887,6 +887,14 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
887 track->textures[i].cpp = 1; 887 track->textures[i].cpp = 1;
888 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 888 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
889 break; 889 break;
890 case R300_TX_FORMAT_ATI2N:
891 if (p->rdev->family < CHIP_R420) {
892 DRM_ERROR("Invalid texture format %u\n",
893 (idx_value & 0x1F));
894 return -EINVAL;
895 }
896 /* The same rules apply as for DXT3/5. */
897 /* Pass through. */
890 case R300_TX_FORMAT_DXT3: 898 case R300_TX_FORMAT_DXT3:
891 case R300_TX_FORMAT_DXT5: 899 case R300_TX_FORMAT_DXT5:
892 track->textures[i].cpp = 1; 900 track->textures[i].cpp = 1;
@@ -951,6 +959,16 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
951 track->textures[i].width_11 = tmp; 959 track->textures[i].width_11 = tmp;
952 tmp = ((idx_value >> 16) & 1) << 11; 960 tmp = ((idx_value >> 16) & 1) << 11;
953 track->textures[i].height_11 = tmp; 961 track->textures[i].height_11 = tmp;
962
963 /* ATI1N */
964 if (idx_value & (1 << 14)) {
965 /* The same rules apply as for DXT1. */
966 track->textures[i].compress_format =
967 R100_TRACK_COMP_DXT1;
968 }
969 } else if (idx_value & (1 << 14)) {
970 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
971 return -EINVAL;
954 } 972 }
955 break; 973 break;
956 case 0x4480: 974 case 0x4480:
@@ -992,6 +1010,18 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
992 } 1010 }
993 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1011 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
994 break; 1012 break;
1013 case 0x4e0c:
1014 /* RB3D_COLOR_CHANNEL_MASK */
1015 track->color_channel_mask = idx_value;
1016 break;
1017 case 0x4d1c:
1018 /* ZB_BW_CNTL */
1019 track->fastfill = !!(idx_value & (1 << 2));
1020 break;
1021 case 0x4e04:
1022 /* RB3D_BLENDCNTL */
1023 track->blend_read_enable = !!(idx_value & (1 << 2));
1024 break;
995 case 0x4be8: 1025 case 0x4be8:
996 /* valid register only on RV530 */ 1026 /* valid register only on RV530 */
997 if (p->rdev->family == CHIP_RV530) 1027 if (p->rdev->family == CHIP_RV530)
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h
index 4b7afef35a65..1735a2b69580 100644
--- a/drivers/gpu/drm/radeon/r300_reg.h
+++ b/drivers/gpu/drm/radeon/r300_reg.h
@@ -900,6 +900,7 @@
900# define R300_TX_FORMAT_FL_I32 0x1B 900# define R300_TX_FORMAT_FL_I32 0x1B
901# define R300_TX_FORMAT_FL_I32A32 0x1C 901# define R300_TX_FORMAT_FL_I32A32 0x1C
902# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D 902# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
903# define R300_TX_FORMAT_ATI2N 0x1F
903 /* alpha modes, convenience mostly */ 904 /* alpha modes, convenience mostly */
904 /* if you have alpha, pick constant appropriate to the 905 /* if you have alpha, pick constant appropriate to the
905 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ 906 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index cd650fd3964e..53b55608102b 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -162,6 +162,7 @@ struct radeon_fence_driver {
162 struct list_head created; 162 struct list_head created;
163 struct list_head emited; 163 struct list_head emited;
164 struct list_head signaled; 164 struct list_head signaled;
165 bool initialized;
165}; 166};
166 167
167struct radeon_fence { 168struct radeon_fence {
@@ -202,8 +203,9 @@ struct radeon_surface_reg {
202struct radeon_mman { 203struct radeon_mman {
203 struct ttm_bo_global_ref bo_global_ref; 204 struct ttm_bo_global_ref bo_global_ref;
204 struct ttm_global_reference mem_global_ref; 205 struct ttm_global_reference mem_global_ref;
205 bool mem_global_referenced;
206 struct ttm_bo_device bdev; 206 struct ttm_bo_device bdev;
207 bool mem_global_referenced;
208 bool initialized;
207}; 209};
208 210
209struct radeon_bo { 211struct radeon_bo {
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 636116bedcb4..eb29217bbf1d 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -33,6 +33,7 @@
33 */ 33 */
34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
36void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
37 38
38uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
@@ -106,7 +107,7 @@ static struct radeon_asic r100_asic = {
106 .copy = &r100_copy_blit, 107 .copy = &r100_copy_blit,
107 .get_engine_clock = &radeon_legacy_get_engine_clock, 108 .get_engine_clock = &radeon_legacy_get_engine_clock,
108 .set_engine_clock = &radeon_legacy_set_engine_clock, 109 .set_engine_clock = &radeon_legacy_set_engine_clock,
109 .get_memory_clock = NULL, 110 .get_memory_clock = &radeon_legacy_get_memory_clock,
110 .set_memory_clock = NULL, 111 .set_memory_clock = NULL,
111 .set_pcie_lanes = NULL, 112 .set_pcie_lanes = NULL,
112 .set_clock_gating = &radeon_legacy_set_clock_gating, 113 .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -166,7 +167,7 @@ static struct radeon_asic r300_asic = {
166 .copy = &r100_copy_blit, 167 .copy = &r100_copy_blit,
167 .get_engine_clock = &radeon_legacy_get_engine_clock, 168 .get_engine_clock = &radeon_legacy_get_engine_clock,
168 .set_engine_clock = &radeon_legacy_set_engine_clock, 169 .set_engine_clock = &radeon_legacy_set_engine_clock,
169 .get_memory_clock = NULL, 170 .get_memory_clock = &radeon_legacy_get_memory_clock,
170 .set_memory_clock = NULL, 171 .set_memory_clock = NULL,
171 .set_pcie_lanes = &rv370_set_pcie_lanes, 172 .set_pcie_lanes = &rv370_set_pcie_lanes,
172 .set_clock_gating = &radeon_legacy_set_clock_gating, 173 .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -259,7 +260,7 @@ static struct radeon_asic rs400_asic = {
259 .copy = &r100_copy_blit, 260 .copy = &r100_copy_blit,
260 .get_engine_clock = &radeon_legacy_get_engine_clock, 261 .get_engine_clock = &radeon_legacy_get_engine_clock,
261 .set_engine_clock = &radeon_legacy_set_engine_clock, 262 .set_engine_clock = &radeon_legacy_set_engine_clock,
262 .get_memory_clock = NULL, 263 .get_memory_clock = &radeon_legacy_get_memory_clock,
263 .set_memory_clock = NULL, 264 .set_memory_clock = NULL,
264 .set_pcie_lanes = NULL, 265 .set_pcie_lanes = NULL,
265 .set_clock_gating = &radeon_legacy_set_clock_gating, 266 .set_clock_gating = &radeon_legacy_set_clock_gating,
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 12a0c760e7ff..321044bef71c 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -745,8 +745,7 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
745 else 745 else
746 radeon_add_legacy_encoder(dev, 746 radeon_add_legacy_encoder(dev,
747 radeon_get_encoder_id(dev, 747 radeon_get_encoder_id(dev,
748 (1 << 748 (1 << i),
749 i),
750 dac), 749 dac),
751 (1 << i)); 750 (1 << i));
752 } 751 }
@@ -758,32 +757,30 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
758 if (bios_connectors[j].valid && (i != j)) { 757 if (bios_connectors[j].valid && (i != j)) {
759 if (bios_connectors[i].line_mux == 758 if (bios_connectors[i].line_mux ==
760 bios_connectors[j].line_mux) { 759 bios_connectors[j].line_mux) {
761 if (((bios_connectors[i]. 760 /* make sure not to combine LVDS */
762 devices & 761 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
763 (ATOM_DEVICE_DFP_SUPPORT)) 762 bios_connectors[i].line_mux = 53;
764 && (bios_connectors[j]. 763 bios_connectors[i].ddc_bus.valid = false;
765 devices & 764 continue;
766 (ATOM_DEVICE_CRT_SUPPORT))) 765 }
767 || 766 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
768 ((bios_connectors[j]. 767 bios_connectors[j].line_mux = 53;
769 devices & 768 bios_connectors[j].ddc_bus.valid = false;
770 (ATOM_DEVICE_DFP_SUPPORT)) 769 continue;
771 && (bios_connectors[i]. 770 }
772 devices & 771 /* combine analog and digital for DVI-I */
773 (ATOM_DEVICE_CRT_SUPPORT)))) { 772 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
774 bios_connectors[i]. 773 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
775 devices |= 774 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
776 bios_connectors[j]. 775 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
777 devices; 776 bios_connectors[i].devices |=
778 bios_connectors[i]. 777 bios_connectors[j].devices;
779 connector_type = 778 bios_connectors[i].connector_type =
780 DRM_MODE_CONNECTOR_DVII; 779 DRM_MODE_CONNECTOR_DVII;
781 if (bios_connectors[j].devices & 780 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
782 (ATOM_DEVICE_DFP_SUPPORT))
783 bios_connectors[i].hpd = 781 bios_connectors[i].hpd =
784 bios_connectors[j].hpd; 782 bios_connectors[j].hpd;
785 bios_connectors[j]. 783 bios_connectors[j].valid = false;
786 valid = false;
787 } 784 }
788 } 785 }
789 } 786 }
@@ -1234,6 +1231,61 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1234 return true; 1231 return true;
1235} 1232}
1236 1233
1234enum radeon_tv_std
1235radeon_atombios_get_tv_info(struct radeon_device *rdev)
1236{
1237 struct radeon_mode_info *mode_info = &rdev->mode_info;
1238 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1239 uint16_t data_offset;
1240 uint8_t frev, crev;
1241 struct _ATOM_ANALOG_TV_INFO *tv_info;
1242 enum radeon_tv_std tv_std = TV_STD_NTSC;
1243
1244 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1245
1246 tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1247
1248 switch (tv_info->ucTV_BootUpDefaultStandard) {
1249 case ATOM_TV_NTSC:
1250 tv_std = TV_STD_NTSC;
1251 DRM_INFO("Default TV standard: NTSC\n");
1252 break;
1253 case ATOM_TV_NTSCJ:
1254 tv_std = TV_STD_NTSC_J;
1255 DRM_INFO("Default TV standard: NTSC-J\n");
1256 break;
1257 case ATOM_TV_PAL:
1258 tv_std = TV_STD_PAL;
1259 DRM_INFO("Default TV standard: PAL\n");
1260 break;
1261 case ATOM_TV_PALM:
1262 tv_std = TV_STD_PAL_M;
1263 DRM_INFO("Default TV standard: PAL-M\n");
1264 break;
1265 case ATOM_TV_PALN:
1266 tv_std = TV_STD_PAL_N;
1267 DRM_INFO("Default TV standard: PAL-N\n");
1268 break;
1269 case ATOM_TV_PALCN:
1270 tv_std = TV_STD_PAL_CN;
1271 DRM_INFO("Default TV standard: PAL-CN\n");
1272 break;
1273 case ATOM_TV_PAL60:
1274 tv_std = TV_STD_PAL_60;
1275 DRM_INFO("Default TV standard: PAL-60\n");
1276 break;
1277 case ATOM_TV_SECAM:
1278 tv_std = TV_STD_SECAM;
1279 DRM_INFO("Default TV standard: SECAM\n");
1280 break;
1281 default:
1282 tv_std = TV_STD_NTSC;
1283 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1284 break;
1285 }
1286 return tv_std;
1287}
1288
1237struct radeon_encoder_tv_dac * 1289struct radeon_encoder_tv_dac *
1238radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1290radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1239{ 1291{
@@ -1269,6 +1321,7 @@ radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1269 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1321 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1270 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1322 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1271 1323
1324 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1272 } 1325 }
1273 return tv_dac; 1326 return tv_dac;
1274} 1327}
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index b062109efbee..812f24dbc2a8 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -62,7 +62,7 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
62} 62}
63 63
64/* 10 khz */ 64/* 10 khz */
65static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev) 65uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
66{ 66{
67 struct radeon_pll *mpll = &rdev->clock.mpll; 67 struct radeon_pll *mpll = &rdev->clock.mpll;
68 uint32_t fb_div, ref_div, post_div, mclk; 68 uint32_t fb_div, ref_div, post_div, mclk;
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index c5021a3445de..fd94dbca33ac 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -634,11 +634,10 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
634 return p_dac; 634 return p_dac;
635} 635}
636 636
637static enum radeon_tv_std 637enum radeon_tv_std
638radeon_combios_get_tv_info(struct radeon_encoder *encoder) 638radeon_combios_get_tv_info(struct radeon_device *rdev)
639{ 639{
640 struct drm_device *dev = encoder->base.dev; 640 struct drm_device *dev = rdev->ddev;
641 struct radeon_device *rdev = dev->dev_private;
642 uint16_t tv_info; 641 uint16_t tv_info;
643 enum radeon_tv_std tv_std = TV_STD_NTSC; 642 enum radeon_tv_std tv_std = TV_STD_NTSC;
644 643
@@ -779,7 +778,7 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
779 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 778 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
780 found = 1; 779 found = 1;
781 } 780 }
782 tv_dac->tv_std = radeon_combios_get_tv_info(encoder); 781 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
783 } 782 }
784 if (!found) { 783 if (!found) {
785 /* then check CRT table */ 784 /* then check CRT table */
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 5eece186e03c..20161567dbff 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -208,6 +208,18 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode
208 drm_mode_set_name(mode); 208 drm_mode_set_name(mode);
209 209
210 DRM_DEBUG("Adding native panel mode %s\n", mode->name); 210 DRM_DEBUG("Adding native panel mode %s\n", mode->name);
211 } else if (native_mode->hdisplay != 0 &&
212 native_mode->vdisplay != 0) {
213 /* mac laptops without an edid */
214 /* Note that this is not necessarily the exact panel mode,
215 * but an approximation based on the cvt formula. For these
216 * systems we should ideally read the mode info out of the
217 * registers or add a mode table, but this works and is much
218 * simpler.
219 */
220 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
221 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
222 DRM_DEBUG("Adding cvt approximation of native panel mode %s\n", mode->name);
211 } 223 }
212 return mode; 224 return mode;
213} 225}
@@ -1171,7 +1183,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1171 1); 1183 1);
1172 drm_connector_attach_property(&radeon_connector->base, 1184 drm_connector_attach_property(&radeon_connector->base,
1173 rdev->mode_info.tv_std_property, 1185 rdev->mode_info.tv_std_property,
1174 1); 1186 radeon_atombios_get_tv_info(rdev));
1175 } 1187 }
1176 break; 1188 break;
1177 case DRM_MODE_CONNECTOR_LVDS: 1189 case DRM_MODE_CONNECTOR_LVDS:
@@ -1315,7 +1327,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1315 1); 1327 1);
1316 drm_connector_attach_property(&radeon_connector->base, 1328 drm_connector_attach_property(&radeon_connector->base,
1317 rdev->mode_info.tv_std_property, 1329 rdev->mode_info.tv_std_property,
1318 1); 1330 radeon_combios_get_tv_info(rdev));
1319 } 1331 }
1320 break; 1332 break;
1321 case DRM_MODE_CONNECTOR_LVDS: 1333 case DRM_MODE_CONNECTOR_LVDS:
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 02bcdb1240c0..7c6848096bcd 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -391,6 +391,12 @@ int radeon_asic_init(struct radeon_device *rdev)
391 /* FIXME: not supported yet */ 391 /* FIXME: not supported yet */
392 return -EINVAL; 392 return -EINVAL;
393 } 393 }
394
395 if (rdev->flags & RADEON_IS_IGP) {
396 rdev->asic->get_memory_clock = NULL;
397 rdev->asic->set_memory_clock = NULL;
398 }
399
394 return 0; 400 return 0;
395} 401}
396 402
@@ -481,6 +487,7 @@ int radeon_atombios_init(struct radeon_device *rdev)
481 atom_card_info->pll_write = cail_pll_write; 487 atom_card_info->pll_write = cail_pll_write;
482 488
483 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 489 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
490 mutex_init(&rdev->mode_info.atom_context->mutex);
484 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 491 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
485 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 492 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
486 return 0; 493 return 0;
@@ -539,9 +546,72 @@ void radeon_agp_disable(struct radeon_device *rdev)
539 } 546 }
540} 547}
541 548
542/* 549void radeon_check_arguments(struct radeon_device *rdev)
543 * Radeon device. 550{
544 */ 551 /* vramlimit must be a power of two */
552 switch (radeon_vram_limit) {
553 case 0:
554 case 4:
555 case 8:
556 case 16:
557 case 32:
558 case 64:
559 case 128:
560 case 256:
561 case 512:
562 case 1024:
563 case 2048:
564 case 4096:
565 break;
566 default:
567 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
568 radeon_vram_limit);
569 radeon_vram_limit = 0;
570 break;
571 }
572 radeon_vram_limit = radeon_vram_limit << 20;
573 /* gtt size must be power of two and greater or equal to 32M */
574 switch (radeon_gart_size) {
575 case 4:
576 case 8:
577 case 16:
578 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
579 radeon_gart_size);
580 radeon_gart_size = 512;
581 break;
582 case 32:
583 case 64:
584 case 128:
585 case 256:
586 case 512:
587 case 1024:
588 case 2048:
589 case 4096:
590 break;
591 default:
592 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
593 radeon_gart_size);
594 radeon_gart_size = 512;
595 break;
596 }
597 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
598 /* AGP mode can only be -1, 1, 2, 4, 8 */
599 switch (radeon_agpmode) {
600 case -1:
601 case 0:
602 case 1:
603 case 2:
604 case 4:
605 case 8:
606 break;
607 default:
608 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
609 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
610 radeon_agpmode = 0;
611 break;
612 }
613}
614
545int radeon_device_init(struct radeon_device *rdev, 615int radeon_device_init(struct radeon_device *rdev,
546 struct drm_device *ddev, 616 struct drm_device *ddev,
547 struct pci_dev *pdev, 617 struct pci_dev *pdev,
@@ -580,9 +650,9 @@ int radeon_device_init(struct radeon_device *rdev,
580 650
581 /* Set asic functions */ 651 /* Set asic functions */
582 r = radeon_asic_init(rdev); 652 r = radeon_asic_init(rdev);
583 if (r) { 653 if (r)
584 return r; 654 return r;
585 } 655 radeon_check_arguments(rdev);
586 656
587 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 657 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
588 radeon_agp_disable(rdev); 658 radeon_agp_disable(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index a133b833e45d..91d72b70abc9 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -739,7 +739,7 @@ static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
739 { TV_STD_SECAM, "secam" }, 739 { TV_STD_SECAM, "secam" },
740}; 740};
741 741
742int radeon_modeset_create_props(struct radeon_device *rdev) 742static int radeon_modeset_create_props(struct radeon_device *rdev)
743{ 743{
744 int i, sz; 744 int i, sz;
745 745
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 0d1d908e5225..ccba95f83d11 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -233,6 +233,8 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
233 if (!ASIC_IS_AVIVO(rdev)) { 233 if (!ASIC_IS_AVIVO(rdev)) {
234 adjusted_mode->hdisplay = mode->hdisplay; 234 adjusted_mode->hdisplay = mode->hdisplay;
235 adjusted_mode->vdisplay = mode->vdisplay; 235 adjusted_mode->vdisplay = mode->vdisplay;
236 adjusted_mode->crtc_hdisplay = mode->hdisplay;
237 adjusted_mode->crtc_vdisplay = mode->vdisplay;
236 } 238 }
237 adjusted_mode->base.id = mode_id; 239 adjusted_mode->base.id = mode_id;
238 } 240 }
@@ -495,9 +497,9 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
495 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 497 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
496 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 498 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
497 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 499 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
498 if (dig->lvds_misc & (1 << 0)) 500 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
499 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 501 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
500 if (dig->lvds_misc & (1 << 1)) 502 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
501 args.v1.ucMisc |= (1 << 1); 503 args.v1.ucMisc |= (1 << 1);
502 } else { 504 } else {
503 if (dig_connector->linkb) 505 if (dig_connector->linkb)
@@ -524,18 +526,18 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
524 args.v2.ucTemporal = 0; 526 args.v2.ucTemporal = 0;
525 args.v2.ucFRC = 0; 527 args.v2.ucFRC = 0;
526 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 528 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
527 if (dig->lvds_misc & (1 << 0)) 529 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
528 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 530 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
529 if (dig->lvds_misc & (1 << 5)) { 531 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
530 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 532 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
531 if (dig->lvds_misc & (1 << 1)) 533 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
532 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 534 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
533 } 535 }
534 if (dig->lvds_misc & (1 << 6)) { 536 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
535 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 537 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
536 if (dig->lvds_misc & (1 << 1)) 538 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
537 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 539 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
538 if (((dig->lvds_misc >> 2) & 0x3) == 2) 540 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
539 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 541 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
540 } 542 }
541 } else { 543 } else {
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index cb4cd97ae39f..4cdd8b4f7549 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -324,7 +324,7 @@ int radeon_fence_driver_init(struct radeon_device *rdev)
324 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); 324 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
325 r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg); 325 r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
326 if (r) { 326 if (r) {
327 DRM_ERROR("Fence failed to get a scratch register."); 327 dev_err(rdev->dev, "fence failed to get scratch register\n");
328 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); 328 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
329 return r; 329 return r;
330 } 330 }
@@ -335,9 +335,10 @@ int radeon_fence_driver_init(struct radeon_device *rdev)
335 INIT_LIST_HEAD(&rdev->fence_drv.signaled); 335 INIT_LIST_HEAD(&rdev->fence_drv.signaled);
336 rdev->fence_drv.count_timeout = 0; 336 rdev->fence_drv.count_timeout = 0;
337 init_waitqueue_head(&rdev->fence_drv.queue); 337 init_waitqueue_head(&rdev->fence_drv.queue);
338 rdev->fence_drv.initialized = true;
338 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); 339 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
339 if (radeon_debugfs_fence_init(rdev)) { 340 if (radeon_debugfs_fence_init(rdev)) {
340 DRM_ERROR("Failed to register debugfs file for fence !\n"); 341 dev_err(rdev->dev, "fence debugfs file creation failed\n");
341 } 342 }
342 return 0; 343 return 0;
343} 344}
@@ -346,11 +347,13 @@ void radeon_fence_driver_fini(struct radeon_device *rdev)
346{ 347{
347 unsigned long irq_flags; 348 unsigned long irq_flags;
348 349
350 if (!rdev->fence_drv.initialized)
351 return;
349 wake_up_all(&rdev->fence_drv.queue); 352 wake_up_all(&rdev->fence_drv.queue);
350 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); 353 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
351 radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg); 354 radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
352 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); 355 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
353 DRM_INFO("radeon: fence finalized\n"); 356 rdev->fence_drv.initialized = false;
354} 357}
355 358
356 359
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index b82ede98e152..cc27485a07ad 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -43,8 +43,7 @@ static void radeon_overscan_setup(struct drm_crtc *crtc,
43} 43}
44 44
45static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 45static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
46 struct drm_display_mode *mode, 46 struct drm_display_mode *mode)
47 struct drm_display_mode *adjusted_mode)
48{ 47{
49 struct drm_device *dev = crtc->dev; 48 struct drm_device *dev = crtc->dev;
50 struct radeon_device *rdev = dev->dev_private; 49 struct radeon_device *rdev = dev->dev_private;
@@ -1059,7 +1058,7 @@ static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1059 radeon_set_pll(crtc, adjusted_mode); 1058 radeon_set_pll(crtc, adjusted_mode);
1060 radeon_overscan_setup(crtc, adjusted_mode); 1059 radeon_overscan_setup(crtc, adjusted_mode);
1061 if (radeon_crtc->crtc_id == 0) { 1060 if (radeon_crtc->crtc_id == 0) {
1062 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode); 1061 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1063 } else { 1062 } else {
1064 if (radeon_crtc->rmx_type != RMX_OFF) { 1063 if (radeon_crtc->rmx_type != RMX_OFF) {
1065 /* FIXME: only first crtc has rmx what should we 1064 /* FIXME: only first crtc has rmx what should we
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index df00515e81fa..981508ff7037 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -207,6 +207,8 @@ static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
207 *adjusted_mode = *native_mode; 207 *adjusted_mode = *native_mode;
208 adjusted_mode->hdisplay = mode->hdisplay; 208 adjusted_mode->hdisplay = mode->hdisplay;
209 adjusted_mode->vdisplay = mode->vdisplay; 209 adjusted_mode->vdisplay = mode->vdisplay;
210 adjusted_mode->crtc_hdisplay = mode->hdisplay;
211 adjusted_mode->crtc_vdisplay = mode->vdisplay;
210 adjusted_mode->base.id = mode_id; 212 adjusted_mode->base.id = mode_id;
211 } 213 }
212 214
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 3dcbe130c422..402369db5ba0 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -88,6 +88,7 @@ enum radeon_tv_std {
88 TV_STD_SCART_PAL, 88 TV_STD_SCART_PAL,
89 TV_STD_SECAM, 89 TV_STD_SECAM,
90 TV_STD_PAL_CN, 90 TV_STD_PAL_CN,
91 TV_STD_PAL_N,
91}; 92};
92 93
93/* radeon gpio-based i2c 94/* radeon gpio-based i2c
@@ -395,6 +396,11 @@ struct radeon_framebuffer {
395 struct drm_gem_object *obj; 396 struct drm_gem_object *obj;
396}; 397};
397 398
399extern enum radeon_tv_std
400radeon_combios_get_tv_info(struct radeon_device *rdev);
401extern enum radeon_tv_std
402radeon_atombios_get_tv_info(struct radeon_device *rdev);
403
398extern void radeon_connector_hotplug(struct drm_connector *connector); 404extern void radeon_connector_hotplug(struct drm_connector *connector);
399extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 405extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
400extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, 406extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 7bed4122528c..a00450743d60 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -494,6 +494,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
494 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 494 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
495 return r; 495 return r;
496 } 496 }
497 rdev->mman.initialized = true;
497 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 498 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
498 rdev->mc.real_vram_size >> PAGE_SHIFT); 499 rdev->mc.real_vram_size >> PAGE_SHIFT);
499 if (r) { 500 if (r) {
@@ -541,6 +542,8 @@ void radeon_ttm_fini(struct radeon_device *rdev)
541{ 542{
542 int r; 543 int r;
543 544
545 if (!rdev->mman.initialized)
546 return;
544 if (rdev->stollen_vga_memory) { 547 if (rdev->stollen_vga_memory) {
545 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 548 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
546 if (r == 0) { 549 if (r == 0) {
@@ -554,6 +557,7 @@ void radeon_ttm_fini(struct radeon_device *rdev)
554 ttm_bo_device_release(&rdev->mman.bdev); 557 ttm_bo_device_release(&rdev->mman.bdev);
555 radeon_gart_fini(rdev); 558 radeon_gart_fini(rdev);
556 radeon_ttm_global_fini(rdev); 559 radeon_ttm_global_fini(rdev);
560 rdev->mman.initialized = false;
557 DRM_INFO("radeon: ttm finalized\n"); 561 DRM_INFO("radeon: ttm finalized\n");
558} 562}
559 563
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 02:30:22 -0500