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authorMichael Chan <mchan@broadcom.com>2007-04-24 18:35:53 -0400
committerDavid S. Miller <davem@davemloft.net>2007-04-24 18:35:53 -0400
commit68c9f75a0539db583db074059d54deb607d1a475 (patch)
tree7c55bcd720a3189c61d40dad97638e232843fd0e /drivers
parent0bcbc92629044b5403719f77fb015e9005b1f504 (diff)
[BNX2]: Fix occasional NETDEV WATCHDOG on 5709.
Tweak a register setting to prevent the tx mailbox from halting. Update version to 1.5.8. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2.c7
-rw-r--r--drivers/net/bnx2.h1
2 files changed, 6 insertions, 2 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 0b7aded8dcfd..e85f5ec48f96 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -54,8 +54,8 @@
54 54
55#define DRV_MODULE_NAME "bnx2" 55#define DRV_MODULE_NAME "bnx2"
56#define PFX DRV_MODULE_NAME ": " 56#define PFX DRV_MODULE_NAME ": "
57#define DRV_MODULE_VERSION "1.5.7" 57#define DRV_MODULE_VERSION "1.5.8"
58#define DRV_MODULE_RELDATE "March 29, 2007" 58#define DRV_MODULE_RELDATE "April 24, 2007"
59 59
60#define RUN_AT(x) (jiffies + (x)) 60#define RUN_AT(x) (jiffies + (x))
61 61
@@ -3421,6 +3421,9 @@ bnx2_init_chip(struct bnx2 *bp)
3421 val = REG_RD(bp, BNX2_MQ_CONFIG); 3421 val = REG_RD(bp, BNX2_MQ_CONFIG);
3422 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3422 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3423 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3423 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3424 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
3425 val |= BNX2_MQ_CONFIG_HALT_DIS;
3426
3424 REG_WR(bp, BNX2_MQ_CONFIG, val); 3427 REG_WR(bp, BNX2_MQ_CONFIG, val);
3425 3428
3426 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 3429 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index ccbdf81c6599..878eee58f12a 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -6518,6 +6518,7 @@ struct bnx2 {
6518#define CHIP_ID_5708_B0 0x57081000 6518#define CHIP_ID_5708_B0 0x57081000
6519#define CHIP_ID_5708_B1 0x57081010 6519#define CHIP_ID_5708_B1 0x57081010
6520#define CHIP_ID_5709_A0 0x57090000 6520#define CHIP_ID_5709_A0 0x57090000
6521#define CHIP_ID_5709_A1 0x57090010
6521 6522
6522#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf) 6523#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf)
6523 6524