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authorZou Nan hai <nanhai.zou@intel.com>2010-06-25 01:40:22 -0400
committerEric Anholt <eric@anholt.net>2010-08-09 17:13:39 -0400
commitce17178094f368d9e3f39b2cb4303da5ed633dd4 (patch)
tree81b0745ea43d217cea9527ed4f67f12de2ac1b52 /drivers
parent8545423a912cf500009cbadfae57f706cf2b28e8 (diff)
drm/i915: Enable RC6 on Ironlake.
RC6 allows the GPU to enter a lower power state when the GPU is idle. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> [anholt: Fixed the !renderctx error path to actually not enable RC6.] Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4668e9bf67d8..149c18b7c375 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5753,7 +5753,8 @@ void intel_init_clock_gating(struct drm_device *dev)
5753 ILK_DPFC_DIS2 | 5753 ILK_DPFC_DIS2 |
5754 ILK_CLK_FBC); 5754 ILK_CLK_FBC);
5755 } 5755 }
5756 return; 5756 if (IS_GEN6(dev))
5757 return;
5757 } else if (IS_G4X(dev)) { 5758 } else if (IS_G4X(dev)) {
5758 uint32_t dspclk_gate; 5759 uint32_t dspclk_gate;
5759 I915_WRITE(RENCLK_GATE_D1, 0); 5760 I915_WRITE(RENCLK_GATE_D1, 0);
@@ -5814,9 +5815,11 @@ void intel_init_clock_gating(struct drm_device *dev)
5814 OUT_RING(MI_FLUSH); 5815 OUT_RING(MI_FLUSH);
5815 ADVANCE_LP_RING(); 5816 ADVANCE_LP_RING();
5816 } 5817 }
5817 } else 5818 } else {
5818 DRM_DEBUG_KMS("Failed to allocate render context." 5819 DRM_DEBUG_KMS("Failed to allocate render context."
5819 "Disable RC6\n"); 5820 "Disable RC6\n");
5821 return;
5822 }
5820 } 5823 }
5821 5824
5822 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { 5825 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {