diff options
author | Devin Heitmueller <dheitmueller@kernellabs.com> | 2011-03-12 23:54:02 -0500 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2011-05-20 06:26:18 -0400 |
commit | ba96796544f3bfc53a3269f0cf65651e349f8033 (patch) | |
tree | d7012fa3524ce3803055fd83f6163fa1fbb0cc9b /drivers | |
parent | 949a12e3a87281e38d3520823e7e171bbe45b448 (diff) |
[media] drxd: provide ability to control rs byte
Provide the ability for the board configuration to specify whether to insert
the RS byte into the TS interconnect to the bridge, while not required for
the ngene in fact is required for the em28xx.
Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/media/dvb/frontends/drxd.h | 1 | ||||
-rw-r--r-- | drivers/media/dvb/frontends/drxd_hard.c | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h index 9b11dc835c44..81093b9b1568 100644 --- a/drivers/media/dvb/frontends/drxd.h +++ b/drivers/media/dvb/frontends/drxd.h | |||
@@ -38,6 +38,7 @@ struct drxd_config | |||
38 | #define DRXD_PLL_MT3X0823 2 | 38 | #define DRXD_PLL_MT3X0823 2 |
39 | 39 | ||
40 | u32 clock; | 40 | u32 clock; |
41 | u8 insert_rs_byte; | ||
41 | 42 | ||
42 | u8 demod_address; | 43 | u8 demod_address; |
43 | u8 demoda_address; | 44 | u8 demoda_address; |
diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c index c4835b32e6d9..994195fe9fbb 100644 --- a/drivers/media/dvb/frontends/drxd_hard.c +++ b/drivers/media/dvb/frontends/drxd_hard.c | |||
@@ -2449,7 +2449,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) | |||
2449 | state->tuner_mirrors=0; | 2449 | state->tuner_mirrors=0; |
2450 | 2450 | ||
2451 | /* modify MPEG output attributes */ | 2451 | /* modify MPEG output attributes */ |
2452 | state->insert_rs_byte = 0; | 2452 | state->insert_rs_byte = state->config.insert_rs_byte; |
2453 | state->enable_parallel = (ulSerialMode != 1); | 2453 | state->enable_parallel = (ulSerialMode != 1); |
2454 | 2454 | ||
2455 | /* Timing div, 250ns/Psys */ | 2455 | /* Timing div, 250ns/Psys */ |