diff options
author | Dmitry Torokhov <dtor_core@ameritech.net> | 2005-09-06 18:19:19 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-09-07 19:57:57 -0400 |
commit | 98b7777331d4344821e900040da5d1d3016d9e67 (patch) | |
tree | d41fb0fca1dc8c8cc17049b2efb11a02c7f3aac1 /drivers | |
parent | 527b6af4133f433542a875dea7a24d58f8871d4b (diff) |
[PATCH] smsc-ircc2: formatting fixes
IRDA: smsc-ircc2 - some formatting changes for better readability.
Signed-off-by: Dmitry Torokhov <dtor@mail.ru>
Cc: Jean Tourrilhes <jt@hpl.hp.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/irda/smsc-ircc2.c | 643 |
1 files changed, 317 insertions, 326 deletions
diff --git a/drivers/net/irda/smsc-ircc2.c b/drivers/net/irda/smsc-ircc2.c index 806e252b2ea0..ab3ff0cd0431 100644 --- a/drivers/net/irda/smsc-ircc2.c +++ b/drivers/net/irda/smsc-ircc2.c | |||
@@ -68,6 +68,36 @@ | |||
68 | #include "smsc-ircc2.h" | 68 | #include "smsc-ircc2.h" |
69 | #include "smsc-sio.h" | 69 | #include "smsc-sio.h" |
70 | 70 | ||
71 | |||
72 | MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>"); | ||
73 | MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver"); | ||
74 | MODULE_LICENSE("GPL"); | ||
75 | |||
76 | |||
77 | static int ircc_dma = 255; | ||
78 | module_param(ircc_dma, int, 0); | ||
79 | MODULE_PARM_DESC(ircc_dma, "DMA channel"); | ||
80 | |||
81 | static int ircc_irq = 255; | ||
82 | module_param(ircc_irq, int, 0); | ||
83 | MODULE_PARM_DESC(ircc_irq, "IRQ line"); | ||
84 | |||
85 | static int ircc_fir; | ||
86 | module_param(ircc_fir, int, 0); | ||
87 | MODULE_PARM_DESC(ircc_fir, "FIR Base Address"); | ||
88 | |||
89 | static int ircc_sir; | ||
90 | module_param(ircc_sir, int, 0); | ||
91 | MODULE_PARM_DESC(ircc_sir, "SIR Base Address"); | ||
92 | |||
93 | static int ircc_cfg; | ||
94 | module_param(ircc_cfg, int, 0); | ||
95 | MODULE_PARM_DESC(ircc_cfg, "Configuration register base address"); | ||
96 | |||
97 | static int ircc_transceiver; | ||
98 | module_param(ircc_transceiver, int, 0); | ||
99 | MODULE_PARM_DESC(ircc_transceiver, "Transceiver type"); | ||
100 | |||
71 | /* Types */ | 101 | /* Types */ |
72 | 102 | ||
73 | struct smsc_transceiver { | 103 | struct smsc_transceiver { |
@@ -136,7 +166,7 @@ static const char *driver_name = "smsc-ircc2"; | |||
136 | #define DIM(x) (sizeof(x)/(sizeof(*(x)))) | 166 | #define DIM(x) (sizeof(x)/(sizeof(*(x)))) |
137 | #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600 | 167 | #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600 |
138 | #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1 | 168 | #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1 |
139 | #define SMSC_IRCC2_C_NET_TIMEOUT 0 | 169 | #define SMSC_IRCC2_C_NET_TIMEOUT 0 |
140 | #define SMSC_IRCC2_C_SIR_STOP 0 | 170 | #define SMSC_IRCC2_C_SIR_STOP 0 |
141 | 171 | ||
142 | /* Prototypes */ | 172 | /* Prototypes */ |
@@ -179,7 +209,7 @@ static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self); | |||
179 | 209 | ||
180 | /* Probing */ | 210 | /* Probing */ |
181 | static int __init smsc_ircc_look_for_chips(void); | 211 | static int __init smsc_ircc_look_for_chips(void); |
182 | static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base,u8 reg,const smsc_chip_t *chip,char *type); | 212 | static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const smsc_chip_t *chip, char *type); |
183 | static int __init smsc_superio_flat(const smsc_chip_t *chips, unsigned short cfg_base, char *type); | 213 | static int __init smsc_superio_flat(const smsc_chip_t *chips, unsigned short cfg_base, char *type); |
184 | static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cfg_base, char *type); | 214 | static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cfg_base, char *type); |
185 | static int __init smsc_superio_fdc(unsigned short cfg_base); | 215 | static int __init smsc_superio_fdc(unsigned short cfg_base); |
@@ -203,12 +233,12 @@ static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data); | |||
203 | 233 | ||
204 | /* Transceivers for SMSC-ircc */ | 234 | /* Transceivers for SMSC-ircc */ |
205 | 235 | ||
206 | static smsc_transceiver_t smsc_transceivers[]= | 236 | static smsc_transceiver_t smsc_transceivers[] = |
207 | { | 237 | { |
208 | { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800}, | 238 | { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 }, |
209 | { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select}, | 239 | { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select }, |
210 | { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc}, | 240 | { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc }, |
211 | { NULL, NULL} | 241 | { NULL, NULL } |
212 | }; | 242 | }; |
213 | #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (DIM(smsc_transceivers)-1) | 243 | #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (DIM(smsc_transceivers)-1) |
214 | 244 | ||
@@ -221,7 +251,7 @@ static smsc_transceiver_t smsc_transceivers[]= | |||
221 | #define FIR 4 /* SuperIO Chip has fast IRDA */ | 251 | #define FIR 4 /* SuperIO Chip has fast IRDA */ |
222 | #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */ | 252 | #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */ |
223 | 253 | ||
224 | static smsc_chip_t __initdata fdc_chips_flat[]= | 254 | static smsc_chip_t __initdata fdc_chips_flat[] = |
225 | { | 255 | { |
226 | /* Base address 0x3f0 or 0x370 */ | 256 | /* Base address 0x3f0 or 0x370 */ |
227 | { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */ | 257 | { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */ |
@@ -235,7 +265,7 @@ static smsc_chip_t __initdata fdc_chips_flat[]= | |||
235 | { NULL } | 265 | { NULL } |
236 | }; | 266 | }; |
237 | 267 | ||
238 | static smsc_chip_t __initdata fdc_chips_paged[]= | 268 | static smsc_chip_t __initdata fdc_chips_paged[] = |
239 | { | 269 | { |
240 | /* Base address 0x3f0 or 0x370 */ | 270 | /* Base address 0x3f0 or 0x370 */ |
241 | { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 }, | 271 | { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 }, |
@@ -254,7 +284,7 @@ static smsc_chip_t __initdata fdc_chips_paged[]= | |||
254 | { NULL } | 284 | { NULL } |
255 | }; | 285 | }; |
256 | 286 | ||
257 | static smsc_chip_t __initdata lpc_chips_flat[]= | 287 | static smsc_chip_t __initdata lpc_chips_flat[] = |
258 | { | 288 | { |
259 | /* Base address 0x2E or 0x4E */ | 289 | /* Base address 0x2E or 0x4E */ |
260 | { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 }, | 290 | { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 }, |
@@ -262,7 +292,7 @@ static smsc_chip_t __initdata lpc_chips_flat[]= | |||
262 | { NULL } | 292 | { NULL } |
263 | }; | 293 | }; |
264 | 294 | ||
265 | static smsc_chip_t __initdata lpc_chips_paged[]= | 295 | static smsc_chip_t __initdata lpc_chips_paged[] = |
266 | { | 296 | { |
267 | /* Base address 0x2E or 0x4E */ | 297 | /* Base address 0x2E or 0x4E */ |
268 | { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 }, | 298 | { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 }, |
@@ -281,33 +311,25 @@ static smsc_chip_t __initdata lpc_chips_paged[]= | |||
281 | #define SMSCSIO_TYPE_FLAT 4 | 311 | #define SMSCSIO_TYPE_FLAT 4 |
282 | #define SMSCSIO_TYPE_PAGED 8 | 312 | #define SMSCSIO_TYPE_PAGED 8 |
283 | 313 | ||
284 | static smsc_chip_address_t __initdata possible_addresses[]= | 314 | static smsc_chip_address_t __initdata possible_addresses[] = |
285 | { | 315 | { |
286 | {0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED}, | 316 | { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, |
287 | {0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED}, | 317 | { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, |
288 | {0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED}, | 318 | { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, |
289 | {0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED}, | 319 | { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, |
290 | {0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED}, | 320 | { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, |
291 | {0,0} | 321 | { 0, 0 } |
292 | }; | 322 | }; |
293 | 323 | ||
294 | /* Globals */ | 324 | /* Globals */ |
295 | 325 | ||
296 | static struct smsc_ircc_cb *dev_self[] = { NULL, NULL}; | 326 | static struct smsc_ircc_cb *dev_self[] = { NULL, NULL }; |
297 | 327 | static unsigned short dev_count; | |
298 | static int ircc_irq=255; | ||
299 | static int ircc_dma=255; | ||
300 | static int ircc_fir=0; | ||
301 | static int ircc_sir=0; | ||
302 | static int ircc_cfg=0; | ||
303 | static int ircc_transceiver=0; | ||
304 | |||
305 | static unsigned short dev_count=0; | ||
306 | 328 | ||
307 | static inline void register_bank(int iobase, int bank) | 329 | static inline void register_bank(int iobase, int bank) |
308 | { | 330 | { |
309 | outb(((inb(iobase+IRCC_MASTER) & 0xf0) | (bank & 0x07)), | 331 | outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)), |
310 | iobase+IRCC_MASTER); | 332 | iobase + IRCC_MASTER); |
311 | } | 333 | } |
312 | 334 | ||
313 | 335 | ||
@@ -327,13 +349,13 @@ static inline void register_bank(int iobase, int bank) | |||
327 | */ | 349 | */ |
328 | static int __init smsc_ircc_init(void) | 350 | static int __init smsc_ircc_init(void) |
329 | { | 351 | { |
330 | int ret=-ENODEV; | 352 | int ret = -ENODEV; |
331 | 353 | ||
332 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | 354 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); |
333 | 355 | ||
334 | dev_count=0; | 356 | dev_count = 0; |
335 | 357 | ||
336 | if ((ircc_fir>0)&&(ircc_sir>0)) { | 358 | if (ircc_fir > 0 && ircc_sir > 0) { |
337 | IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir); | 359 | IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir); |
338 | IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir); | 360 | IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir); |
339 | 361 | ||
@@ -344,7 +366,7 @@ static int __init smsc_ircc_init(void) | |||
344 | } | 366 | } |
345 | 367 | ||
346 | /* try user provided configuration register base address */ | 368 | /* try user provided configuration register base address */ |
347 | if (ircc_cfg>0) { | 369 | if (ircc_cfg > 0) { |
348 | IRDA_MESSAGE(" Overriding configuration address 0x%04x\n", | 370 | IRDA_MESSAGE(" Overriding configuration address 0x%04x\n", |
349 | ircc_cfg); | 371 | ircc_cfg); |
350 | if (!smsc_superio_fdc(ircc_cfg)) | 372 | if (!smsc_superio_fdc(ircc_cfg)) |
@@ -353,7 +375,8 @@ static int __init smsc_ircc_init(void) | |||
353 | ret = 0; | 375 | ret = 0; |
354 | } | 376 | } |
355 | 377 | ||
356 | if(smsc_ircc_look_for_chips()>0) ret = 0; | 378 | if (smsc_ircc_look_for_chips() > 0) |
379 | ret = 0; | ||
357 | 380 | ||
358 | return ret; | 381 | return ret; |
359 | } | 382 | } |
@@ -373,7 +396,7 @@ static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u | |||
373 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | 396 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); |
374 | 397 | ||
375 | err = smsc_ircc_present(fir_base, sir_base); | 398 | err = smsc_ircc_present(fir_base, sir_base); |
376 | if(err) | 399 | if (err) |
377 | goto err_out; | 400 | goto err_out; |
378 | 401 | ||
379 | err = -ENOMEM; | 402 | err = -ENOMEM; |
@@ -396,7 +419,7 @@ static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u | |||
396 | dev->hard_start_xmit = smsc_ircc_hard_xmit_sir; | 419 | dev->hard_start_xmit = smsc_ircc_hard_xmit_sir; |
397 | #if SMSC_IRCC2_C_NET_TIMEOUT | 420 | #if SMSC_IRCC2_C_NET_TIMEOUT |
398 | dev->tx_timeout = smsc_ircc_timeout; | 421 | dev->tx_timeout = smsc_ircc_timeout; |
399 | dev->watchdog_timeo = HZ*2; /* Allow enough time for speed change */ | 422 | dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */ |
400 | #endif | 423 | #endif |
401 | dev->open = smsc_ircc_net_open; | 424 | dev->open = smsc_ircc_net_open; |
402 | dev->stop = smsc_ircc_net_close; | 425 | dev->stop = smsc_ircc_net_close; |
@@ -444,19 +467,17 @@ static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u | |||
444 | self->rx_buff.data = self->rx_buff.head; | 467 | self->rx_buff.data = self->rx_buff.head; |
445 | 468 | ||
446 | smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq); | 469 | smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq); |
447 | |||
448 | smsc_ircc_setup_qos(self); | 470 | smsc_ircc_setup_qos(self); |
449 | |||
450 | smsc_ircc_init_chip(self); | 471 | smsc_ircc_init_chip(self); |
451 | 472 | ||
452 | if(ircc_transceiver > 0 && | 473 | if (ircc_transceiver > 0 && |
453 | ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS) | 474 | ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS) |
454 | self->transceiver = ircc_transceiver; | 475 | self->transceiver = ircc_transceiver; |
455 | else | 476 | else |
456 | smsc_ircc_probe_transceiver(self); | 477 | smsc_ircc_probe_transceiver(self); |
457 | 478 | ||
458 | err = register_netdev(self->netdev); | 479 | err = register_netdev(self->netdev); |
459 | if(err) { | 480 | if (err) { |
460 | IRDA_ERROR("%s, Network device registration failed!\n", | 481 | IRDA_ERROR("%s, Network device registration failed!\n", |
461 | driver_name); | 482 | driver_name); |
462 | goto err_out4; | 483 | goto err_out4; |
@@ -469,6 +490,7 @@ static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u | |||
469 | IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name); | 490 | IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name); |
470 | 491 | ||
471 | return 0; | 492 | return 0; |
493 | |||
472 | err_out4: | 494 | err_out4: |
473 | dma_free_coherent(NULL, self->tx_buff.truesize, | 495 | dma_free_coherent(NULL, self->tx_buff.truesize, |
474 | self->tx_buff.head, self->tx_buff_dma); | 496 | self->tx_buff.head, self->tx_buff_dma); |
@@ -511,16 +533,16 @@ static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base) | |||
511 | 533 | ||
512 | register_bank(fir_base, 3); | 534 | register_bank(fir_base, 3); |
513 | 535 | ||
514 | high = inb(fir_base+IRCC_ID_HIGH); | 536 | high = inb(fir_base + IRCC_ID_HIGH); |
515 | low = inb(fir_base+IRCC_ID_LOW); | 537 | low = inb(fir_base + IRCC_ID_LOW); |
516 | chip = inb(fir_base+IRCC_CHIP_ID); | 538 | chip = inb(fir_base + IRCC_CHIP_ID); |
517 | version = inb(fir_base+IRCC_VERSION); | 539 | version = inb(fir_base + IRCC_VERSION); |
518 | config = inb(fir_base+IRCC_INTERFACE); | 540 | config = inb(fir_base + IRCC_INTERFACE); |
519 | dma = config & IRCC_INTERFACE_DMA_MASK; | 541 | dma = config & IRCC_INTERFACE_DMA_MASK; |
520 | irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; | 542 | irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; |
521 | 543 | ||
522 | if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) { | 544 | if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) { |
523 | IRDA_WARNING("%s(), addr 0x%04x - no device found!\n", | 545 | IRDA_WARNING("%s(), addr 0x%04x - no device found!\n", |
524 | __FUNCTION__, fir_base); | 546 | __FUNCTION__, fir_base); |
525 | goto out3; | 547 | goto out3; |
526 | } | 548 | } |
@@ -529,6 +551,7 @@ static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base) | |||
529 | chip & 0x0f, version, fir_base, sir_base, dma, irq); | 551 | chip & 0x0f, version, fir_base, sir_base, dma, irq); |
530 | 552 | ||
531 | return 0; | 553 | return 0; |
554 | |||
532 | out3: | 555 | out3: |
533 | release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); | 556 | release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); |
534 | out2: | 557 | out2: |
@@ -550,9 +573,9 @@ static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, | |||
550 | unsigned char config, chip_dma, chip_irq; | 573 | unsigned char config, chip_dma, chip_irq; |
551 | 574 | ||
552 | register_bank(fir_base, 3); | 575 | register_bank(fir_base, 3); |
553 | config = inb(fir_base+IRCC_INTERFACE); | 576 | config = inb(fir_base + IRCC_INTERFACE); |
554 | chip_dma = config & IRCC_INTERFACE_DMA_MASK; | 577 | chip_dma = config & IRCC_INTERFACE_DMA_MASK; |
555 | chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; | 578 | chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; |
556 | 579 | ||
557 | self->io.fir_base = fir_base; | 580 | self->io.fir_base = fir_base; |
558 | self->io.sir_base = sir_base; | 581 | self->io.sir_base = sir_base; |
@@ -566,8 +589,7 @@ static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, | |||
566 | IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n", | 589 | IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n", |
567 | driver_name, chip_irq, irq); | 590 | driver_name, chip_irq, irq); |
568 | self->io.irq = irq; | 591 | self->io.irq = irq; |
569 | } | 592 | } else |
570 | else | ||
571 | self->io.irq = chip_irq; | 593 | self->io.irq = chip_irq; |
572 | 594 | ||
573 | if (dma < 255) { | 595 | if (dma < 255) { |
@@ -575,8 +597,7 @@ static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, | |||
575 | IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n", | 597 | IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n", |
576 | driver_name, chip_dma, dma); | 598 | driver_name, chip_dma, dma); |
577 | self->io.dma = dma; | 599 | self->io.dma = dma; |
578 | } | 600 | } else |
579 | else | ||
580 | self->io.dma = chip_dma; | 601 | self->io.dma = chip_dma; |
581 | 602 | ||
582 | } | 603 | } |
@@ -610,41 +631,41 @@ static void smsc_ircc_init_chip(struct smsc_ircc_cb *self) | |||
610 | { | 631 | { |
611 | int iobase, ir_mode, ctrl, fast; | 632 | int iobase, ir_mode, ctrl, fast; |
612 | 633 | ||
613 | IRDA_ASSERT( self != NULL, return; ); | 634 | IRDA_ASSERT(self != NULL, return;); |
614 | iobase = self->io.fir_base; | ||
615 | 635 | ||
636 | iobase = self->io.fir_base; | ||
616 | ir_mode = IRCC_CFGA_IRDA_SIR_A; | 637 | ir_mode = IRCC_CFGA_IRDA_SIR_A; |
617 | ctrl = 0; | 638 | ctrl = 0; |
618 | fast = 0; | 639 | fast = 0; |
619 | 640 | ||
620 | register_bank(iobase, 0); | 641 | register_bank(iobase, 0); |
621 | outb(IRCC_MASTER_RESET, iobase+IRCC_MASTER); | 642 | outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); |
622 | outb(0x00, iobase+IRCC_MASTER); | 643 | outb(0x00, iobase + IRCC_MASTER); |
623 | 644 | ||
624 | register_bank(iobase, 1); | 645 | register_bank(iobase, 1); |
625 | outb(((inb(iobase+IRCC_SCE_CFGA) & 0x87) | ir_mode), | 646 | outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | ir_mode), |
626 | iobase+IRCC_SCE_CFGA); | 647 | iobase + IRCC_SCE_CFGA); |
627 | 648 | ||
628 | #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */ | 649 | #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */ |
629 | outb(((inb(iobase+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), | 650 | outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), |
630 | iobase+IRCC_SCE_CFGB); | 651 | iobase + IRCC_SCE_CFGB); |
631 | #else | 652 | #else |
632 | outb(((inb(iobase+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), | 653 | outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), |
633 | iobase+IRCC_SCE_CFGB); | 654 | iobase + IRCC_SCE_CFGB); |
634 | #endif | 655 | #endif |
635 | (void) inb(iobase+IRCC_FIFO_THRESHOLD); | 656 | (void) inb(iobase + IRCC_FIFO_THRESHOLD); |
636 | outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase+IRCC_FIFO_THRESHOLD); | 657 | outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD); |
637 | 658 | ||
638 | register_bank(iobase, 4); | 659 | register_bank(iobase, 4); |
639 | outb((inb(iobase+IRCC_CONTROL) & 0x30) | ctrl, iobase+IRCC_CONTROL); | 660 | outb((inb(iobase + IRCC_CONTROL) & 0x30) | ctrl, iobase + IRCC_CONTROL); |
640 | 661 | ||
641 | register_bank(iobase, 0); | 662 | register_bank(iobase, 0); |
642 | outb(fast, iobase+IRCC_LCR_A); | 663 | outb(fast, iobase + IRCC_LCR_A); |
643 | 664 | ||
644 | smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); | 665 | smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); |
645 | 666 | ||
646 | /* Power on device */ | 667 | /* Power on device */ |
647 | outb(0x00, iobase+IRCC_MASTER); | 668 | outb(0x00, iobase + IRCC_MASTER); |
648 | } | 669 | } |
649 | 670 | ||
650 | /* | 671 | /* |
@@ -770,7 +791,7 @@ int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev) | |||
770 | 791 | ||
771 | /* Check if we need to change the speed */ | 792 | /* Check if we need to change the speed */ |
772 | speed = irda_get_next_speed(skb); | 793 | speed = irda_get_next_speed(skb); |
773 | if ((speed != self->io.speed) && (speed != -1)) { | 794 | if (speed != self->io.speed && speed != -1) { |
774 | /* Check for empty frame */ | 795 | /* Check for empty frame */ |
775 | if (!skb->len) { | 796 | if (!skb->len) { |
776 | /* | 797 | /* |
@@ -787,9 +808,8 @@ int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev) | |||
787 | spin_unlock_irqrestore(&self->lock, flags); | 808 | spin_unlock_irqrestore(&self->lock, flags); |
788 | dev_kfree_skb(skb); | 809 | dev_kfree_skb(skb); |
789 | return 0; | 810 | return 0; |
790 | } else { | ||
791 | self->new_speed = speed; | ||
792 | } | 811 | } |
812 | self->new_speed = speed; | ||
793 | } | 813 | } |
794 | 814 | ||
795 | /* Init tx buffer */ | 815 | /* Init tx buffer */ |
@@ -802,7 +822,7 @@ int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev) | |||
802 | self->stats.tx_bytes += self->tx_buff.len; | 822 | self->stats.tx_bytes += self->tx_buff.len; |
803 | 823 | ||
804 | /* Turn on transmit finished interrupt. Will fire immediately! */ | 824 | /* Turn on transmit finished interrupt. Will fire immediately! */ |
805 | outb(UART_IER_THRI, iobase+UART_IER); | 825 | outb(UART_IER_THRI, iobase + UART_IER); |
806 | 826 | ||
807 | spin_unlock_irqrestore(&self->lock, flags); | 827 | spin_unlock_irqrestore(&self->lock, flags); |
808 | 828 | ||
@@ -826,7 +846,7 @@ static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed) | |||
826 | 846 | ||
827 | self->io.speed = speed; | 847 | self->io.speed = speed; |
828 | 848 | ||
829 | switch(speed) { | 849 | switch (speed) { |
830 | default: | 850 | default: |
831 | case 576000: | 851 | case 576000: |
832 | ir_mode = IRCC_CFGA_IRDA_HDLC; | 852 | ir_mode = IRCC_CFGA_IRDA_HDLC; |
@@ -853,14 +873,14 @@ static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed) | |||
853 | Now in tranceiver! | 873 | Now in tranceiver! |
854 | /* This causes an interrupt */ | 874 | /* This causes an interrupt */ |
855 | register_bank(fir_base, 0); | 875 | register_bank(fir_base, 0); |
856 | outb((inb(fir_base+IRCC_LCR_A) & 0xbf) | fast, fir_base+IRCC_LCR_A); | 876 | outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A); |
857 | #endif | 877 | #endif |
858 | 878 | ||
859 | register_bank(fir_base, 1); | 879 | register_bank(fir_base, 1); |
860 | outb(((inb(fir_base+IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base+IRCC_SCE_CFGA); | 880 | outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA); |
861 | 881 | ||
862 | register_bank(fir_base, 4); | 882 | register_bank(fir_base, 4); |
863 | outb((inb(fir_base+IRCC_CONTROL) & 0x30) | ctrl, fir_base+IRCC_CONTROL); | 883 | outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL); |
864 | } | 884 | } |
865 | 885 | ||
866 | /* | 886 | /* |
@@ -888,28 +908,28 @@ static void smsc_ircc_fir_start(struct smsc_ircc_cb *self) | |||
888 | dev->hard_start_xmit = smsc_ircc_hard_xmit_fir; | 908 | dev->hard_start_xmit = smsc_ircc_hard_xmit_fir; |
889 | 909 | ||
890 | /* Clear FIFO */ | 910 | /* Clear FIFO */ |
891 | outb(inb(fir_base+IRCC_LCR_A)|IRCC_LCR_A_FIFO_RESET, fir_base+IRCC_LCR_A); | 911 | outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A); |
892 | 912 | ||
893 | /* Enable interrupt */ | 913 | /* Enable interrupt */ |
894 | /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base+IRCC_IER);*/ | 914 | /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/ |
895 | 915 | ||
896 | register_bank(fir_base, 1); | 916 | register_bank(fir_base, 1); |
897 | 917 | ||
898 | /* Select the TX/RX interface */ | 918 | /* Select the TX/RX interface */ |
899 | #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */ | 919 | #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */ |
900 | outb(((inb(fir_base+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), | 920 | outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), |
901 | fir_base+IRCC_SCE_CFGB); | 921 | fir_base + IRCC_SCE_CFGB); |
902 | #else | 922 | #else |
903 | outb(((inb(fir_base+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), | 923 | outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), |
904 | fir_base+IRCC_SCE_CFGB); | 924 | fir_base + IRCC_SCE_CFGB); |
905 | #endif | 925 | #endif |
906 | (void) inb(fir_base+IRCC_FIFO_THRESHOLD); | 926 | (void) inb(fir_base + IRCC_FIFO_THRESHOLD); |
907 | 927 | ||
908 | /* Enable SCE interrupts */ | 928 | /* Enable SCE interrupts */ |
909 | outb(0, fir_base+IRCC_MASTER); | 929 | outb(0, fir_base + IRCC_MASTER); |
910 | register_bank(fir_base, 0); | 930 | register_bank(fir_base, 0); |
911 | outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base+IRCC_IER); | 931 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER); |
912 | outb(IRCC_MASTER_INT_EN, fir_base+IRCC_MASTER); | 932 | outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER); |
913 | } | 933 | } |
914 | 934 | ||
915 | /* | 935 | /* |
@@ -928,8 +948,8 @@ static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self) | |||
928 | 948 | ||
929 | fir_base = self->io.fir_base; | 949 | fir_base = self->io.fir_base; |
930 | register_bank(fir_base, 0); | 950 | register_bank(fir_base, 0); |
931 | /*outb(IRCC_MASTER_RESET, fir_base+IRCC_MASTER);*/ | 951 | /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/ |
932 | outb(inb(fir_base+IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base+IRCC_LCR_B); | 952 | outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B); |
933 | } | 953 | } |
934 | 954 | ||
935 | 955 | ||
@@ -964,26 +984,26 @@ static void smsc_ircc_change_speed(void *priv, u32 speed) | |||
964 | smsc_ircc_fir_start(self); | 984 | smsc_ircc_fir_start(self); |
965 | #endif | 985 | #endif |
966 | 986 | ||
967 | if(self->io.speed == 0) | 987 | if (self->io.speed == 0) |
968 | smsc_ircc_sir_start(self); | 988 | smsc_ircc_sir_start(self); |
969 | 989 | ||
970 | #if 0 | 990 | #if 0 |
971 | if(!last_speed_was_sir) speed = self->io.speed; | 991 | if (!last_speed_was_sir) speed = self->io.speed; |
972 | #endif | 992 | #endif |
973 | 993 | ||
974 | if(self->io.speed != speed) smsc_ircc_set_transceiver_for_speed(self, speed); | 994 | if (self->io.speed != speed) |
995 | smsc_ircc_set_transceiver_for_speed(self, speed); | ||
975 | 996 | ||
976 | self->io.speed = speed; | 997 | self->io.speed = speed; |
977 | 998 | ||
978 | if(speed <= SMSC_IRCC2_MAX_SIR_SPEED) { | 999 | if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) { |
979 | if(!last_speed_was_sir) { | 1000 | if (!last_speed_was_sir) { |
980 | smsc_ircc_fir_stop(self); | 1001 | smsc_ircc_fir_stop(self); |
981 | smsc_ircc_sir_start(self); | 1002 | smsc_ircc_sir_start(self); |
982 | } | 1003 | } |
983 | smsc_ircc_set_sir_speed(self, speed); | 1004 | smsc_ircc_set_sir_speed(self, speed); |
984 | } | 1005 | } else { |
985 | else { | 1006 | if (last_speed_was_sir) { |
986 | if(last_speed_was_sir) { | ||
987 | #if SMSC_IRCC2_C_SIR_STOP | 1007 | #if SMSC_IRCC2_C_SIR_STOP |
988 | smsc_ircc_sir_stop(self); | 1008 | smsc_ircc_sir_stop(self); |
989 | #endif | 1009 | #endif |
@@ -1027,9 +1047,9 @@ void smsc_ircc_set_sir_speed(void *priv, __u32 speed) | |||
1027 | self->io.speed = speed; | 1047 | self->io.speed = speed; |
1028 | 1048 | ||
1029 | /* Turn off interrupts */ | 1049 | /* Turn off interrupts */ |
1030 | outb(0, iobase+UART_IER); | 1050 | outb(0, iobase + UART_IER); |
1031 | 1051 | ||
1032 | divisor = SMSC_IRCC2_MAX_SIR_SPEED/speed; | 1052 | divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed; |
1033 | 1053 | ||
1034 | fcr = UART_FCR_ENABLE_FIFO; | 1054 | fcr = UART_FCR_ENABLE_FIFO; |
1035 | 1055 | ||
@@ -1038,22 +1058,20 @@ void smsc_ircc_set_sir_speed(void *priv, __u32 speed) | |||
1038 | * almost 1,7 ms at 19200 bps. At speeds above that we can just forget | 1058 | * almost 1,7 ms at 19200 bps. At speeds above that we can just forget |
1039 | * about this timeout since it will always be fast enough. | 1059 | * about this timeout since it will always be fast enough. |
1040 | */ | 1060 | */ |
1041 | if (self->io.speed < 38400) | 1061 | fcr |= self->io.speed < 38400 ? |
1042 | fcr |= UART_FCR_TRIGGER_1; | 1062 | UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; |
1043 | else | ||
1044 | fcr |= UART_FCR_TRIGGER_14; | ||
1045 | 1063 | ||
1046 | /* IrDA ports use 8N1 */ | 1064 | /* IrDA ports use 8N1 */ |
1047 | lcr = UART_LCR_WLEN8; | 1065 | lcr = UART_LCR_WLEN8; |
1048 | 1066 | ||
1049 | outb(UART_LCR_DLAB | lcr, iobase+UART_LCR); /* Set DLAB */ | 1067 | outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */ |
1050 | outb(divisor & 0xff, iobase+UART_DLL); /* Set speed */ | 1068 | outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */ |
1051 | outb(divisor >> 8, iobase+UART_DLM); | 1069 | outb(divisor >> 8, iobase + UART_DLM); |
1052 | outb(lcr, iobase+UART_LCR); /* Set 8N1 */ | 1070 | outb(lcr, iobase + UART_LCR); /* Set 8N1 */ |
1053 | outb(fcr, iobase+UART_FCR); /* Enable FIFO's */ | 1071 | outb(fcr, iobase + UART_FCR); /* Enable FIFO's */ |
1054 | 1072 | ||
1055 | /* Turn on interrups */ | 1073 | /* Turn on interrups */ |
1056 | outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, iobase+UART_IER); | 1074 | outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER); |
1057 | 1075 | ||
1058 | IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed); | 1076 | IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed); |
1059 | } | 1077 | } |
@@ -1086,7 +1104,7 @@ static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev) | |||
1086 | 1104 | ||
1087 | /* Check if we need to change the speed after this frame */ | 1105 | /* Check if we need to change the speed after this frame */ |
1088 | speed = irda_get_next_speed(skb); | 1106 | speed = irda_get_next_speed(skb); |
1089 | if ((speed != self->io.speed) && (speed != -1)) { | 1107 | if (speed != self->io.speed && speed != -1) { |
1090 | /* Check for empty frame */ | 1108 | /* Check for empty frame */ |
1091 | if (!skb->len) { | 1109 | if (!skb->len) { |
1092 | /* Note : you should make sure that speed changes | 1110 | /* Note : you should make sure that speed changes |
@@ -1096,8 +1114,9 @@ static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev) | |||
1096 | spin_unlock_irqrestore(&self->lock, flags); | 1114 | spin_unlock_irqrestore(&self->lock, flags); |
1097 | dev_kfree_skb(skb); | 1115 | dev_kfree_skb(skb); |
1098 | return 0; | 1116 | return 0; |
1099 | } else | 1117 | } |
1100 | self->new_speed = speed; | 1118 | |
1119 | self->new_speed = speed; | ||
1101 | } | 1120 | } |
1102 | 1121 | ||
1103 | memcpy(self->tx_buff.head, skb->data, skb->len); | 1122 | memcpy(self->tx_buff.head, skb->data, skb->len); |
@@ -1122,6 +1141,7 @@ static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev) | |||
1122 | /* Transmit frame */ | 1141 | /* Transmit frame */ |
1123 | smsc_ircc_dma_xmit(self, iobase, 0); | 1142 | smsc_ircc_dma_xmit(self, iobase, 0); |
1124 | } | 1143 | } |
1144 | |||
1125 | spin_unlock_irqrestore(&self->lock, flags); | 1145 | spin_unlock_irqrestore(&self->lock, flags); |
1126 | dev_kfree_skb(skb); | 1146 | dev_kfree_skb(skb); |
1127 | 1147 | ||
@@ -1142,30 +1162,30 @@ static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs) | |||
1142 | #if 1 | 1162 | #if 1 |
1143 | /* Disable Rx */ | 1163 | /* Disable Rx */ |
1144 | register_bank(iobase, 0); | 1164 | register_bank(iobase, 0); |
1145 | outb(0x00, iobase+IRCC_LCR_B); | 1165 | outb(0x00, iobase + IRCC_LCR_B); |
1146 | #endif | 1166 | #endif |
1147 | register_bank(iobase, 1); | 1167 | register_bank(iobase, 1); |
1148 | outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, | 1168 | outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, |
1149 | iobase+IRCC_SCE_CFGB); | 1169 | iobase + IRCC_SCE_CFGB); |
1150 | 1170 | ||
1151 | self->io.direction = IO_XMIT; | 1171 | self->io.direction = IO_XMIT; |
1152 | 1172 | ||
1153 | /* Set BOF additional count for generating the min turn time */ | 1173 | /* Set BOF additional count for generating the min turn time */ |
1154 | register_bank(iobase, 4); | 1174 | register_bank(iobase, 4); |
1155 | outb(bofs & 0xff, iobase+IRCC_BOF_COUNT_LO); | 1175 | outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO); |
1156 | ctrl = inb(iobase+IRCC_CONTROL) & 0xf0; | 1176 | ctrl = inb(iobase + IRCC_CONTROL) & 0xf0; |
1157 | outb(ctrl | ((bofs >> 8) & 0x0f), iobase+IRCC_BOF_COUNT_HI); | 1177 | outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI); |
1158 | 1178 | ||
1159 | /* Set max Tx frame size */ | 1179 | /* Set max Tx frame size */ |
1160 | outb(self->tx_buff.len >> 8, iobase+IRCC_TX_SIZE_HI); | 1180 | outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI); |
1161 | outb(self->tx_buff.len & 0xff, iobase+IRCC_TX_SIZE_LO); | 1181 | outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO); |
1162 | 1182 | ||
1163 | /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/ | 1183 | /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/ |
1164 | 1184 | ||
1165 | /* Enable burst mode chip Tx DMA */ | 1185 | /* Enable burst mode chip Tx DMA */ |
1166 | register_bank(iobase, 1); | 1186 | register_bank(iobase, 1); |
1167 | outb(inb(iobase+IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | | 1187 | outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | |
1168 | IRCC_CFGB_DMA_BURST, iobase+IRCC_SCE_CFGB); | 1188 | IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); |
1169 | 1189 | ||
1170 | /* Setup DMA controller (must be done after enabling chip DMA) */ | 1190 | /* Setup DMA controller (must be done after enabling chip DMA) */ |
1171 | irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len, | 1191 | irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len, |
@@ -1174,11 +1194,11 @@ static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs) | |||
1174 | /* Enable interrupt */ | 1194 | /* Enable interrupt */ |
1175 | 1195 | ||
1176 | register_bank(iobase, 0); | 1196 | register_bank(iobase, 0); |
1177 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase+IRCC_IER); | 1197 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); |
1178 | outb(IRCC_MASTER_INT_EN, iobase+IRCC_MASTER); | 1198 | outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); |
1179 | 1199 | ||
1180 | /* Enable transmit */ | 1200 | /* Enable transmit */ |
1181 | outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase+IRCC_LCR_B); | 1201 | outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B); |
1182 | } | 1202 | } |
1183 | 1203 | ||
1184 | /* | 1204 | /* |
@@ -1194,25 +1214,25 @@ static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self, int iobase) | |||
1194 | #if 0 | 1214 | #if 0 |
1195 | /* Disable Tx */ | 1215 | /* Disable Tx */ |
1196 | register_bank(iobase, 0); | 1216 | register_bank(iobase, 0); |
1197 | outb(0x00, iobase+IRCC_LCR_B); | 1217 | outb(0x00, iobase + IRCC_LCR_B); |
1198 | #endif | 1218 | #endif |
1199 | register_bank(self->io.fir_base, 1); | 1219 | register_bank(self->io.fir_base, 1); |
1200 | outb(inb(self->io.fir_base+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, | 1220 | outb(inb(self->io.fir_base + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, |
1201 | self->io.fir_base+IRCC_SCE_CFGB); | 1221 | self->io.fir_base + IRCC_SCE_CFGB); |
1202 | 1222 | ||
1203 | /* Check for underrun! */ | 1223 | /* Check for underrun! */ |
1204 | register_bank(iobase, 0); | 1224 | register_bank(iobase, 0); |
1205 | if (inb(iobase+IRCC_LSR) & IRCC_LSR_UNDERRUN) { | 1225 | if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) { |
1206 | self->stats.tx_errors++; | 1226 | self->stats.tx_errors++; |
1207 | self->stats.tx_fifo_errors++; | 1227 | self->stats.tx_fifo_errors++; |
1208 | 1228 | ||
1209 | /* Reset error condition */ | 1229 | /* Reset error condition */ |
1210 | register_bank(iobase, 0); | 1230 | register_bank(iobase, 0); |
1211 | outb(IRCC_MASTER_ERROR_RESET, iobase+IRCC_MASTER); | 1231 | outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER); |
1212 | outb(0x00, iobase+IRCC_MASTER); | 1232 | outb(0x00, iobase + IRCC_MASTER); |
1213 | } else { | 1233 | } else { |
1214 | self->stats.tx_packets++; | 1234 | self->stats.tx_packets++; |
1215 | self->stats.tx_bytes += self->tx_buff.len; | 1235 | self->stats.tx_bytes += self->tx_buff.len; |
1216 | } | 1236 | } |
1217 | 1237 | ||
1218 | /* Check if it's time to change the speed */ | 1238 | /* Check if it's time to change the speed */ |
@@ -1236,26 +1256,26 @@ static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase) | |||
1236 | #if 0 | 1256 | #if 0 |
1237 | /* Turn off chip DMA */ | 1257 | /* Turn off chip DMA */ |
1238 | register_bank(iobase, 1); | 1258 | register_bank(iobase, 1); |
1239 | outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, | 1259 | outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, |
1240 | iobase+IRCC_SCE_CFGB); | 1260 | iobase + IRCC_SCE_CFGB); |
1241 | #endif | 1261 | #endif |
1242 | 1262 | ||
1243 | /* Disable Tx */ | 1263 | /* Disable Tx */ |
1244 | register_bank(iobase, 0); | 1264 | register_bank(iobase, 0); |
1245 | outb(0x00, iobase+IRCC_LCR_B); | 1265 | outb(0x00, iobase + IRCC_LCR_B); |
1246 | 1266 | ||
1247 | /* Turn off chip DMA */ | 1267 | /* Turn off chip DMA */ |
1248 | register_bank(iobase, 1); | 1268 | register_bank(iobase, 1); |
1249 | outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, | 1269 | outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, |
1250 | iobase+IRCC_SCE_CFGB); | 1270 | iobase + IRCC_SCE_CFGB); |
1251 | 1271 | ||
1252 | self->io.direction = IO_RECV; | 1272 | self->io.direction = IO_RECV; |
1253 | self->rx_buff.data = self->rx_buff.head; | 1273 | self->rx_buff.data = self->rx_buff.head; |
1254 | 1274 | ||
1255 | /* Set max Rx frame size */ | 1275 | /* Set max Rx frame size */ |
1256 | register_bank(iobase, 4); | 1276 | register_bank(iobase, 4); |
1257 | outb((2050 >> 8) & 0x0f, iobase+IRCC_RX_SIZE_HI); | 1277 | outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI); |
1258 | outb(2050 & 0xff, iobase+IRCC_RX_SIZE_LO); | 1278 | outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO); |
1259 | 1279 | ||
1260 | /* Setup DMA controller */ | 1280 | /* Setup DMA controller */ |
1261 | irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize, | 1281 | irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize, |
@@ -1263,19 +1283,18 @@ static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase) | |||
1263 | 1283 | ||
1264 | /* Enable burst mode chip Rx DMA */ | 1284 | /* Enable burst mode chip Rx DMA */ |
1265 | register_bank(iobase, 1); | 1285 | register_bank(iobase, 1); |
1266 | outb(inb(iobase+IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | | 1286 | outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | |
1267 | IRCC_CFGB_DMA_BURST, iobase+IRCC_SCE_CFGB); | 1287 | IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); |
1268 | 1288 | ||
1269 | /* Enable interrupt */ | 1289 | /* Enable interrupt */ |
1270 | register_bank(iobase, 0); | 1290 | register_bank(iobase, 0); |
1271 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase+IRCC_IER); | 1291 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); |
1272 | outb(IRCC_MASTER_INT_EN, iobase+IRCC_MASTER); | 1292 | outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); |
1273 | |||
1274 | 1293 | ||
1275 | /* Enable receiver */ | 1294 | /* Enable receiver */ |
1276 | register_bank(iobase, 0); | 1295 | register_bank(iobase, 0); |
1277 | outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE, | 1296 | outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE, |
1278 | iobase+IRCC_LCR_B); | 1297 | iobase + IRCC_LCR_B); |
1279 | 1298 | ||
1280 | return 0; | 1299 | return 0; |
1281 | } | 1300 | } |
@@ -1297,43 +1316,43 @@ static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self, int iobase | |||
1297 | #if 0 | 1316 | #if 0 |
1298 | /* Disable Rx */ | 1317 | /* Disable Rx */ |
1299 | register_bank(iobase, 0); | 1318 | register_bank(iobase, 0); |
1300 | outb(0x00, iobase+IRCC_LCR_B); | 1319 | outb(0x00, iobase + IRCC_LCR_B); |
1301 | #endif | 1320 | #endif |
1302 | register_bank(iobase, 0); | 1321 | register_bank(iobase, 0); |
1303 | outb(inb(iobase+IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase+IRCC_LSAR); | 1322 | outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR); |
1304 | lsr= inb(iobase+IRCC_LSR); | 1323 | lsr= inb(iobase + IRCC_LSR); |
1305 | msgcnt = inb(iobase+IRCC_LCR_B) & 0x08; | 1324 | msgcnt = inb(iobase + IRCC_LCR_B) & 0x08; |
1306 | 1325 | ||
1307 | IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__, | 1326 | IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__, |
1308 | get_dma_residue(self->io.dma)); | 1327 | get_dma_residue(self->io.dma)); |
1309 | 1328 | ||
1310 | len = self->rx_buff.truesize - get_dma_residue(self->io.dma); | 1329 | len = self->rx_buff.truesize - get_dma_residue(self->io.dma); |
1311 | 1330 | ||
1312 | /* Look for errors | 1331 | /* Look for errors */ |
1313 | */ | 1332 | if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) { |
1314 | |||
1315 | if(lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) { | ||
1316 | self->stats.rx_errors++; | 1333 | self->stats.rx_errors++; |
1317 | if(lsr & IRCC_LSR_FRAME_ERROR) self->stats.rx_frame_errors++; | 1334 | if (lsr & IRCC_LSR_FRAME_ERROR) |
1318 | if(lsr & IRCC_LSR_CRC_ERROR) self->stats.rx_crc_errors++; | 1335 | self->stats.rx_frame_errors++; |
1319 | if(lsr & IRCC_LSR_SIZE_ERROR) self->stats.rx_length_errors++; | 1336 | if (lsr & IRCC_LSR_CRC_ERROR) |
1320 | if(lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN)) self->stats.rx_length_errors++; | 1337 | self->stats.rx_crc_errors++; |
1338 | if (lsr & IRCC_LSR_SIZE_ERROR) | ||
1339 | self->stats.rx_length_errors++; | ||
1340 | if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN)) | ||
1341 | self->stats.rx_length_errors++; | ||
1321 | return; | 1342 | return; |
1322 | } | 1343 | } |
1344 | |||
1323 | /* Remove CRC */ | 1345 | /* Remove CRC */ |
1324 | if (self->io.speed < 4000000) | 1346 | len -= self->io.speed < 4000000 ? 2 : 4; |
1325 | len -= 2; | ||
1326 | else | ||
1327 | len -= 4; | ||
1328 | 1347 | ||
1329 | if ((len < 2) || (len > 2050)) { | 1348 | if (len < 2 || len > 2050) { |
1330 | IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len); | 1349 | IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len); |
1331 | return; | 1350 | return; |
1332 | } | 1351 | } |
1333 | IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len); | 1352 | IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len); |
1334 | 1353 | ||
1335 | skb = dev_alloc_skb(len+1); | 1354 | skb = dev_alloc_skb(len + 1); |
1336 | if (!skb) { | 1355 | if (!skb) { |
1337 | IRDA_WARNING("%s(), memory squeeze, dropping frame.\n", | 1356 | IRDA_WARNING("%s(), memory squeeze, dropping frame.\n", |
1338 | __FUNCTION__); | 1357 | __FUNCTION__); |
1339 | return; | 1358 | return; |
@@ -1372,14 +1391,14 @@ static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self) | |||
1372 | */ | 1391 | */ |
1373 | do { | 1392 | do { |
1374 | async_unwrap_char(self->netdev, &self->stats, &self->rx_buff, | 1393 | async_unwrap_char(self->netdev, &self->stats, &self->rx_buff, |
1375 | inb(iobase+UART_RX)); | 1394 | inb(iobase + UART_RX)); |
1376 | 1395 | ||
1377 | /* Make sure we don't stay here to long */ | 1396 | /* Make sure we don't stay here to long */ |
1378 | if (boguscount++ > 32) { | 1397 | if (boguscount++ > 32) { |
1379 | IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__); | 1398 | IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__); |
1380 | break; | 1399 | break; |
1381 | } | 1400 | } |
1382 | } while (inb(iobase+UART_LSR) & UART_LSR_DR); | 1401 | } while (inb(iobase + UART_LSR) & UART_LSR_DR); |
1383 | } | 1402 | } |
1384 | 1403 | ||
1385 | 1404 | ||
@@ -1408,7 +1427,7 @@ static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *re | |||
1408 | spin_lock(&self->lock); | 1427 | spin_lock(&self->lock); |
1409 | 1428 | ||
1410 | /* Check if we should use the SIR interrupt handler */ | 1429 | /* Check if we should use the SIR interrupt handler */ |
1411 | if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) { | 1430 | if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) { |
1412 | ret = smsc_ircc_interrupt_sir(dev); | 1431 | ret = smsc_ircc_interrupt_sir(dev); |
1413 | goto irq_ret_unlock; | 1432 | goto irq_ret_unlock; |
1414 | } | 1433 | } |
@@ -1416,15 +1435,15 @@ static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *re | |||
1416 | iobase = self->io.fir_base; | 1435 | iobase = self->io.fir_base; |
1417 | 1436 | ||
1418 | register_bank(iobase, 0); | 1437 | register_bank(iobase, 0); |
1419 | iir = inb(iobase+IRCC_IIR); | 1438 | iir = inb(iobase + IRCC_IIR); |
1420 | if (iir == 0) | 1439 | if (iir == 0) |
1421 | goto irq_ret_unlock; | 1440 | goto irq_ret_unlock; |
1422 | ret = IRQ_HANDLED; | 1441 | ret = IRQ_HANDLED; |
1423 | 1442 | ||
1424 | /* Disable interrupts */ | 1443 | /* Disable interrupts */ |
1425 | outb(0, iobase+IRCC_IER); | 1444 | outb(0, iobase + IRCC_IER); |
1426 | lcra = inb(iobase+IRCC_LCR_A); | 1445 | lcra = inb(iobase + IRCC_LCR_A); |
1427 | lsr = inb(iobase+IRCC_LSR); | 1446 | lsr = inb(iobase + IRCC_LSR); |
1428 | 1447 | ||
1429 | IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir); | 1448 | IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir); |
1430 | 1449 | ||
@@ -1444,7 +1463,7 @@ static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *re | |||
1444 | /* Enable interrupts again */ | 1463 | /* Enable interrupts again */ |
1445 | 1464 | ||
1446 | register_bank(iobase, 0); | 1465 | register_bank(iobase, 0); |
1447 | outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, iobase+IRCC_IER); | 1466 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); |
1448 | 1467 | ||
1449 | irq_ret_unlock: | 1468 | irq_ret_unlock: |
1450 | spin_unlock(&self->lock); | 1469 | spin_unlock(&self->lock); |
@@ -1469,12 +1488,12 @@ static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev) | |||
1469 | 1488 | ||
1470 | iobase = self->io.sir_base; | 1489 | iobase = self->io.sir_base; |
1471 | 1490 | ||
1472 | iir = inb(iobase+UART_IIR) & UART_IIR_ID; | 1491 | iir = inb(iobase + UART_IIR) & UART_IIR_ID; |
1473 | if (iir == 0) | 1492 | if (iir == 0) |
1474 | return IRQ_NONE; | 1493 | return IRQ_NONE; |
1475 | while (iir) { | 1494 | while (iir) { |
1476 | /* Clear interrupt */ | 1495 | /* Clear interrupt */ |
1477 | lsr = inb(iobase+UART_LSR); | 1496 | lsr = inb(iobase + UART_LSR); |
1478 | 1497 | ||
1479 | IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n", | 1498 | IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n", |
1480 | __FUNCTION__, iir, lsr, iobase); | 1499 | __FUNCTION__, iir, lsr, iobase); |
@@ -1624,9 +1643,7 @@ static int smsc_ircc_net_close(struct net_device *dev) | |||
1624 | self->irlap = NULL; | 1643 | self->irlap = NULL; |
1625 | 1644 | ||
1626 | free_irq(self->io.irq, dev); | 1645 | free_irq(self->io.irq, dev); |
1627 | |||
1628 | disable_dma(self->io.dma); | 1646 | disable_dma(self->io.dma); |
1629 | |||
1630 | free_dma(self->io.dma); | 1647 | free_dma(self->io.dma); |
1631 | 1648 | ||
1632 | return 0; | 1649 | return 0; |
@@ -1637,12 +1654,10 @@ static void smsc_ircc_suspend(struct smsc_ircc_cb *self) | |||
1637 | { | 1654 | { |
1638 | IRDA_MESSAGE("%s, Suspending\n", driver_name); | 1655 | IRDA_MESSAGE("%s, Suspending\n", driver_name); |
1639 | 1656 | ||
1640 | if (self->io.suspended) | 1657 | if (!self->io.suspended) { |
1641 | return; | 1658 | smsc_ircc_net_close(self->netdev); |
1642 | 1659 | self->io.suspended = 1; | |
1643 | smsc_ircc_net_close(self->netdev); | 1660 | } |
1644 | |||
1645 | self->io.suspended = 1; | ||
1646 | } | 1661 | } |
1647 | 1662 | ||
1648 | static void smsc_ircc_wakeup(struct smsc_ircc_cb *self) | 1663 | static void smsc_ircc_wakeup(struct smsc_ircc_cb *self) |
@@ -1703,14 +1718,14 @@ static int __exit smsc_ircc_close(struct smsc_ircc_cb *self) | |||
1703 | 1718 | ||
1704 | /* Stop interrupts */ | 1719 | /* Stop interrupts */ |
1705 | register_bank(iobase, 0); | 1720 | register_bank(iobase, 0); |
1706 | outb(0, iobase+IRCC_IER); | 1721 | outb(0, iobase + IRCC_IER); |
1707 | outb(IRCC_MASTER_RESET, iobase+IRCC_MASTER); | 1722 | outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); |
1708 | outb(0x00, iobase+IRCC_MASTER); | 1723 | outb(0x00, iobase + IRCC_MASTER); |
1709 | #if 0 | 1724 | #if 0 |
1710 | /* Reset to SIR mode */ | 1725 | /* Reset to SIR mode */ |
1711 | register_bank(iobase, 1); | 1726 | register_bank(iobase, 1); |
1712 | outb(IRCC_CFGA_IRDA_SIR_A|IRCC_CFGA_TX_POLARITY, iobase+IRCC_SCE_CFGA); | 1727 | outb(IRCC_CFGA_IRDA_SIR_A|IRCC_CFGA_TX_POLARITY, iobase + IRCC_SCE_CFGA); |
1713 | outb(IRCC_CFGB_IR, iobase+IRCC_SCE_CFGB); | 1728 | outb(IRCC_CFGB_IR, iobase + IRCC_SCE_CFGB); |
1714 | #endif | 1729 | #endif |
1715 | spin_unlock_irqrestore(&self->lock, flags); | 1730 | spin_unlock_irqrestore(&self->lock, flags); |
1716 | 1731 | ||
@@ -1744,7 +1759,7 @@ static void __exit smsc_ircc_cleanup(void) | |||
1744 | 1759 | ||
1745 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | 1760 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); |
1746 | 1761 | ||
1747 | for (i=0; i < 2; i++) { | 1762 | for (i = 0; i < 2; i++) { |
1748 | if (dev_self[i]) | 1763 | if (dev_self[i]) |
1749 | smsc_ircc_close(dev_self[i]); | 1764 | smsc_ircc_close(dev_self[i]); |
1750 | } | 1765 | } |
@@ -1764,7 +1779,7 @@ void smsc_ircc_sir_start(struct smsc_ircc_cb *self) | |||
1764 | IRDA_DEBUG(3, "%s\n", __FUNCTION__); | 1779 | IRDA_DEBUG(3, "%s\n", __FUNCTION__); |
1765 | 1780 | ||
1766 | IRDA_ASSERT(self != NULL, return;); | 1781 | IRDA_ASSERT(self != NULL, return;); |
1767 | dev= self->netdev; | 1782 | dev = self->netdev; |
1768 | IRDA_ASSERT(dev != NULL, return;); | 1783 | IRDA_ASSERT(dev != NULL, return;); |
1769 | dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir; | 1784 | dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir; |
1770 | 1785 | ||
@@ -1772,25 +1787,25 @@ void smsc_ircc_sir_start(struct smsc_ircc_cb *self) | |||
1772 | sir_base = self->io.sir_base; | 1787 | sir_base = self->io.sir_base; |
1773 | 1788 | ||
1774 | /* Reset everything */ | 1789 | /* Reset everything */ |
1775 | outb(IRCC_MASTER_RESET, fir_base+IRCC_MASTER); | 1790 | outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER); |
1776 | 1791 | ||
1777 | #if SMSC_IRCC2_C_SIR_STOP | 1792 | #if SMSC_IRCC2_C_SIR_STOP |
1778 | /*smsc_ircc_sir_stop(self);*/ | 1793 | /*smsc_ircc_sir_stop(self);*/ |
1779 | #endif | 1794 | #endif |
1780 | 1795 | ||
1781 | register_bank(fir_base, 1); | 1796 | register_bank(fir_base, 1); |
1782 | outb(((inb(fir_base+IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base+IRCC_SCE_CFGA); | 1797 | outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA); |
1783 | 1798 | ||
1784 | /* Initialize UART */ | 1799 | /* Initialize UART */ |
1785 | outb(UART_LCR_WLEN8, sir_base+UART_LCR); /* Reset DLAB */ | 1800 | outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */ |
1786 | outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base+UART_MCR); | 1801 | outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR); |
1787 | 1802 | ||
1788 | /* Turn on interrups */ | 1803 | /* Turn on interrups */ |
1789 | outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base+UART_IER); | 1804 | outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER); |
1790 | 1805 | ||
1791 | IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__); | 1806 | IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__); |
1792 | 1807 | ||
1793 | outb(0x00, fir_base+IRCC_MASTER); | 1808 | outb(0x00, fir_base + IRCC_MASTER); |
1794 | } | 1809 | } |
1795 | 1810 | ||
1796 | #if SMSC_IRCC2_C_SIR_STOP | 1811 | #if SMSC_IRCC2_C_SIR_STOP |
@@ -1802,10 +1817,10 @@ void smsc_ircc_sir_stop(struct smsc_ircc_cb *self) | |||
1802 | iobase = self->io.sir_base; | 1817 | iobase = self->io.sir_base; |
1803 | 1818 | ||
1804 | /* Reset UART */ | 1819 | /* Reset UART */ |
1805 | outb(0, iobase+UART_MCR); | 1820 | outb(0, iobase + UART_MCR); |
1806 | 1821 | ||
1807 | /* Turn off interrupts */ | 1822 | /* Turn off interrupts */ |
1808 | outb(0, iobase+UART_IER); | 1823 | outb(0, iobase + UART_IER); |
1809 | } | 1824 | } |
1810 | #endif | 1825 | #endif |
1811 | 1826 | ||
@@ -1856,21 +1871,19 @@ static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self) | |||
1856 | } | 1871 | } |
1857 | self->stats.tx_packets++; | 1872 | self->stats.tx_packets++; |
1858 | 1873 | ||
1859 | if(self->io.speed <= 115200) { | 1874 | if (self->io.speed <= 115200) { |
1860 | /* | 1875 | /* |
1861 | * Reset Rx FIFO to make sure that all reflected transmit data | 1876 | * Reset Rx FIFO to make sure that all reflected transmit data |
1862 | * is discarded. This is needed for half duplex operation | 1877 | * is discarded. This is needed for half duplex operation |
1863 | */ | 1878 | */ |
1864 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR; | 1879 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR; |
1865 | if (self->io.speed < 38400) | 1880 | fcr |= self->io.speed < 38400 ? |
1866 | fcr |= UART_FCR_TRIGGER_1; | 1881 | UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; |
1867 | else | ||
1868 | fcr |= UART_FCR_TRIGGER_14; | ||
1869 | 1882 | ||
1870 | outb(fcr, iobase+UART_FCR); | 1883 | outb(fcr, iobase + UART_FCR); |
1871 | 1884 | ||
1872 | /* Turn on receive interrupts */ | 1885 | /* Turn on receive interrupts */ |
1873 | outb(UART_IER_RDI, iobase+UART_IER); | 1886 | outb(UART_IER_RDI, iobase + UART_IER); |
1874 | } | 1887 | } |
1875 | } | 1888 | } |
1876 | } | 1889 | } |
@@ -1886,15 +1899,15 @@ static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len) | |||
1886 | int actual = 0; | 1899 | int actual = 0; |
1887 | 1900 | ||
1888 | /* Tx FIFO should be empty! */ | 1901 | /* Tx FIFO should be empty! */ |
1889 | if (!(inb(iobase+UART_LSR) & UART_LSR_THRE)) { | 1902 | if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) { |
1890 | IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__); | 1903 | IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__); |
1891 | return 0; | 1904 | return 0; |
1892 | } | 1905 | } |
1893 | 1906 | ||
1894 | /* Fill FIFO with current frame */ | 1907 | /* Fill FIFO with current frame */ |
1895 | while ((fifo_size-- > 0) && (actual < len)) { | 1908 | while (fifo_size-- > 0 && actual < len) { |
1896 | /* Transmit next byte */ | 1909 | /* Transmit next byte */ |
1897 | outb(buf[actual], iobase+UART_TX); | 1910 | outb(buf[actual], iobase + UART_TX); |
1898 | actual++; | 1911 | actual++; |
1899 | } | 1912 | } |
1900 | return actual; | 1913 | return actual; |
@@ -1924,17 +1937,18 @@ static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self) | |||
1924 | 1937 | ||
1925 | IRDA_ASSERT(self != NULL, return;); | 1938 | IRDA_ASSERT(self != NULL, return;); |
1926 | 1939 | ||
1927 | for(i=0; smsc_transceivers[i].name!=NULL; i++) | 1940 | for (i = 0; smsc_transceivers[i].name != NULL; i++) |
1928 | if((*smsc_transceivers[i].probe)(self->io.fir_base)) { | 1941 | if (smsc_transceivers[i].probe(self->io.fir_base)) { |
1929 | IRDA_MESSAGE(" %s transceiver found\n", | 1942 | IRDA_MESSAGE(" %s transceiver found\n", |
1930 | smsc_transceivers[i].name); | 1943 | smsc_transceivers[i].name); |
1931 | self->transceiver= i+1; | 1944 | self->transceiver= i + 1; |
1932 | return; | 1945 | return; |
1933 | } | 1946 | } |
1947 | |||
1934 | IRDA_MESSAGE("No transceiver found. Defaulting to %s\n", | 1948 | IRDA_MESSAGE("No transceiver found. Defaulting to %s\n", |
1935 | smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name); | 1949 | smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name); |
1936 | 1950 | ||
1937 | self->transceiver= SMSC_IRCC2_C_DEFAULT_TRANSCEIVER; | 1951 | self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER; |
1938 | } | 1952 | } |
1939 | 1953 | ||
1940 | 1954 | ||
@@ -1949,7 +1963,8 @@ static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 s | |||
1949 | unsigned int trx; | 1963 | unsigned int trx; |
1950 | 1964 | ||
1951 | trx = self->transceiver; | 1965 | trx = self->transceiver; |
1952 | if(trx>0) (*smsc_transceivers[trx-1].set_for_speed)(self->io.fir_base, speed); | 1966 | if (trx > 0) |
1967 | smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed); | ||
1953 | } | 1968 | } |
1954 | 1969 | ||
1955 | /* | 1970 | /* |
@@ -1977,16 +1992,14 @@ static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 s | |||
1977 | 1992 | ||
1978 | static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self) | 1993 | static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self) |
1979 | { | 1994 | { |
1980 | int iobase; | 1995 | int iobase = self->io.sir_base; |
1981 | int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US; | 1996 | int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US; |
1982 | 1997 | ||
1983 | iobase = self->io.sir_base; | ||
1984 | |||
1985 | /* Calibrated busy loop */ | 1998 | /* Calibrated busy loop */ |
1986 | while((count-- > 0) && !(inb(iobase+UART_LSR) & UART_LSR_TEMT)) | 1999 | while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT)) |
1987 | udelay(1); | 2000 | udelay(1); |
1988 | 2001 | ||
1989 | if(count == 0) | 2002 | if (count == 0) |
1990 | IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__); | 2003 | IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__); |
1991 | } | 2004 | } |
1992 | 2005 | ||
@@ -1999,34 +2012,36 @@ static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self) | |||
1999 | static int __init smsc_ircc_look_for_chips(void) | 2012 | static int __init smsc_ircc_look_for_chips(void) |
2000 | { | 2013 | { |
2001 | smsc_chip_address_t *address; | 2014 | smsc_chip_address_t *address; |
2002 | char *type; | 2015 | char *type; |
2003 | unsigned int cfg_base, found; | 2016 | unsigned int cfg_base, found; |
2004 | 2017 | ||
2005 | found = 0; | 2018 | found = 0; |
2006 | address = possible_addresses; | 2019 | address = possible_addresses; |
2007 | 2020 | ||
2008 | while(address->cfg_base){ | 2021 | while (address->cfg_base) { |
2009 | cfg_base = address->cfg_base; | 2022 | cfg_base = address->cfg_base; |
2010 | 2023 | ||
2011 | /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/ | 2024 | /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/ |
2012 | 2025 | ||
2013 | if( address->type & SMSCSIO_TYPE_FDC){ | 2026 | if (address->type & SMSCSIO_TYPE_FDC) { |
2014 | type = "FDC"; | 2027 | type = "FDC"; |
2015 | if((address->type) & SMSCSIO_TYPE_FLAT) { | 2028 | if (address->type & SMSCSIO_TYPE_FLAT) |
2016 | if(!smsc_superio_flat(fdc_chips_flat,cfg_base, type)) found++; | 2029 | if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type)) |
2017 | } | 2030 | found++; |
2018 | if((address->type) & SMSCSIO_TYPE_PAGED) { | 2031 | |
2019 | if(!smsc_superio_paged(fdc_chips_paged,cfg_base, type)) found++; | 2032 | if (address->type & SMSCSIO_TYPE_PAGED) |
2020 | } | 2033 | if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type)) |
2034 | found++; | ||
2021 | } | 2035 | } |
2022 | if( address->type & SMSCSIO_TYPE_LPC){ | 2036 | if (address->type & SMSCSIO_TYPE_LPC) { |
2023 | type = "LPC"; | 2037 | type = "LPC"; |
2024 | if((address->type) & SMSCSIO_TYPE_FLAT) { | 2038 | if (address->type & SMSCSIO_TYPE_FLAT) |
2025 | if(!smsc_superio_flat(lpc_chips_flat,cfg_base,type)) found++; | 2039 | if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type)) |
2026 | } | 2040 | found++; |
2027 | if((address->type) & SMSCSIO_TYPE_PAGED) { | 2041 | |
2028 | if(!smsc_superio_paged(lpc_chips_paged,cfg_base,"LPC")) found++; | 2042 | if (address->type & SMSCSIO_TYPE_PAGED) |
2029 | } | 2043 | if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type)) |
2044 | found++; | ||
2030 | } | 2045 | } |
2031 | address++; | 2046 | address++; |
2032 | } | 2047 | } |
@@ -2047,38 +2062,36 @@ static int __init smsc_superio_flat(const smsc_chip_t *chips, unsigned short cfg | |||
2047 | 2062 | ||
2048 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | 2063 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); |
2049 | 2064 | ||
2050 | if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type)==NULL) | 2065 | if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL) |
2051 | return ret; | 2066 | return ret; |
2052 | 2067 | ||
2053 | outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase); | 2068 | outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase); |
2054 | mode = inb(cfgbase+1); | 2069 | mode = inb(cfgbase + 1); |
2055 | 2070 | ||
2056 | /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/ | 2071 | /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/ |
2057 | 2072 | ||
2058 | if(!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA)) | 2073 | if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA)) |
2059 | IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__); | 2074 | IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__); |
2060 | 2075 | ||
2061 | outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase); | 2076 | outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase); |
2062 | sirbase = inb(cfgbase+1) << 2; | 2077 | sirbase = inb(cfgbase + 1) << 2; |
2063 | 2078 | ||
2064 | /* FIR iobase */ | 2079 | /* FIR iobase */ |
2065 | outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase); | 2080 | outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase); |
2066 | firbase = inb(cfgbase+1) << 3; | 2081 | firbase = inb(cfgbase + 1) << 3; |
2067 | 2082 | ||
2068 | /* DMA */ | 2083 | /* DMA */ |
2069 | outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase); | 2084 | outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase); |
2070 | dma = inb(cfgbase+1) & SMSCSIOFLAT_FIRDMASELECT_MASK; | 2085 | dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK; |
2071 | 2086 | ||
2072 | /* IRQ */ | 2087 | /* IRQ */ |
2073 | outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase); | 2088 | outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase); |
2074 | irq = inb(cfgbase+1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; | 2089 | irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; |
2075 | 2090 | ||
2076 | IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode); | 2091 | IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode); |
2077 | 2092 | ||
2078 | if (firbase) { | 2093 | if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0) |
2079 | if (smsc_ircc_open(firbase, sirbase, dma, irq) == 0) | 2094 | ret = 0; |
2080 | ret=0; | ||
2081 | } | ||
2082 | 2095 | ||
2083 | /* Exit configuration */ | 2096 | /* Exit configuration */ |
2084 | outb(SMSCSIO_CFGEXITKEY, cfgbase); | 2097 | outb(SMSCSIO_CFGEXITKEY, cfgbase); |
@@ -2099,7 +2112,7 @@ static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cf | |||
2099 | 2112 | ||
2100 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | 2113 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); |
2101 | 2114 | ||
2102 | if (smsc_ircc_probe(cfg_base,0x20,chips,type)==NULL) | 2115 | if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL) |
2103 | return ret; | 2116 | return ret; |
2104 | 2117 | ||
2105 | /* Select logical device (UART2) */ | 2118 | /* Select logical device (UART2) */ |
@@ -2108,7 +2121,7 @@ static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cf | |||
2108 | 2121 | ||
2109 | /* SIR iobase */ | 2122 | /* SIR iobase */ |
2110 | outb(0x60, cfg_base); | 2123 | outb(0x60, cfg_base); |
2111 | sir_io = inb(cfg_base + 1) << 8; | 2124 | sir_io = inb(cfg_base + 1) << 8; |
2112 | outb(0x61, cfg_base); | 2125 | outb(0x61, cfg_base); |
2113 | sir_io |= inb(cfg_base + 1); | 2126 | sir_io |= inb(cfg_base + 1); |
2114 | 2127 | ||
@@ -2119,10 +2132,8 @@ static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cf | |||
2119 | fir_io |= inb(cfg_base + 1); | 2132 | fir_io |= inb(cfg_base + 1); |
2120 | outb(0x2b, cfg_base); /* ??? */ | 2133 | outb(0x2b, cfg_base); /* ??? */ |
2121 | 2134 | ||
2122 | if (fir_io) { | 2135 | if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0) |
2123 | if (smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0) | 2136 | ret = 0; |
2124 | ret=0; | ||
2125 | } | ||
2126 | 2137 | ||
2127 | /* Exit configuration */ | 2138 | /* Exit configuration */ |
2128 | outb(SMSCSIO_CFGEXITKEY, cfg_base); | 2139 | outb(SMSCSIO_CFGEXITKEY, cfg_base); |
@@ -2131,21 +2142,17 @@ static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cf | |||
2131 | } | 2142 | } |
2132 | 2143 | ||
2133 | 2144 | ||
2134 | static int __init smsc_access(unsigned short cfg_base,unsigned char reg) | 2145 | static int __init smsc_access(unsigned short cfg_base, unsigned char reg) |
2135 | { | 2146 | { |
2136 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | 2147 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); |
2137 | 2148 | ||
2138 | outb(reg, cfg_base); | 2149 | outb(reg, cfg_base); |
2139 | 2150 | return inb(cfg_base) != reg ? -1 : 0; | |
2140 | if (inb(cfg_base)!=reg) | ||
2141 | return -1; | ||
2142 | |||
2143 | return 0; | ||
2144 | } | 2151 | } |
2145 | 2152 | ||
2146 | static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base,u8 reg,const smsc_chip_t *chip,char *type) | 2153 | static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const smsc_chip_t *chip, char *type) |
2147 | { | 2154 | { |
2148 | u8 devid,xdevid,rev; | 2155 | u8 devid, xdevid, rev; |
2149 | 2156 | ||
2150 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | 2157 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); |
2151 | 2158 | ||
@@ -2158,7 +2165,7 @@ static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base,u8 reg | |||
2158 | 2165 | ||
2159 | outb(reg, cfg_base); | 2166 | outb(reg, cfg_base); |
2160 | 2167 | ||
2161 | xdevid=inb(cfg_base+1); | 2168 | xdevid = inb(cfg_base + 1); |
2162 | 2169 | ||
2163 | /* Enter configuration */ | 2170 | /* Enter configuration */ |
2164 | 2171 | ||
@@ -2171,48 +2178,46 @@ static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base,u8 reg | |||
2171 | 2178 | ||
2172 | /* probe device ID */ | 2179 | /* probe device ID */ |
2173 | 2180 | ||
2174 | if (smsc_access(cfg_base,reg)) | 2181 | if (smsc_access(cfg_base, reg)) |
2175 | return NULL; | 2182 | return NULL; |
2176 | 2183 | ||
2177 | devid=inb(cfg_base+1); | 2184 | devid = inb(cfg_base + 1); |
2178 | 2185 | ||
2179 | if (devid==0) /* typical value for unused port */ | 2186 | if (devid == 0 || devid == 0xff) /* typical values for unused port */ |
2180 | return NULL; | ||
2181 | |||
2182 | if (devid==0xff) /* typical value for unused port */ | ||
2183 | return NULL; | 2187 | return NULL; |
2184 | 2188 | ||
2185 | /* probe revision ID */ | 2189 | /* probe revision ID */ |
2186 | 2190 | ||
2187 | if (smsc_access(cfg_base,reg+1)) | 2191 | if (smsc_access(cfg_base, reg + 1)) |
2188 | return NULL; | 2192 | return NULL; |
2189 | 2193 | ||
2190 | rev=inb(cfg_base+1); | 2194 | rev = inb(cfg_base + 1); |
2191 | 2195 | ||
2192 | if (rev>=128) /* i think this will make no sense */ | 2196 | if (rev >= 128) /* i think this will make no sense */ |
2193 | return NULL; | 2197 | return NULL; |
2194 | 2198 | ||
2195 | if (devid==xdevid) /* protection against false positives */ | 2199 | if (devid == xdevid) /* protection against false positives */ |
2196 | return NULL; | 2200 | return NULL; |
2197 | 2201 | ||
2198 | /* Check for expected device ID; are there others? */ | 2202 | /* Check for expected device ID; are there others? */ |
2199 | 2203 | ||
2200 | while(chip->devid!=devid) { | 2204 | while (chip->devid != devid) { |
2201 | 2205 | ||
2202 | chip++; | 2206 | chip++; |
2203 | 2207 | ||
2204 | if (chip->name==NULL) | 2208 | if (chip->name == NULL) |
2205 | return NULL; | 2209 | return NULL; |
2206 | } | 2210 | } |
2207 | 2211 | ||
2208 | IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",devid,rev,cfg_base,type,chip->name); | 2212 | IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n", |
2213 | devid, rev, cfg_base, type, chip->name); | ||
2209 | 2214 | ||
2210 | if (chip->rev>rev){ | 2215 | if (chip->rev > rev) { |
2211 | IRDA_MESSAGE("Revision higher than expected\n"); | 2216 | IRDA_MESSAGE("Revision higher than expected\n"); |
2212 | return NULL; | 2217 | return NULL; |
2213 | } | 2218 | } |
2214 | 2219 | ||
2215 | if (chip->flags&NoIRDA) | 2220 | if (chip->flags & NoIRDA) |
2216 | IRDA_MESSAGE("chipset does not support IRDA\n"); | 2221 | IRDA_MESSAGE("chipset does not support IRDA\n"); |
2217 | 2222 | ||
2218 | return chip; | 2223 | return chip; |
@@ -2226,8 +2231,8 @@ static int __init smsc_superio_fdc(unsigned short cfg_base) | |||
2226 | IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", | 2231 | IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", |
2227 | __FUNCTION__, cfg_base); | 2232 | __FUNCTION__, cfg_base); |
2228 | } else { | 2233 | } else { |
2229 | if (!smsc_superio_flat(fdc_chips_flat,cfg_base,"FDC") | 2234 | if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") || |
2230 | ||!smsc_superio_paged(fdc_chips_paged,cfg_base,"FDC")) | 2235 | !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC")) |
2231 | ret = 0; | 2236 | ret = 0; |
2232 | 2237 | ||
2233 | release_region(cfg_base, 2); | 2238 | release_region(cfg_base, 2); |
@@ -2244,9 +2249,10 @@ static int __init smsc_superio_lpc(unsigned short cfg_base) | |||
2244 | IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", | 2249 | IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", |
2245 | __FUNCTION__, cfg_base); | 2250 | __FUNCTION__, cfg_base); |
2246 | } else { | 2251 | } else { |
2247 | if (!smsc_superio_flat(lpc_chips_flat,cfg_base,"LPC") | 2252 | if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") || |
2248 | ||!smsc_superio_paged(lpc_chips_paged,cfg_base,"LPC")) | 2253 | !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC")) |
2249 | ret = 0; | 2254 | ret = 0; |
2255 | |||
2250 | release_region(cfg_base, 2); | 2256 | release_region(cfg_base, 2); |
2251 | } | 2257 | } |
2252 | return ret; | 2258 | return ret; |
@@ -2269,18 +2275,23 @@ static int __init smsc_superio_lpc(unsigned short cfg_base) | |||
2269 | static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed) | 2275 | static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed) |
2270 | { | 2276 | { |
2271 | unsigned long jiffies_now, jiffies_timeout; | 2277 | unsigned long jiffies_now, jiffies_timeout; |
2272 | u8 val; | 2278 | u8 val; |
2273 | 2279 | ||
2274 | jiffies_now= jiffies; | 2280 | jiffies_now = jiffies; |
2275 | jiffies_timeout= jiffies+SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES; | 2281 | jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES; |
2276 | 2282 | ||
2277 | /* ATC */ | 2283 | /* ATC */ |
2278 | register_bank(fir_base, 4); | 2284 | register_bank(fir_base, 4); |
2279 | outb((inb(fir_base+IRCC_ATC) & IRCC_ATC_MASK) |IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, fir_base+IRCC_ATC); | 2285 | outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, |
2280 | while((val=(inb(fir_base+IRCC_ATC) & IRCC_ATC_nPROGREADY)) && !time_after(jiffies, jiffies_timeout)); | 2286 | fir_base + IRCC_ATC); |
2281 | if(val) | 2287 | |
2288 | while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) && | ||
2289 | !time_after(jiffies, jiffies_timeout)) | ||
2290 | /* empty */; | ||
2291 | |||
2292 | if (val) | ||
2282 | IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__, | 2293 | IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__, |
2283 | inb(fir_base+IRCC_ATC)); | 2294 | inb(fir_base + IRCC_ATC)); |
2284 | } | 2295 | } |
2285 | 2296 | ||
2286 | /* | 2297 | /* |
@@ -2304,22 +2315,20 @@ static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base) | |||
2304 | 2315 | ||
2305 | static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed) | 2316 | static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed) |
2306 | { | 2317 | { |
2307 | u8 fast_mode; | 2318 | u8 fast_mode; |
2308 | 2319 | ||
2309 | switch(speed) | 2320 | switch (speed) { |
2310 | { | 2321 | default: |
2311 | default: | 2322 | case 576000 : |
2312 | case 576000 : | ||
2313 | fast_mode = 0; | 2323 | fast_mode = 0; |
2314 | break; | 2324 | break; |
2315 | case 1152000 : | 2325 | case 1152000 : |
2316 | case 4000000 : | 2326 | case 4000000 : |
2317 | fast_mode = IRCC_LCR_A_FAST; | 2327 | fast_mode = IRCC_LCR_A_FAST; |
2318 | break; | 2328 | break; |
2319 | |||
2320 | } | 2329 | } |
2321 | register_bank(fir_base, 0); | 2330 | register_bank(fir_base, 0); |
2322 | outb((inb(fir_base+IRCC_LCR_A) & 0xbf) | fast_mode, fir_base+IRCC_LCR_A); | 2331 | outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); |
2323 | } | 2332 | } |
2324 | 2333 | ||
2325 | /* | 2334 | /* |
@@ -2343,23 +2352,22 @@ static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base) | |||
2343 | 2352 | ||
2344 | static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed) | 2353 | static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed) |
2345 | { | 2354 | { |
2346 | u8 fast_mode; | 2355 | u8 fast_mode; |
2347 | 2356 | ||
2348 | switch(speed) | 2357 | switch (speed) { |
2349 | { | 2358 | default: |
2350 | default: | 2359 | case 576000 : |
2351 | case 576000 : | ||
2352 | fast_mode = 0; | 2360 | fast_mode = 0; |
2353 | break; | 2361 | break; |
2354 | case 1152000 : | 2362 | case 1152000 : |
2355 | case 4000000 : | 2363 | case 4000000 : |
2356 | fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA; | 2364 | fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA; |
2357 | break; | 2365 | break; |
2358 | 2366 | ||
2359 | } | 2367 | } |
2360 | /* This causes an interrupt */ | 2368 | /* This causes an interrupt */ |
2361 | register_bank(fir_base, 0); | 2369 | register_bank(fir_base, 0); |
2362 | outb((inb(fir_base+IRCC_LCR_A) & 0xbf) | fast_mode, fir_base+IRCC_LCR_A); | 2370 | outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); |
2363 | } | 2371 | } |
2364 | 2372 | ||
2365 | /* | 2373 | /* |
@@ -2377,20 +2385,3 @@ static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base) | |||
2377 | 2385 | ||
2378 | module_init(smsc_ircc_init); | 2386 | module_init(smsc_ircc_init); |
2379 | module_exit(smsc_ircc_cleanup); | 2387 | module_exit(smsc_ircc_cleanup); |
2380 | |||
2381 | MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>"); | ||
2382 | MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver"); | ||
2383 | MODULE_LICENSE("GPL"); | ||
2384 | |||
2385 | module_param(ircc_dma, int, 0); | ||
2386 | MODULE_PARM_DESC(ircc_dma, "DMA channel"); | ||
2387 | module_param(ircc_irq, int, 0); | ||
2388 | MODULE_PARM_DESC(ircc_irq, "IRQ line"); | ||
2389 | module_param(ircc_fir, int, 0); | ||
2390 | MODULE_PARM_DESC(ircc_fir, "FIR Base Address"); | ||
2391 | module_param(ircc_sir, int, 0); | ||
2392 | MODULE_PARM_DESC(ircc_sir, "SIR Base Address"); | ||
2393 | module_param(ircc_cfg, int, 0); | ||
2394 | MODULE_PARM_DESC(ircc_cfg, "Configuration register base address"); | ||
2395 | module_param(ircc_transceiver, int, 0); | ||
2396 | MODULE_PARM_DESC(ircc_transceiver, "Transceiver type"); | ||