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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2009-04-26 10:06:28 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2009-06-19 14:00:50 -0400
commit59fe2d89b6ca0c046fde77e8b504d7a250758f44 (patch)
tree1ca7a4ab8efb09963f77d43d84c0a9c567af9811 /drivers
parent3fb468abc878cb8967d063c0d10094569c987d68 (diff)
Staging: rt2860: prepare for rt28[67]0/common/*.[ch] merge
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/rt2860/common/action.c6
-rw-r--r--drivers/staging/rt2860/common/ba_action.c63
-rw-r--r--drivers/staging/rt2860/common/cmm_data.c230
-rw-r--r--drivers/staging/rt2860/common/cmm_info.c45
-rw-r--r--drivers/staging/rt2860/common/cmm_sync.c13
-rw-r--r--drivers/staging/rt2860/common/cmm_wpa.c12
-rw-r--r--drivers/staging/rt2860/common/eeprom.c1268
-rw-r--r--drivers/staging/rt2860/common/mlme.c1163
-rw-r--r--drivers/staging/rt2860/common/rtmp_init.c861
-rw-r--r--drivers/staging/rt2860/common/spectrum.c5
10 files changed, 3644 insertions, 22 deletions
diff --git a/drivers/staging/rt2860/common/action.c b/drivers/staging/rt2860/common/action.c
index c270ccda2c11..a4d9fdc0736e 100644
--- a/drivers/staging/rt2860/common/action.c
+++ b/drivers/staging/rt2860/common/action.c
@@ -527,9 +527,15 @@ VOID SendRefreshBAR(
527 MakeOutgoingFrame(pOutBuffer, &FrameLen, 527 MakeOutgoingFrame(pOutBuffer, &FrameLen,
528 sizeof(FRAME_BAR), &FrameBar, 528 sizeof(FRAME_BAR), &FrameBar,
529 END_OF_ARGS); 529 END_OF_ARGS);
530
530 if (1) // Now we always send BAR. 531 if (1) // Now we always send BAR.
531 { 532 {
533#ifndef RT30xx
532 MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen); 534 MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
535#endif
536#ifdef RT30xx
537 MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen);
538#endif
533 } 539 }
534 MlmeFreeMemory(pAd, pOutBuffer); 540 MlmeFreeMemory(pAd, pOutBuffer);
535 } 541 }
diff --git a/drivers/staging/rt2860/common/ba_action.c b/drivers/staging/rt2860/common/ba_action.c
index 6b0898dc2087..b95a341caacd 100644
--- a/drivers/staging/rt2860/common/ba_action.c
+++ b/drivers/staging/rt2860/common/ba_action.c
@@ -531,6 +531,13 @@ VOID BAOriSessionSetUp(
531 pBAEntry->TimeOutValue = TimeOut; 531 pBAEntry->TimeOutValue = TimeOut;
532 pBAEntry->pAdapter = pAd; 532 pBAEntry->pAdapter = pAd;
533 533
534#ifdef RT30xx
535 DBGPRINT(RT_DEBUG_TRACE,("Send AddBA to %02x:%02x:%02x:%02x:%02x:%02x Tid:%d isForced:%d Wcid:%d\n"
536 ,pEntry->Addr[0],pEntry->Addr[1],pEntry->Addr[2]
537 ,pEntry->Addr[3],pEntry->Addr[4],pEntry->Addr[5]
538 ,TID,isForced,pEntry->Aid));
539#endif
540
534 if (!(pEntry->TXBAbitmap & (1<<TID))) 541 if (!(pEntry->TXBAbitmap & (1<<TID)))
535 { 542 {
536 RTMPInitTimer(pAd, &pBAEntry->ORIBATimer, GET_TIMER_FUNCTION(BAOriSessionSetupTimeout), pBAEntry, FALSE); 543 RTMPInitTimer(pAd, &pBAEntry->ORIBATimer, GET_TIMER_FUNCTION(BAOriSessionSetupTimeout), pBAEntry, FALSE);
@@ -1071,8 +1078,16 @@ VOID BAOriSessionSetupTimeout(
1071 AddbaReq.Token = pBAEntry->Token; 1078 AddbaReq.Token = pBAEntry->Token;
1072 MlmeEnqueue(pAd, ACTION_STATE_MACHINE, MT2_MLME_ADD_BA_CATE, sizeof(MLME_ADDBA_REQ_STRUCT), (PVOID)&AddbaReq); 1079 MlmeEnqueue(pAd, ACTION_STATE_MACHINE, MT2_MLME_ADD_BA_CATE, sizeof(MLME_ADDBA_REQ_STRUCT), (PVOID)&AddbaReq);
1073 RT28XX_MLME_HANDLER(pAd); 1080 RT28XX_MLME_HANDLER(pAd);
1081#ifndef RT30xx
1074 DBGPRINT(RT_DEBUG_TRACE,("BA Ori Session Timeout(%d) : Send ADD BA again\n", pBAEntry->Token)); 1082 DBGPRINT(RT_DEBUG_TRACE,("BA Ori Session Timeout(%d) : Send ADD BA again\n", pBAEntry->Token));
1075 1083#endif
1084#ifdef RT30xx
1085 DBGPRINT(RT_DEBUG_TRACE,("BA Ori Session Timeout(%d) to %02x:%02x:%02x:%02x:%02x:%02x Tid:%d Wcid:%d\n"
1086 ,pBAEntry->Token
1087 ,pEntry->Addr[0],pEntry->Addr[1],pEntry->Addr[2]
1088 ,pEntry->Addr[3],pEntry->Addr[4],pEntry->Addr[5]
1089 ,pBAEntry->TID,pEntry->Aid));
1090#endif
1076 pBAEntry->Token++; 1091 pBAEntry->Token++;
1077 RTMPSetTimer(&pBAEntry->ORIBATimer, ORI_BA_SESSION_TIMEOUT); 1092 RTMPSetTimer(&pBAEntry->ORIBATimer, ORI_BA_SESSION_TIMEOUT);
1078 } 1093 }
@@ -1376,6 +1391,10 @@ VOID SendPSMPAction(
1376 //ULONG Idx; 1391 //ULONG Idx;
1377 FRAME_PSMP_ACTION Frame; 1392 FRAME_PSMP_ACTION Frame;
1378 ULONG FrameLen; 1393 ULONG FrameLen;
1394#ifdef RT30xx
1395 UCHAR bbpdata=0;
1396 UINT32 macdata;
1397#endif // RT30xx //
1379 1398
1380 NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); //Get an unused nonpaged memory 1399 NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); //Get an unused nonpaged memory
1381 if (NStatus != NDIS_STATUS_SUCCESS) 1400 if (NStatus != NDIS_STATUS_SUCCESS)
@@ -1391,12 +1410,54 @@ VOID SendPSMPAction(
1391 switch (Psmp) 1410 switch (Psmp)
1392 { 1411 {
1393 case MMPS_ENABLE: 1412 case MMPS_ENABLE:
1413#ifdef RT30xx
1414 if (IS_RT3090(pAd))
1415 {
1416 // disable MMPS BBP control register
1417 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &bbpdata);
1418 bbpdata &= ~(0x04); //bit 2
1419 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, bbpdata);
1420
1421 // disable MMPS MAC control register
1422 RTMP_IO_READ32(pAd, 0x1210, &macdata);
1423 macdata &= ~(0x09); //bit 0, 3
1424 RTMP_IO_WRITE32(pAd, 0x1210, macdata);
1425 }
1426#endif // RT30xx //
1394 Frame.Psmp = 0; 1427 Frame.Psmp = 0;
1395 break; 1428 break;
1396 case MMPS_DYNAMIC: 1429 case MMPS_DYNAMIC:
1430#ifdef RT30xx
1431 if (IS_RT3090(pAd))
1432 {
1433 // enable MMPS BBP control register
1434 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &bbpdata);
1435 bbpdata |= 0x04; //bit 2
1436 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, bbpdata);
1437
1438 // enable MMPS MAC control register
1439 RTMP_IO_READ32(pAd, 0x1210, &macdata);
1440 macdata |= 0x09; //bit 0, 3
1441 RTMP_IO_WRITE32(pAd, 0x1210, macdata);
1442 }
1443#endif // RT30xx //
1397 Frame.Psmp = 3; 1444 Frame.Psmp = 3;
1398 break; 1445 break;
1399 case MMPS_STATIC: 1446 case MMPS_STATIC:
1447#ifdef RT30xx
1448 if (IS_RT3090(pAd))
1449 {
1450 // enable MMPS BBP control register
1451 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &bbpdata);
1452 bbpdata |= 0x04; //bit 2
1453 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, bbpdata);
1454
1455 // enable MMPS MAC control register
1456 RTMP_IO_READ32(pAd, 0x1210, &macdata);
1457 macdata |= 0x09; //bit 0, 3
1458 RTMP_IO_WRITE32(pAd, 0x1210, macdata);
1459 }
1460#endif // RT30xx //
1400 Frame.Psmp = 1; 1461 Frame.Psmp = 1;
1401 break; 1462 break;
1402 } 1463 }
diff --git a/drivers/staging/rt2860/common/cmm_data.c b/drivers/staging/rt2860/common/cmm_data.c
index d857d06fd772..66eca202eae4 100644
--- a/drivers/staging/rt2860/common/cmm_data.c
+++ b/drivers/staging/rt2860/common/cmm_data.c
@@ -105,7 +105,9 @@ NDIS_STATUS MiniportMMRequest(
105 PNDIS_PACKET pPacket; 105 PNDIS_PACKET pPacket;
106 NDIS_STATUS Status = NDIS_STATUS_SUCCESS; 106 NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
107 ULONG FreeNum; 107 ULONG FreeNum;
108#ifdef RT2860
108 unsigned long IrqFlags = 0; 109 unsigned long IrqFlags = 0;
110#endif
109 UCHAR IrqState; 111 UCHAR IrqState;
110 UCHAR rtmpHwHdr[TXINFO_SIZE + TXWI_SIZE]; //RTMP_HW_HDR_LEN]; 112 UCHAR rtmpHwHdr[TXINFO_SIZE + TXWI_SIZE]; //RTMP_HW_HDR_LEN];
111 113
@@ -117,9 +119,10 @@ NDIS_STATUS MiniportMMRequest(
117 119
118 IrqState = pAd->irq_disabled; 120 IrqState = pAd->irq_disabled;
119 121
122#ifdef RT2860
120 if ((pAd->MACVersion == 0x28600100) && (!IrqState)) 123 if ((pAd->MACVersion == 0x28600100) && (!IrqState))
121 RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags); 124 RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags);
122 125#endif
123 do 126 do
124 { 127 {
125 // Reset is in progress, stop immediately 128 // Reset is in progress, stop immediately
@@ -172,14 +175,15 @@ NDIS_STATUS MiniportMMRequest(
172 175
173 } while (FALSE); 176 } while (FALSE);
174 177
178#ifdef RT2860
175 // 2860C use Tx Ring 179 // 2860C use Tx Ring
176 if ((pAd->MACVersion == 0x28600100) && (!IrqState)) 180 if ((pAd->MACVersion == 0x28600100) && (!IrqState))
177 RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags); 181 RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags);
178 182#endif
179 return Status; 183 return Status;
180} 184}
181 185
182 186#ifdef RT2860
183NDIS_STATUS MiniportMMRequestUnlock( 187NDIS_STATUS MiniportMMRequestUnlock(
184 IN PRTMP_ADAPTER pAd, 188 IN PRTMP_ADAPTER pAd,
185 IN UCHAR QueIdx, 189 IN UCHAR QueIdx,
@@ -247,8 +251,116 @@ NDIS_STATUS MiniportMMRequestUnlock(
247 251
248 return Status; 252 return Status;
249} 253}
254#endif
255#ifdef RT30xx
256NDIS_STATUS MlmeDataHardTransmit(
257 IN PRTMP_ADAPTER pAd,
258 IN UCHAR QueIdx,
259 IN PNDIS_PACKET pPacket);
260
261#define MAX_DATAMM_RETRY 3
262/*
263 ========================================================================
264
265 Routine Description:
266 API for MLME to transmit management frame to AP (BSS Mode)
267 or station (IBSS Mode)
268
269 Arguments:
270 pAd Pointer to our adapter
271 pData Pointer to the outgoing 802.11 frame
272 Length Size of outgoing management frame
273
274 Return Value:
275 NDIS_STATUS_FAILURE
276 NDIS_STATUS_PENDING
277 NDIS_STATUS_SUCCESS
278
279 IRQL = PASSIVE_LEVEL
280 IRQL = DISPATCH_LEVEL
281
282 Note:
283
284 ========================================================================
285*/
286NDIS_STATUS MiniportDataMMRequest(
287 IN PRTMP_ADAPTER pAd,
288 IN UCHAR QueIdx,
289 IN PUCHAR pData,
290 IN UINT Length)
291{
292 PNDIS_PACKET pPacket;
293 NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
294 ULONG FreeNum;
295 int retry = 0;
296 UCHAR IrqState;
297 UCHAR rtmpHwHdr[TXINFO_SIZE + TXWI_SIZE]; //RTMP_HW_HDR_LEN];
298
299 ASSERT(Length <= MGMT_DMA_BUFFER_SIZE);
300
301 // 2860C use Tx Ring
302 IrqState = pAd->irq_disabled;
303
304 do
305 {
306 // Reset is in progress, stop immediately
307 if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS) ||
308 RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST)||
309 !RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_START_UP))
310 {
311 Status = NDIS_STATUS_FAILURE;
312 break;
313 }
314
315 // Check Free priority queue
316 // Since we use PBF Queue2 for management frame. Its corresponding DMA ring should be using TxRing.
317
318 // 2860C use Tx Ring
319
320 // free Tx(QueIdx) resources
321 FreeNum = GET_TXRING_FREENO(pAd, QueIdx);
322
323 if ((FreeNum > 0))
324 {
325 // We need to reserve space for rtmp hardware header. i.e., TxWI for RT2860 and TxInfo+TxWI for RT2870
326 NdisZeroMemory(&rtmpHwHdr, (TXINFO_SIZE + TXWI_SIZE));
327 Status = RTMPAllocateNdisPacket(pAd, &pPacket, (PUCHAR)&rtmpHwHdr, (TXINFO_SIZE + TXWI_SIZE), pData, Length);
328 if (Status != NDIS_STATUS_SUCCESS)
329 {
330 DBGPRINT(RT_DEBUG_WARN, ("MiniportMMRequest (error:: can't allocate NDIS PACKET)\n"));
331 break;
332 }
333
334 //pAd->CommonCfg.MlmeTransmit.field.MODE = MODE_CCK;
335 //pAd->CommonCfg.MlmeRate = RATE_2;
250 336
251 337
338 Status = MlmeDataHardTransmit(pAd, QueIdx, pPacket);
339 if (Status != NDIS_STATUS_SUCCESS)
340 RTMPFreeNdisPacket(pAd, pPacket);
341 retry = MAX_DATAMM_RETRY;
342 }
343 else
344 {
345 retry ++;
346
347 printk("retry %d\n", retry);
348 pAd->RalinkCounters.MgmtRingFullCount++;
349
350 if (retry >= MAX_DATAMM_RETRY)
351 {
352 DBGPRINT(RT_DEBUG_ERROR, ("Qidx(%d), not enough space in DataRing, MgmtRingFullCount=%ld!\n",
353 QueIdx, pAd->RalinkCounters.MgmtRingFullCount));
354 }
355 }
356
357 } while (retry < MAX_DATAMM_RETRY);
358
359
360 return Status;
361}
362#endif /* RT30xx */
363
252/* 364/*
253 ======================================================================== 365 ========================================================================
254 366
@@ -283,14 +395,16 @@ NDIS_STATUS MlmeHardTransmit(
283 return NDIS_STATUS_FAILURE; 395 return NDIS_STATUS_FAILURE;
284 } 396 }
285 397
398#ifdef RT2860
286 if ( pAd->MACVersion == 0x28600100 ) 399 if ( pAd->MACVersion == 0x28600100 )
287 return MlmeHardTransmitTxRing(pAd,QueIdx,pPacket); 400 return MlmeHardTransmitTxRing(pAd,QueIdx,pPacket);
288 else 401 else
402#endif
289 return MlmeHardTransmitMgmtRing(pAd,QueIdx,pPacket); 403 return MlmeHardTransmitMgmtRing(pAd,QueIdx,pPacket);
290 404
291} 405}
292 406
293 407#ifdef RT2860
294NDIS_STATUS MlmeHardTransmitTxRing( 408NDIS_STATUS MlmeHardTransmitTxRing(
295 IN PRTMP_ADAPTER pAd, 409 IN PRTMP_ADAPTER pAd,
296 IN UCHAR QueIdx, 410 IN UCHAR QueIdx,
@@ -472,7 +586,25 @@ NDIS_STATUS MlmeHardTransmitTxRing(
472 586
473 return NDIS_STATUS_SUCCESS; 587 return NDIS_STATUS_SUCCESS;
474} 588}
589#endif /* RT2860 */
590
591#ifdef RT30xx
592NDIS_STATUS MlmeDataHardTransmit(
593 IN PRTMP_ADAPTER pAd,
594 IN UCHAR QueIdx,
595 IN PNDIS_PACKET pPacket)
596{
597 if ((pAd->CommonCfg.RadarDetect.RDMode != RD_NORMAL_MODE)
598 )
599 {
600 return NDIS_STATUS_FAILURE;
601 }
475 602
603#ifdef RT2870
604 return MlmeHardTransmitMgmtRing(pAd,QueIdx,pPacket);
605#endif // RT2870 //
606}
607#endif /* RT30xx */
476 608
477NDIS_STATUS MlmeHardTransmitMgmtRing( 609NDIS_STATUS MlmeHardTransmitMgmtRing(
478 IN PRTMP_ADAPTER pAd, 610 IN PRTMP_ADAPTER pAd,
@@ -500,7 +632,12 @@ NDIS_STATUS MlmeHardTransmitMgmtRing(
500 632
501 // outgoing frame always wakeup PHY to prevent frame lost 633 // outgoing frame always wakeup PHY to prevent frame lost
502 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) 634 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
635#ifdef RT2860
503 AsicForceWakeup(pAd, FROM_TX); 636 AsicForceWakeup(pAd, FROM_TX);
637#endif
638#ifdef RT2870
639 AsicForceWakeup(pAd, TRUE);
640#endif
504 641
505 pFirstTxWI = (PTXWI_STRUC)(pSrcBufVA + TXINFO_SIZE); 642 pFirstTxWI = (PTXWI_STRUC)(pSrcBufVA + TXINFO_SIZE);
506 pHeader_802_11 = (PHEADER_802_11) (pSrcBufVA + TXINFO_SIZE + TXWI_SIZE); //TXWI_SIZE); 643 pHeader_802_11 = (PHEADER_802_11) (pSrcBufVA + TXINFO_SIZE + TXWI_SIZE); //TXWI_SIZE);
@@ -823,7 +960,13 @@ BOOLEAN RTMP_FillTxBlkInfo(
823 960
824 { 961 {
825 // If support WMM, enable it. 962 // If support WMM, enable it.
963#ifdef RT2860
826 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED)) 964 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED))
965#endif
966#ifdef RT2870
967 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED) &&
968 CLIENT_STATUS_TEST_FLAG(pMacEntry, fCLIENT_STATUS_WMM_CAPABLE))
969#endif
827 TX_BLK_SET_FLAG(pTxBlk, fTX_bWMM); 970 TX_BLK_SET_FLAG(pTxBlk, fTX_bWMM);
828 } 971 }
829 972
@@ -870,6 +1013,11 @@ BOOLEAN RTMP_FillTxBlkInfo(
870 } 1013 }
871 1014
872 return TRUE; 1015 return TRUE;
1016
1017#ifdef RT30xx
1018FillTxBlkErr:
1019 return FALSE;
1020#endif
873} 1021}
874 1022
875 1023
@@ -957,6 +1105,7 @@ VOID RTMPDeQueuePacket(
957 if (QIdx == NUM_OF_TX_RING) 1105 if (QIdx == NUM_OF_TX_RING)
958 { 1106 {
959 sQIdx = 0; 1107 sQIdx = 0;
1108//PS packets use HCCA queue when dequeue from PS unicast queue (WiFi WPA2 MA9_DT1 for Marvell B STA)
960 eQIdx = 3; // 4 ACs, start from 0. 1109 eQIdx = 3; // 4 ACs, start from 0.
961 } 1110 }
962 else 1111 else
@@ -999,7 +1148,7 @@ VOID RTMPDeQueuePacket(
999 DEQUEUE_UNLOCK(&pAd->irq_lock, bIntContext, IrqFlags); 1148 DEQUEUE_UNLOCK(&pAd->irq_lock, bIntContext, IrqFlags);
1000 break; 1149 break;
1001 } 1150 }
1002 1151#ifdef RT2860
1003 FreeNumber[QueIdx] = GET_TXRING_FREENO(pAd, QueIdx); 1152 FreeNumber[QueIdx] = GET_TXRING_FREENO(pAd, QueIdx);
1004 1153
1005#ifdef DBG_DIAGNOSE 1154#ifdef DBG_DIAGNOSE
@@ -1024,7 +1173,7 @@ VOID RTMPDeQueuePacket(
1024 RTMPFreeTXDUponTxDmaDone(pAd, QueIdx); 1173 RTMPFreeTXDUponTxDmaDone(pAd, QueIdx);
1025 FreeNumber[QueIdx] = GET_TXRING_FREENO(pAd, QueIdx); 1174 FreeNumber[QueIdx] = GET_TXRING_FREENO(pAd, QueIdx);
1026 } 1175 }
1027 1176#endif /* RT2860 */
1028 // probe the Queue Head 1177 // probe the Queue Head
1029 pQueue = &pAd->TxSwQueue[QueIdx]; 1178 pQueue = &pAd->TxSwQueue[QueIdx];
1030 if ((pEntry = pQueue->Head) == NULL) 1179 if ((pEntry = pQueue->Head) == NULL)
@@ -1093,19 +1242,29 @@ VOID RTMPDeQueuePacket(
1093 pTxBlk->TxFrameType = TX_LEGACY_FRAME; 1242 pTxBlk->TxFrameType = TX_LEGACY_FRAME;
1094 } 1243 }
1095 1244
1245#ifdef RT2870
1246 DEQUEUE_UNLOCK(&pAd->irq_lock, bIntContext, IrqFlags);
1247#endif // RT2870 //
1096 1248
1097 Count += pTxBlk->TxPacketList.Number; 1249 Count += pTxBlk->TxPacketList.Number;
1098 1250
1099 // Do HardTransmit now. 1251 // Do HardTransmit now.
1100 Status = STAHardTransmit(pAd, pTxBlk, QueIdx); 1252 Status = STAHardTransmit(pAd, pTxBlk, QueIdx);
1101 1253
1254#ifdef RT2860
1102 DEQUEUE_UNLOCK(&pAd->irq_lock, bIntContext, IrqFlags); 1255 DEQUEUE_UNLOCK(&pAd->irq_lock, bIntContext, IrqFlags);
1103 // static rate also need NICUpdateFifoStaCounters() function. 1256 // static rate also need NICUpdateFifoStaCounters() function.
1104 //if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED)) 1257 //if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED))
1105 NICUpdateFifoStaCounters(pAd); 1258 NICUpdateFifoStaCounters(pAd);
1259#endif
1106 } 1260 }
1107 1261
1108 RT28XX_STOP_DEQUEUE(pAd, QueIdx, IrqFlags); 1262 RT28XX_STOP_DEQUEUE(pAd, QueIdx, IrqFlags);
1263
1264#ifdef RT2870
1265 if (!hasTxDesc)
1266 RTUSBKickBulkOut(pAd);
1267#endif // RT2870 //
1109 } 1268 }
1110 1269
1111} 1270}
@@ -1633,7 +1792,7 @@ PQUEUE_HEADER RTMPCheckTxSwQueue(
1633 return (NULL); 1792 return (NULL);
1634} 1793}
1635 1794
1636 1795#ifdef RT2860
1637BOOLEAN RTMPFreeTXDUponTxDmaDone( 1796BOOLEAN RTMPFreeTXDUponTxDmaDone(
1638 IN PRTMP_ADAPTER pAd, 1797 IN PRTMP_ADAPTER pAd,
1639 IN UCHAR QueIdx) 1798 IN UCHAR QueIdx)
@@ -2016,6 +2175,7 @@ VOID DBGPRINT_RX_RING(
2016 DBGPRINT_RAW(RT_DEBUG_TRACE,(" RxSwReadIdx [%d]=", AC0freeIdx)); 2175 DBGPRINT_RAW(RT_DEBUG_TRACE,(" RxSwReadIdx [%d]=", AC0freeIdx));
2017 DBGPRINT_RAW(RT_DEBUG_TRACE,(" pending-NDIS=%ld\n", pAd->RalinkCounters.PendingNdisPacketCount)); 2176 DBGPRINT_RAW(RT_DEBUG_TRACE,(" pending-NDIS=%ld\n", pAd->RalinkCounters.PendingNdisPacketCount));
2018} 2177}
2178#endif /* RT2860 */
2019 2179
2020/* 2180/*
2021 ======================================================================== 2181 ========================================================================
@@ -2075,7 +2235,15 @@ VOID RTMPResumeMsduTransmission(
2075{ 2235{
2076 DBGPRINT(RT_DEBUG_TRACE,("SCAN done, resume MSDU transmission ...\n")); 2236 DBGPRINT(RT_DEBUG_TRACE,("SCAN done, resume MSDU transmission ...\n"));
2077 2237
2078 2238#ifdef RT30xx
2239 // After finish BSS_SCAN_IN_PROGRESS, we need to restore Current R66 value
2240 // R66 should not be 0
2241 if (pAd->BbpTuning.R66CurrentValue == 0)
2242 {
2243 pAd->BbpTuning.R66CurrentValue = 0x38;
2244 DBGPRINT_ERR(("RTMPResumeMsduTransmission, R66CurrentValue=0...\n"));
2245 }
2246#endif
2079 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, pAd->BbpTuning.R66CurrentValue); 2247 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, pAd->BbpTuning.R66CurrentValue);
2080 2248
2081 RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS); 2249 RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS);
@@ -2298,7 +2466,9 @@ MAC_TABLE_ENTRY *MacTableInsertEntry(
2298 pEntry->AuthMode = pAd->StaCfg.AuthMode; 2466 pEntry->AuthMode = pAd->StaCfg.AuthMode;
2299 pEntry->WepStatus = pAd->StaCfg.WepStatus; 2467 pEntry->WepStatus = pAd->StaCfg.WepStatus;
2300 pEntry->PrivacyFilter = Ndis802_11PrivFilterAcceptAll; 2468 pEntry->PrivacyFilter = Ndis802_11PrivFilterAcceptAll;
2469#ifdef RT2860
2301 AsicRemovePairwiseKeyEntry(pAd, pEntry->apidx, (UCHAR)i); 2470 AsicRemovePairwiseKeyEntry(pAd, pEntry->apidx, (UCHAR)i);
2471#endif
2302 } 2472 }
2303 } 2473 }
2304 2474
@@ -2306,10 +2476,12 @@ MAC_TABLE_ENTRY *MacTableInsertEntry(
2306 pEntry->PairwiseKey.KeyLen = 0; 2476 pEntry->PairwiseKey.KeyLen = 0;
2307 pEntry->PairwiseKey.CipherAlg = CIPHER_NONE; 2477 pEntry->PairwiseKey.CipherAlg = CIPHER_NONE;
2308 2478
2479#ifdef RT2860
2309 if ((pAd->OpMode == OPMODE_STA) && 2480 if ((pAd->OpMode == OPMODE_STA) &&
2310 (pAd->StaCfg.BssType == BSS_ADHOC)) 2481 (pAd->StaCfg.BssType == BSS_ADHOC))
2311 pEntry->PortSecured = WPA_802_1X_PORT_SECURED; 2482 pEntry->PortSecured = WPA_802_1X_PORT_SECURED;
2312 else 2483 else
2484#endif
2313 pEntry->PortSecured = WPA_802_1X_PORT_NOT_SECURED; 2485 pEntry->PortSecured = WPA_802_1X_PORT_NOT_SECURED;
2314 2486
2315 pEntry->PMKID_CacheIdx = ENTRY_NOT_FOUND; 2487 pEntry->PMKID_CacheIdx = ENTRY_NOT_FOUND;
@@ -2445,7 +2617,12 @@ BOOLEAN MacTableDeleteEntry(
2445 if (pAd->MacTab.Size == 0) 2617 if (pAd->MacTab.Size == 0)
2446 { 2618 {
2447 pAd->CommonCfg.AddHTInfo.AddHtInfo2.OperaionMode = 0; 2619 pAd->CommonCfg.AddHTInfo.AddHtInfo2.OperaionMode = 0;
2620#ifndef RT30xx
2448 AsicUpdateProtect(pAd, 0 /*pAd->CommonCfg.AddHTInfo.AddHtInfo2.OperaionMode*/, (ALLN_SETPROTECT), TRUE, 0 /*pAd->MacTab.fAnyStationNonGF*/); 2621 AsicUpdateProtect(pAd, 0 /*pAd->CommonCfg.AddHTInfo.AddHtInfo2.OperaionMode*/, (ALLN_SETPROTECT), TRUE, 0 /*pAd->MacTab.fAnyStationNonGF*/);
2622#endif
2623#ifdef RT30xx
2624 RT28XX_UPDATE_PROTECT(pAd); // edit by johnli, fix "in_interrupt" error when call "MacTableDeleteEntry" in Rx tasklet
2625#endif
2449 } 2626 }
2450 2627
2451 return TRUE; 2628 return TRUE;
@@ -2469,7 +2646,9 @@ VOID MacTableReset(
2469 2646
2470 for (i=1; i<MAX_LEN_OF_MAC_TABLE; i++) 2647 for (i=1; i<MAX_LEN_OF_MAC_TABLE; i++)
2471 { 2648 {
2649#ifdef RT2860
2472 RT28XX_STA_ENTRY_MAC_RESET(pAd, i); 2650 RT28XX_STA_ENTRY_MAC_RESET(pAd, i);
2651#endif
2473 if (pAd->MacTab.Content[i].ValidAsCLI == TRUE) 2652 if (pAd->MacTab.Content[i].ValidAsCLI == TRUE)
2474 { 2653 {
2475 // free resources of BA 2654 // free resources of BA
@@ -2479,6 +2658,10 @@ VOID MacTableReset(
2479 2658
2480 2659
2481 2660
2661#ifdef RT2870
2662 NdisZeroMemory(pAd->MacTab.Content[i].Addr, 6);
2663 RT28XX_STA_ENTRY_MAC_RESET(pAd, i);
2664#endif // RT2870 //
2482 2665
2483 //AsicDelWcidTab(pAd, i); 2666 //AsicDelWcidTab(pAd, i);
2484 } 2667 }
@@ -2791,6 +2974,37 @@ VOID Indicate_Legacy_Packet(
2791 2974
2792 STATS_INC_RX_PACKETS(pAd, FromWhichBSSID); 2975 STATS_INC_RX_PACKETS(pAd, FromWhichBSSID);
2793 2976
2977#ifdef RT2870
2978 if (pAd->CommonCfg.bDisableReordering == 0)
2979 {
2980 PBA_REC_ENTRY pBAEntry;
2981 ULONG Now32;
2982 UCHAR Wcid = pRxBlk->pRxWI->WirelessCliID;
2983 UCHAR TID = pRxBlk->pRxWI->TID;
2984 USHORT Idx;
2985
2986#define REORDERING_PACKET_TIMEOUT ((100 * HZ)/1000) // system ticks -- 100 ms
2987
2988 if (Wcid < MAX_LEN_OF_MAC_TABLE)
2989 {
2990 Idx = pAd->MacTab.Content[Wcid].BARecWcidArray[TID];
2991 if (Idx != 0)
2992 {
2993 pBAEntry = &pAd->BATable.BARecEntry[Idx];
2994 // update last rx time
2995 NdisGetSystemUpTime(&Now32);
2996 if ((pBAEntry->list.qlen > 0) &&
2997 RTMP_TIME_AFTER((unsigned long)Now32, (unsigned long)(pBAEntry->LastIndSeqAtTimer+(REORDERING_PACKET_TIMEOUT)))
2998 )
2999 {
3000 printk("Indicate_Legacy_Packet():flush reordering_timeout_mpdus! RxWI->Flags=%d, pRxWI.TID=%d, RxD->AMPDU=%d!\n", pRxBlk->Flags, pRxBlk->pRxWI->TID, pRxBlk->RxD.AMPDU);
3001 hex_dump("Dump the legacy Packet:", GET_OS_PKT_DATAPTR(pRxBlk->pRxPacket), 64);
3002 ba_flush_reordering_timeout_mpdus(pAd, pBAEntry, Now32);
3003 }
3004 }
3005 }
3006 }
3007#endif // RT2870 //
2794 3008
2795 wlan_802_11_to_802_3_packet(pAd, pRxBlk, Header802_3, FromWhichBSSID); 3009 wlan_802_11_to_802_3_packet(pAd, pRxBlk, Header802_3, FromWhichBSSID);
2796 3010
diff --git a/drivers/staging/rt2860/common/cmm_info.c b/drivers/staging/rt2860/common/cmm_info.c
index ea76f5b252cf..306c3a21f905 100644
--- a/drivers/staging/rt2860/common/cmm_info.c
+++ b/drivers/staging/rt2860/common/cmm_info.c
@@ -762,6 +762,7 @@ INT Show_DescInfo_Proc(
762 IN PRTMP_ADAPTER pAd, 762 IN PRTMP_ADAPTER pAd,
763 IN PUCHAR arg) 763 IN PUCHAR arg)
764{ 764{
765#ifdef RT2860
765 INT i, QueIdx=0; 766 INT i, QueIdx=0;
766 PRT28XX_RXD_STRUC pRxD; 767 PRT28XX_RXD_STRUC pRxD;
767 PTXD_STRUC pTxD; 768 PTXD_STRUC pTxD;
@@ -792,7 +793,7 @@ INT Show_DescInfo_Proc(
792 hex_dump("Rx Descriptor", (char *)pRxD, 16); 793 hex_dump("Rx Descriptor", (char *)pRxD, 16);
793 printk("pRxD->DDONE = %x\n", pRxD->DDONE); 794 printk("pRxD->DDONE = %x\n", pRxD->DDONE);
794 } 795 }
795 796#endif /* RT2860 */
796 return TRUE; 797 return TRUE;
797} 798}
798 799
@@ -1418,6 +1419,16 @@ VOID RTMPSetHT(
1418 pAd->CommonCfg.DesiredHtPhy.RxSTBC = 0; 1419 pAd->CommonCfg.DesiredHtPhy.RxSTBC = 0;
1419 } 1420 }
1420 1421
1422#ifndef RT30xx
1423#ifdef RT2870
1424 /* Frank recommend ,If not, Tx maybe block in high power. Rx has no problem*/
1425 if(IS_RT3070(pAd) && ((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020)))
1426 {
1427 pAd->CommonCfg.HtCapability.HtCapInfo.TxSTBC = 0;
1428 pAd->CommonCfg.DesiredHtPhy.TxSTBC = 0;
1429 }
1430#endif // RT2870 //
1431#endif
1421 1432
1422 if(pHTPhyMode->SHORTGI == GI_400) 1433 if(pHTPhyMode->SHORTGI == GI_400)
1423 { 1434 {
@@ -1696,7 +1707,12 @@ VOID RTMPAddWcidAttributeEntry(
1696 } 1707 }
1697 1708
1698 // For key index and ext IV bit, so only need to update the position(offset+3). 1709 // For key index and ext IV bit, so only need to update the position(offset+3).
1710#ifdef RT2860
1699 RTMP_IO_WRITE8(pAd, offset+3, IVEIV); 1711 RTMP_IO_WRITE8(pAd, offset+3, IVEIV);
1712#endif
1713#ifdef RT2870
1714 RTUSBMultiWrite_OneByte(pAd, offset+3, &IVEIV);
1715#endif // RT2870 //
1700 1716
1701 DBGPRINT(RT_DEBUG_TRACE,("RTMPAddWcidAttributeEntry: WCID #%d, KeyIndex #%d, Alg=%s\n",Wcid, KeyIdx, CipherName[CipherAlg])); 1717 DBGPRINT(RT_DEBUG_TRACE,("RTMPAddWcidAttributeEntry: WCID #%d, KeyIndex #%d, Alg=%s\n",Wcid, KeyIdx, CipherName[CipherAlg]));
1702 DBGPRINT(RT_DEBUG_TRACE,(" WCIDAttri = 0x%x \n", WCIDAttri)); 1718 DBGPRINT(RT_DEBUG_TRACE,(" WCIDAttri = 0x%x \n", WCIDAttri));
@@ -2473,13 +2489,26 @@ INT Set_HtAutoBa_Proc(
2473 2489
2474 Value = simple_strtol(arg, 0, 10); 2490 Value = simple_strtol(arg, 0, 10);
2475 if (Value == 0) 2491 if (Value == 0)
2492 {
2476 pAd->CommonCfg.BACapability.field.AutoBA = FALSE; 2493 pAd->CommonCfg.BACapability.field.AutoBA = FALSE;
2494#ifdef RT30xx
2495 pAd->CommonCfg.BACapability.field.Policy = BA_NOTUSE;
2496#endif
2497 }
2477 else if (Value == 1) 2498 else if (Value == 1)
2499 {
2478 pAd->CommonCfg.BACapability.field.AutoBA = TRUE; 2500 pAd->CommonCfg.BACapability.field.AutoBA = TRUE;
2501#ifdef RT30xx
2502 pAd->CommonCfg.BACapability.field.Policy = IMMED_BA;
2503#endif
2504 }
2479 else 2505 else
2480 return FALSE; //Invalid argument 2506 return FALSE; //Invalid argument
2481 2507
2482 pAd->CommonCfg.REGBACapability.field.AutoBA = pAd->CommonCfg.BACapability.field.AutoBA; 2508 pAd->CommonCfg.REGBACapability.field.AutoBA = pAd->CommonCfg.BACapability.field.AutoBA;
2509#ifdef RT30xx
2510 pAd->CommonCfg.REGBACapability.field.Policy = pAd->CommonCfg.BACapability.field.Policy;
2511#endif
2483 SetCommonHT(pAd); 2512 SetCommonHT(pAd);
2484 2513
2485 DBGPRINT(RT_DEBUG_TRACE, ("Set_HtAutoBa_Proc::(HtAutoBa=%d)\n",pAd->CommonCfg.BACapability.field.AutoBA)); 2514 DBGPRINT(RT_DEBUG_TRACE, ("Set_HtAutoBa_Proc::(HtAutoBa=%d)\n",pAd->CommonCfg.BACapability.field.AutoBA));
@@ -2696,7 +2725,9 @@ PCHAR RTMPGetRalinkAuthModeStr(
2696 { 2725 {
2697 case Ndis802_11AuthModeOpen: 2726 case Ndis802_11AuthModeOpen:
2698 return "OPEN"; 2727 return "OPEN";
2728#if defined(RT2860) || defined(RT30xx)
2699 default: 2729 default:
2730#endif
2700 case Ndis802_11AuthModeWPAPSK: 2731 case Ndis802_11AuthModeWPAPSK:
2701 return "WPAPSK"; 2732 return "WPAPSK";
2702 case Ndis802_11AuthModeShared: 2733 case Ndis802_11AuthModeShared:
@@ -2711,8 +2742,14 @@ PCHAR RTMPGetRalinkAuthModeStr(
2711 return "WPAPSKWPA2PSK"; 2742 return "WPAPSKWPA2PSK";
2712 case Ndis802_11AuthModeWPA1WPA2: 2743 case Ndis802_11AuthModeWPA1WPA2:
2713 return "WPA1WPA2"; 2744 return "WPA1WPA2";
2745#ifndef RT30xx
2714 case Ndis802_11AuthModeWPANone: 2746 case Ndis802_11AuthModeWPANone:
2715 return "WPANONE"; 2747 return "WPANONE";
2748#ifdef RT2870
2749 default:
2750 return "UNKNOW";
2751#endif
2752#endif
2716 } 2753 }
2717} 2754}
2718 2755
@@ -2721,7 +2758,9 @@ PCHAR RTMPGetRalinkEncryModeStr(
2721{ 2758{
2722 switch(encryMode) 2759 switch(encryMode)
2723 { 2760 {
2761#if defined(RT2860) || defined(RT30xx)
2724 default: 2762 default:
2763#endif
2725 case Ndis802_11WEPDisabled: 2764 case Ndis802_11WEPDisabled:
2726 return "NONE"; 2765 return "NONE";
2727 case Ndis802_11WEPEnabled: 2766 case Ndis802_11WEPEnabled:
@@ -2732,6 +2771,10 @@ PCHAR RTMPGetRalinkEncryModeStr(
2732 return "AES"; 2771 return "AES";
2733 case Ndis802_11Encryption4Enabled: 2772 case Ndis802_11Encryption4Enabled:
2734 return "TKIPAES"; 2773 return "TKIPAES";
2774#if !defined(RT2860) && !defined(RT30xx)
2775 default:
2776 return "UNKNOW";
2777#endif
2735 } 2778 }
2736} 2779}
2737 2780
diff --git a/drivers/staging/rt2860/common/cmm_sync.c b/drivers/staging/rt2860/common/cmm_sync.c
index 360b3bcb97d3..a6e1b6ddfe57 100644
--- a/drivers/staging/rt2860/common/cmm_sync.c
+++ b/drivers/staging/rt2860/common/cmm_sync.c
@@ -440,13 +440,24 @@ VOID ScanNextChannel(
440 440
441 RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS); 441 RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS);
442 } 442 }
443#ifdef RT2870
444 else if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST) && (pAd->OpMode == OPMODE_STA))
445 {
446 pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
447 MlmeCntlConfirm(pAd, MT2_SCAN_CONF, MLME_FAIL_NO_RESOURCE);
448 }
449#endif // RT2870 //
443 else 450 else
444 { 451 {
445 { 452 {
446 // BBP and RF are not accessible in PS mode, we has to wake them up first 453 // BBP and RF are not accessible in PS mode, we has to wake them up first
447 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) 454 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
455#ifdef RT2860
448 AsicForceWakeup(pAd, FROM_TX); 456 AsicForceWakeup(pAd, FROM_TX);
449 457#endif
458#ifdef RT2870
459 AsicForceWakeup(pAd, TRUE);
460#endif
450 // leave PSM during scanning. otherwise we may lost ProbeRsp & BEACON 461 // leave PSM during scanning. otherwise we may lost ProbeRsp & BEACON
451 if (pAd->StaCfg.Psm == PWR_SAVE) 462 if (pAd->StaCfg.Psm == PWR_SAVE)
452 MlmeSetPsmBit(pAd, PWR_ACTIVE); 463 MlmeSetPsmBit(pAd, PWR_ACTIVE);
diff --git a/drivers/staging/rt2860/common/cmm_wpa.c b/drivers/staging/rt2860/common/cmm_wpa.c
index e206077e278a..d467f5338c45 100644
--- a/drivers/staging/rt2860/common/cmm_wpa.c
+++ b/drivers/staging/rt2860/common/cmm_wpa.c
@@ -39,10 +39,14 @@
39// WPA OUI 39// WPA OUI
40UCHAR OUI_WPA_NONE_AKM[4] = {0x00, 0x50, 0xF2, 0x00}; 40UCHAR OUI_WPA_NONE_AKM[4] = {0x00, 0x50, 0xF2, 0x00};
41UCHAR OUI_WPA_VERSION[4] = {0x00, 0x50, 0xF2, 0x01}; 41UCHAR OUI_WPA_VERSION[4] = {0x00, 0x50, 0xF2, 0x01};
42#ifndef RT30xx
42UCHAR OUI_WPA_WEP40[4] = {0x00, 0x50, 0xF2, 0x01}; 43UCHAR OUI_WPA_WEP40[4] = {0x00, 0x50, 0xF2, 0x01};
44#endif
43UCHAR OUI_WPA_TKIP[4] = {0x00, 0x50, 0xF2, 0x02}; 45UCHAR OUI_WPA_TKIP[4] = {0x00, 0x50, 0xF2, 0x02};
44UCHAR OUI_WPA_CCMP[4] = {0x00, 0x50, 0xF2, 0x04}; 46UCHAR OUI_WPA_CCMP[4] = {0x00, 0x50, 0xF2, 0x04};
47#ifndef RT30xx
45UCHAR OUI_WPA_WEP104[4] = {0x00, 0x50, 0xF2, 0x05}; 48UCHAR OUI_WPA_WEP104[4] = {0x00, 0x50, 0xF2, 0x05};
49#endif
46UCHAR OUI_WPA_8021X_AKM[4] = {0x00, 0x50, 0xF2, 0x01}; 50UCHAR OUI_WPA_8021X_AKM[4] = {0x00, 0x50, 0xF2, 0x01};
47UCHAR OUI_WPA_PSK_AKM[4] = {0x00, 0x50, 0xF2, 0x02}; 51UCHAR OUI_WPA_PSK_AKM[4] = {0x00, 0x50, 0xF2, 0x02};
48// WPA2 OUI 52// WPA2 OUI
@@ -51,7 +55,9 @@ UCHAR OUI_WPA2_TKIP[4] = {0x00, 0x0F, 0xAC, 0x02};
51UCHAR OUI_WPA2_CCMP[4] = {0x00, 0x0F, 0xAC, 0x04}; 55UCHAR OUI_WPA2_CCMP[4] = {0x00, 0x0F, 0xAC, 0x04};
52UCHAR OUI_WPA2_8021X_AKM[4] = {0x00, 0x0F, 0xAC, 0x01}; 56UCHAR OUI_WPA2_8021X_AKM[4] = {0x00, 0x0F, 0xAC, 0x01};
53UCHAR OUI_WPA2_PSK_AKM[4] = {0x00, 0x0F, 0xAC, 0x02}; 57UCHAR OUI_WPA2_PSK_AKM[4] = {0x00, 0x0F, 0xAC, 0x02};
58#ifndef RT30xx
54UCHAR OUI_WPA2_WEP104[4] = {0x00, 0x0F, 0xAC, 0x05}; 59UCHAR OUI_WPA2_WEP104[4] = {0x00, 0x0F, 0xAC, 0x05};
60#endif
55// MSA OUI 61// MSA OUI
56UCHAR OUI_MSA_8021X_AKM[4] = {0x00, 0x0F, 0xAC, 0x05}; // Not yet final - IEEE 802.11s-D1.06 62UCHAR OUI_MSA_8021X_AKM[4] = {0x00, 0x0F, 0xAC, 0x05}; // Not yet final - IEEE 802.11s-D1.06
57UCHAR OUI_MSA_PSK_AKM[4] = {0x00, 0x0F, 0xAC, 0x06}; // Not yet final - IEEE 802.11s-D1.06 63UCHAR OUI_MSA_PSK_AKM[4] = {0x00, 0x0F, 0xAC, 0x06}; // Not yet final - IEEE 802.11s-D1.06
@@ -370,6 +376,7 @@ static VOID RTMPInsertRsnIeCipher(
370 break; 376 break;
371 } 377 }
372 378
379#ifndef RT30xx
373 if ((pAd->OpMode == OPMODE_STA) && 380 if ((pAd->OpMode == OPMODE_STA) &&
374 (pAd->StaCfg.GroupCipher != Ndis802_11Encryption2Enabled) && 381 (pAd->StaCfg.GroupCipher != Ndis802_11Encryption2Enabled) &&
375 (pAd->StaCfg.GroupCipher != Ndis802_11Encryption3Enabled)) 382 (pAd->StaCfg.GroupCipher != Ndis802_11Encryption3Enabled))
@@ -385,7 +392,7 @@ static VOID RTMPInsertRsnIeCipher(
385 break; 392 break;
386 } 393 }
387 } 394 }
388 395#endif
389 // swap for big-endian platform 396 // swap for big-endian platform
390 pRsnie_cipher->version = cpu2le16(pRsnie_cipher->version); 397 pRsnie_cipher->version = cpu2le16(pRsnie_cipher->version);
391 pRsnie_cipher->ucount = cpu2le16(pRsnie_cipher->ucount); 398 pRsnie_cipher->ucount = cpu2le16(pRsnie_cipher->ucount);
@@ -446,6 +453,7 @@ static VOID RTMPInsertRsnIeCipher(
446 break; 453 break;
447 } 454 }
448 455
456#ifndef RT30xx
449 if ((pAd->OpMode == OPMODE_STA) && 457 if ((pAd->OpMode == OPMODE_STA) &&
450 (pAd->StaCfg.GroupCipher != Ndis802_11Encryption2Enabled) && 458 (pAd->StaCfg.GroupCipher != Ndis802_11Encryption2Enabled) &&
451 (pAd->StaCfg.GroupCipher != Ndis802_11Encryption3Enabled)) 459 (pAd->StaCfg.GroupCipher != Ndis802_11Encryption3Enabled))
@@ -461,7 +469,7 @@ static VOID RTMPInsertRsnIeCipher(
461 break; 469 break;
462 } 470 }
463 } 471 }
464 472#endif
465 // swap for big-endian platform 473 // swap for big-endian platform
466 pRsnie_cipher->version = cpu2le16(pRsnie_cipher->version); 474 pRsnie_cipher->version = cpu2le16(pRsnie_cipher->version);
467 pRsnie_cipher->ucount = cpu2le16(pRsnie_cipher->ucount); 475 pRsnie_cipher->ucount = cpu2le16(pRsnie_cipher->ucount);
diff --git a/drivers/staging/rt2860/common/eeprom.c b/drivers/staging/rt2860/common/eeprom.c
index bed2d666629c..9729323baca5 100644
--- a/drivers/staging/rt2860/common/eeprom.c
+++ b/drivers/staging/rt2860/common/eeprom.c
@@ -73,12 +73,16 @@ USHORT ShiftInBits(
73 RaiseClock(pAd, &x); 73 RaiseClock(pAd, &x);
74 74
75 RTMP_IO_READ32(pAd, E2PROM_CSR, &x); 75 RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
76 76#ifdef RT30xx
77 LowerClock(pAd, &x); //prevent read failed
78#endif
77 x &= ~(EEDI); 79 x &= ~(EEDI);
78 if(x & EEDO) 80 if(x & EEDO)
79 data |= 1; 81 data |= 1;
80 82
83#ifndef RT30xx
81 LowerClock(pAd, &x); 84 LowerClock(pAd, &x);
85#endif
82 } 86 }
83 87
84 return data; 88 return data;
@@ -181,6 +185,15 @@ USHORT RTMP_EEPROM_READ16(
181 UINT32 x; 185 UINT32 x;
182 USHORT data; 186 USHORT data;
183 187
188#ifdef RT30xx
189 if (pAd->NicConfig2.field.AntDiversity)
190 {
191 pAd->EepromAccess = TRUE;
192 }
193//2008/09/11:KH add to support efuse<--
194//2008/09/11:KH add to support efuse-->
195{
196#endif
184 Offset /= 2; 197 Offset /= 2;
185 // reset bits and set EECS 198 // reset bits and set EECS
186 RTMP_IO_READ32(pAd, E2PROM_CSR, &x); 199 RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
@@ -188,9 +201,17 @@ USHORT RTMP_EEPROM_READ16(
188 x |= EECS; 201 x |= EECS;
189 RTMP_IO_WRITE32(pAd, E2PROM_CSR, x); 202 RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
190 203
204#ifdef RT30xx
205 // patch can not access e-Fuse issue
206 if (!IS_RT3090(pAd))
207 {
208#endif
191 // kick a pulse 209 // kick a pulse
192 RaiseClock(pAd, &x); 210 RaiseClock(pAd, &x);
193 LowerClock(pAd, &x); 211 LowerClock(pAd, &x);
212#ifdef RT30xx
213 }
214#endif
194 215
195 // output the read_opcode and register number in that order 216 // output the read_opcode and register number in that order
196 ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3); 217 ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3);
@@ -201,6 +222,17 @@ USHORT RTMP_EEPROM_READ16(
201 222
202 EEpromCleanup(pAd); 223 EEpromCleanup(pAd);
203 224
225#ifdef RT30xx
226 // Antenna and EEPROM access are both using EESK pin,
227 // Therefor we should avoid accessing EESK at the same time
228 // Then restore antenna after EEPROM access
229 if ((pAd->NicConfig2.field.AntDiversity) || (pAd->RfIcType == RFIC_3020))
230 {
231 pAd->EepromAccess = FALSE;
232 AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
233 }
234}
235#endif
204 return data; 236 return data;
205} //ReadEEprom 237} //ReadEEprom
206 238
@@ -211,6 +243,15 @@ VOID RTMP_EEPROM_WRITE16(
211{ 243{
212 UINT32 x; 244 UINT32 x;
213 245
246#ifdef RT30xx
247 if (pAd->NicConfig2.field.AntDiversity)
248 {
249 pAd->EepromAccess = TRUE;
250 }
251 //2008/09/11:KH add to support efuse<--
252//2008/09/11:KH add to support efuse-->
253 {
254#endif
214 Offset /= 2; 255 Offset /= 2;
215 256
216 EWEN(pAd); 257 EWEN(pAd);
@@ -221,9 +262,17 @@ VOID RTMP_EEPROM_WRITE16(
221 x |= EECS; 262 x |= EECS;
222 RTMP_IO_WRITE32(pAd, E2PROM_CSR, x); 263 RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
223 264
265#ifdef RT30xx
266 // patch can not access e-Fuse issue
267 if (!IS_RT3090(pAd))
268 {
269#endif
224 // kick a pulse 270 // kick a pulse
225 RaiseClock(pAd, &x); 271 RaiseClock(pAd, &x);
226 LowerClock(pAd, &x); 272 LowerClock(pAd, &x);
273#ifdef RT30xx
274 }
275#endif
227 276
228 // output the read_opcode ,register number and data in that order 277 // output the read_opcode ,register number and data in that order
229 ShiftOutBits(pAd, EEPROM_WRITE_OPCODE, 3); 278 ShiftOutBits(pAd, EEPROM_WRITE_OPCODE, 3);
@@ -240,5 +289,1222 @@ VOID RTMP_EEPROM_WRITE16(
240 EWDS(pAd); 289 EWDS(pAd);
241 290
242 EEpromCleanup(pAd); 291 EEpromCleanup(pAd);
292
293#ifdef RT30xx
294 // Antenna and EEPROM access are both using EESK pin,
295 // Therefor we should avoid accessing EESK at the same time
296 // Then restore antenna after EEPROM access
297 if ((pAd->NicConfig2.field.AntDiversity) || (pAd->RfIcType == RFIC_3020))
298 {
299 pAd->EepromAccess = FALSE;
300 AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
301 }
302}
303#endif
304}
305
306//2008/09/11:KH add to support efuse<--
307#ifdef RT30xx
308/*
309 ========================================================================
310
311 Routine Description:
312
313 Arguments:
314
315 Return Value:
316
317 IRQL =
318
319 Note:
320
321 ========================================================================
322*/
323UCHAR eFuseReadRegisters(
324 IN PRTMP_ADAPTER pAd,
325 IN USHORT Offset,
326 IN USHORT Length,
327 OUT USHORT* pData)
328{
329 EFUSE_CTRL_STRUC eFuseCtrlStruc;
330 int i;
331 USHORT efuseDataOffset;
332 UINT32 data;
333
334 RTMP_IO_READ32(pAd, EFUSE_CTRL, (PUINT32) &eFuseCtrlStruc);
335
336 //Step0. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment.
337 //Use the eeprom logical address and covert to address to block number
338 eFuseCtrlStruc.field.EFSROM_AIN = Offset & 0xfff0;
339
340 //Step1. Write EFSROM_MODE (0x580, bit7:bit6) to 0.
341 eFuseCtrlStruc.field.EFSROM_MODE = 0;
342
343 //Step2. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical read procedure.
344 eFuseCtrlStruc.field.EFSROM_KICK = 1;
345
346 NdisMoveMemory(&data, &eFuseCtrlStruc, 4);
347 RTMP_IO_WRITE32(pAd, EFUSE_CTRL, data);
348
349 //Step3. Polling EFSROM_KICK(0x580, bit30) until it become 0 again.
350 i = 0;
351 while(i < 100)
352 {
353 //rtmp.HwMemoryReadDword(EFUSE_CTRL, (DWORD *) &eFuseCtrlStruc, 4);
354 RTMP_IO_READ32(pAd, EFUSE_CTRL, (PUINT32) &eFuseCtrlStruc);
355 if(eFuseCtrlStruc.field.EFSROM_KICK == 0)
356 {
357 break;
358 }
359 RTMPusecDelay(2);
360 i++;
361 }
362
363 //if EFSROM_AOUT is not found in physical address, write 0xffff
364 if (eFuseCtrlStruc.field.EFSROM_AOUT == 0x3f)
365 {
366 for(i=0; i<Length/2; i++)
367 *(pData+2*i) = 0xffff;
368 }
369 else
370 {
371 //Step4. Read 16-byte of data from EFUSE_DATA0-3 (0x590-0x59C)
372 efuseDataOffset = EFUSE_DATA3 - (Offset & 0xC) ;
373 //data hold 4 bytes data.
374 //In RTMP_IO_READ32 will automatically execute 32-bytes swapping
375 RTMP_IO_READ32(pAd, efuseDataOffset, &data);
376 //Decide the upper 2 bytes or the bottom 2 bytes.
377 // Little-endian S | S Big-endian
378 // addr 3 2 1 0 | 0 1 2 3
379 // Ori-V D C B A | A B C D
380 //After swapping
381 // D C B A | D C B A
382 //Return 2-bytes
383 //The return byte statrs from S. Therefore, the little-endian will return BA, the Big-endian will return DC.
384 //For returning the bottom 2 bytes, the Big-endian should shift right 2-bytes.
385 data = data >> (8*(Offset & 0x3));
386
387 NdisMoveMemory(pData, &data, Length);
388 }
389
390 return (UCHAR) eFuseCtrlStruc.field.EFSROM_AOUT;
391
392}
393
394/*
395 ========================================================================
396
397 Routine Description:
398
399 Arguments:
400
401 Return Value:
402
403 IRQL =
404
405 Note:
406
407 ========================================================================
408*/
409VOID eFusePhysicalReadRegisters(
410 IN PRTMP_ADAPTER pAd,
411 IN USHORT Offset,
412 IN USHORT Length,
413 OUT USHORT* pData)
414{
415 EFUSE_CTRL_STRUC eFuseCtrlStruc;
416 int i;
417 USHORT efuseDataOffset;
418 UINT32 data;
419
420 RTMP_IO_READ32(pAd, EFUSE_CTRL, (PUINT32) &eFuseCtrlStruc);
421
422 //Step0. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment.
423 eFuseCtrlStruc.field.EFSROM_AIN = Offset & 0xfff0;
424
425 //Step1. Write EFSROM_MODE (0x580, bit7:bit6) to 1.
426 //Read in physical view
427 eFuseCtrlStruc.field.EFSROM_MODE = 1;
428
429 //Step2. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical read procedure.
430 eFuseCtrlStruc.field.EFSROM_KICK = 1;
431
432 NdisMoveMemory(&data, &eFuseCtrlStruc, 4);
433 RTMP_IO_WRITE32(pAd, EFUSE_CTRL, data);
434
435 //Step3. Polling EFSROM_KICK(0x580, bit30) until it become 0 again.
436 i = 0;
437 while(i < 100)
438 {
439 RTMP_IO_READ32(pAd, EFUSE_CTRL, (PUINT32) &eFuseCtrlStruc);
440 if(eFuseCtrlStruc.field.EFSROM_KICK == 0)
441 break;
442 RTMPusecDelay(2);
443 i++;
444 }
445
446 //Step4. Read 16-byte of data from EFUSE_DATA0-3 (0x59C-0x590)
447 //Because the size of each EFUSE_DATA is 4 Bytes, the size of address of each is 2 bits.
448 //The previous 2 bits is the EFUSE_DATA number, the last 2 bits is used to decide which bytes
449 //Decide which EFUSE_DATA to read
450 //590:F E D C
451 //594:B A 9 8
452 //598:7 6 5 4
453 //59C:3 2 1 0
454 efuseDataOffset = EFUSE_DATA3 - (Offset & 0xC) ;
455
456 RTMP_IO_READ32(pAd, efuseDataOffset, &data);
457
458 data = data >> (8*(Offset & 0x3));
459
460 NdisMoveMemory(pData, &data, Length);
461
462}
463
464/*
465 ========================================================================
466
467 Routine Description:
468
469 Arguments:
470
471 Return Value:
472
473 IRQL =
474
475 Note:
476
477 ========================================================================
478*/
479VOID eFuseReadPhysical(
480 IN PRTMP_ADAPTER pAd,
481 IN PUSHORT lpInBuffer,
482 IN ULONG nInBufferSize,
483 OUT PUSHORT lpOutBuffer,
484 IN ULONG nOutBufferSize
485)
486{
487 USHORT* pInBuf = (USHORT*)lpInBuffer;
488 USHORT* pOutBuf = (USHORT*)lpOutBuffer;
489
490 USHORT Offset = pInBuf[0]; //addr
491 USHORT Length = pInBuf[1]; //length
492 int i;
493
494 for(i=0; i<Length; i+=2)
495 {
496 eFusePhysicalReadRegisters(pAd,Offset+i, 2, &pOutBuf[i/2]);
497 }
498}
499
500/*
501 ========================================================================
502
503 Routine Description:
504
505 Arguments:
506
507 Return Value:
508
509 IRQL =
510
511 Note:
512
513 ========================================================================
514*/
515NTSTATUS eFuseRead(
516 IN PRTMP_ADAPTER pAd,
517 IN USHORT Offset,
518 OUT PUCHAR pData,
519 IN USHORT Length)
520{
521 USHORT* pOutBuf = (USHORT*)pData;
522 NTSTATUS Status = STATUS_SUCCESS;
523 UCHAR EFSROM_AOUT;
524 int i;
525
526 for(i=0; i<Length; i+=2)
527 {
528 EFSROM_AOUT = eFuseReadRegisters(pAd, Offset+i, 2, &pOutBuf[i/2]);
529 }
530 return Status;
531}
532
533/*
534 ========================================================================
535
536 Routine Description:
537
538 Arguments:
539
540 Return Value:
541
542 IRQL =
543
544 Note:
545
546 ========================================================================
547*/
548VOID eFusePhysicalWriteRegisters(
549 IN PRTMP_ADAPTER pAd,
550 IN USHORT Offset,
551 IN USHORT Length,
552 OUT USHORT* pData)
553{
554 EFUSE_CTRL_STRUC eFuseCtrlStruc;
555 int i;
556 USHORT efuseDataOffset;
557 UINT32 data, eFuseDataBuffer[4];
558
559 //Step0. Write 16-byte of data to EFUSE_DATA0-3 (0x590-0x59C), where EFUSE_DATA0 is the LSB DW, EFUSE_DATA3 is the MSB DW.
560
561 /////////////////////////////////////////////////////////////////
562 //read current values of 16-byte block
563 RTMP_IO_READ32(pAd, EFUSE_CTRL, (PUINT32) &eFuseCtrlStruc);
564
565 //Step0. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment.
566 eFuseCtrlStruc.field.EFSROM_AIN = Offset & 0xfff0;
567
568 //Step1. Write EFSROM_MODE (0x580, bit7:bit6) to 1.
569 eFuseCtrlStruc.field.EFSROM_MODE = 1;
570
571 //Step2. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical read procedure.
572 eFuseCtrlStruc.field.EFSROM_KICK = 1;
573
574 NdisMoveMemory(&data, &eFuseCtrlStruc, 4);
575 RTMP_IO_WRITE32(pAd, EFUSE_CTRL, data);
576
577 //Step3. Polling EFSROM_KICK(0x580, bit30) until it become 0 again.
578 i = 0;
579 while(i < 100)
580 {
581 RTMP_IO_READ32(pAd, EFUSE_CTRL, (PUINT32) &eFuseCtrlStruc);
582
583 if(eFuseCtrlStruc.field.EFSROM_KICK == 0)
584 break;
585 RTMPusecDelay(2);
586 i++;
587 }
588
589 //Step4. Read 16-byte of data from EFUSE_DATA0-3 (0x59C-0x590)
590 efuseDataOffset = EFUSE_DATA3;
591 for(i=0; i< 4; i++)
592 {
593 RTMP_IO_READ32(pAd, efuseDataOffset, (PUINT32) &eFuseDataBuffer[i]);
594 efuseDataOffset -= 4;
595 }
596
597 //Update the value, the offset is multiple of 2, length is 2
598 efuseDataOffset = (Offset & 0xc) >> 2;
599 data = pData[0] & 0xffff;
600 //The offset should be 0x***10 or 0x***00
601 if((Offset % 4) != 0)
602 {
603 eFuseDataBuffer[efuseDataOffset] = (eFuseDataBuffer[efuseDataOffset] & 0xffff) | (data << 16);
604 }
605 else
606 {
607 eFuseDataBuffer[efuseDataOffset] = (eFuseDataBuffer[efuseDataOffset] & 0xffff0000) | data;
608 }
609
610 efuseDataOffset = EFUSE_DATA3;
611 for(i=0; i< 4; i++)
612 {
613 RTMP_IO_WRITE32(pAd, efuseDataOffset, eFuseDataBuffer[i]);
614 efuseDataOffset -= 4;
615 }
616 /////////////////////////////////////////////////////////////////
617
618 //Step1. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment.
619 eFuseCtrlStruc.field.EFSROM_AIN = Offset & 0xfff0;
620
621 //Step2. Write EFSROM_MODE (0x580, bit7:bit6) to 3.
622 eFuseCtrlStruc.field.EFSROM_MODE = 3;
623
624 //Step3. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical write procedure.
625 eFuseCtrlStruc.field.EFSROM_KICK = 1;
626
627 NdisMoveMemory(&data, &eFuseCtrlStruc, 4);
628 RTMP_IO_WRITE32(pAd, EFUSE_CTRL, data);
629
630 //Step4. Polling EFSROM_KICK(0x580, bit30) until it become 0 again. It��s done.
631 i = 0;
632 while(i < 100)
633 {
634 RTMP_IO_READ32(pAd, EFUSE_CTRL, (PUINT32) &eFuseCtrlStruc);
635
636 if(eFuseCtrlStruc.field.EFSROM_KICK == 0)
637 break;
638
639 RTMPusecDelay(2);
640 i++;
641 }
642}
643
644/*
645 ========================================================================
646
647 Routine Description:
648
649 Arguments:
650
651 Return Value:
652
653 IRQL =
654
655 Note:
656
657 ========================================================================
658*/
659NTSTATUS eFuseWriteRegisters(
660 IN PRTMP_ADAPTER pAd,
661 IN USHORT Offset,
662 IN USHORT Length,
663 IN USHORT* pData)
664{
665 USHORT i;
666 USHORT eFuseData;
667 USHORT LogicalAddress, BlkNum = 0xffff;
668 UCHAR EFSROM_AOUT;
669
670 USHORT addr,tmpaddr, InBuf[3], tmpOffset;
671 USHORT buffer[8];
672 BOOLEAN bWriteSuccess = TRUE;
673
674 DBGPRINT(RT_DEBUG_TRACE, ("eFuseWriteRegisters Offset=%x, pData=%x\n", Offset, *pData));
675
676 //Step 0. find the entry in the mapping table
677 //The address of EEPROM is 2-bytes alignment.
678 //The last bit is used for alignment, so it must be 0.
679 tmpOffset = Offset & 0xfffe;
680 EFSROM_AOUT = eFuseReadRegisters(pAd, tmpOffset, 2, &eFuseData);
681
682 if( EFSROM_AOUT == 0x3f)
683 { //find available logical address pointer
684 //the logical address does not exist, find an empty one
685 //from the first address of block 45=16*45=0x2d0 to the last address of block 47
686 //==>48*16-3(reserved)=2FC
687 for (i=EFUSE_USAGE_MAP_START; i<=EFUSE_USAGE_MAP_END; i+=2)
688 {
689 //Retrive the logical block nubmer form each logical address pointer
690 //It will access two logical address pointer each time.
691 eFusePhysicalReadRegisters(pAd, i, 2, &LogicalAddress);
692 if( (LogicalAddress & 0xff) == 0)
693 {//Not used logical address pointer
694 BlkNum = i-EFUSE_USAGE_MAP_START;
695 break;
696 }
697 else if(( (LogicalAddress >> 8) & 0xff) == 0)
698 {//Not used logical address pointer
699 if (i != EFUSE_USAGE_MAP_END)
700 {
701 BlkNum = i-EFUSE_USAGE_MAP_START+1;
702 }
703 break;
704 }
705 }
706 }
707 else
708 {
709 BlkNum = EFSROM_AOUT;
710 }
711
712 DBGPRINT(RT_DEBUG_TRACE, ("eFuseWriteRegisters BlkNum = %d \n", BlkNum));
713
714 if(BlkNum == 0xffff)
715 {
716 DBGPRINT(RT_DEBUG_TRACE, ("eFuseWriteRegisters: out of free E-fuse space!!!\n"));
717 return FALSE;
718 }
719
720 //Step 1. Save data of this block which is pointed by the avaible logical address pointer
721 // read and save the original block data
722 for(i =0; i<8; i++)
723 {
724 addr = BlkNum * 0x10 ;
725
726 InBuf[0] = addr+2*i;
727 InBuf[1] = 2;
728 InBuf[2] = 0x0;
729
730 eFuseReadPhysical(pAd, &InBuf[0], 4, &InBuf[2], 2);
731
732 buffer[i] = InBuf[2];
733 }
734
735 //Step 2. Update the data in buffer, and write the data to Efuse
736 buffer[ (Offset >> 1) % 8] = pData[0];
737
738 do
739 {
740 //Step 3. Write the data to Efuse
741 if(!bWriteSuccess)
742 {
743 for(i =0; i<8; i++)
744 {
745 addr = BlkNum * 0x10 ;
746
747 InBuf[0] = addr+2*i;
748 InBuf[1] = 2;
749 InBuf[2] = buffer[i];
750
751 eFuseWritePhysical(pAd, &InBuf[0], 6, NULL, 2);
752 }
753 }
754 else
755 {
756 addr = BlkNum * 0x10 ;
757
758 InBuf[0] = addr+(Offset % 16);
759 InBuf[1] = 2;
760 InBuf[2] = pData[0];
761
762 eFuseWritePhysical(pAd, &InBuf[0], 6, NULL, 2);
763 }
764
765 //Step 4. Write mapping table
766 addr = EFUSE_USAGE_MAP_START+BlkNum;
767
768 tmpaddr = addr;
769
770 if(addr % 2 != 0)
771 addr = addr -1;
772 InBuf[0] = addr;
773 InBuf[1] = 2;
774
775 //convert the address from 10 to 8 bit ( bit7, 6 = parity and bit5 ~ 0 = bit9~4), and write to logical map entry
776 tmpOffset = Offset;
777 tmpOffset >>= 4;
778 tmpOffset |= ((~((tmpOffset & 0x01) ^ ( tmpOffset >> 1 & 0x01) ^ (tmpOffset >> 2 & 0x01) ^ (tmpOffset >> 3 & 0x01))) << 6) & 0x40;
779 tmpOffset |= ((~( (tmpOffset >> 2 & 0x01) ^ (tmpOffset >> 3 & 0x01) ^ (tmpOffset >> 4 & 0x01) ^ ( tmpOffset >> 5 & 0x01))) << 7) & 0x80;
780
781 // write the logical address
782 if(tmpaddr%2 != 0)
783 InBuf[2] = tmpOffset<<8;
784 else
785 InBuf[2] = tmpOffset;
786
787 eFuseWritePhysical(pAd,&InBuf[0], 6, NULL, 0);
788
789 //Step 5. Compare data if not the same, invalidate the mapping entry, then re-write the data until E-fuse is exhausted
790 bWriteSuccess = TRUE;
791 for(i =0; i<8; i++)
792 {
793 addr = BlkNum * 0x10 ;
794
795 InBuf[0] = addr+2*i;
796 InBuf[1] = 2;
797 InBuf[2] = 0x0;
798
799 eFuseReadPhysical(pAd, &InBuf[0], 4, &InBuf[2], 2);
800
801 if(buffer[i] != InBuf[2])
802 {
803 bWriteSuccess = FALSE;
804 break;
805 }
806 }
807
808 //Step 6. invlidate mapping entry and find a free mapping entry if not succeed
809 if (!bWriteSuccess)
810 {
811 DBGPRINT(RT_DEBUG_TRACE, ("Not bWriteSuccess BlkNum = %d\n", BlkNum));
812
813 // the offset of current mapping entry
814 addr = EFUSE_USAGE_MAP_START+BlkNum;
815
816 //find a new mapping entry
817 BlkNum = 0xffff;
818 for (i=EFUSE_USAGE_MAP_START; i<=EFUSE_USAGE_MAP_END; i+=2)
819 {
820 eFusePhysicalReadRegisters(pAd, i, 2, &LogicalAddress);
821 if( (LogicalAddress & 0xff) == 0)
822 {
823 BlkNum = i-EFUSE_USAGE_MAP_START;
824 break;
825 }
826 else if(( (LogicalAddress >> 8) & 0xff) == 0)
827 {
828 if (i != EFUSE_USAGE_MAP_END)
829 {
830 BlkNum = i+1-EFUSE_USAGE_MAP_START;
831 }
832 break;
833 }
834 }
835 DBGPRINT(RT_DEBUG_TRACE, ("Not bWriteSuccess new BlkNum = %d\n", BlkNum));
836 if(BlkNum == 0xffff)
837 {
838 DBGPRINT(RT_DEBUG_TRACE, ("eFuseWriteRegisters: out of free E-fuse space!!!\n"));
839 return FALSE;
840 }
841
842 //invalidate the original mapping entry if new entry is not found
843 tmpaddr = addr;
844
845 if(addr % 2 != 0)
846 addr = addr -1;
847 InBuf[0] = addr;
848 InBuf[1] = 2;
849
850 eFuseReadPhysical(pAd, &InBuf[0], 4, &InBuf[2], 2);
851
852 // write the logical address
853 if(tmpaddr%2 != 0)
854 {
855 // Invalidate the high byte
856 for (i=8; i<15; i++)
857 {
858 if( ( (InBuf[2] >> i) & 0x01) == 0)
859 {
860 InBuf[2] |= (0x1 <<i);
861 break;
862 }
863 }
864 }
865 else
866 {
867 // invalidate the low byte
868 for (i=0; i<8; i++)
869 {
870 if( ( (InBuf[2] >> i) & 0x01) == 0)
871 {
872 InBuf[2] |= (0x1 <<i);
873 break;
874 }
875 }
876 }
877 eFuseWritePhysical(pAd, &InBuf[0], 6, NULL, 0);
878 }
879 }
880 while(!bWriteSuccess);
881
882 return TRUE;
883}
884
885/*
886 ========================================================================
887
888 Routine Description:
889
890 Arguments:
891
892 Return Value:
893
894 IRQL =
895
896 Note:
897
898 ========================================================================
899*/
900VOID eFuseWritePhysical(
901 IN PRTMP_ADAPTER pAd,
902 PUSHORT lpInBuffer,
903 ULONG nInBufferSize,
904 PUCHAR lpOutBuffer,
905 ULONG nOutBufferSize
906)
907{
908 USHORT* pInBuf = (USHORT*)lpInBuffer;
909 int i;
910 //USHORT* pOutBuf = (USHORT*)ioBuffer;
911
912 USHORT Offset = pInBuf[0]; //addr
913 USHORT Length = pInBuf[1]; //length
914 USHORT* pValueX = &pInBuf[2]; //value ...
915 // Little-endian S | S Big-endian
916 // addr 3 2 1 0 | 0 1 2 3
917 // Ori-V D C B A | A B C D
918 //After swapping
919 // D C B A | D C B A
920 //Both the little and big-endian use the same sequence to write data.
921 //Therefore, we only need swap data when read the data.
922 for(i=0; i<Length; i+=2)
923 {
924 eFusePhysicalWriteRegisters(pAd, Offset+i, 2, &pValueX[i/2]);
925 }
926}
927
928
929/*
930 ========================================================================
931
932 Routine Description:
933
934 Arguments:
935
936 Return Value:
937
938 IRQL =
939
940 Note:
941
942 ========================================================================
943*/
944NTSTATUS eFuseWrite(
945 IN PRTMP_ADAPTER pAd,
946 IN USHORT Offset,
947 IN PUCHAR pData,
948 IN USHORT length)
949{
950 int i;
951
952 USHORT* pValueX = (PUSHORT) pData; //value ...
953 //The input value=3070 will be stored as following
954 // Little-endian S | S Big-endian
955 // addr 1 0 | 0 1
956 // Ori-V 30 70 | 30 70
957 //After swapping
958 // 30 70 | 70 30
959 //Casting
960 // 3070 | 7030 (x)
961 //The swapping should be removed for big-endian
962 for(i=0; i<length; i+=2)
963 {
964 eFuseWriteRegisters(pAd, Offset+i, 2, &pValueX[i/2]);
965 }
966
967 return TRUE;
968}
969
970/*
971 ========================================================================
972
973 Routine Description:
974
975 Arguments:
976
977 Return Value:
978
979 IRQL =
980
981 Note:
982
983 ========================================================================
984*/
985INT set_eFuseGetFreeBlockCount_Proc(
986 IN PRTMP_ADAPTER pAd,
987 IN PUCHAR arg)
988{
989 USHORT i;
990 USHORT LogicalAddress;
991 USHORT efusefreenum=0;
992 if(!pAd->bUseEfuse)
993 return FALSE;
994 for (i = EFUSE_USAGE_MAP_START; i <= EFUSE_USAGE_MAP_END; i+=2)
995 {
996 eFusePhysicalReadRegisters(pAd, i, 2, &LogicalAddress);
997 if( (LogicalAddress & 0xff) == 0)
998 {
999 efusefreenum= (UCHAR) (EFUSE_USAGE_MAP_END-i+1);
1000 break;
1001 }
1002 else if(( (LogicalAddress >> 8) & 0xff) == 0)
1003 {
1004 efusefreenum = (UCHAR) (EFUSE_USAGE_MAP_END-i);
1005 break;
1006 }
1007
1008 if(i == EFUSE_USAGE_MAP_END)
1009 efusefreenum = 0;
1010 }
1011 printk("efuseFreeNumber is %d\n",efusefreenum);
1012 return TRUE;
1013}
1014INT set_eFusedump_Proc(
1015 IN PRTMP_ADAPTER pAd,
1016 IN PUCHAR arg)
1017{
1018USHORT InBuf[3];
1019 INT i=0;
1020 if(!pAd->bUseEfuse)
1021 return FALSE;
1022 for(i =0; i<EFUSE_USAGE_MAP_END/2; i++)
1023 {
1024 InBuf[0] = 2*i;
1025 InBuf[1] = 2;
1026 InBuf[2] = 0x0;
1027
1028 eFuseReadPhysical(pAd, &InBuf[0], 4, &InBuf[2], 2);
1029 if(i%4==0)
1030 printk("\nBlock %x:",i/8);
1031 printk("%04x ",InBuf[2]);
1032 }
1033 return TRUE;
1034}
1035INT set_eFuseLoadFromBin_Proc(
1036 IN PRTMP_ADAPTER pAd,
1037 IN PUCHAR arg)
1038{
1039 CHAR *src;
1040 struct file *srcf;
1041 INT retval, orgfsuid, orgfsgid;
1042 mm_segment_t orgfs;
1043 UCHAR *buffer;
1044 UCHAR BinFileSize=0;
1045 INT i = 0,j=0,k=1;
1046 USHORT *PDATA;
1047 USHORT DATA;
1048 BinFileSize=strlen("RT30xxEEPROM.bin");
1049 src = kmalloc(128, MEM_ALLOC_FLAG);
1050 NdisZeroMemory(src, 128);
1051
1052 if(strlen(arg)>0)
1053 {
1054
1055 NdisMoveMemory(src, arg, strlen(arg));
1056 }
1057
1058 else
1059 {
1060
1061 NdisMoveMemory(src, "RT30xxEEPROM.bin", BinFileSize);
1062 }
1063
1064 DBGPRINT(RT_DEBUG_TRACE, ("FileName=%s\n",src));
1065 buffer = kmalloc(MAX_EEPROM_BIN_FILE_SIZE, MEM_ALLOC_FLAG);
1066
1067 if(buffer == NULL)
1068 {
1069 kfree(src);
1070 return FALSE;
1071}
1072 PDATA=kmalloc(sizeof(USHORT)*8,MEM_ALLOC_FLAG);
1073
1074 if(PDATA==NULL)
1075 {
1076 kfree(src);
1077
1078 kfree(buffer);
1079 return FALSE;
1080 }
1081 /* Don't change to uid 0, let the file be opened as the "normal" user */
1082#if 0
1083 orgfsuid = current->fsuid;
1084 orgfsgid = current->fsgid;
1085 current->fsuid=current->fsgid = 0;
1086#endif
1087 orgfs = get_fs();
1088 set_fs(KERNEL_DS);
1089
1090 if (src && *src)
1091 {
1092 srcf = filp_open(src, O_RDONLY, 0);
1093 if (IS_ERR(srcf))
1094 {
1095 DBGPRINT(RT_DEBUG_ERROR, ("--> Error %ld opening %s\n", -PTR_ERR(srcf),src));
1096 return FALSE;
1097 }
1098 else
1099 {
1100 // The object must have a read method
1101 if (srcf->f_op && srcf->f_op->read)
1102 {
1103 memset(buffer, 0x00, MAX_EEPROM_BIN_FILE_SIZE);
1104 while(srcf->f_op->read(srcf, &buffer[i], 1, &srcf->f_pos)==1)
1105 {
1106 DBGPRINT(RT_DEBUG_TRACE, ("%02X ",buffer[i]));
1107 if((i+1)%8==0)
1108 DBGPRINT(RT_DEBUG_TRACE, ("\n"));
1109 i++;
1110 if(i>=MAX_EEPROM_BIN_FILE_SIZE)
1111 {
1112 DBGPRINT(RT_DEBUG_ERROR, ("--> Error %ld reading %s, The file is too large[1024]\n", -PTR_ERR(srcf),src));
1113 kfree(PDATA);
1114 kfree(buffer);
1115 kfree(src);
1116 return FALSE;
1117 }
1118 }
1119 }
1120 else
1121 {
1122 DBGPRINT(RT_DEBUG_ERROR, ("--> Error!! System doest not support read function\n"));
1123 kfree(PDATA);
1124 kfree(buffer);
1125 kfree(src);
1126 return FALSE;
1127 }
1128 }
1129
1130
1131 }
1132 else
1133 {
1134 DBGPRINT(RT_DEBUG_ERROR, ("--> Error src or srcf is null\n"));
1135 kfree(PDATA);
1136 kfree(buffer);
1137 return FALSE;
1138
1139 }
1140
1141
1142 retval=filp_close(srcf,NULL);
1143
1144 if (retval)
1145 {
1146 DBGPRINT(RT_DEBUG_TRACE, ("--> Error %d closing %s\n", -retval, src));
1147 }
1148 set_fs(orgfs);
1149#if 0
1150 current->fsuid = orgfsuid;
1151 current->fsgid = orgfsgid;
1152#endif
1153 for(j=0;j<i;j++)
1154 {
1155 DBGPRINT(RT_DEBUG_TRACE, ("%02X ",buffer[j]));
1156 if((j+1)%2==0)
1157 PDATA[j/2%8]=((buffer[j]<<8)&0xff00)|(buffer[j-1]&0xff);
1158 if(j%16==0)
1159 {
1160 k=buffer[j];
1161 }
1162 else
1163 {
1164 k&=buffer[j];
1165 if((j+1)%16==0)
1166 {
1167
1168 DBGPRINT(RT_DEBUG_TRACE, (" result=%02X,blk=%02x\n",k,j/16));
1169
1170 if(k!=0xff)
1171 eFuseWriteRegistersFromBin(pAd,(USHORT)j-15, 16, PDATA);
1172 else
1173 {
1174 if(eFuseReadRegisters(pAd,j, 2,(PUSHORT)&DATA)!=0x3f)
1175 eFuseWriteRegistersFromBin(pAd,(USHORT)j-15, 16, PDATA);
1176 }
1177 /*
1178 for(l=0;l<8;l++)
1179 printk("%04x ",PDATA[l]);
1180 printk("\n");
1181 */
1182 NdisZeroMemory(PDATA,16);
1183
1184
1185 }
1186 }
1187
1188
1189 }
1190
1191
1192 kfree(PDATA);
1193 kfree(buffer);
1194 kfree(src);
1195 return TRUE;
1196}
1197NTSTATUS eFuseWriteRegistersFromBin(
1198 IN PRTMP_ADAPTER pAd,
1199 IN USHORT Offset,
1200 IN USHORT Length,
1201 IN USHORT* pData)
1202{
1203 USHORT i;
1204 USHORT eFuseData;
1205 USHORT LogicalAddress, BlkNum = 0xffff;
1206 UCHAR EFSROM_AOUT,Loop=0;
1207 EFUSE_CTRL_STRUC eFuseCtrlStruc;
1208 USHORT efuseDataOffset;
1209 UINT32 data,tempbuffer;
1210 USHORT addr,tmpaddr, InBuf[3], tmpOffset;
1211 UINT32 buffer[4];
1212 BOOLEAN bWriteSuccess = TRUE;
1213 BOOLEAN bNotWrite=TRUE;
1214 BOOLEAN bAllocateNewBlk=TRUE;
1215
1216 DBGPRINT(RT_DEBUG_TRACE, ("eFuseWriteRegistersFromBin Offset=%x, pData=%04x:%04x:%04x:%04x\n", Offset, *pData,*(pData+1),*(pData+2),*(pData+3)));
1217
1218 do
1219 {
1220 //Step 0. find the entry in the mapping table
1221 //The address of EEPROM is 2-bytes alignment.
1222 //The last bit is used for alignment, so it must be 0.
1223 Loop++;
1224 tmpOffset = Offset & 0xfffe;
1225 EFSROM_AOUT = eFuseReadRegisters(pAd, tmpOffset, 2, &eFuseData);
1226
1227 if( EFSROM_AOUT == 0x3f)
1228 { //find available logical address pointer
1229 //the logical address does not exist, find an empty one
1230 //from the first address of block 45=16*45=0x2d0 to the last address of block 47
1231 //==>48*16-3(reserved)=2FC
1232 bAllocateNewBlk=TRUE;
1233 for (i=EFUSE_USAGE_MAP_START; i<=EFUSE_USAGE_MAP_END; i+=2)
1234 {
1235 //Retrive the logical block nubmer form each logical address pointer
1236 //It will access two logical address pointer each time.
1237 eFusePhysicalReadRegisters(pAd, i, 2, &LogicalAddress);
1238 if( (LogicalAddress & 0xff) == 0)
1239 {//Not used logical address pointer
1240 BlkNum = i-EFUSE_USAGE_MAP_START;
1241 break;
1242 }
1243 else if(( (LogicalAddress >> 8) & 0xff) == 0)
1244 {//Not used logical address pointer
1245 if (i != EFUSE_USAGE_MAP_END)
1246 {
1247 BlkNum = i-EFUSE_USAGE_MAP_START+1;
1248 }
1249 break;
1250 }
1251 }
1252 }
1253 else
1254 {
1255 bAllocateNewBlk=FALSE;
1256 BlkNum = EFSROM_AOUT;
1257 }
1258
1259 DBGPRINT(RT_DEBUG_TRACE, ("eFuseWriteRegisters BlkNum = %d \n", BlkNum));
1260
1261 if(BlkNum == 0xffff)
1262 {
1263 DBGPRINT(RT_DEBUG_TRACE, ("eFuseWriteRegisters: out of free E-fuse space!!!\n"));
1264 return FALSE;
1265 }
1266 //Step 1.1.0
1267 //If the block is not existing in mapping table, create one
1268 //and write down the 16-bytes data to the new block
1269 if(bAllocateNewBlk)
1270 {
1271 DBGPRINT(RT_DEBUG_TRACE, ("Allocate New Blk\n"));
1272 efuseDataOffset = EFUSE_DATA3;
1273 for(i=0; i< 4; i++)
1274 {
1275 DBGPRINT(RT_DEBUG_TRACE, ("Allocate New Blk, Data%d=%04x%04x\n",3-i,pData[2*i+1],pData[2*i]));
1276 tempbuffer=((pData[2*i+1]<<16)&0xffff0000)|pData[2*i];
1277
1278
1279 RTMP_IO_WRITE32(pAd, efuseDataOffset,tempbuffer);
1280 efuseDataOffset -= 4;
1281
1282 }
1283 /////////////////////////////////////////////////////////////////
1284
1285 //Step1.1.1. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment.
1286 eFuseCtrlStruc.field.EFSROM_AIN = BlkNum* 0x10 ;
1287
1288 //Step1.1.2. Write EFSROM_MODE (0x580, bit7:bit6) to 3.
1289 eFuseCtrlStruc.field.EFSROM_MODE = 3;
1290
1291 //Step1.1.3. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical write procedure.
1292 eFuseCtrlStruc.field.EFSROM_KICK = 1;
1293
1294 NdisMoveMemory(&data, &eFuseCtrlStruc, 4);
1295
1296 RTMP_IO_WRITE32(pAd, EFUSE_CTRL, data);
1297
1298 //Step1.1.4. Polling EFSROM_KICK(0x580, bit30) until it become 0 again. It��s done.
1299 i = 0;
1300 while(i < 100)
1301 {
1302 RTMP_IO_READ32(pAd, EFUSE_CTRL, (PUINT32) &eFuseCtrlStruc);
1303
1304 if(eFuseCtrlStruc.field.EFSROM_KICK == 0)
1305 break;
1306
1307 RTMPusecDelay(2);
1308 i++;
1309 }
1310
1311 }
1312 else
1313 { //Step1.2.
1314 //If the same logical number is existing, check if the writting data and the data
1315 //saving in this block are the same.
1316 /////////////////////////////////////////////////////////////////
1317 //read current values of 16-byte block
1318 RTMP_IO_READ32(pAd, EFUSE_CTRL, (PUINT32) &eFuseCtrlStruc);
1319
1320 //Step1.2.0. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment.
1321 eFuseCtrlStruc.field.EFSROM_AIN = Offset & 0xfff0;
1322
1323 //Step1.2.1. Write EFSROM_MODE (0x580, bit7:bit6) to 1.
1324 eFuseCtrlStruc.field.EFSROM_MODE = 0;
1325
1326 //Step1.2.2. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical read procedure.
1327 eFuseCtrlStruc.field.EFSROM_KICK = 1;
1328
1329 NdisMoveMemory(&data, &eFuseCtrlStruc, 4);
1330 RTMP_IO_WRITE32(pAd, EFUSE_CTRL, data);
1331
1332 //Step1.2.3. Polling EFSROM_KICK(0x580, bit30) until it become 0 again.
1333 i = 0;
1334 while(i < 100)
1335 {
1336 RTMP_IO_READ32(pAd, EFUSE_CTRL, (PUINT32) &eFuseCtrlStruc);
1337
1338 if(eFuseCtrlStruc.field.EFSROM_KICK == 0)
1339 break;
1340 RTMPusecDelay(2);
1341 i++;
1342 }
1343
1344 //Step1.2.4. Read 16-byte of data from EFUSE_DATA0-3 (0x59C-0x590)
1345 efuseDataOffset = EFUSE_DATA3;
1346 for(i=0; i< 4; i++)
1347 {
1348 RTMP_IO_READ32(pAd, efuseDataOffset, (PUINT32) &buffer[i]);
1349 efuseDataOffset -= 4;
1350 }
1351 //Step1.2.5. Check if the data of efuse and the writing data are the same.
1352 for(i =0; i<4; i++)
1353 {
1354 tempbuffer=((pData[2*i+1]<<16)&0xffff0000)|pData[2*i];
1355 DBGPRINT(RT_DEBUG_TRACE, ("buffer[%d]=%x,pData[%d]=%x,pData[%d]=%x,tempbuffer=%x\n",i,buffer[i],2*i,pData[2*i],2*i+1,pData[2*i+1],tempbuffer));
1356
1357 if(((buffer[i]&0xffff0000)==(pData[2*i+1]<<16))&&((buffer[i]&0xffff)==pData[2*i]))
1358 bNotWrite&=TRUE;
1359 else
1360 {
1361 bNotWrite&=FALSE;
1362 break;
1363 }
1364 }
1365 if(!bNotWrite)
1366 {
1367 printk("The data is not the same\n");
1368
1369 for(i =0; i<8; i++)
1370 {
1371 addr = BlkNum * 0x10 ;
1372
1373 InBuf[0] = addr+2*i;
1374 InBuf[1] = 2;
1375 InBuf[2] = pData[i];
1376
1377 eFuseWritePhysical(pAd, &InBuf[0], 6, NULL, 2);
1378 }
1379
1380 }
1381 else
1382 return TRUE;
1383 }
1384
1385
1386
1387 //Step 2. Write mapping table
1388 addr = EFUSE_USAGE_MAP_START+BlkNum;
1389
1390 tmpaddr = addr;
1391
1392 if(addr % 2 != 0)
1393 addr = addr -1;
1394 InBuf[0] = addr;
1395 InBuf[1] = 2;
1396
1397 //convert the address from 10 to 8 bit ( bit7, 6 = parity and bit5 ~ 0 = bit9~4), and write to logical map entry
1398 tmpOffset = Offset;
1399 tmpOffset >>= 4;
1400 tmpOffset |= ((~((tmpOffset & 0x01) ^ ( tmpOffset >> 1 & 0x01) ^ (tmpOffset >> 2 & 0x01) ^ (tmpOffset >> 3 & 0x01))) << 6) & 0x40;
1401 tmpOffset |= ((~( (tmpOffset >> 2 & 0x01) ^ (tmpOffset >> 3 & 0x01) ^ (tmpOffset >> 4 & 0x01) ^ ( tmpOffset >> 5 & 0x01))) << 7) & 0x80;
1402
1403 // write the logical address
1404 if(tmpaddr%2 != 0)
1405 InBuf[2] = tmpOffset<<8;
1406 else
1407 InBuf[2] = tmpOffset;
1408
1409 eFuseWritePhysical(pAd,&InBuf[0], 6, NULL, 0);
1410
1411 //Step 3. Compare data if not the same, invalidate the mapping entry, then re-write the data until E-fuse is exhausted
1412 bWriteSuccess = TRUE;
1413 for(i =0; i<8; i++)
1414 {
1415 addr = BlkNum * 0x10 ;
1416
1417 InBuf[0] = addr+2*i;
1418 InBuf[1] = 2;
1419 InBuf[2] = 0x0;
1420
1421 eFuseReadPhysical(pAd, &InBuf[0], 4, &InBuf[2], 2);
1422 DBGPRINT(RT_DEBUG_TRACE, ("addr=%x, buffer[i]=%x,InBuf[2]=%x\n",InBuf[0],pData[i],InBuf[2]));
1423 if(pData[i] != InBuf[2])
1424 {
1425 bWriteSuccess = FALSE;
1426 break;
1427 }
1428 }
1429
1430 //Step 4. invlidate mapping entry and find a free mapping entry if not succeed
1431
1432 if (!bWriteSuccess&&Loop<2)
1433 {
1434 DBGPRINT(RT_DEBUG_TRACE, ("eFuseWriteRegistersFromBin::Not bWriteSuccess BlkNum = %d\n", BlkNum));
1435
1436 // the offset of current mapping entry
1437 addr = EFUSE_USAGE_MAP_START+BlkNum;
1438
1439 //find a new mapping entry
1440 BlkNum = 0xffff;
1441 for (i=EFUSE_USAGE_MAP_START; i<=EFUSE_USAGE_MAP_END; i+=2)
1442 {
1443 eFusePhysicalReadRegisters(pAd, i, 2, &LogicalAddress);
1444 if( (LogicalAddress & 0xff) == 0)
1445 {
1446 BlkNum = i-EFUSE_USAGE_MAP_START;
1447 break;
1448 }
1449 else if(( (LogicalAddress >> 8) & 0xff) == 0)
1450 {
1451 if (i != EFUSE_USAGE_MAP_END)
1452 {
1453 BlkNum = i+1-EFUSE_USAGE_MAP_START;
1454 }
1455 break;
1456 }
1457 }
1458 DBGPRINT(RT_DEBUG_TRACE, ("eFuseWriteRegistersFromBin::Not bWriteSuccess new BlkNum = %d\n", BlkNum));
1459 if(BlkNum == 0xffff)
1460 {
1461 DBGPRINT(RT_DEBUG_TRACE, ("eFuseWriteRegistersFromBin: out of free E-fuse space!!!\n"));
1462 return FALSE;
1463 }
1464
1465 //invalidate the original mapping entry if new entry is not found
1466 tmpaddr = addr;
1467
1468 if(addr % 2 != 0)
1469 addr = addr -1;
1470 InBuf[0] = addr;
1471 InBuf[1] = 2;
1472
1473 eFuseReadPhysical(pAd, &InBuf[0], 4, &InBuf[2], 2);
1474
1475 // write the logical address
1476 if(tmpaddr%2 != 0)
1477 {
1478 // Invalidate the high byte
1479 for (i=8; i<15; i++)
1480 {
1481 if( ( (InBuf[2] >> i) & 0x01) == 0)
1482 {
1483 InBuf[2] |= (0x1 <<i);
1484 break;
1485 }
1486 }
1487 }
1488 else
1489 {
1490 // invalidate the low byte
1491 for (i=0; i<8; i++)
1492 {
1493 if( ( (InBuf[2] >> i) & 0x01) == 0)
1494 {
1495 InBuf[2] |= (0x1 <<i);
1496 break;
1497 }
1498 }
1499 }
1500 eFuseWritePhysical(pAd, &InBuf[0], 6, NULL, 0);
1501 }
1502
1503 }
1504 while(!bWriteSuccess&&Loop<2);
1505
1506 return TRUE;
243} 1507}
244 1508
1509#endif // RT30xx //
1510//2008/09/11:KH add to support efuse-->
diff --git a/drivers/staging/rt2860/common/mlme.c b/drivers/staging/rt2860/common/mlme.c
index 51468689a382..e9e69c539e6f 100644
--- a/drivers/staging/rt2860/common/mlme.c
+++ b/drivers/staging/rt2860/common/mlme.c
@@ -338,6 +338,9 @@ UCHAR WpaIe = IE_WPA;
338UCHAR Wpa2Ie = IE_WPA2; 338UCHAR Wpa2Ie = IE_WPA2;
339UCHAR IbssIe = IE_IBSS_PARM; 339UCHAR IbssIe = IE_IBSS_PARM;
340UCHAR Ccx2Ie = IE_CCX_V2; 340UCHAR Ccx2Ie = IE_CCX_V2;
341#ifdef RT2870
342UCHAR WapiIe = IE_WAPI;
343#endif
341 344
342extern UCHAR WPA_OUI[]; 345extern UCHAR WPA_OUI[];
343 346
@@ -446,7 +449,13 @@ FREQUENCY_ITEM FreqItems3020[] =
446 {13, 247, 2, 2}, 449 {13, 247, 2, 2},
447 {14, 248, 2, 4}, 450 {14, 248, 2, 4},
448}; 451};
452#ifndef RT30xx
449#define NUM_OF_3020_CHNL (sizeof(FreqItems3020) / sizeof(FREQUENCY_ITEM)) 453#define NUM_OF_3020_CHNL (sizeof(FreqItems3020) / sizeof(FREQUENCY_ITEM))
454#endif
455#ifdef RT30xx
456//2008/07/10:KH Modified to share this variable
457UCHAR NUM_OF_3020_CHNL=(sizeof(FreqItems3020) / sizeof(FREQUENCY_ITEM));
458#endif
450 459
451/* 460/*
452 ========================================================================== 461 ==========================================================================
@@ -504,6 +513,7 @@ NDIS_STATUS MlmeInit(
504 // software-based RX Antenna diversity 513 // software-based RX Antenna diversity
505 RTMPInitTimer(pAd, &pAd->Mlme.RxAntEvalTimer, GET_TIMER_FUNCTION(AsicRxAntEvalTimeout), pAd, FALSE); 514 RTMPInitTimer(pAd, &pAd->Mlme.RxAntEvalTimer, GET_TIMER_FUNCTION(AsicRxAntEvalTimeout), pAd, FALSE);
506 515
516#ifdef RT2860
507 { 517 {
508 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) 518 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE))
509 { 519 {
@@ -512,6 +522,7 @@ NDIS_STATUS MlmeInit(
512 RTMPInitTimer(pAd, &pAd->Mlme.RadioOnOffTimer, GET_TIMER_FUNCTION(RadioOnExec), pAd, FALSE); 522 RTMPInitTimer(pAd, &pAd->Mlme.RadioOnOffTimer, GET_TIMER_FUNCTION(RadioOnExec), pAd, FALSE);
513 } 523 }
514 } 524 }
525#endif
515 } while (FALSE); 526 } while (FALSE);
516 527
517 DBGPRINT(RT_DEBUG_TRACE, ("<-- MLME Initialize\n")); 528 DBGPRINT(RT_DEBUG_TRACE, ("<-- MLME Initialize\n"));
@@ -566,6 +577,16 @@ VOID MlmeHandler(
566 //From message type, determine which state machine I should drive 577 //From message type, determine which state machine I should drive
567 if (MlmeDequeue(&pAd->Mlme.Queue, &Elem)) 578 if (MlmeDequeue(&pAd->Mlme.Queue, &Elem))
568 { 579 {
580#ifdef RT2870
581 if (Elem->MsgType == MT2_RESET_CONF)
582 {
583 DBGPRINT_RAW(RT_DEBUG_TRACE, ("!!! reset MLME state machine !!!\n"));
584 MlmeRestartStateMachine(pAd);
585 Elem->Occupied = FALSE;
586 Elem->MsgLen = 0;
587 continue;
588 }
589#endif // RT2870 //
569 590
570 // if dequeue success 591 // if dequeue success
571 switch (Elem->Machine) 592 switch (Elem->Machine)
@@ -636,6 +657,9 @@ VOID MlmeHalt(
636 IN PRTMP_ADAPTER pAd) 657 IN PRTMP_ADAPTER pAd)
637{ 658{
638 BOOLEAN Cancelled; 659 BOOLEAN Cancelled;
660#ifdef RT3070
661 UINT32 TxPinCfg = 0x00050F0F;
662#endif // RT3070 //
639 663
640 DBGPRINT(RT_DEBUG_TRACE, ("==> MlmeHalt\n")); 664 DBGPRINT(RT_DEBUG_TRACE, ("==> MlmeHalt\n"));
641 665
@@ -653,11 +677,13 @@ VOID MlmeHalt(
653 RTMPCancelTimer(&pAd->MlmeAux.AuthTimer, &Cancelled); 677 RTMPCancelTimer(&pAd->MlmeAux.AuthTimer, &Cancelled);
654 RTMPCancelTimer(&pAd->MlmeAux.BeaconTimer, &Cancelled); 678 RTMPCancelTimer(&pAd->MlmeAux.BeaconTimer, &Cancelled);
655 RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &Cancelled); 679 RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &Cancelled);
680#ifdef RT2860
656 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) 681 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE))
657 { 682 {
658 RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled); 683 RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled);
659 RTMPCancelTimer(&pAd->Mlme.RadioOnOffTimer, &Cancelled); 684 RTMPCancelTimer(&pAd->Mlme.RadioOnOffTimer, &Cancelled);
660 } 685 }
686#endif
661 } 687 }
662 688
663 RTMPCancelTimer(&pAd->Mlme.PeriodicTimer, &Cancelled); 689 RTMPCancelTimer(&pAd->Mlme.PeriodicTimer, &Cancelled);
@@ -670,6 +696,27 @@ VOID MlmeHalt(
670 // Set LED 696 // Set LED
671 RTMPSetLED(pAd, LED_HALT); 697 RTMPSetLED(pAd, LED_HALT);
672 RTMPSetSignalLED(pAd, -100); // Force signal strength Led to be turned off, firmware is not done it. 698 RTMPSetSignalLED(pAd, -100); // Force signal strength Led to be turned off, firmware is not done it.
699#ifdef RT2870
700 {
701 LED_CFG_STRUC LedCfg;
702 RTMP_IO_READ32(pAd, LED_CFG, &LedCfg.word);
703 LedCfg.field.LedPolar = 0;
704 LedCfg.field.RLedMode = 0;
705 LedCfg.field.GLedMode = 0;
706 LedCfg.field.YLedMode = 0;
707 RTMP_IO_WRITE32(pAd, LED_CFG, LedCfg.word);
708 }
709#endif // RT2870 //
710#ifdef RT3070
711 //
712 // Turn off LNA_PE
713 //
714 if (IS_RT3070(pAd) || IS_RT3071(pAd))
715 {
716 TxPinCfg &= 0xFFFFF0F0;
717 RTUSBWriteMACRegister(pAd, TX_PIN_CFG, TxPinCfg);
718 }
719#endif // RT3070 //
673 } 720 }
674 721
675 RTMPusecDelay(5000); // 5 msec to gurantee Ant Diversity timer canceled 722 RTMPusecDelay(5000); // 5 msec to gurantee Ant Diversity timer canceled
@@ -740,6 +787,7 @@ VOID MlmePeriodicExec(
740 ULONG TxTotalCnt; 787 ULONG TxTotalCnt;
741 PRTMP_ADAPTER pAd = (RTMP_ADAPTER *)FunctionContext; 788 PRTMP_ADAPTER pAd = (RTMP_ADAPTER *)FunctionContext;
742 789
790#ifdef RT2860
743 //Baron 2008/07/10 791 //Baron 2008/07/10
744 //printk("Baron_Test:\t%s", RTMPGetRalinkEncryModeStr(pAd->StaCfg.WepStatus)); 792 //printk("Baron_Test:\t%s", RTMPGetRalinkEncryModeStr(pAd->StaCfg.WepStatus));
745 //If the STA security setting is OPEN or WEP, pAd->StaCfg.WpaSupplicantUP = 0. 793 //If the STA security setting is OPEN or WEP, pAd->StaCfg.WpaSupplicantUP = 0.
@@ -792,6 +840,7 @@ VOID MlmePeriodicExec(
792 } 840 }
793 } 841 }
794 } 842 }
843#endif /* RT2860 */
795 844
796 // Do nothing if the driver is starting halt state. 845 // Do nothing if the driver is starting halt state.
797 // This might happen when timer already been fired before cancel timer with mlmehalt 846 // This might happen when timer already been fired before cancel timer with mlmehalt
@@ -801,6 +850,7 @@ VOID MlmePeriodicExec(
801 fRTMP_ADAPTER_RESET_IN_PROGRESS)))) 850 fRTMP_ADAPTER_RESET_IN_PROGRESS))))
802 return; 851 return;
803 852
853#ifdef RT2860
804 { 854 {
805 if ((pAd->RalinkCounters.LastReceivedByteCount == pAd->RalinkCounters.ReceivedByteCount) && (pAd->StaCfg.bRadio == TRUE)) 855 if ((pAd->RalinkCounters.LastReceivedByteCount == pAd->RalinkCounters.ReceivedByteCount) && (pAd->StaCfg.bRadio == TRUE))
806 { 856 {
@@ -838,7 +888,7 @@ VOID MlmePeriodicExec(
838 AsicResetFromDMABusy(pAd); 888 AsicResetFromDMABusy(pAd);
839 } 889 }
840 } 890 }
841 891#endif /* RT2860 */
842 RT28XX_MLME_PRE_SANITY_CHECK(pAd); 892 RT28XX_MLME_PRE_SANITY_CHECK(pAd);
843 893
844 { 894 {
@@ -871,6 +921,10 @@ VOID MlmePeriodicExec(
871// RECBATimerTimeout(SystemSpecific1,FunctionContext,SystemSpecific2,SystemSpecific3); 921// RECBATimerTimeout(SystemSpecific1,FunctionContext,SystemSpecific2,SystemSpecific3);
872 pAd->Mlme.PeriodicRound ++; 922 pAd->Mlme.PeriodicRound ++;
873 923
924#ifdef RT3070
925 // execute every 100ms, update the Tx FIFO Cnt for update Tx Rate.
926 NICUpdateFifoStaCounters(pAd);
927#endif // RT3070 //
874 // execute every 500ms 928 // execute every 500ms
875 if ((pAd->Mlme.PeriodicRound % 5 == 0) && RTMPAutoRateSwitchCheck(pAd)/*(OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED))*/) 929 if ((pAd->Mlme.PeriodicRound % 5 == 0) && RTMPAutoRateSwitchCheck(pAd)/*(OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED))*/)
876 { 930 {
@@ -919,6 +973,10 @@ VOID MlmePeriodicExec(
919 // the dynamic tuning mechanism below are based on most up-to-date information 973 // the dynamic tuning mechanism below are based on most up-to-date information
920 NICUpdateRawCounters(pAd); 974 NICUpdateRawCounters(pAd);
921 975
976#ifdef RT2870
977 RT2870_WatchDog(pAd);
978#endif // RT2870 //
979
922 // Need statistics after read counter. So put after NICUpdateRawCounters 980 // Need statistics after read counter. So put after NICUpdateRawCounters
923 ORIBATimerTimeout(pAd); 981 ORIBATimerTimeout(pAd);
924 982
@@ -929,6 +987,7 @@ VOID MlmePeriodicExec(
929 pAd->RalinkCounters.OneSecTxRetryOkCount + 987 pAd->RalinkCounters.OneSecTxRetryOkCount +
930 pAd->RalinkCounters.OneSecTxFailCount; 988 pAd->RalinkCounters.OneSecTxFailCount;
931 989
990 // dynamic adjust antenna evaluation period according to the traffic
932 if (TxTotalCnt > 50) 991 if (TxTotalCnt > 50)
933 { 992 {
934 if (pAd->Mlme.OneSecPeriodicRound % 10 == 0) 993 if (pAd->Mlme.OneSecPeriodicRound % 10 == 0)
@@ -950,7 +1009,9 @@ VOID MlmePeriodicExec(
950 MlmeResetRalinkCounters(pAd); 1009 MlmeResetRalinkCounters(pAd);
951 1010
952 { 1011 {
1012#ifdef RT2860
953 if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST) && (pAd->bPCIclkOff == FALSE)) 1013 if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST) && (pAd->bPCIclkOff == FALSE))
1014#endif
954 { 1015 {
955 // When Adhoc beacon is enabled and RTS/CTS is enabled, there is a chance that hardware MAC FSM will run into a deadlock 1016 // When Adhoc beacon is enabled and RTS/CTS is enabled, there is a chance that hardware MAC FSM will run into a deadlock
956 // and sending CTS-to-self over and over. 1017 // and sending CTS-to-self over and over.
@@ -976,14 +1037,19 @@ VOID MlmePeriodicExec(
976 RT28XX_MLME_HANDLER(pAd); 1037 RT28XX_MLME_HANDLER(pAd);
977 } 1038 }
978 1039
979
980 pAd->bUpdateBcnCntDone = FALSE; 1040 pAd->bUpdateBcnCntDone = FALSE;
981} 1041}
982 1042
983VOID STAMlmePeriodicExec( 1043VOID STAMlmePeriodicExec(
984 PRTMP_ADAPTER pAd) 1044 PRTMP_ADAPTER pAd)
985{ 1045{
1046#ifdef RT2860
986 ULONG TxTotalCnt; 1047 ULONG TxTotalCnt;
1048#endif
1049#ifdef RT2870
1050 ULONG TxTotalCnt;
1051 int i;
1052#endif
987 1053
988 if (pAd->StaCfg.WpaSupplicantUP == WPA_SUPPLICANT_DISABLE) 1054 if (pAd->StaCfg.WpaSupplicantUP == WPA_SUPPLICANT_DISABLE)
989 { 1055 {
@@ -992,6 +1058,7 @@ VOID STAMlmePeriodicExec(
992 pAd->StaCfg.bBlockAssoc = FALSE; 1058 pAd->StaCfg.bBlockAssoc = FALSE;
993 } 1059 }
994 1060
1061#ifdef RT2860
995 //Baron 2008/07/10 1062 //Baron 2008/07/10
996 //printk("Baron_Test:\t%s", RTMPGetRalinkEncryModeStr(pAd->StaCfg.WepStatus)); 1063 //printk("Baron_Test:\t%s", RTMPGetRalinkEncryModeStr(pAd->StaCfg.WepStatus));
997 //If the STA security setting is OPEN or WEP, pAd->StaCfg.WpaSupplicantUP = 0. 1064 //If the STA security setting is OPEN or WEP, pAd->StaCfg.WpaSupplicantUP = 0.
@@ -1004,6 +1071,7 @@ VOID STAMlmePeriodicExec(
1004 { 1071 {
1005 pAd->StaCfg.WpaSupplicantUP = 1; 1072 pAd->StaCfg.WpaSupplicantUP = 1;
1006 } 1073 }
1074#endif
1007 1075
1008 if ((pAd->PreMediaState != pAd->IndicateMediaState) && (pAd->CommonCfg.bWirelessEvent)) 1076 if ((pAd->PreMediaState != pAd->IndicateMediaState) && (pAd->CommonCfg.bWirelessEvent))
1009 { 1077 {
@@ -1014,6 +1082,7 @@ VOID STAMlmePeriodicExec(
1014 pAd->PreMediaState = pAd->IndicateMediaState; 1082 pAd->PreMediaState = pAd->IndicateMediaState;
1015 } 1083 }
1016 1084
1085#ifdef RT2860
1017 if ((pAd->OpMode == OPMODE_STA) && (IDLE_ON(pAd)) && 1086 if ((pAd->OpMode == OPMODE_STA) && (IDLE_ON(pAd)) &&
1018 (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) && 1087 (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) &&
1019 (pAd->Mlme.SyncMachine.CurrState == SYNC_IDLE) && 1088 (pAd->Mlme.SyncMachine.CurrState == SYNC_IDLE) &&
@@ -1023,6 +1092,7 @@ VOID STAMlmePeriodicExec(
1023 { 1092 {
1024 RT28xxPciAsicRadioOff(pAd, GUI_IDLE_POWER_SAVE, 0); 1093 RT28xxPciAsicRadioOff(pAd, GUI_IDLE_POWER_SAVE, 0);
1025 } 1094 }
1095#endif
1026 1096
1027 1097
1028 1098
@@ -1119,6 +1189,7 @@ VOID STAMlmePeriodicExec(
1119 } 1189 }
1120 else if (ADHOC_ON(pAd)) 1190 else if (ADHOC_ON(pAd))
1121 { 1191 {
1192#ifdef RT2860
1122 // 2003-04-17 john. this is a patch that driver forces a BEACON out if ASIC fails 1193 // 2003-04-17 john. this is a patch that driver forces a BEACON out if ASIC fails
1123 // the "TX BEACON competition" for the entire past 1 sec. 1194 // the "TX BEACON competition" for the entire past 1 sec.
1124 // So that even when ASIC's BEACONgen engine been blocked 1195 // So that even when ASIC's BEACONgen engine been blocked
@@ -1159,6 +1230,7 @@ VOID STAMlmePeriodicExec(
1159 pAd->StaCfg.Adhoc20NJoined = FALSE; 1230 pAd->StaCfg.Adhoc20NJoined = FALSE;
1160 } 1231 }
1161 } 1232 }
1233#endif /* RT2860 */
1162 1234
1163 //radar detect 1235 //radar detect
1164 if ((pAd->CommonCfg.Channel > 14) 1236 if ((pAd->CommonCfg.Channel > 14)
@@ -1183,6 +1255,19 @@ VOID STAMlmePeriodicExec(
1183 MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_MLME_START_REQ, sizeof(MLME_START_REQ_STRUCT), &StartReq); 1255 MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_MLME_START_REQ, sizeof(MLME_START_REQ_STRUCT), &StartReq);
1184 pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_START; 1256 pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_START;
1185 } 1257 }
1258
1259#ifdef RT2870
1260 for (i = 1; i < MAX_LEN_OF_MAC_TABLE; i++)
1261 {
1262 MAC_TABLE_ENTRY *pEntry = &pAd->MacTab.Content[i];
1263
1264 if (pEntry->ValidAsCLI == FALSE)
1265 continue;
1266
1267 if (pEntry->LastBeaconRxTime + ADHOC_BEACON_LOST_TIME < pAd->Mlme.Now32)
1268 MacTableDeleteEntry(pAd, pEntry->Aid, pEntry->Addr);
1269 }
1270#endif
1186 } 1271 }
1187 else // no INFRA nor ADHOC connection 1272 else // no INFRA nor ADHOC connection
1188 { 1273 {
@@ -1350,10 +1435,16 @@ VOID MlmeSelectTxRateTable(
1350 if ((pAd->OpMode == OPMODE_STA) && ADHOC_ON(pAd)) 1435 if ((pAd->OpMode == OPMODE_STA) && ADHOC_ON(pAd))
1351 { 1436 {
1352 if ((pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED) && 1437 if ((pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED) &&
1438#ifdef RT2860
1353 !pAd->StaCfg.AdhocBOnlyJoined && 1439 !pAd->StaCfg.AdhocBOnlyJoined &&
1354 !pAd->StaCfg.AdhocBGJoined && 1440 !pAd->StaCfg.AdhocBGJoined &&
1355 (pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0xff) && 1441 (pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0xff) &&
1356 ((pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0x00) || (pAd->Antenna.field.TxPath == 1))) 1442 ((pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0x00) || (pAd->Antenna.field.TxPath == 1)))
1443#endif
1444#ifdef RT2870
1445 (pEntry->HTCapability.MCSSet[0] == 0xff) &&
1446 ((pEntry->HTCapability.MCSSet[1] == 0x00) || (pAd->Antenna.field.TxPath == 1)))
1447#endif
1357 {// 11N 1S Adhoc 1448 {// 11N 1S Adhoc
1358 *ppTable = RateSwitchTable11N1S; 1449 *ppTable = RateSwitchTable11N1S;
1359 *pTableSize = RateSwitchTable11N1S[0]; 1450 *pTableSize = RateSwitchTable11N1S[0];
@@ -1361,10 +1452,16 @@ VOID MlmeSelectTxRateTable(
1361 1452
1362 } 1453 }
1363 else if ((pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED) && 1454 else if ((pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED) &&
1455#ifdef RT2860
1364 !pAd->StaCfg.AdhocBOnlyJoined && 1456 !pAd->StaCfg.AdhocBOnlyJoined &&
1365 !pAd->StaCfg.AdhocBGJoined && 1457 !pAd->StaCfg.AdhocBGJoined &&
1366 (pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0xff) && 1458 (pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0xff) &&
1367 (pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0xff) && 1459 (pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0xff) &&
1460#endif
1461#ifdef RT2870
1462 (pEntry->HTCapability.MCSSet[0] == 0xff) &&
1463 (pEntry->HTCapability.MCSSet[1] == 0xff) &&
1464#endif
1368 (pAd->Antenna.field.TxPath == 2)) 1465 (pAd->Antenna.field.TxPath == 2))
1369 {// 11N 2S Adhoc 1466 {// 11N 2S Adhoc
1370 if (pAd->LatchRfRegs.Channel <= 14) 1467 if (pAd->LatchRfRegs.Channel <= 14)
@@ -1382,6 +1479,7 @@ VOID MlmeSelectTxRateTable(
1382 1479
1383 } 1480 }
1384 else 1481 else
1482#ifdef RT2860
1385 if (pAd->CommonCfg.PhyMode == PHY_11B) 1483 if (pAd->CommonCfg.PhyMode == PHY_11B)
1386 { 1484 {
1387 *ppTable = RateSwitchTable11B; 1485 *ppTable = RateSwitchTable11B;
@@ -1390,6 +1488,12 @@ VOID MlmeSelectTxRateTable(
1390 1488
1391 } 1489 }
1392 else if((pAd->LatchRfRegs.Channel <= 14) && (pAd->StaCfg.AdhocBOnlyJoined == TRUE)) 1490 else if((pAd->LatchRfRegs.Channel <= 14) && (pAd->StaCfg.AdhocBOnlyJoined == TRUE))
1491#endif
1492#ifdef RT2870
1493 if ((pEntry->RateLen == 4)
1494 && (pEntry->HTCapability.MCSSet[0] == 0) && (pEntry->HTCapability.MCSSet[1] == 0)
1495 )
1496#endif
1393 { 1497 {
1394 // USe B Table when Only b-only Station in my IBSS . 1498 // USe B Table when Only b-only Station in my IBSS .
1395 *ppTable = RateSwitchTable11B; 1499 *ppTable = RateSwitchTable11B;
@@ -1473,7 +1577,10 @@ VOID MlmeSelectTxRateTable(
1473 1577
1474 //else if ((pAd->StaActive.SupRateLen == 4) && (pAd->StaActive.ExtRateLen == 0) && (pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0) && (pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0)) 1578 //else if ((pAd->StaActive.SupRateLen == 4) && (pAd->StaActive.ExtRateLen == 0) && (pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0) && (pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0))
1475 if ((pEntry->RateLen == 4) 1579 if ((pEntry->RateLen == 4)
1580#ifndef RT30xx
1581//Iverson mark for Adhoc b mode,sta will use rate 54 Mbps when connect with sta b/g/n mode
1476 && (pEntry->HTCapability.MCSSet[0] == 0) && (pEntry->HTCapability.MCSSet[1] == 0) 1582 && (pEntry->HTCapability.MCSSet[0] == 0) && (pEntry->HTCapability.MCSSet[1] == 0)
1583#endif
1477 ) 1584 )
1478 {// B only AP 1585 {// B only AP
1479 *ppTable = RateSwitchTable11B; 1586 *ppTable = RateSwitchTable11B;
@@ -1934,7 +2041,15 @@ VOID MlmeDynamicTxRateSwitching(
1934 2041
1935 if ((pAd->MacTab.Size == 1) || (pEntry->ValidAsDls)) 2042 if ((pAd->MacTab.Size == 1) || (pEntry->ValidAsDls))
1936 { 2043 {
2044#ifdef RT2860
1937 Rssi = RTMPMaxRssi(pAd, (CHAR)pAd->StaCfg.RssiSample.AvgRssi0, (CHAR)pAd->StaCfg.RssiSample.AvgRssi1, (CHAR)pAd->StaCfg.RssiSample.AvgRssi2); 2045 Rssi = RTMPMaxRssi(pAd, (CHAR)pAd->StaCfg.RssiSample.AvgRssi0, (CHAR)pAd->StaCfg.RssiSample.AvgRssi1, (CHAR)pAd->StaCfg.RssiSample.AvgRssi2);
2046#endif
2047#ifdef RT2870
2048 Rssi = RTMPMaxRssi(pAd,
2049 pAd->StaCfg.RssiSample.AvgRssi0,
2050 pAd->StaCfg.RssiSample.AvgRssi1,
2051 pAd->StaCfg.RssiSample.AvgRssi2);
2052#endif
1938 2053
1939 // Update statistic counter 2054 // Update statistic counter
1940 RTMP_IO_READ32(pAd, TX_STA_CNT0, &TxStaCnt0.word); 2055 RTMP_IO_READ32(pAd, TX_STA_CNT0, &TxStaCnt0.word);
@@ -1964,7 +2079,21 @@ VOID MlmeDynamicTxRateSwitching(
1964 } 2079 }
1965 else 2080 else
1966 { 2081 {
2082#ifdef RT2860
1967 Rssi = RTMPMaxRssi(pAd, (CHAR)pEntry->RssiSample.AvgRssi0, (CHAR)pEntry->RssiSample.AvgRssi1, (CHAR)pEntry->RssiSample.AvgRssi2); 2083 Rssi = RTMPMaxRssi(pAd, (CHAR)pEntry->RssiSample.AvgRssi0, (CHAR)pEntry->RssiSample.AvgRssi1, (CHAR)pEntry->RssiSample.AvgRssi2);
2084#endif
2085#ifdef RT2870
2086 if (INFRA_ON(pAd) && (i == 1))
2087 Rssi = RTMPMaxRssi(pAd,
2088 pAd->StaCfg.RssiSample.AvgRssi0,
2089 pAd->StaCfg.RssiSample.AvgRssi1,
2090 pAd->StaCfg.RssiSample.AvgRssi2);
2091 else
2092 Rssi = RTMPMaxRssi(pAd,
2093 pEntry->RssiSample.AvgRssi0,
2094 pEntry->RssiSample.AvgRssi1,
2095 pEntry->RssiSample.AvgRssi2);
2096#endif
1968 2097
1969 TxTotalCnt = pEntry->OneSecTxNoRetryOkCount + 2098 TxTotalCnt = pEntry->OneSecTxNoRetryOkCount +
1970 pEntry->OneSecTxRetryOkCount + 2099 pEntry->OneSecTxRetryOkCount +
@@ -2388,7 +2517,12 @@ VOID StaQuickResponeForRateUpExec(
2388 UCHAR UpRateIdx = 0, DownRateIdx = 0, CurrRateIdx = 0; 2517 UCHAR UpRateIdx = 0, DownRateIdx = 0, CurrRateIdx = 0;
2389 ULONG TxTotalCnt; 2518 ULONG TxTotalCnt;
2390 ULONG TxErrorRatio = 0; 2519 ULONG TxErrorRatio = 0;
2520#ifdef RT2860
2391 BOOLEAN bTxRateChanged = TRUE; //, bUpgradeQuality = FALSE; 2521 BOOLEAN bTxRateChanged = TRUE; //, bUpgradeQuality = FALSE;
2522#endif
2523#ifdef RT2870
2524 BOOLEAN bTxRateChanged; //, bUpgradeQuality = FALSE;
2525#endif
2392 PRTMP_TX_RATE_SWITCH pCurrTxRate, pNextTxRate = NULL; 2526 PRTMP_TX_RATE_SWITCH pCurrTxRate, pNextTxRate = NULL;
2393 PUCHAR pTable; 2527 PUCHAR pTable;
2394 UCHAR TableSize = 0; 2528 UCHAR TableSize = 0;
@@ -2413,11 +2547,25 @@ VOID StaQuickResponeForRateUpExec(
2413 if (RTMPCheckEntryEnableAutoRateSwitch(pAd, pEntry) == FALSE) 2547 if (RTMPCheckEntryEnableAutoRateSwitch(pAd, pEntry) == FALSE)
2414 continue; 2548 continue;
2415 2549
2550#ifdef RT2860
2416 //Rssi = RTMPMaxRssi(pAd, (CHAR)pAd->StaCfg.AvgRssi0, (CHAR)pAd->StaCfg.AvgRssi1, (CHAR)pAd->StaCfg.AvgRssi2); 2551 //Rssi = RTMPMaxRssi(pAd, (CHAR)pAd->StaCfg.AvgRssi0, (CHAR)pAd->StaCfg.AvgRssi1, (CHAR)pAd->StaCfg.AvgRssi2);
2417 if (pAd->Antenna.field.TxPath > 1) 2552 if (pAd->Antenna.field.TxPath > 1)
2418 Rssi = (pAd->StaCfg.RssiSample.AvgRssi0 + pAd->StaCfg.RssiSample.AvgRssi1) >> 1; 2553 Rssi = (pAd->StaCfg.RssiSample.AvgRssi0 + pAd->StaCfg.RssiSample.AvgRssi1) >> 1;
2419 else 2554 else
2420 Rssi = pAd->StaCfg.RssiSample.AvgRssi0; 2555 Rssi = pAd->StaCfg.RssiSample.AvgRssi0;
2556#endif
2557#ifdef RT2870
2558 if (INFRA_ON(pAd) && (i == 1))
2559 Rssi = RTMPMaxRssi(pAd,
2560 pAd->StaCfg.RssiSample.AvgRssi0,
2561 pAd->StaCfg.RssiSample.AvgRssi1,
2562 pAd->StaCfg.RssiSample.AvgRssi2);
2563 else
2564 Rssi = RTMPMaxRssi(pAd,
2565 pEntry->RssiSample.AvgRssi0,
2566 pEntry->RssiSample.AvgRssi1,
2567 pEntry->RssiSample.AvgRssi2);
2568#endif
2421 2569
2422 CurrRateIdx = pAd->CommonCfg.TxRateIndex; 2570 CurrRateIdx = pAd->CommonCfg.TxRateIndex;
2423 2571
@@ -2557,6 +2705,9 @@ VOID StaQuickResponeForRateUpExec(
2557 pAd->DrsCounters.TxRateUpPenalty = 0; 2705 pAd->DrsCounters.TxRateUpPenalty = 0;
2558 NdisZeroMemory(pAd->DrsCounters.TxQuality, sizeof(USHORT) * MAX_STEP_OF_TX_RATE_SWITCH); 2706 NdisZeroMemory(pAd->DrsCounters.TxQuality, sizeof(USHORT) * MAX_STEP_OF_TX_RATE_SWITCH);
2559 NdisZeroMemory(pAd->DrsCounters.PER, sizeof(UCHAR) * MAX_STEP_OF_TX_RATE_SWITCH); 2707 NdisZeroMemory(pAd->DrsCounters.PER, sizeof(UCHAR) * MAX_STEP_OF_TX_RATE_SWITCH);
2708#ifdef RT2870
2709 bTxRateChanged = TRUE;
2710#endif
2560 } 2711 }
2561 // if rate-down happen, only clear DownRate's bad history 2712 // if rate-down happen, only clear DownRate's bad history
2562 else if (pAd->CommonCfg.TxRateIndex < CurrRateIdx) 2713 else if (pAd->CommonCfg.TxRateIndex < CurrRateIdx)
@@ -2566,6 +2717,9 @@ VOID StaQuickResponeForRateUpExec(
2566 pAd->DrsCounters.TxRateUpPenalty = 0; // no penalty 2717 pAd->DrsCounters.TxRateUpPenalty = 0; // no penalty
2567 pAd->DrsCounters.TxQuality[pAd->CommonCfg.TxRateIndex] = 0; 2718 pAd->DrsCounters.TxQuality[pAd->CommonCfg.TxRateIndex] = 0;
2568 pAd->DrsCounters.PER[pAd->CommonCfg.TxRateIndex] = 0; 2719 pAd->DrsCounters.PER[pAd->CommonCfg.TxRateIndex] = 0;
2720#ifdef RT2870
2721 bTxRateChanged = TRUE;
2722#endif
2569 } 2723 }
2570 else 2724 else
2571 { 2725 {
@@ -2621,7 +2775,13 @@ VOID MlmeCheckPsmChange(
2621 if (INFRA_ON(pAd) && 2775 if (INFRA_ON(pAd) &&
2622 (PowerMode != Ndis802_11PowerModeCAM) && 2776 (PowerMode != Ndis802_11PowerModeCAM) &&
2623 (pAd->StaCfg.Psm == PWR_ACTIVE) && 2777 (pAd->StaCfg.Psm == PWR_ACTIVE) &&
2778#ifdef RT2860
2624 RTMP_TEST_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP)) 2779 RTMP_TEST_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP))
2780#endif
2781#if !defined(RT2860) && !defined(RT30xx)
2782 (pAd->Mlme.CntlMachine.CurrState == CNTL_IDLE))
2783#endif
2784#ifndef RT30xx
2625 { 2785 {
2626 NdisGetSystemUpTime(&pAd->Mlme.LastSendNULLpsmTime); 2786 NdisGetSystemUpTime(&pAd->Mlme.LastSendNULLpsmTime);
2627 pAd->RalinkCounters.RxCountSinceLastNULL = 0; 2787 pAd->RalinkCounters.RxCountSinceLastNULL = 0;
@@ -2635,6 +2795,42 @@ VOID MlmeCheckPsmChange(
2635 RTMPSendNullFrame(pAd, pAd->CommonCfg.TxRate, TRUE); 2795 RTMPSendNullFrame(pAd, pAd->CommonCfg.TxRate, TRUE);
2636 } 2796 }
2637 } 2797 }
2798#endif
2799#ifdef RT30xx
2800// (! RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS))
2801 (pAd->Mlme.CntlMachine.CurrState == CNTL_IDLE) /*&&
2802 (pAd->RalinkCounters.OneSecTxNoRetryOkCount == 0) &&
2803 (pAd->RalinkCounters.OneSecTxRetryOkCount == 0)*/)
2804 {
2805 // add by johnli, use Rx OK data count per second to calculate throughput
2806 // If Ttraffic is too high ( > 400 Rx per second), don't go to sleep mode. If tx rate is low, use low criteria
2807 // Mode=CCK/MCS=3 => 11 Mbps, Mode=OFDM/MCS=3 => 18 Mbps
2808 if (((pAd->StaCfg.HTPhyMode.field.MCS <= 3) &&
2809/* Iverson mark
2810 (pAd->StaCfg.HTPhyMode.field.MODE <= MODE_OFDM) &&
2811*/
2812 (pAd->RalinkCounters.OneSecRxOkDataCnt < (ULONG)100)) ||
2813 ((pAd->StaCfg.HTPhyMode.field.MCS > 3) &&
2814/* Iverson mark
2815 (pAd->StaCfg.HTPhyMode.field.MODE > MODE_OFDM) &&
2816*/
2817 (pAd->RalinkCounters.OneSecRxOkDataCnt < (ULONG)400)))
2818 {
2819 // Get this time
2820 NdisGetSystemUpTime(&pAd->Mlme.LastSendNULLpsmTime);
2821 pAd->RalinkCounters.RxCountSinceLastNULL = 0;
2822 MlmeSetPsmBit(pAd, PWR_SAVE);
2823 if (!(pAd->CommonCfg.bAPSDCapable && pAd->CommonCfg.APEdcaParm.bAPSDCapable))
2824 {
2825 RTMPSendNullFrame(pAd, pAd->CommonCfg.TxRate, FALSE);
2826 }
2827 else
2828 {
2829 RTMPSendNullFrame(pAd, pAd->CommonCfg.TxRate, TRUE);
2830 }
2831 }
2832 }
2833#endif
2638} 2834}
2639 2835
2640// IRQL = PASSIVE_LEVEL 2836// IRQL = PASSIVE_LEVEL
@@ -2649,7 +2845,9 @@ VOID MlmeSetPsmBit(
2649 RTMP_IO_READ32(pAd, AUTO_RSP_CFG, &csr4.word); 2845 RTMP_IO_READ32(pAd, AUTO_RSP_CFG, &csr4.word);
2650 csr4.field.AckCtsPsmBit = (psm == PWR_SAVE)? 1:0; 2846 csr4.field.AckCtsPsmBit = (psm == PWR_SAVE)? 1:0;
2651 RTMP_IO_WRITE32(pAd, AUTO_RSP_CFG, csr4.word); 2847 RTMP_IO_WRITE32(pAd, AUTO_RSP_CFG, csr4.word);
2848#ifndef RT30xx
2652 DBGPRINT(RT_DEBUG_TRACE, ("MlmeSetPsmBit = %d\n", psm)); 2849 DBGPRINT(RT_DEBUG_TRACE, ("MlmeSetPsmBit = %d\n", psm));
2850#endif
2653} 2851}
2654 2852
2655// IRQL = DISPATCH_LEVEL 2853// IRQL = DISPATCH_LEVEL
@@ -3679,9 +3877,18 @@ ULONG BssTableSetEntry(
3679 } 3877 }
3680 else 3878 else
3681 { 3879 {
3880#ifdef RT30xx
3881 /* avoid Hidden SSID form beacon to overwirite correct SSID from probe response */
3882 if ((SSID_EQUAL(Ssid, SsidLen, Tab->BssEntry[Idx].Ssid, Tab->BssEntry[Idx].SsidLen)) ||
3883 (NdisEqualMemory(Tab->BssEntry[Idx].Ssid, ZeroSsid, Tab->BssEntry[Idx].SsidLen)))
3884 {
3885#endif
3682 BssEntrySet(pAd, &Tab->BssEntry[Idx], pBssid, Ssid, SsidLen, BssType, BeaconPeriod,CfParm, AtimWin, 3886 BssEntrySet(pAd, &Tab->BssEntry[Idx], pBssid, Ssid, SsidLen, BssType, BeaconPeriod,CfParm, AtimWin,
3683 CapabilityInfo, SupRate, SupRateLen, ExtRate, ExtRateLen,pHtCapability, pAddHtInfo,HtCapabilityLen, AddHtInfoLen, 3887 CapabilityInfo, SupRate, SupRateLen, ExtRate, ExtRateLen,pHtCapability, pAddHtInfo,HtCapabilityLen, AddHtInfoLen,
3684 NewExtChanOffset, ChannelNo, Rssi, TimeStamp, CkipFlag, pEdcaParm, pQosCapability, pQbssLoad, LengthVIE, pVIE); 3888 NewExtChanOffset, ChannelNo, Rssi, TimeStamp, CkipFlag, pEdcaParm, pQosCapability, pQbssLoad, LengthVIE, pVIE);
3889#ifdef RT30xx
3890 }
3891#endif
3685 } 3892 }
3686 3893
3687 return Idx; 3894 return Idx;
@@ -3742,9 +3949,14 @@ VOID BssTableSsidSort(
3742 continue; 3949 continue;
3743 3950
3744 // check group cipher 3951 // check group cipher
3952#ifndef RT30xx
3745 if ((pAd->StaCfg.WepStatus < pInBss->WPA.GroupCipher) && 3953 if ((pAd->StaCfg.WepStatus < pInBss->WPA.GroupCipher) &&
3746 (pInBss->WPA.GroupCipher != Ndis802_11GroupWEP40Enabled) && 3954 (pInBss->WPA.GroupCipher != Ndis802_11GroupWEP40Enabled) &&
3747 (pInBss->WPA.GroupCipher != Ndis802_11GroupWEP104Enabled)) 3955 (pInBss->WPA.GroupCipher != Ndis802_11GroupWEP104Enabled))
3956#endif
3957#ifdef RT30xx
3958 if (pAd->StaCfg.WepStatus < pInBss->WPA.GroupCipher)
3959#endif
3748 continue; 3960 continue;
3749 3961
3750 // check pairwise cipher, skip if none matched 3962 // check pairwise cipher, skip if none matched
@@ -3763,9 +3975,14 @@ VOID BssTableSsidSort(
3763 continue; 3975 continue;
3764 3976
3765 // check group cipher 3977 // check group cipher
3978#ifndef RT30xx
3766 if ((pAd->StaCfg.WepStatus < pInBss->WPA.GroupCipher) && 3979 if ((pAd->StaCfg.WepStatus < pInBss->WPA.GroupCipher) &&
3767 (pInBss->WPA2.GroupCipher != Ndis802_11GroupWEP40Enabled) && 3980 (pInBss->WPA2.GroupCipher != Ndis802_11GroupWEP40Enabled) &&
3768 (pInBss->WPA2.GroupCipher != Ndis802_11GroupWEP104Enabled)) 3981 (pInBss->WPA2.GroupCipher != Ndis802_11GroupWEP104Enabled))
3982#endif
3983#ifdef RT30xx
3984 if (pAd->StaCfg.WepStatus < pInBss->WPA2.GroupCipher)
3985#endif
3769 continue; 3986 continue;
3770 3987
3771 // check pairwise cipher, skip if none matched 3988 // check pairwise cipher, skip if none matched
@@ -4043,10 +4260,16 @@ VOID BssCipherParse(
4043 switch (*pTmp) 4260 switch (*pTmp)
4044 { 4261 {
4045 case 1: 4262 case 1:
4263#ifndef RT30xx
4046 pBss->WPA.GroupCipher = Ndis802_11GroupWEP40Enabled; 4264 pBss->WPA.GroupCipher = Ndis802_11GroupWEP40Enabled;
4047 break; 4265 break;
4048 case 5: 4266 case 5:
4049 pBss->WPA.GroupCipher = Ndis802_11GroupWEP104Enabled; 4267 pBss->WPA.GroupCipher = Ndis802_11GroupWEP104Enabled;
4268#endif
4269#ifdef RT30xx
4270 case 5: // Although WEP is not allowed in WPA related auth mode, we parse it anyway
4271 pBss->WPA.GroupCipher = Ndis802_11Encryption1Enabled;
4272#endif
4050 break; 4273 break;
4051 case 2: 4274 case 2:
4052 pBss->WPA.GroupCipher = Ndis802_11Encryption2Enabled; 4275 pBss->WPA.GroupCipher = Ndis802_11Encryption2Enabled;
@@ -4133,7 +4356,6 @@ VOID BssCipherParse(
4133 pBss->AuthMode = Ndis802_11AuthModeWPANone; 4356 pBss->AuthMode = Ndis802_11AuthModeWPANone;
4134 pBss->AuthModeAux = Ndis802_11AuthModeWPANone; 4357 pBss->AuthModeAux = Ndis802_11AuthModeWPANone;
4135 pBss->WepStatus = pBss->WPA.GroupCipher; 4358 pBss->WepStatus = pBss->WPA.GroupCipher;
4136 // Patched bugs for old driver
4137 if (pBss->WPA.PairCipherAux == Ndis802_11WEPDisabled) 4359 if (pBss->WPA.PairCipherAux == Ndis802_11WEPDisabled)
4138 pBss->WPA.PairCipherAux = pBss->WPA.GroupCipher; 4360 pBss->WPA.PairCipherAux = pBss->WPA.GroupCipher;
4139 } 4361 }
@@ -4163,10 +4385,16 @@ VOID BssCipherParse(
4163 switch (pCipher->Type) 4385 switch (pCipher->Type)
4164 { 4386 {
4165 case 1: 4387 case 1:
4388#ifndef RT30xx
4166 pBss->WPA2.GroupCipher = Ndis802_11GroupWEP40Enabled; 4389 pBss->WPA2.GroupCipher = Ndis802_11GroupWEP40Enabled;
4167 break; 4390 break;
4168 case 5: 4391 case 5:
4169 pBss->WPA2.GroupCipher = Ndis802_11GroupWEP104Enabled; 4392 pBss->WPA2.GroupCipher = Ndis802_11GroupWEP104Enabled;
4393#endif
4394#ifdef RT30xx
4395 case 5: // Although WEP is not allowed in WPA related auth mode, we parse it anyway
4396 pBss->WPA2.GroupCipher = Ndis802_11Encryption1Enabled;
4397#endif
4170 break; 4398 break;
4171 case 2: 4399 case 2:
4172 pBss->WPA2.GroupCipher = Ndis802_11Encryption2Enabled; 4400 pBss->WPA2.GroupCipher = Ndis802_11Encryption2Enabled;
@@ -4260,7 +4488,6 @@ VOID BssCipherParse(
4260 pBss->WPA.PairCipherAux = pBss->WPA2.PairCipherAux; 4488 pBss->WPA.PairCipherAux = pBss->WPA2.PairCipherAux;
4261 pBss->WPA.GroupCipher = pBss->WPA2.GroupCipher; 4489 pBss->WPA.GroupCipher = pBss->WPA2.GroupCipher;
4262 pBss->WepStatus = pBss->WPA.GroupCipher; 4490 pBss->WepStatus = pBss->WPA.GroupCipher;
4263 // Patched bugs for old driver
4264 if (pBss->WPA.PairCipherAux == Ndis802_11WEPDisabled) 4491 if (pBss->WPA.PairCipherAux == Ndis802_11WEPDisabled)
4265 pBss->WPA.PairCipherAux = pBss->WPA.GroupCipher; 4492 pBss->WPA.PairCipherAux = pBss->WPA.GroupCipher;
4266 } 4493 }
@@ -4619,11 +4846,14 @@ BOOLEAN MlmeDequeue(
4619VOID MlmeRestartStateMachine( 4846VOID MlmeRestartStateMachine(
4620 IN PRTMP_ADAPTER pAd) 4847 IN PRTMP_ADAPTER pAd)
4621{ 4848{
4849#ifdef RT2860
4622 MLME_QUEUE_ELEM *Elem = NULL; 4850 MLME_QUEUE_ELEM *Elem = NULL;
4851#endif
4623 BOOLEAN Cancelled; 4852 BOOLEAN Cancelled;
4624 4853
4625 DBGPRINT(RT_DEBUG_TRACE, ("MlmeRestartStateMachine \n")); 4854 DBGPRINT(RT_DEBUG_TRACE, ("MlmeRestartStateMachine \n"));
4626 4855
4856#ifdef RT2860
4627 NdisAcquireSpinLock(&pAd->Mlme.TaskLock); 4857 NdisAcquireSpinLock(&pAd->Mlme.TaskLock);
4628 if(pAd->Mlme.bRunning) 4858 if(pAd->Mlme.bRunning)
4629 { 4859 {
@@ -4651,6 +4881,7 @@ VOID MlmeRestartStateMachine(
4651 DBGPRINT_ERR(("MlmeRestartStateMachine: MlmeQueue empty\n")); 4881 DBGPRINT_ERR(("MlmeRestartStateMachine: MlmeQueue empty\n"));
4652 } 4882 }
4653 } 4883 }
4884#endif /* RT2860 */
4654 4885
4655 { 4886 {
4656 // Cancel all timer events 4887 // Cancel all timer events
@@ -4680,10 +4911,12 @@ VOID MlmeRestartStateMachine(
4680 pAd->Mlme.ActMachine.CurrState = ACT_IDLE; 4911 pAd->Mlme.ActMachine.CurrState = ACT_IDLE;
4681 } 4912 }
4682 4913
4914#ifdef RT2860
4683 // Remove running state 4915 // Remove running state
4684 NdisAcquireSpinLock(&pAd->Mlme.TaskLock); 4916 NdisAcquireSpinLock(&pAd->Mlme.TaskLock);
4685 pAd->Mlme.bRunning = FALSE; 4917 pAd->Mlme.bRunning = FALSE;
4686 NdisReleaseSpinLock(&pAd->Mlme.TaskLock); 4918 NdisReleaseSpinLock(&pAd->Mlme.TaskLock);
4919#endif
4687} 4920}
4688 4921
4689/*! \brief test if the MLME Queue is empty 4922/*! \brief test if the MLME Queue is empty
@@ -5402,6 +5635,276 @@ VOID AsicUpdateProtect(
5402 } 5635 }
5403} 5636}
5404 5637
5638#ifdef RT30xx
5639/*
5640 ========================================================================
5641
5642 Routine Description: Write RT30xx RF register through MAC
5643
5644 Arguments:
5645
5646 Return Value:
5647
5648 IRQL =
5649
5650 Note:
5651
5652 ========================================================================
5653*/
5654NTSTATUS RT30xxWriteRFRegister(
5655 IN PRTMP_ADAPTER pAd,
5656 IN UCHAR RegID,
5657 IN UCHAR Value)
5658{
5659 RF_CSR_CFG_STRUC rfcsr;
5660 UINT i = 0;
5661
5662 do
5663 {
5664 RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
5665
5666 if (!rfcsr.field.RF_CSR_KICK)
5667 break;
5668 i++;
5669 }
5670 while ((i < RETRY_LIMIT) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)));
5671
5672 if ((i == RETRY_LIMIT) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
5673 {
5674 DBGPRINT_RAW(RT_DEBUG_ERROR, ("Retry count exhausted or device removed!!!\n"));
5675 return STATUS_UNSUCCESSFUL;
5676 }
5677
5678 rfcsr.field.RF_CSR_WR = 1;
5679 rfcsr.field.RF_CSR_KICK = 1;
5680 rfcsr.field.TESTCSR_RFACC_REGNUM = RegID;
5681 rfcsr.field.RF_CSR_DATA = Value;
5682
5683 RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
5684
5685 return STATUS_SUCCESS;
5686}
5687
5688
5689/*
5690 ========================================================================
5691
5692 Routine Description: Read RT30xx RF register through MAC
5693
5694 Arguments:
5695
5696 Return Value:
5697
5698 IRQL =
5699
5700 Note:
5701
5702 ========================================================================
5703*/
5704NTSTATUS RT30xxReadRFRegister(
5705 IN PRTMP_ADAPTER pAd,
5706 IN UCHAR RegID,
5707 IN PUCHAR pValue)
5708{
5709 RF_CSR_CFG_STRUC rfcsr;
5710 UINT i=0, k=0;
5711
5712 for (i=0; i<MAX_BUSY_COUNT; i++)
5713 {
5714 RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
5715
5716 if (rfcsr.field.RF_CSR_KICK == BUSY)
5717 {
5718 continue;
5719 }
5720 rfcsr.word = 0;
5721 rfcsr.field.RF_CSR_WR = 0;
5722 rfcsr.field.RF_CSR_KICK = 1;
5723 rfcsr.field.TESTCSR_RFACC_REGNUM = RegID;
5724 RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
5725 for (k=0; k<MAX_BUSY_COUNT; k++)
5726 {
5727 RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
5728
5729 if (rfcsr.field.RF_CSR_KICK == IDLE)
5730 break;
5731 }
5732 if ((rfcsr.field.RF_CSR_KICK == IDLE) &&
5733 (rfcsr.field.TESTCSR_RFACC_REGNUM == RegID))
5734 {
5735 *pValue = (UCHAR)rfcsr.field.RF_CSR_DATA;
5736 break;
5737 }
5738 }
5739 if (rfcsr.field.RF_CSR_KICK == BUSY)
5740 {
5741 DBGPRINT_ERR(("RF read R%d=0x%x fail, i[%d], k[%d]\n", RegID, rfcsr.word,i,k));
5742 return STATUS_UNSUCCESSFUL;
5743 }
5744
5745 return STATUS_SUCCESS;
5746}
5747#endif // RT30xx //
5748
5749#ifdef RT30xx
5750// add by johnli, RF power sequence setup
5751/*
5752 ==========================================================================
5753 Description:
5754
5755 Load RF normal operation-mode setup
5756
5757 ==========================================================================
5758 */
5759VOID RT30xxLoadRFNormalModeSetup(
5760 IN PRTMP_ADAPTER pAd)
5761{
5762 UCHAR RFValue;
5763
5764 // RX0_PD & TX0_PD, RF R1 register Bit 2 & Bit 3 to 0 and RF_BLOCK_en,RX1_PD & TX1_PD, Bit0, Bit 4 & Bit5 to 1
5765 RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
5766 RFValue = (RFValue & (~0x0C)) | 0x31;
5767 RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
5768
5769 // TX_LO2_en, RF R15 register Bit 3 to 0
5770 RT30xxReadRFRegister(pAd, RF_R15, &RFValue);
5771 RFValue &= (~0x08);
5772 RT30xxWriteRFRegister(pAd, RF_R15, RFValue);
5773
5774 // TX_LO1_en, RF R17 register Bit 3 to 0
5775 RT30xxReadRFRegister(pAd, RF_R17, &RFValue);
5776 RFValue &= (~0x08);
5777 // to fix rx long range issue
5778 if (((pAd->MACVersion & 0xffff) >= 0x0211) && (pAd->NicConfig2.field.ExternalLNAForG == 0))
5779 {
5780 RFValue |= 0x20;
5781 }
5782 RT30xxWriteRFRegister(pAd, RF_R17, RFValue);
5783
5784 // RX_LO1_en, RF R20 register Bit 3 to 0
5785 RT30xxReadRFRegister(pAd, RF_R20, &RFValue);
5786 RFValue &= (~0x08);
5787 RT30xxWriteRFRegister(pAd, RF_R20, RFValue);
5788
5789 // RX_LO2_en, RF R21 register Bit 3 to 0
5790 RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
5791 RFValue &= (~0x08);
5792 RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
5793
5794 // LDORF_VC, RF R27 register Bit 2 to 0
5795 RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
5796 if ((pAd->MACVersion & 0xffff) < 0x0211)
5797 RFValue = (RFValue & (~0x77)) | 0x3;
5798 else
5799 RFValue = (RFValue & (~0x77));
5800 RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
5801 /* end johnli */
5802}
5803
5804/*
5805 ==========================================================================
5806 Description:
5807
5808 Load RF sleep-mode setup
5809
5810 ==========================================================================
5811 */
5812VOID RT30xxLoadRFSleepModeSetup(
5813 IN PRTMP_ADAPTER pAd)
5814{
5815 UCHAR RFValue;
5816 UINT32 MACValue;
5817
5818 // RF_BLOCK_en. RF R1 register Bit 0 to 0
5819 RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
5820 RFValue &= (~0x01);
5821 RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
5822
5823 // VCO_IC, RF R7 register Bit 4 & Bit 5 to 0
5824 RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
5825 RFValue &= (~0x30);
5826 RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
5827
5828 // Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0
5829 RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
5830 RFValue &= (~0x0E);
5831 RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
5832
5833 // RX_CTB_en, RF R21 register Bit 7 to 0
5834 RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
5835 RFValue &= (~0x80);
5836 RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
5837
5838 // LDORF_VC, RF R27 register Bit 0, Bit 1 & Bit 2 to 1
5839 RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
5840 RFValue |= 0x77;
5841 RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
5842
5843 RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
5844 MACValue |= 0x1D000000;
5845 RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
5846}
5847
5848/*
5849 ==========================================================================
5850 Description:
5851
5852 Reverse RF sleep-mode setup
5853
5854 ==========================================================================
5855 */
5856VOID RT30xxReverseRFSleepModeSetup(
5857 IN PRTMP_ADAPTER pAd)
5858{
5859 UCHAR RFValue;
5860 UINT32 MACValue;
5861
5862 // RF_BLOCK_en, RF R1 register Bit 0 to 1
5863 RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
5864 RFValue |= 0x01;
5865 RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
5866
5867 // VCO_IC, RF R7 register Bit 4 & Bit 5 to 1
5868 RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
5869 RFValue |= 0x30;
5870 RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
5871
5872 // Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1
5873 RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
5874 RFValue |= 0x0E;
5875 RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
5876
5877 // RX_CTB_en, RF R21 register Bit 7 to 1
5878 RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
5879 RFValue |= 0x80;
5880 RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
5881
5882 // LDORF_VC, RF R27 register Bit 2 to 0
5883 RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
5884 if ((pAd->MACVersion & 0xffff) < 0x0211)
5885 RFValue = (RFValue & (~0x77)) | 0x3;
5886 else
5887 RFValue = (RFValue & (~0x77));
5888 RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
5889
5890 // RT3071 version E has fixed this issue
5891 if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
5892 {
5893 // patch tx EVM issue temporarily
5894 RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
5895 MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000);
5896 RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
5897 }
5898 else
5899 {
5900 RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
5901 MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000);
5902 RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
5903 }
5904}
5905// end johnli
5906#endif // RT30xx //
5907
5405/* 5908/*
5406 ========================================================================== 5909 ==========================================================================
5407 Description: 5910 Description:
@@ -5423,6 +5926,21 @@ VOID AsicSwitchChannel(
5423 RTMP_RF_REGS *RFRegTable; 5926 RTMP_RF_REGS *RFRegTable;
5424 5927
5425 // Search Tx power value 5928 // Search Tx power value
5929#ifdef RT30xx
5930 // We can't use ChannelList to search channel, since some central channl's txpowr doesn't list
5931 // in ChannelList, so use TxPower array instead.
5932 //
5933 for (index = 0; index < MAX_NUM_OF_CHANNELS; index++)
5934 {
5935 if (Channel == pAd->TxPower[index].Channel)
5936 {
5937 TxPwer = pAd->TxPower[index].Power;
5938 TxPwer2 = pAd->TxPower[index].Power2;
5939 break;
5940 }
5941 }
5942#endif
5943#ifndef RT30xx
5426 for (index = 0; index < pAd->ChannelListNum; index++) 5944 for (index = 0; index < pAd->ChannelListNum; index++)
5427 { 5945 {
5428 if (Channel == pAd->ChannelList[index].Channel) 5946 if (Channel == pAd->ChannelList[index].Channel)
@@ -5432,12 +5950,152 @@ VOID AsicSwitchChannel(
5432 break; 5950 break;
5433 } 5951 }
5434 } 5952 }
5953#endif
5435 5954
5436 if (index == MAX_NUM_OF_CHANNELS) 5955 if (index == MAX_NUM_OF_CHANNELS)
5437 { 5956 {
5957#ifndef RT30xx
5438 DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Cant find the Channel#%d \n", Channel)); 5958 DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Cant find the Channel#%d \n", Channel));
5959#endif
5960#ifdef RT30xx
5961 DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel));
5962#endif
5439 } 5963 }
5440 5964
5965#ifdef RT2870
5966 // The RF programming sequence is difference between 3xxx and 2xxx
5967#ifdef RT30xx
5968 if ((IS_RT3070(pAd) || IS_RT3090(pAd)) && ((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020) ||
5969 (pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022)))
5970#endif
5971#ifndef RT30xx
5972 if (IS_RT3070(pAd) && ((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020)))
5973#endif
5974 {
5975 /* modify by WY for Read RF Reg. error */
5976 UCHAR RFValue;
5977
5978 for (index = 0; index < NUM_OF_3020_CHNL; index++)
5979 {
5980 if (Channel == FreqItems3020[index].Channel)
5981 {
5982 // Programming channel parameters
5983 RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3020[index].N);
5984 RT30xxWriteRFRegister(pAd, RF_R03, FreqItems3020[index].K);
5985
5986#ifndef RT30xx
5987 RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RFValue);
5988 RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
5989 RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RFValue);
5990
5991 // Set Tx Power
5992 RT30xxReadRFRegister(pAd, RF_R12, (PUCHAR)&RFValue);
5993 RFValue = (RFValue & 0xE0) | TxPwer;
5994 RT30xxWriteRFRegister(pAd, RF_R12, (UCHAR)RFValue);
5995
5996 // Set RF offset
5997 RT30xxReadRFRegister(pAd, RF_R23, (PUCHAR)&RFValue);
5998 RFValue = (RFValue & 0x80) | pAd->RfFreqOffset;
5999 RT30xxWriteRFRegister(pAd, RF_R23, (UCHAR)RFValue);
6000#endif
6001#ifdef RT30xx
6002 RT30xxReadRFRegister(pAd, RF_R06, &RFValue);
6003 RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
6004 RT30xxWriteRFRegister(pAd, RF_R06, RFValue);
6005
6006 // Set Tx0 Power
6007 RT30xxReadRFRegister(pAd, RF_R12, &RFValue);
6008 RFValue = (RFValue & 0xE0) | TxPwer;
6009 RT30xxWriteRFRegister(pAd, RF_R12, RFValue);
6010
6011 // Set Tx1 Power
6012 RT30xxReadRFRegister(pAd, RF_R13, &RFValue);
6013 RFValue = (RFValue & 0xE0) | TxPwer2;
6014 RT30xxWriteRFRegister(pAd, RF_R13, RFValue);
6015
6016 // Tx/Rx Stream setting
6017 RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
6018 //if (IS_RT3090(pAd))
6019 // RFValue |= 0x01; // Enable RF block.
6020 RFValue &= 0x03; //clear bit[7~2]
6021 if (pAd->Antenna.field.TxPath == 1)
6022 RFValue |= 0xA0;
6023 else if (pAd->Antenna.field.TxPath == 2)
6024 RFValue |= 0x80;
6025 if (pAd->Antenna.field.RxPath == 1)
6026 RFValue |= 0x50;
6027 else if (pAd->Antenna.field.RxPath == 2)
6028 RFValue |= 0x40;
6029 RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
6030
6031 // Set RF offset
6032 RT30xxReadRFRegister(pAd, RF_R23, &RFValue);
6033 RFValue = (RFValue & 0x80) | pAd->RfFreqOffset;
6034 RT30xxWriteRFRegister(pAd, RF_R23, RFValue);
6035#endif
6036
6037 // Set BW
6038 if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
6039 {
6040 RFValue = pAd->Mlme.CaliBW40RfR24;
6041 //DISABLE_11N_CHECK(pAd);
6042 }
6043 else
6044 {
6045 RFValue = pAd->Mlme.CaliBW20RfR24;
6046 }
6047#ifndef RT30xx
6048 RT30xxWriteRFRegister(pAd, RF_R24, (UCHAR)RFValue);
6049
6050 // Enable RF tuning
6051 RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)&RFValue);
6052 RFValue = RFValue | 0x1;
6053 RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue);
6054
6055 // latch channel for future usage.
6056 pAd->LatchRfRegs.Channel = Channel;
6057#endif
6058#ifdef RT30xx
6059 RT30xxWriteRFRegister(pAd, RF_R24, RFValue);
6060 RT30xxWriteRFRegister(pAd, RF_R31, RFValue);
6061
6062 // Enable RF tuning
6063 RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
6064 RFValue = RFValue | 0x1;
6065 RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
6066
6067 // latch channel for future usage.
6068 pAd->LatchRfRegs.Channel = Channel;
6069
6070 DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
6071 Channel,
6072 pAd->RfIcType,
6073 TxPwer,
6074 TxPwer2,
6075 pAd->Antenna.field.TxPath,
6076 FreqItems3020[index].N,
6077 FreqItems3020[index].K,
6078 FreqItems3020[index].R));
6079#endif
6080
6081 break;
6082 }
6083 }
6084
6085#ifndef RT30xx
6086 DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
6087 Channel,
6088 pAd->RfIcType,
6089 TxPwer,
6090 TxPwer2,
6091 pAd->Antenna.field.TxPath,
6092 FreqItems3020[index].N,
6093 FreqItems3020[index].K,
6094 FreqItems3020[index].R));
6095#endif
6096 }
6097 else
6098#endif // RT2870 //
5441 { 6099 {
5442 RFRegTable = RF2850RegTable; 6100 RFRegTable = RF2850RegTable;
5443 6101
@@ -5691,6 +6349,53 @@ VOID AsicAntennaSelect(
5691 IN PRTMP_ADAPTER pAd, 6349 IN PRTMP_ADAPTER pAd,
5692 IN UCHAR Channel) 6350 IN UCHAR Channel)
5693{ 6351{
6352#ifdef RT30xx
6353 if (pAd->Mlme.OneSecPeriodicRound % 2 == 1)
6354 {
6355 // patch for AsicSetRxAnt failed
6356 pAd->RxAnt.EvaluatePeriod = 0;
6357
6358 // check every 2 second. If rcv-beacon less than 5 in the past 2 second, then AvgRSSI is no longer a
6359 // valid indication of the distance between this AP and its clients.
6360 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED))
6361 {
6362 SHORT realavgrssi1;
6363
6364 // if no traffic then reset average rssi to trigger evaluation
6365 if (pAd->StaCfg.NumOfAvgRssiSample < 5)
6366 {
6367 pAd->RxAnt.Pair1LastAvgRssi = (-99);
6368 pAd->RxAnt.Pair2LastAvgRssi = (-99);
6369 DBGPRINT(RT_DEBUG_TRACE, ("MlmePeriodicExec: no traffic/beacon, reset RSSI\n"));
6370 }
6371
6372 pAd->StaCfg.NumOfAvgRssiSample = 0;
6373 realavgrssi1 = (pAd->RxAnt.Pair1AvgRssi[pAd->RxAnt.Pair1PrimaryRxAnt] >> 3);
6374
6375 DBGPRINT(RT_DEBUG_TRACE,("Ant-realrssi0(%d), Lastrssi0(%d), EvaluateStableCnt=%d\n", realavgrssi1, pAd->RxAnt.Pair1LastAvgRssi, pAd->RxAnt.EvaluateStableCnt));
6376
6377 // if the difference between two rssi is larger or less than 5, then evaluate the other antenna
6378 if ((pAd->RxAnt.EvaluateStableCnt < 2) || (realavgrssi1 > (pAd->RxAnt.Pair1LastAvgRssi + 5)) || (realavgrssi1 < (pAd->RxAnt.Pair1LastAvgRssi - 5)))
6379 {
6380 pAd->RxAnt.Pair1LastAvgRssi = realavgrssi1;
6381 AsicEvaluateRxAnt(pAd);
6382 }
6383 }
6384 else
6385 {
6386 // if not connected, always switch antenna to try to connect
6387 UCHAR temp;
6388
6389 temp = pAd->RxAnt.Pair1PrimaryRxAnt;
6390 pAd->RxAnt.Pair1PrimaryRxAnt = pAd->RxAnt.Pair1SecondaryRxAnt;
6391 pAd->RxAnt.Pair1SecondaryRxAnt = temp;
6392
6393 DBGPRINT(RT_DEBUG_TRACE, ("MlmePeriodicExec: no connect, switch to another one to try connection\n"));
6394
6395 AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
6396 }
6397 }
6398#endif /* RT30xx */
5694} 6399}
5695 6400
5696/* 6401/*
@@ -5760,11 +6465,13 @@ VOID AsicAdjustTxPower(
5760 ULONG TxPwr[5]; 6465 ULONG TxPwr[5];
5761 CHAR Value; 6466 CHAR Value;
5762 6467
6468#ifdef RT2860
5763 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) 6469 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)
5764 || (pAd->bPCIclkOff == TRUE) 6470 || (pAd->bPCIclkOff == TRUE)
5765 || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF) 6471 || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF)
5766 || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS)) 6472 || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS))
5767 return; 6473 return;
6474#endif
5768 6475
5769 if (pAd->CommonCfg.BBPCurrentBW == BW_40) 6476 if (pAd->CommonCfg.BBPCurrentBW == BW_40)
5770 { 6477 {
@@ -6020,10 +6727,20 @@ VOID AsicForceSleep(
6020 */ 6727 */
6021VOID AsicForceWakeup( 6728VOID AsicForceWakeup(
6022 IN PRTMP_ADAPTER pAd, 6729 IN PRTMP_ADAPTER pAd,
6730#ifdef RT2860
6023 IN UCHAR Level) 6731 IN UCHAR Level)
6732#endif
6733#ifdef RT2870
6734 IN BOOLEAN bFromTx)
6735#endif
6024{ 6736{
6025 DBGPRINT(RT_DEBUG_TRACE, ("--> AsicForceWakeup \n")); 6737 DBGPRINT(RT_DEBUG_TRACE, ("--> AsicForceWakeup \n"));
6738#ifdef RT2860
6026 RT28XX_STA_FORCE_WAKEUP(pAd, Level); 6739 RT28XX_STA_FORCE_WAKEUP(pAd, Level);
6740#endif
6741#ifdef RT2870
6742 RT28XX_STA_FORCE_WAKEUP(pAd, bFromTx);
6743#endif
6027} 6744}
6028 6745
6029/* 6746/*
@@ -6234,6 +6951,7 @@ VOID AsicEnableIbssSync(
6234 csr9.field.bTsfTicking = 0; 6951 csr9.field.bTsfTicking = 0;
6235 RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr9.word); 6952 RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr9.word);
6236 6953
6954#ifdef RT2860
6237 // move BEACON TXD and frame content to on-chip memory 6955 // move BEACON TXD and frame content to on-chip memory
6238 ptr = (PUCHAR)&pAd->BeaconTxWI; 6956 ptr = (PUCHAR)&pAd->BeaconTxWI;
6239 for (i=0; i<TXWI_SIZE; i+=4) // 16-byte TXWI field 6957 for (i=0; i<TXWI_SIZE; i+=4) // 16-byte TXWI field
@@ -6251,6 +6969,24 @@ VOID AsicEnableIbssSync(
6251 RTMP_IO_WRITE32(pAd, HW_BEACON_BASE0 + TXWI_SIZE + i, longptr); 6969 RTMP_IO_WRITE32(pAd, HW_BEACON_BASE0 + TXWI_SIZE + i, longptr);
6252 ptr +=4; 6970 ptr +=4;
6253 } 6971 }
6972#endif
6973#ifdef RT2870
6974 // move BEACON TXD and frame content to on-chip memory
6975 ptr = (PUCHAR)&pAd->BeaconTxWI;
6976 for (i=0; i<TXWI_SIZE; i+=2) // 16-byte TXWI field
6977 {
6978 RTUSBMultiWrite(pAd, HW_BEACON_BASE0 + i, ptr, 2);
6979 ptr += 2;
6980 }
6981
6982 // start right after the 16-byte TXWI field
6983 ptr = pAd->BeaconBuf;
6984 for (i=0; i< pAd->BeaconTxWI.MPDUtotalByteCount; i+=2)
6985 {
6986 RTUSBMultiWrite(pAd, HW_BEACON_BASE0 + TXWI_SIZE + i, ptr, 2);
6987 ptr +=2;
6988 }
6989#endif // RT2870 //
6254 6990
6255 // start sending BEACON 6991 // start sending BEACON
6256 csr9.field.BeaconInterval = pAd->CommonCfg.BeaconPeriod << 4; // ASIC register in units of 1/16 TU 6992 csr9.field.BeaconInterval = pAd->CommonCfg.BeaconPeriod << 4; // ASIC register in units of 1/16 TU
@@ -6406,13 +7142,21 @@ VOID AsicSetEdcaParm(
6406 Ac2Cfg.field.Aifsn -= 1; 7142 Ac2Cfg.field.Aifsn -= 1;
6407 7143
6408 // Tuning for TGn Wi-Fi 5.2.32 7144 // Tuning for TGn Wi-Fi 5.2.32
6409 // STA TestBed changes in this item: conexant legacy sta ==> broadcom 11n sta 7145 // STA TestBed changes in this item: connexant legacy sta ==> broadcom 11n sta
6410 if (STA_TGN_WIFI_ON(pAd) && 7146 if (STA_TGN_WIFI_ON(pAd) &&
6411 pEdcaParm->Aifsn[QID_AC_VI] == 10) 7147 pEdcaParm->Aifsn[QID_AC_VI] == 10)
6412 { 7148 {
6413 Ac0Cfg.field.Aifsn = 3; 7149 Ac0Cfg.field.Aifsn = 3;
6414 Ac2Cfg.field.AcTxop = 5; 7150 Ac2Cfg.field.AcTxop = 5;
6415 } 7151 }
7152
7153#ifdef RT30xx
7154 if (pAd->RfIcType == RFIC_3020 || pAd->RfIcType == RFIC_2020)
7155 {
7156 // Tuning for WiFi WMM S3-T07: connexant legacy sta ==> broadcom 11n sta.
7157 Ac2Cfg.field.Aifsn = 5;
7158 }
7159#endif // RT30xx //
6416 } 7160 }
6417 7161
6418 Ac3Cfg.field.AcTxop = pEdcaParm->Txop[QID_AC_VO]; 7162 Ac3Cfg.field.AcTxop = pEdcaParm->Txop[QID_AC_VO];
@@ -6479,16 +7223,24 @@ VOID AsicSetEdcaParm(
6479 AifsnCsr.field.Aifsn2 = Ac2Cfg.field.Aifsn - 4; 7223 AifsnCsr.field.Aifsn2 = Ac2Cfg.field.Aifsn - 4;
6480 7224
6481 // Tuning for TGn Wi-Fi 5.2.32 7225 // Tuning for TGn Wi-Fi 5.2.32
6482 // STA TestBed changes in this item: conexant legacy sta ==> broadcom 11n sta 7226 // STA TestBed changes in this item: connexant legacy sta ==> broadcom 11n sta
6483 if (STA_TGN_WIFI_ON(pAd) && 7227 if (STA_TGN_WIFI_ON(pAd) &&
6484 pEdcaParm->Aifsn[QID_AC_VI] == 10) 7228 pEdcaParm->Aifsn[QID_AC_VI] == 10)
6485 { 7229 {
6486 AifsnCsr.field.Aifsn0 = 3; 7230 AifsnCsr.field.Aifsn0 = 3;
6487 AifsnCsr.field.Aifsn2 = 7; 7231 AifsnCsr.field.Aifsn2 = 7;
6488 } 7232 }
7233#ifdef RT2870
7234 if (INFRA_ON(pAd))
7235 CLIENT_STATUS_SET_FLAG(&pAd->MacTab.Content[BSSID_WCID], fCLIENT_STATUS_WMM_CAPABLE);
7236#endif
6489 } 7237 }
6490 7238
6491 AifsnCsr.field.Aifsn3 = Ac3Cfg.field.Aifsn - 1; //pEdcaParm->Aifsn[QID_AC_VO]; //for TGn wifi test 7239 AifsnCsr.field.Aifsn3 = Ac3Cfg.field.Aifsn - 1; //pEdcaParm->Aifsn[QID_AC_VO]; //for TGn wifi test
7240#ifdef RT30xx
7241 if (pAd->RfIcType == RFIC_3020 || pAd->RfIcType == RFIC_2020)
7242 AifsnCsr.field.Aifsn2 = 0x2; //pEdcaParm->Aifsn[QID_AC_VI]; //for WiFi WMM S4-T04.
7243#endif // RT30xx //
6492 7244
6493 RTMP_IO_WRITE32(pAd, WMM_AIFSN_CFG, AifsnCsr.word); 7245 RTMP_IO_WRITE32(pAd, WMM_AIFSN_CFG, AifsnCsr.word);
6494 7246
@@ -6551,6 +7303,7 @@ VOID AsicSetSlotTime(
6551 SlotTime = (bUseShortSlotTime)? 9 : 20; 7303 SlotTime = (bUseShortSlotTime)? 9 : 20;
6552 7304
6553 { 7305 {
7306#ifndef RT30xx
6554 // force using short SLOT time for FAE to demo performance when TxBurst is ON 7307 // force using short SLOT time for FAE to demo performance when TxBurst is ON
6555 if (((pAd->StaActive.SupportedPhyInfo.bHtEnable == FALSE) && (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED))) 7308 if (((pAd->StaActive.SupportedPhyInfo.bHtEnable == FALSE) && (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED)))
6556 || ((pAd->StaActive.SupportedPhyInfo.bHtEnable == TRUE) && (pAd->CommonCfg.BACapability.field.Policy == BA_NOTUSE)) 7309 || ((pAd->StaActive.SupportedPhyInfo.bHtEnable == TRUE) && (pAd->CommonCfg.BACapability.field.Policy == BA_NOTUSE))
@@ -6560,6 +7313,10 @@ VOID AsicSetSlotTime(
6560 // And we will not set to short slot when bEnableTxBurst is TRUE. 7313 // And we will not set to short slot when bEnableTxBurst is TRUE.
6561 } 7314 }
6562 else if (pAd->CommonCfg.bEnableTxBurst) 7315 else if (pAd->CommonCfg.bEnableTxBurst)
7316#endif
7317#ifdef RT30xx
7318 if (pAd->CommonCfg.bEnableTxBurst)
7319#endif
6563 SlotTime = 9; 7320 SlotTime = 9;
6564 } 7321 }
6565 7322
@@ -6600,7 +7357,9 @@ VOID AsicAddSharedKeyEntry(
6600{ 7357{
6601 ULONG offset; //, csr0; 7358 ULONG offset; //, csr0;
6602 SHAREDKEY_MODE_STRUC csr1; 7359 SHAREDKEY_MODE_STRUC csr1;
7360#ifdef RT2860
6603 INT i; 7361 INT i;
7362#endif
6604 7363
6605 DBGPRINT(RT_DEBUG_TRACE, ("AsicAddSharedKeyEntry BssIndex=%d, KeyIdx=%d\n", BssIndex,KeyIdx)); 7364 DBGPRINT(RT_DEBUG_TRACE, ("AsicAddSharedKeyEntry BssIndex=%d, KeyIdx=%d\n", BssIndex,KeyIdx));
6606//============================================================================================ 7365//============================================================================================
@@ -6622,28 +7381,43 @@ VOID AsicAddSharedKeyEntry(
6622 // 7381 //
6623 // fill key material - key + TX MIC + RX MIC 7382 // fill key material - key + TX MIC + RX MIC
6624 // 7383 //
7384
6625 offset = SHARED_KEY_TABLE_BASE + (4*BssIndex + KeyIdx)*HW_KEY_ENTRY_SIZE; 7385 offset = SHARED_KEY_TABLE_BASE + (4*BssIndex + KeyIdx)*HW_KEY_ENTRY_SIZE;
7386#ifdef RT2860
6626 for (i=0; i<MAX_LEN_OF_SHARE_KEY; i++) 7387 for (i=0; i<MAX_LEN_OF_SHARE_KEY; i++)
6627 { 7388 {
6628 RTMP_IO_WRITE8(pAd, offset + i, pKey[i]); 7389 RTMP_IO_WRITE8(pAd, offset + i, pKey[i]);
6629 } 7390 }
6630 7391#endif
7392#ifdef RT2870
7393 RTUSBMultiWrite(pAd, offset, pKey, MAX_LEN_OF_SHARE_KEY);
7394#endif
6631 offset += MAX_LEN_OF_SHARE_KEY; 7395 offset += MAX_LEN_OF_SHARE_KEY;
6632 if (pTxMic) 7396 if (pTxMic)
6633 { 7397 {
7398#ifdef RT2860
6634 for (i=0; i<8; i++) 7399 for (i=0; i<8; i++)
6635 { 7400 {
6636 RTMP_IO_WRITE8(pAd, offset + i, pTxMic[i]); 7401 RTMP_IO_WRITE8(pAd, offset + i, pTxMic[i]);
6637 } 7402 }
7403#endif
7404#ifdef RT2870
7405 RTUSBMultiWrite(pAd, offset, pTxMic, 8);
7406#endif
6638 } 7407 }
6639 7408
6640 offset += 8; 7409 offset += 8;
6641 if (pRxMic) 7410 if (pRxMic)
6642 { 7411 {
7412#ifdef RT2860
6643 for (i=0; i<8; i++) 7413 for (i=0; i<8; i++)
6644 { 7414 {
6645 RTMP_IO_WRITE8(pAd, offset + i, pRxMic[i]); 7415 RTMP_IO_WRITE8(pAd, offset + i, pRxMic[i]);
6646 } 7416 }
7417#endif
7418#ifdef RT2870
7419 RTUSBMultiWrite(pAd, offset, pRxMic, 8);
7420#endif
6647 } 7421 }
6648 7422
6649 7423
@@ -6819,7 +7593,9 @@ VOID AsicAddKeyEntry(
6819 PUCHAR pTxtsc = pCipherKey->TxTsc; 7593 PUCHAR pTxtsc = pCipherKey->TxTsc;
6820 UCHAR CipherAlg = pCipherKey->CipherAlg; 7594 UCHAR CipherAlg = pCipherKey->CipherAlg;
6821 SHAREDKEY_MODE_STRUC csr1; 7595 SHAREDKEY_MODE_STRUC csr1;
7596#ifdef RT2860
6822 UCHAR i; 7597 UCHAR i;
7598#endif
6823 7599
6824 DBGPRINT(RT_DEBUG_TRACE, ("==> AsicAddKeyEntry\n")); 7600 DBGPRINT(RT_DEBUG_TRACE, ("==> AsicAddKeyEntry\n"));
6825 // 7601 //
@@ -6834,10 +7610,15 @@ VOID AsicAddKeyEntry(
6834 // 2.) Set Key to Asic 7610 // 2.) Set Key to Asic
6835 // 7611 //
6836 //for (i = 0; i < KeyLen; i++) 7612 //for (i = 0; i < KeyLen; i++)
7613#ifdef RT2860
6837 for (i = 0; i < MAX_LEN_OF_PEER_KEY; i++) 7614 for (i = 0; i < MAX_LEN_OF_PEER_KEY; i++)
6838 { 7615 {
6839 RTMP_IO_WRITE8(pAd, offset + i, pKey[i]); 7616 RTMP_IO_WRITE8(pAd, offset + i, pKey[i]);
6840 } 7617 }
7618#endif
7619#ifdef RT2870
7620 RTUSBMultiWrite(pAd, offset, pKey, MAX_LEN_OF_PEER_KEY);
7621#endif
6841 offset += MAX_LEN_OF_PEER_KEY; 7622 offset += MAX_LEN_OF_PEER_KEY;
6842 7623
6843 // 7624 //
@@ -6845,19 +7626,29 @@ VOID AsicAddKeyEntry(
6845 // 7626 //
6846 if (pTxMic) 7627 if (pTxMic)
6847 { 7628 {
7629#ifdef RT2860
6848 for (i = 0; i < 8; i++) 7630 for (i = 0; i < 8; i++)
6849 { 7631 {
6850 RTMP_IO_WRITE8(pAd, offset + i, pTxMic[i]); 7632 RTMP_IO_WRITE8(pAd, offset + i, pTxMic[i]);
6851 } 7633 }
7634#endif
7635#ifdef RT2870
7636 RTUSBMultiWrite(pAd, offset, pTxMic, 8);
7637#endif
6852 } 7638 }
6853 offset += LEN_TKIP_TXMICK; 7639 offset += LEN_TKIP_TXMICK;
6854 7640
6855 if (pRxMic) 7641 if (pRxMic)
6856 { 7642 {
7643#ifdef RT2860
6857 for (i = 0; i < 8; i++) 7644 for (i = 0; i < 8; i++)
6858 { 7645 {
6859 RTMP_IO_WRITE8(pAd, offset + i, pRxMic[i]); 7646 RTMP_IO_WRITE8(pAd, offset + i, pRxMic[i]);
6860 } 7647 }
7648#endif
7649#ifdef RT2870
7650 RTUSBMultiWrite(pAd, offset, pRxMic, 8);
7651#endif
6861 } 7652 }
6862 7653
6863 7654
@@ -6867,6 +7658,7 @@ VOID AsicAddKeyEntry(
6867 // 7658 //
6868 if (bTxKey) 7659 if (bTxKey)
6869 { 7660 {
7661#ifdef RT2860
6870 offset = MAC_IVEIV_TABLE_BASE + (WCID * HW_IVEIV_ENTRY_SIZE); 7662 offset = MAC_IVEIV_TABLE_BASE + (WCID * HW_IVEIV_ENTRY_SIZE);
6871 // 7663 //
6872 // Write IV 7664 // Write IV
@@ -6890,6 +7682,26 @@ VOID AsicAddKeyEntry(
6890 RTMP_IO_WRITE8(pAd, offset + i, pTxtsc[i + 2]); 7682 RTMP_IO_WRITE8(pAd, offset + i, pTxtsc[i + 2]);
6891 } 7683 }
6892 7684
7685#endif
7686#ifdef RT2870
7687 UINT32 tmpVal;
7688
7689 //
7690 // Write IV
7691 //
7692 IV4 = (KeyIdx << 6);
7693 if ((CipherAlg == CIPHER_TKIP) || (CipherAlg == CIPHER_TKIP_NO_MIC) ||(CipherAlg == CIPHER_AES))
7694 IV4 |= 0x20; // turn on extension bit means EIV existence
7695
7696 tmpVal = pTxtsc[1] + (((pTxtsc[1] | 0x20) & 0x7f) << 8) + (pTxtsc[0] << 16) + (IV4 << 24);
7697 RTMP_IO_WRITE32(pAd, offset, tmpVal);
7698
7699 //
7700 // Write EIV
7701 //
7702 offset += 4;
7703 RTMP_IO_WRITE32(pAd, offset, *(PUINT32)&pCipherKey->TxTsc[2]);
7704#endif // RT2870 //
6893 AsicUpdateWCIDAttribute(pAd, WCID, BssIndex, CipherAlg, bUsePairewiseKeyTable); 7705 AsicUpdateWCIDAttribute(pAd, WCID, BssIndex, CipherAlg, bUsePairewiseKeyTable);
6894 } 7706 }
6895 7707
@@ -6954,10 +7766,15 @@ VOID AsicAddPairwiseKeyEntry(
6954 7766
6955 // EKEY 7767 // EKEY
6956 offset = PAIRWISE_KEY_TABLE_BASE + (WCID * HW_KEY_ENTRY_SIZE); 7768 offset = PAIRWISE_KEY_TABLE_BASE + (WCID * HW_KEY_ENTRY_SIZE);
7769#ifdef RT2860
6957 for (i=0; i<MAX_LEN_OF_PEER_KEY; i++) 7770 for (i=0; i<MAX_LEN_OF_PEER_KEY; i++)
6958 { 7771 {
6959 RTMP_IO_WRITE8(pAd, offset + i, pKey[i]); 7772 RTMP_IO_WRITE8(pAd, offset + i, pKey[i]);
6960 } 7773 }
7774#endif
7775#ifdef RT2870
7776 RTUSBMultiWrite(pAd, offset, &pCipherKey->Key[0], MAX_LEN_OF_PEER_KEY);
7777#endif // RT2870 //
6961 for (i=0; i<MAX_LEN_OF_PEER_KEY; i+=4) 7778 for (i=0; i<MAX_LEN_OF_PEER_KEY; i+=4)
6962 { 7779 {
6963 UINT32 Value; 7780 UINT32 Value;
@@ -6969,18 +7786,28 @@ VOID AsicAddPairwiseKeyEntry(
6969 // MIC KEY 7786 // MIC KEY
6970 if (pTxMic) 7787 if (pTxMic)
6971 { 7788 {
7789#ifdef RT2860
6972 for (i=0; i<8; i++) 7790 for (i=0; i<8; i++)
6973 { 7791 {
6974 RTMP_IO_WRITE8(pAd, offset+i, pTxMic[i]); 7792 RTMP_IO_WRITE8(pAd, offset+i, pTxMic[i]);
6975 } 7793 }
7794#endif
7795#ifdef RT2870
7796 RTUSBMultiWrite(pAd, offset, &pCipherKey->TxMic[0], 8);
7797#endif // RT2870 //
6976 } 7798 }
6977 offset += 8; 7799 offset += 8;
6978 if (pRxMic) 7800 if (pRxMic)
6979 { 7801 {
7802#ifdef RT2860
6980 for (i=0; i<8; i++) 7803 for (i=0; i<8; i++)
6981 { 7804 {
6982 RTMP_IO_WRITE8(pAd, offset+i, pRxMic[i]); 7805 RTMP_IO_WRITE8(pAd, offset+i, pRxMic[i]);
6983 } 7806 }
7807#endif
7808#ifdef RT2870
7809 RTUSBMultiWrite(pAd, offset, &pCipherKey->RxMic[0], 8);
7810#endif // RT2870 //
6984 } 7811 }
6985 7812
6986 DBGPRINT(RT_DEBUG_TRACE,("AsicAddPairwiseKeyEntry: WCID #%d Alg=%s\n",WCID, CipherName[CipherAlg])); 7813 DBGPRINT(RT_DEBUG_TRACE,("AsicAddPairwiseKeyEntry: WCID #%d Alg=%s\n",WCID, CipherName[CipherAlg]));
@@ -7042,6 +7869,7 @@ BOOLEAN AsicSendCommandToMcu(
7042 if (i >= 100) 7869 if (i >= 100)
7043 { 7870 {
7044 { 7871 {
7872#ifdef RT2860
7045 UINT32 Data; 7873 UINT32 Data;
7046 7874
7047 // Reset DMA 7875 // Reset DMA
@@ -7063,9 +7891,13 @@ BOOLEAN AsicSendCommandToMcu(
7063 RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &Data); 7891 RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &Data);
7064 Data &= 0xfffffffd; 7892 Data &= 0xfffffffd;
7065 RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, Data); 7893 RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, Data);
7894#endif /* RT2860 */
7066 DBGPRINT_ERR(("H2M_MAILBOX still hold by MCU. command fail\n")); 7895 DBGPRINT_ERR(("H2M_MAILBOX still hold by MCU. command fail\n"));
7067 } 7896 }
7068 //return FALSE; 7897 //return FALSE;
7898#ifdef RT2870
7899 return FALSE;
7900#endif
7069 } 7901 }
7070 7902
7071 H2MMailbox.field.Owner = 1; // pass ownership to MCU 7903 H2MMailbox.field.Owner = 1; // pass ownership to MCU
@@ -7085,6 +7917,7 @@ BOOLEAN AsicSendCommandToMcu(
7085 return TRUE; 7917 return TRUE;
7086} 7918}
7087 7919
7920#ifdef RT2860
7088BOOLEAN AsicCheckCommanOk( 7921BOOLEAN AsicCheckCommanOk(
7089 IN PRTMP_ADAPTER pAd, 7922 IN PRTMP_ADAPTER pAd,
7090 IN UCHAR Command) 7923 IN UCHAR Command)
@@ -7149,6 +7982,7 @@ BOOLEAN AsicCheckCommanOk(
7149 7982
7150 return FALSE; 7983 return FALSE;
7151} 7984}
7985#endif /* RT8260 */
7152 7986
7153/* 7987/*
7154 ======================================================================== 7988 ========================================================================
@@ -7497,6 +8331,58 @@ CHAR RTMPMaxRssi(
7497 return larger; 8331 return larger;
7498} 8332}
7499 8333
8334#ifdef RT30xx
8335// Antenna divesity use GPIO3 and EESK pin for control
8336// Antenna and EEPROM access are both using EESK pin,
8337// Therefor we should avoid accessing EESK at the same time
8338// Then restore antenna after EEPROM access
8339VOID AsicSetRxAnt(
8340 IN PRTMP_ADAPTER pAd,
8341 IN UCHAR Ant)
8342{
8343#ifdef RT30xx
8344 UINT32 Value;
8345 UINT32 x;
8346
8347 if ((pAd->EepromAccess) ||
8348 (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) ||
8349 (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) ||
8350 (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) ||
8351 (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
8352 {
8353 return;
8354 }
8355
8356 // the antenna selection is through firmware and MAC register(GPIO3)
8357 if (Ant == 0)
8358 {
8359 // Main antenna
8360 RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
8361 x |= (EESK);
8362 RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
8363
8364 RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
8365 Value &= ~(0x0808);
8366 RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
8367 DBGPRINT_RAW(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to main antenna\n"));
8368 }
8369 else
8370 {
8371 // Aux antenna
8372 RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
8373 x &= ~(EESK);
8374 RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
8375
8376 RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
8377 Value &= ~(0x0808);
8378 Value |= 0x08;
8379 RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
8380 DBGPRINT_RAW(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to aux antenna\n"));
8381 }
8382#endif // RT30xx //
8383}
8384#endif /* RT30xx */
8385
7500/* 8386/*
7501 ======================================================================== 8387 ========================================================================
7502 Routine Description: 8388 Routine Description:
@@ -7515,6 +8401,7 @@ VOID AsicEvaluateRxAnt(
7515{ 8401{
7516 UCHAR BBPR3 = 0; 8402 UCHAR BBPR3 = 0;
7517 8403
8404#ifndef RT30xx
7518 { 8405 {
7519 if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS | 8406 if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS |
7520 fRTMP_ADAPTER_HALT_IN_PROGRESS | 8407 fRTMP_ADAPTER_HALT_IN_PROGRESS |
@@ -7543,7 +8430,92 @@ VOID AsicEvaluateRxAnt(
7543 } 8430 }
7544 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3); 8431 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3);
7545 8432
8433#ifdef RT2860
7546 pAd->StaCfg.BBPR3 = BBPR3; 8434 pAd->StaCfg.BBPR3 = BBPR3;
8435#endif
8436#ifdef RT2870
8437 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)
8438 )
8439 {
8440 ULONG TxTotalCnt = pAd->RalinkCounters.OneSecTxNoRetryOkCount +
8441 pAd->RalinkCounters.OneSecTxRetryOkCount +
8442 pAd->RalinkCounters.OneSecTxFailCount;
8443
8444 if (TxTotalCnt > 50)
8445 {
8446 RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 20);
8447 pAd->Mlme.bLowThroughput = FALSE;
8448 }
8449 else
8450 {
8451 RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 300);
8452 pAd->Mlme.bLowThroughput = TRUE;
8453 }
8454 }
8455#endif
8456#endif /* RT30xx */
8457#ifdef RT30xx
8458 if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS |
8459 fRTMP_ADAPTER_HALT_IN_PROGRESS |
8460 fRTMP_ADAPTER_RADIO_OFF |
8461 fRTMP_ADAPTER_NIC_NOT_EXIST |
8462 fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS) ||
8463 OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)
8464#ifdef RT30xx
8465 || (pAd->EepromAccess)
8466#endif // RT30xx //
8467 )
8468 return;
8469
8470
8471 {
8472 //if (pAd->StaCfg.Psm == PWR_SAVE)
8473 // return;
8474 }
8475
8476 // two antenna selection mechanism- one is antenna diversity, the other is failed antenna remove
8477 // one is antenna diversity:there is only one antenna can rx and tx
8478 // the other is failed antenna remove:two physical antenna can rx and tx
8479 if (pAd->NicConfig2.field.AntDiversity)
8480 {
8481 DBGPRINT(RT_DEBUG_TRACE,("AntDiv - before evaluate Pair1-Ant (%d,%d)\n",
8482 pAd->RxAnt.Pair1PrimaryRxAnt, pAd->RxAnt.Pair1SecondaryRxAnt));
8483
8484 AsicSetRxAnt(pAd, pAd->RxAnt.Pair1SecondaryRxAnt);
8485
8486 pAd->RxAnt.EvaluatePeriod = 1; // 1:Means switch to SecondaryRxAnt, 0:Means switch to Pair1PrimaryRxAnt
8487 pAd->RxAnt.FirstPktArrivedWhenEvaluate = FALSE;
8488 pAd->RxAnt.RcvPktNumWhenEvaluate = 0;
8489
8490 // a one-shot timer to end the evalution
8491 // dynamic adjust antenna evaluation period according to the traffic
8492 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED))
8493 RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 100);
8494 else
8495 RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 300);
8496 }
8497 else
8498 {
8499 if (pAd->StaCfg.Psm == PWR_SAVE)
8500 return;
8501
8502 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPR3);
8503 BBPR3 &= (~0x18);
8504 if(pAd->Antenna.field.RxPath == 3)
8505 {
8506 BBPR3 |= (0x10);
8507 }
8508 else if(pAd->Antenna.field.RxPath == 2)
8509 {
8510 BBPR3 |= (0x8);
8511 }
8512 else if(pAd->Antenna.field.RxPath == 1)
8513 {
8514 BBPR3 |= (0x0);
8515 }
8516 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3);
8517 }
8518#endif /* RT30xx */
7547 8519
7548 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED) 8520 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)
7549 ) 8521 )
@@ -7552,6 +8524,7 @@ VOID AsicEvaluateRxAnt(
7552 pAd->RalinkCounters.OneSecTxRetryOkCount + 8524 pAd->RalinkCounters.OneSecTxRetryOkCount +
7553 pAd->RalinkCounters.OneSecTxFailCount; 8525 pAd->RalinkCounters.OneSecTxFailCount;
7554 8526
8527 // dynamic adjust antenna evaluation period according to the traffic
7555 if (TxTotalCnt > 50) 8528 if (TxTotalCnt > 50)
7556 { 8529 {
7557 RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 20); 8530 RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 20);
@@ -7588,6 +8561,7 @@ VOID AsicRxAntEvalTimeout(
7588 UCHAR BBPR3 = 0; 8561 UCHAR BBPR3 = 0;
7589 CHAR larger = -127, rssi0, rssi1, rssi2; 8562 CHAR larger = -127, rssi0, rssi1, rssi2;
7590 8563
8564#ifndef RT30xx
7591 { 8565 {
7592 if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS) || 8566 if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS) ||
7593 RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS) || 8567 RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS) ||
@@ -7645,8 +8619,111 @@ VOID AsicRxAntEvalTimeout(
7645 BBPR3 |= (0x0); 8619 BBPR3 |= (0x0);
7646 } 8620 }
7647 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3); 8621 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3);
8622#ifdef RT2860
7648 pAd->StaCfg.BBPR3 = BBPR3; 8623 pAd->StaCfg.BBPR3 = BBPR3;
8624#endif
7649 } 8625 }
8626#endif /* RT30xx */
8627#ifdef RT30xx
8628 if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS |
8629 fRTMP_ADAPTER_HALT_IN_PROGRESS |
8630 fRTMP_ADAPTER_RADIO_OFF |
8631 fRTMP_ADAPTER_NIC_NOT_EXIST) ||
8632 OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)
8633#ifdef RT30xx
8634 || (pAd->EepromAccess)
8635#endif // RT30xx //
8636 )
8637 return;
8638
8639 {
8640 //if (pAd->StaCfg.Psm == PWR_SAVE)
8641 // return;
8642
8643 if (pAd->NicConfig2.field.AntDiversity)
8644 {
8645 if ((pAd->RxAnt.RcvPktNumWhenEvaluate != 0) && (pAd->RxAnt.Pair1AvgRssi[pAd->RxAnt.Pair1SecondaryRxAnt] >= pAd->RxAnt.Pair1AvgRssi[pAd->RxAnt.Pair1PrimaryRxAnt]))
8646 {
8647 UCHAR temp;
8648
8649 //
8650 // select PrimaryRxAntPair
8651 // Role change, Used Pair1SecondaryRxAnt as PrimaryRxAntPair.
8652 // Since Pair1SecondaryRxAnt Quality good than Pair1PrimaryRxAnt
8653 //
8654 temp = pAd->RxAnt.Pair1PrimaryRxAnt;
8655 pAd->RxAnt.Pair1PrimaryRxAnt = pAd->RxAnt.Pair1SecondaryRxAnt;
8656 pAd->RxAnt.Pair1SecondaryRxAnt = temp;
8657
8658 pAd->RxAnt.Pair1LastAvgRssi = (pAd->RxAnt.Pair1AvgRssi[pAd->RxAnt.Pair1SecondaryRxAnt] >> 3);
8659 pAd->RxAnt.EvaluateStableCnt = 0;
8660 }
8661 else
8662 {
8663 // if the evaluated antenna is not better than original, switch back to original antenna
8664 AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
8665 pAd->RxAnt.EvaluateStableCnt ++;
8666 }
8667
8668 pAd->RxAnt.EvaluatePeriod = 0; // 1:Means switch to SecondaryRxAnt, 0:Means switch to Pair1PrimaryRxAnt
8669
8670 DBGPRINT(RT_DEBUG_TRACE,("AsicRxAntEvalAction::After Eval(fix in #%d), <%d, %d>, RcvPktNumWhenEvaluate=%ld\n",
8671 pAd->RxAnt.Pair1PrimaryRxAnt, (pAd->RxAnt.Pair1AvgRssi[0] >> 3), (pAd->RxAnt.Pair1AvgRssi[1] >> 3), pAd->RxAnt.RcvPktNumWhenEvaluate));
8672 }
8673 else
8674 {
8675 if (pAd->StaCfg.Psm == PWR_SAVE)
8676 return;
8677
8678 // if the traffic is low, use average rssi as the criteria
8679 if (pAd->Mlme.bLowThroughput == TRUE)
8680 {
8681 rssi0 = pAd->StaCfg.RssiSample.LastRssi0;
8682 rssi1 = pAd->StaCfg.RssiSample.LastRssi1;
8683 rssi2 = pAd->StaCfg.RssiSample.LastRssi2;
8684 }
8685 else
8686 {
8687 rssi0 = pAd->StaCfg.RssiSample.AvgRssi0;
8688 rssi1 = pAd->StaCfg.RssiSample.AvgRssi1;
8689 rssi2 = pAd->StaCfg.RssiSample.AvgRssi2;
8690 }
8691
8692 if(pAd->Antenna.field.RxPath == 3)
8693 {
8694 larger = max(rssi0, rssi1);
8695
8696 if (larger > (rssi2 + 20))
8697 pAd->Mlme.RealRxPath = 2;
8698 else
8699 pAd->Mlme.RealRxPath = 3;
8700 }
8701 else if(pAd->Antenna.field.RxPath == 2)
8702 {
8703 if (rssi0 > (rssi1 + 20))
8704 pAd->Mlme.RealRxPath = 1;
8705 else
8706 pAd->Mlme.RealRxPath = 2;
8707 }
8708
8709 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPR3);
8710 BBPR3 &= (~0x18);
8711 if(pAd->Mlme.RealRxPath == 3)
8712 {
8713 BBPR3 |= (0x10);
8714 }
8715 else if(pAd->Mlme.RealRxPath == 2)
8716 {
8717 BBPR3 |= (0x8);
8718 }
8719 else if(pAd->Mlme.RealRxPath == 1)
8720 {
8721 BBPR3 |= (0x0);
8722 }
8723 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3);
8724 }
8725 }
8726#endif /* RT30xx */
7650} 8727}
7651 8728
7652 8729
@@ -7845,7 +8922,12 @@ VOID AsicStaBbpTuning(
7845 && (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED) 8922 && (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)
7846 ) 8923 )
7847 && !(OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) 8924 && !(OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
8925#ifdef RT2860
7848 && (pAd->bPCIclkOff == FALSE)) 8926 && (pAd->bPCIclkOff == FALSE))
8927#endif
8928#ifdef RT2870
8929 )
8930#endif
7849 { 8931 {
7850 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R66, &OrigR66Value); 8932 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R66, &OrigR66Value);
7851 R66 = OrigR66Value; 8933 R66 = OrigR66Value;
@@ -7857,6 +8939,45 @@ VOID AsicStaBbpTuning(
7857 8939
7858 if (pAd->LatchRfRegs.Channel <= 14) 8940 if (pAd->LatchRfRegs.Channel <= 14)
7859 { //BG band 8941 { //BG band
8942#ifdef RT2870
8943 // RT3070 is a no LNA solution, it should have different control regarding to AGC gain control
8944 // Otherwise, it will have some throughput side effect when low RSSI
8945#ifndef RT30xx
8946 if (IS_RT3070(pAd))
8947#endif
8948#ifdef RT30xx
8949 if (IS_RT30xx(pAd))
8950#endif
8951 {
8952 if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
8953 {
8954 R66 = 0x1C + 2*GET_LNA_GAIN(pAd) + 0x20;
8955 if (OrigR66Value != R66)
8956 {
8957#ifndef RT30xx
8958 RTUSBWriteBBPRegister(pAd, BBP_R66, R66);
8959#endif
8960#ifdef RT30xx
8961 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
8962#endif
8963 }
8964 }
8965 else
8966 {
8967 R66 = 0x1C + 2*GET_LNA_GAIN(pAd);
8968 if (OrigR66Value != R66)
8969 {
8970#ifndef RT30xx
8971 RTUSBWriteBBPRegister(pAd, BBP_R66, R66);
8972#endif
8973#ifdef RT30xx
8974 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
8975#endif
8976 }
8977 }
8978 }
8979 else
8980#endif // RT2870 //
7860 { 8981 {
7861 if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) 8982 if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
7862 { 8983 {
@@ -7922,6 +9043,7 @@ VOID AsicStaBbpTuning(
7922 } 9043 }
7923} 9044}
7924 9045
9046#ifdef RT2860
7925VOID AsicResetFromDMABusy( 9047VOID AsicResetFromDMABusy(
7926 IN PRTMP_ADAPTER pAd) 9048 IN PRTMP_ADAPTER pAd)
7927{ 9049{
@@ -8021,6 +9143,7 @@ VOID AsicResetPBF(
8021 DBGPRINT(RT_DEBUG_TRACE, ("<--- Asic HardReset PBF !!!! \n")); 9143 DBGPRINT(RT_DEBUG_TRACE, ("<--- Asic HardReset PBF !!!! \n"));
8022 } 9144 }
8023} 9145}
9146#endif /* RT2860 */
8024 9147
8025VOID RTMPSetAGCInitValue( 9148VOID RTMPSetAGCInitValue(
8026 IN PRTMP_ADAPTER pAd, 9149 IN PRTMP_ADAPTER pAd,
@@ -8059,6 +9182,15 @@ VOID AsicTurnOffRFClk(
8059 UCHAR index; 9182 UCHAR index;
8060 RTMP_RF_REGS *RFRegTable; 9183 RTMP_RF_REGS *RFRegTable;
8061 9184
9185#ifdef RT30xx
9186 // The RF programming sequence is difference between 3xxx and 2xxx
9187 if (IS_RT3090(pAd))
9188 {
9189 RT30xxLoadRFSleepModeSetup(pAd); // add by johnli, RF power sequence setup, load RF sleep-mode setup
9190 }
9191 else
9192 {
9193#endif // RT30xx //
8062 RFRegTable = RF2850RegTable; 9194 RFRegTable = RF2850RegTable;
8063 9195
8064 switch (pAd->RfIcType) 9196 switch (pAd->RfIcType)
@@ -8100,6 +9232,10 @@ VOID AsicTurnOffRFClk(
8100 default: 9232 default:
8101 break; 9233 break;
8102 } 9234 }
9235#ifdef RT30xx
9236 }
9237#endif // RT30xx //
9238
8103} 9239}
8104 9240
8105 9241
@@ -8113,6 +9249,14 @@ VOID AsicTurnOnRFClk(
8113 UCHAR index; 9249 UCHAR index;
8114 RTMP_RF_REGS *RFRegTable; 9250 RTMP_RF_REGS *RFRegTable;
8115 9251
9252#ifdef RT30xx
9253 // The RF programming sequence is difference between 3xxx and 2xxx
9254 if (IS_RT3090(pAd))
9255 {
9256 }
9257 else
9258 {
9259#endif // RT30xx //
8116 RFRegTable = RF2850RegTable; 9260 RFRegTable = RF2850RegTable;
8117 9261
8118 switch (pAd->RfIcType) 9262 switch (pAd->RfIcType)
@@ -8159,9 +9303,14 @@ VOID AsicTurnOnRFClk(
8159 break; 9303 break;
8160 } 9304 }
8161 9305
9306#ifndef RT30xx
8162 DBGPRINT(RT_DEBUG_TRACE, ("AsicTurnOnRFClk#%d(RF=%d, ) , R2=0x%08x\n", 9307 DBGPRINT(RT_DEBUG_TRACE, ("AsicTurnOnRFClk#%d(RF=%d, ) , R2=0x%08x\n",
8163 Channel, 9308 Channel,
8164 pAd->RfIcType, 9309 pAd->RfIcType,
8165 R2)); 9310 R2));
9311#endif
9312#ifdef RT30xx
9313 }
9314#endif // RT30xx //
8166} 9315}
8167 9316
diff --git a/drivers/staging/rt2860/common/rtmp_init.c b/drivers/staging/rt2860/common/rtmp_init.c
index d79877e1e82a..c2facac5cf88 100644
--- a/drivers/staging/rt2860/common/rtmp_init.c
+++ b/drivers/staging/rt2860/common/rtmp_init.c
@@ -38,8 +38,18 @@
38 Jan Lee 2006-09-15 RT2860. Change for 802.11n , EEPROM, Led, BA, HT. 38 Jan Lee 2006-09-15 RT2860. Change for 802.11n , EEPROM, Led, BA, HT.
39*/ 39*/
40#include "../rt_config.h" 40#include "../rt_config.h"
41#include "firmware.h" 41#ifndef RT30xx
42#ifdef RT2860
43#include "firmware.h"
42#include <linux/bitrev.h> 44#include <linux/bitrev.h>
45#endif
46#ifdef RT2870
47#include "../../rt2870/common/firmware.h"
48#endif
49#endif
50#ifdef RT30xx
51#include "../../rt3070/firmware.h"
52#endif
43 53
44UCHAR BIT8[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80}; 54UCHAR BIT8[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
45ULONG BIT32[] = {0x00000001, 0x00000002, 0x00000004, 0x00000008, 55ULONG BIT32[] = {0x00000001, 0x00000002, 0x00000004, 0x00000008,
@@ -90,6 +100,22 @@ const unsigned short ccitt_16Table[] = {
90#define ByteCRC16(v, crc) \ 100#define ByteCRC16(v, crc) \
91 (unsigned short)((crc << 8) ^ ccitt_16Table[((crc >> 8) ^ (v)) & 255]) 101 (unsigned short)((crc << 8) ^ ccitt_16Table[((crc >> 8) ^ (v)) & 255])
92 102
103#ifdef RT2870
104unsigned char BitReverse(unsigned char x)
105{
106 int i;
107 unsigned char Temp=0;
108 for(i=0; ; i++)
109 {
110 if(x & 0x80) Temp |= 0x80;
111 if(i==7) break;
112 x <<= 1;
113 Temp >>= 1;
114 }
115 return Temp;
116}
117#endif
118
93// 119//
94// BBP register initialization set 120// BBP register initialization set
95// 121//
@@ -114,6 +140,38 @@ REG_PAIR BBPRegTable[] = {
114// 140//
115// RF register initialization set 141// RF register initialization set
116// 142//
143#ifdef RT2870
144REG_PAIR RT30xx_RFRegTable[] = {
145 {RF_R04, 0x40},
146 {RF_R05, 0x03},
147 {RF_R06, 0x02},
148 {RF_R07, 0x70},
149 {RF_R09, 0x0F},
150#ifndef RT30xx
151 {RF_R10, 0x71},
152#endif
153#ifdef RT30xx
154 {RF_R10, 0x41},
155#endif
156 {RF_R11, 0x21},
157 {RF_R12, 0x7B},
158 {RF_R14, 0x90},
159 {RF_R15, 0x58},
160 {RF_R16, 0xB3},
161 {RF_R17, 0x92},
162 {RF_R18, 0x2C},
163 {RF_R19, 0x02},
164 {RF_R20, 0xBA},
165 {RF_R21, 0xDB},
166 {RF_R24, 0x16},
167 {RF_R25, 0x01},
168#ifndef RT30xx
169 {RF_R27, 0x03},
170#endif
171 {RF_R29, 0x1F},
172};
173#define NUM_RF_REG_PARMS (sizeof(RT30xx_RFRegTable) / sizeof(REG_PAIR))
174#endif // RT2870 //
117 175
118// 176//
119// ASIC register initialization sets 177// ASIC register initialization sets
@@ -146,10 +204,18 @@ RTMP_REG_PAIR MACRegTable[] = {
146 {AUTO_RSP_CFG, 0x00000013}, // Initial Auto_Responder, because QA will turn off Auto-Responder 204 {AUTO_RSP_CFG, 0x00000013}, // Initial Auto_Responder, because QA will turn off Auto-Responder
147 {CCK_PROT_CFG, 0x05740003 /*0x01740003*/}, // Initial Auto_Responder, because QA will turn off Auto-Responder. And RTS threshold is enabled. 205 {CCK_PROT_CFG, 0x05740003 /*0x01740003*/}, // Initial Auto_Responder, because QA will turn off Auto-Responder. And RTS threshold is enabled.
148 {OFDM_PROT_CFG, 0x05740003 /*0x01740003*/}, // Initial Auto_Responder, because QA will turn off Auto-Responder. And RTS threshold is enabled. 206 {OFDM_PROT_CFG, 0x05740003 /*0x01740003*/}, // Initial Auto_Responder, because QA will turn off Auto-Responder. And RTS threshold is enabled.
207//PS packets use Tx1Q (for HCCA) when dequeue from PS unicast queue (WiFi WPA2 MA9_DT1 for Marvell B STA)
208#ifdef RT2870
209 {PBF_CFG, 0xf40006}, // Only enable Queue 2
210 {MM40_PROT_CFG, 0x3F44084}, // Initial Auto_Responder, because QA will turn off Auto-Responder
211 {WPDMA_GLO_CFG, 0x00000030},
212#endif // RT2870 //
149 {GF20_PROT_CFG, 0x01744004}, // set 19:18 --> Short NAV for MIMO PS 213 {GF20_PROT_CFG, 0x01744004}, // set 19:18 --> Short NAV for MIMO PS
150 {GF40_PROT_CFG, 0x03F44084}, 214 {GF40_PROT_CFG, 0x03F44084},
151 {MM20_PROT_CFG, 0x01744004}, 215 {MM20_PROT_CFG, 0x01744004},
216#ifdef RT2860
152 {MM40_PROT_CFG, 0x03F54084}, 217 {MM40_PROT_CFG, 0x03F54084},
218#endif
153 {TXOP_CTRL_CFG, 0x0000583f, /*0x0000243f*/ /*0x000024bf*/}, //Extension channel backoff. 219 {TXOP_CTRL_CFG, 0x0000583f, /*0x0000243f*/ /*0x000024bf*/}, //Extension channel backoff.
154 {TX_RTS_CFG, 0x00092b20}, 220 {TX_RTS_CFG, 0x00092b20},
155 {EXP_ACK_TIME, 0x002400ca}, // default value 221 {EXP_ACK_TIME, 0x002400ca}, // default value
@@ -172,6 +238,13 @@ RTMP_REG_PAIR STAMACRegTable[] = {
172#define NUM_MAC_REG_PARMS (sizeof(MACRegTable) / sizeof(RTMP_REG_PAIR)) 238#define NUM_MAC_REG_PARMS (sizeof(MACRegTable) / sizeof(RTMP_REG_PAIR))
173#define NUM_STA_MAC_REG_PARMS (sizeof(STAMACRegTable) / sizeof(RTMP_REG_PAIR)) 239#define NUM_STA_MAC_REG_PARMS (sizeof(STAMACRegTable) / sizeof(RTMP_REG_PAIR))
174 240
241#ifdef RT2870
242//
243// RT2870 Firmware Spec only used 1 oct for version expression
244//
245#define FIRMWARE_MINOR_VERSION 7
246
247#endif // RT2870 //
175 248
176// New 8k byte firmware size for RT3071/RT3072 249// New 8k byte firmware size for RT3071/RT3072
177#define FIRMWAREIMAGE_MAX_LENGTH 0x2000 250#define FIRMWAREIMAGE_MAX_LENGTH 0x2000
@@ -181,7 +254,9 @@ RTMP_REG_PAIR STAMACRegTable[] = {
181#define FIRMWAREIMAGEV1_LENGTH 0x1000 254#define FIRMWAREIMAGEV1_LENGTH 0x1000
182#define FIRMWAREIMAGEV2_LENGTH 0x1000 255#define FIRMWAREIMAGEV2_LENGTH 0x1000
183 256
257#ifdef RT2860
184#define FIRMWARE_MINOR_VERSION 2 258#define FIRMWARE_MINOR_VERSION 2
259#endif
185 260
186 261
187/* 262/*
@@ -239,7 +314,9 @@ NDIS_STATUS RTMPAllocAdapterBlock(
239 314
240 // Init spin locks 315 // Init spin locks
241 NdisAllocateSpinLock(&pAd->MgmtRingLock); 316 NdisAllocateSpinLock(&pAd->MgmtRingLock);
317#ifdef RT2860
242 NdisAllocateSpinLock(&pAd->RxRingLock); 318 NdisAllocateSpinLock(&pAd->RxRingLock);
319#endif
243 320
244 for (index =0 ; index < NUM_OF_TX_RING; index++) 321 for (index =0 ; index < NUM_OF_TX_RING; index++)
245 { 322 {
@@ -1005,6 +1082,425 @@ NDIS_STATUS NICReadRegParameters(
1005} 1082}
1006 1083
1007 1084
1085#ifdef RT2870
1086/*
1087 ========================================================================
1088
1089 Routine Description:
1090 For RF filter calibration purpose
1091
1092 Arguments:
1093 pAd Pointer to our adapter
1094
1095 Return Value:
1096 None
1097
1098 IRQL = PASSIVE_LEVEL
1099
1100 ========================================================================
1101*/
1102#ifndef RT30xx
1103VOID RTUSBFilterCalibration(
1104 IN PRTMP_ADAPTER pAd)
1105{
1106 UCHAR R55x = 0, value, FilterTarget = 0x1E, BBPValue;
1107 UINT loop = 0, count = 0, loopcnt = 0, ReTry = 0;
1108 UCHAR RF_R24_Value = 0;
1109
1110 // Give bbp filter initial value
1111 pAd->Mlme.CaliBW20RfR24 = 0x16;
1112 pAd->Mlme.CaliBW40RfR24 = 0x36; //Bit[5] must be 1 for BW 40
1113
1114 do
1115 {
1116 if (loop == 1) //BandWidth = 40 MHz
1117 {
1118 // Write 0x27 to RF_R24 to program filter
1119 RF_R24_Value = 0x27;
1120 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
1121 FilterTarget = 0x19;
1122
1123 // when calibrate BW40, BBP mask must set to BW40.
1124 RTUSBReadBBPRegister(pAd, BBP_R4, &BBPValue);
1125 BBPValue&= (~0x18);
1126 BBPValue|= (0x10);
1127 RTUSBWriteBBPRegister(pAd, BBP_R4, BBPValue);
1128 }
1129 else //BandWidth = 20 MHz
1130 {
1131 // Write 0x07 to RF_R24 to program filter
1132 RF_R24_Value = 0x07;
1133 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
1134 FilterTarget = 0x16;
1135 }
1136
1137 // Write 0x01 to RF_R22 to enable baseband loopback mode
1138 RT30xxReadRFRegister(pAd, RF_R22, &value);
1139 value |= 0x01;
1140 RT30xxWriteRFRegister(pAd, RF_R22, value);
1141
1142 // Write 0x00 to BBP_R24 to set power & frequency of passband test tone
1143 RTUSBWriteBBPRegister(pAd, BBP_R24, 0);
1144
1145 do
1146 {
1147 // Write 0x90 to BBP_R25 to transmit test tone
1148 RTUSBWriteBBPRegister(pAd, BBP_R25, 0x90);
1149
1150 RTMPusecDelay(1000);
1151 // Read BBP_R55[6:0] for received power, set R55x = BBP_R55[6:0]
1152 RTUSBReadBBPRegister(pAd, BBP_R55, &value);
1153 R55x = value & 0xFF;
1154
1155 } while ((ReTry++ < 100) && (R55x == 0));
1156
1157 // Write 0x06 to BBP_R24 to set power & frequency of stopband test tone
1158 RTUSBWriteBBPRegister(pAd, BBP_R24, 0x06);
1159
1160 while(TRUE)
1161 {
1162 // Write 0x90 to BBP_R25 to transmit test tone
1163 RTUSBWriteBBPRegister(pAd, BBP_R25, 0x90);
1164
1165 //We need to wait for calibration
1166 RTMPusecDelay(1000);
1167 RTUSBReadBBPRegister(pAd, BBP_R55, &value);
1168 value &= 0xFF;
1169 if ((R55x - value) < FilterTarget)
1170 {
1171 RF_R24_Value ++;
1172 }
1173 else if ((R55x - value) == FilterTarget)
1174 {
1175 RF_R24_Value ++;
1176 count ++;
1177 }
1178 else
1179 {
1180 break;
1181 }
1182
1183 // prevent infinite loop cause driver hang.
1184 if (loopcnt++ > 100)
1185 {
1186 DBGPRINT(RT_DEBUG_ERROR, ("RTUSBFilterCalibration - can't find a valid value, loopcnt=%d stop calibrating", loopcnt));
1187 break;
1188 }
1189
1190 // Write RF_R24 to program filter
1191 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
1192 }
1193
1194 if (count > 0)
1195 {
1196 RF_R24_Value = RF_R24_Value - ((count) ? (1) : (0));
1197 }
1198
1199 // Store for future usage
1200 if (loopcnt < 100)
1201 {
1202 if (loop++ == 0)
1203 {
1204 //BandWidth = 20 MHz
1205 pAd->Mlme.CaliBW20RfR24 = (UCHAR)RF_R24_Value;
1206 }
1207 else
1208 {
1209 //BandWidth = 40 MHz
1210 pAd->Mlme.CaliBW40RfR24 = (UCHAR)RF_R24_Value;
1211 break;
1212 }
1213 }
1214 else
1215 break;
1216
1217 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
1218
1219 // reset count
1220 count = 0;
1221 } while(TRUE);
1222
1223 //
1224 // Set back to initial state
1225 //
1226 RTUSBWriteBBPRegister(pAd, BBP_R24, 0);
1227
1228 RT30xxReadRFRegister(pAd, RF_R22, &value);
1229 value &= ~(0x01);
1230 RT30xxWriteRFRegister(pAd, RF_R22, value);
1231
1232 // set BBP back to BW20
1233 RTUSBReadBBPRegister(pAd, BBP_R4, &BBPValue);
1234 BBPValue&= (~0x18);
1235 RTUSBWriteBBPRegister(pAd, BBP_R4, BBPValue);
1236
1237 DBGPRINT(RT_DEBUG_TRACE, ("RTUSBFilterCalibration - CaliBW20RfR24=0x%x, CaliBW40RfR24=0x%x\n", pAd->Mlme.CaliBW20RfR24, pAd->Mlme.CaliBW40RfR24));
1238}
1239#endif /* RT30xx */
1240#ifdef RT30xx
1241VOID RTMPFilterCalibration(
1242 IN PRTMP_ADAPTER pAd)
1243{
1244 UCHAR R55x = 0, value, FilterTarget = 0x1E, BBPValue=0;
1245 UINT loop = 0, count = 0, loopcnt = 0, ReTry = 0;
1246 UCHAR RF_R24_Value = 0;
1247
1248 // Give bbp filter initial value
1249 pAd->Mlme.CaliBW20RfR24 = 0x1F;
1250 pAd->Mlme.CaliBW40RfR24 = 0x2F; //Bit[5] must be 1 for BW 40
1251
1252 do
1253 {
1254 if (loop == 1) //BandWidth = 40 MHz
1255 {
1256 // Write 0x27 to RF_R24 to program filter
1257 RF_R24_Value = 0x27;
1258 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
1259 if (IS_RT3090(pAd))
1260 FilterTarget = 0x15;
1261 else
1262 FilterTarget = 0x19;
1263
1264 // when calibrate BW40, BBP mask must set to BW40.
1265 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
1266 BBPValue&= (~0x18);
1267 BBPValue|= (0x10);
1268 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
1269
1270 // set to BW40
1271 RT30xxReadRFRegister(pAd, RF_R31, &value);
1272 value |= 0x20;
1273 RT30xxWriteRFRegister(pAd, RF_R31, value);
1274 }
1275 else //BandWidth = 20 MHz
1276 {
1277 // Write 0x07 to RF_R24 to program filter
1278 RF_R24_Value = 0x07;
1279 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
1280 if (IS_RT3090(pAd))
1281 FilterTarget = 0x13;
1282 else
1283 FilterTarget = 0x16;
1284
1285 // set to BW20
1286 RT30xxReadRFRegister(pAd, RF_R31, &value);
1287 value &= (~0x20);
1288 RT30xxWriteRFRegister(pAd, RF_R31, value);
1289 }
1290
1291 // Write 0x01 to RF_R22 to enable baseband loopback mode
1292 RT30xxReadRFRegister(pAd, RF_R22, &value);
1293 value |= 0x01;
1294 RT30xxWriteRFRegister(pAd, RF_R22, value);
1295
1296 // Write 0x00 to BBP_R24 to set power & frequency of passband test tone
1297 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);
1298
1299 do
1300 {
1301 // Write 0x90 to BBP_R25 to transmit test tone
1302 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);
1303
1304 RTMPusecDelay(1000);
1305 // Read BBP_R55[6:0] for received power, set R55x = BBP_R55[6:0]
1306 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
1307 R55x = value & 0xFF;
1308
1309 } while ((ReTry++ < 100) && (R55x == 0));
1310
1311 // Write 0x06 to BBP_R24 to set power & frequency of stopband test tone
1312 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0x06);
1313
1314 while(TRUE)
1315 {
1316 // Write 0x90 to BBP_R25 to transmit test tone
1317 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);
1318
1319 //We need to wait for calibration
1320 RTMPusecDelay(1000);
1321 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
1322 value &= 0xFF;
1323 if ((R55x - value) < FilterTarget)
1324 {
1325 RF_R24_Value ++;
1326 }
1327 else if ((R55x - value) == FilterTarget)
1328 {
1329 RF_R24_Value ++;
1330 count ++;
1331 }
1332 else
1333 {
1334 break;
1335 }
1336
1337 // prevent infinite loop cause driver hang.
1338 if (loopcnt++ > 100)
1339 {
1340 DBGPRINT(RT_DEBUG_ERROR, ("RTMPFilterCalibration - can't find a valid value, loopcnt=%d stop calibrating", loopcnt));
1341 break;
1342 }
1343
1344 // Write RF_R24 to program filter
1345 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
1346 }
1347
1348 if (count > 0)
1349 {
1350 RF_R24_Value = RF_R24_Value - ((count) ? (1) : (0));
1351 }
1352
1353 // Store for future usage
1354 if (loopcnt < 100)
1355 {
1356 if (loop++ == 0)
1357 {
1358 //BandWidth = 20 MHz
1359 pAd->Mlme.CaliBW20RfR24 = (UCHAR)RF_R24_Value;
1360 }
1361 else
1362 {
1363 //BandWidth = 40 MHz
1364 pAd->Mlme.CaliBW40RfR24 = (UCHAR)RF_R24_Value;
1365 break;
1366 }
1367 }
1368 else
1369 break;
1370
1371 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
1372
1373 // reset count
1374 count = 0;
1375 } while(TRUE);
1376
1377 //
1378 // Set back to initial state
1379 //
1380 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);
1381
1382 RT30xxReadRFRegister(pAd, RF_R22, &value);
1383 value &= ~(0x01);
1384 RT30xxWriteRFRegister(pAd, RF_R22, value);
1385
1386 // set BBP back to BW20
1387 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
1388 BBPValue&= (~0x18);
1389 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
1390
1391 DBGPRINT(RT_DEBUG_TRACE, ("RTMPFilterCalibration - CaliBW20RfR24=0x%x, CaliBW40RfR24=0x%x\n", pAd->Mlme.CaliBW20RfR24, pAd->Mlme.CaliBW40RfR24));
1392}
1393#endif /* RT30xx */
1394
1395VOID NICInitRT30xxRFRegisters(IN PRTMP_ADAPTER pAd)
1396{
1397 INT i;
1398 // Driver must read EEPROM to get RfIcType before initial RF registers
1399 // Initialize RF register to default value
1400#ifndef RT30xx
1401 if (IS_RT3070(pAd) && ((pAd->RfIcType == RFIC_3020) ||(pAd->RfIcType == RFIC_2020)))
1402 {
1403 // Init RF calibration
1404 // Driver should toggle RF R30 bit7 before init RF registers
1405 ULONG RfReg = 0;
1406 RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
1407 RfReg |= 0x80;
1408 RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
1409 RTMPusecDelay(1000);
1410 RfReg &= 0x7F;
1411 RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
1412
1413 // Initialize RF register to default value
1414 for (i = 0; i < NUM_RF_REG_PARMS; i++)
1415 {
1416 RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value);
1417 }
1418
1419 //For RF filter Calibration
1420 RTUSBFilterCalibration(pAd);
1421 }
1422#endif
1423#ifdef RT30xx
1424 if (IS_RT3070(pAd) || IS_RT3071(pAd))
1425 {
1426 // Init RF calibration
1427 // Driver should toggle RF R30 bit7 before init RF registers
1428 UINT32 RfReg = 0;
1429 UINT32 data;
1430
1431 RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
1432 RfReg |= 0x80;
1433 RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
1434 RTMPusecDelay(1000);
1435 RfReg &= 0x7F;
1436 RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
1437
1438 // Initialize RF register to default value
1439 for (i = 0; i < NUM_RF_REG_PARMS; i++)
1440 {
1441 RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value);
1442 }
1443
1444 // add by johnli
1445 if (IS_RT3070(pAd))
1446 {
1447 // Update MAC 0x05D4 from 01xxxxxx to 0Dxxxxxx (voltage 1.2V to 1.35V) for RT3070 to improve yield rate
1448 RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
1449 data = ((data & 0xF0FFFFFF) | 0x0D000000);
1450 RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
1451 }
1452 else if (IS_RT3071(pAd))
1453 {
1454 // Driver should set RF R6 bit6 on before init RF registers
1455 RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
1456 RfReg |= 0x40;
1457 RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
1458
1459 // init R31
1460 RT30xxWriteRFRegister(pAd, RF_R31, 0x14);
1461
1462 // RT3071 version E has fixed this issue
1463 if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
1464 {
1465 // patch tx EVM issue temporarily
1466 RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
1467 data = ((data & 0xE0FFFFFF) | 0x0D000000);
1468 RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
1469 }
1470 else
1471 {
1472 RTMP_IO_READ32(pAd, LDO_CFG0, &data);
1473 data = ((data & 0xE0FFFFFF) | 0x01000000);
1474 RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
1475 }
1476
1477 // patch LNA_PE_G1 failed issue
1478 RTUSBReadMACRegister(pAd, GPIO_SWITCH, &data);
1479 data &= ~(0x20);
1480 RTUSBWriteMACRegister(pAd, GPIO_SWITCH, data);
1481 }
1482
1483 //For RF filter Calibration
1484 RTMPFilterCalibration(pAd);
1485
1486 // Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration()
1487 if ((pAd->MACVersion & 0xffff) < 0x0211)
1488 RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
1489
1490 // set led open drain enable
1491 RTUSBReadMACRegister(pAd, OPT_14, &data);
1492 data |= 0x01;
1493 RTUSBWriteMACRegister(pAd, OPT_14, data);
1494
1495 if (IS_RT3071(pAd))
1496 {
1497 // add by johnli, RF power sequence setup, load RF normal operation-mode setup
1498 RT30xxLoadRFNormalModeSetup(pAd);
1499 }
1500 }
1501#endif
1502}
1503#endif // RT2870 //
1008 1504
1009 1505
1010/* 1506/*
@@ -1179,11 +1675,25 @@ VOID NICReadEEPROMParameters(
1179 Antenna.word = pAd->EEPROMDefaultValue[0]; 1675 Antenna.word = pAd->EEPROMDefaultValue[0];
1180 if (Antenna.word == 0xFFFF) 1676 if (Antenna.word == 0xFFFF)
1181 { 1677 {
1678#ifdef RT30xx
1679 if(IS_RT3090(pAd))
1680 {
1681 Antenna.word = 0;
1682 Antenna.field.RfIcType = RFIC_3020;
1683 Antenna.field.TxPath = 1;
1684 Antenna.field.RxPath = 1;
1685 }
1686 else
1687 {
1688#endif // RT30xx //
1182 Antenna.word = 0; 1689 Antenna.word = 0;
1183 Antenna.field.RfIcType = RFIC_2820; 1690 Antenna.field.RfIcType = RFIC_2820;
1184 Antenna.field.TxPath = 1; 1691 Antenna.field.TxPath = 1;
1185 Antenna.field.RxPath = 2; 1692 Antenna.field.RxPath = 2;
1186 DBGPRINT(RT_DEBUG_WARN, ("E2PROM error, hard code as 0x%04x\n", Antenna.word)); 1693 DBGPRINT(RT_DEBUG_WARN, ("E2PROM error, hard code as 0x%04x\n", Antenna.word));
1694#ifdef RT30xx
1695 }
1696#endif // RT30xx //
1187 } 1697 }
1188 1698
1189 // Choose the desired Tx&Rx stream. 1699 // Choose the desired Tx&Rx stream.
@@ -1212,7 +1722,9 @@ VOID NICReadEEPROMParameters(
1212 NicConfig2.word = pAd->EEPROMDefaultValue[1]; 1722 NicConfig2.word = pAd->EEPROMDefaultValue[1];
1213 1723
1214 { 1724 {
1725#ifndef RT30xx
1215 NicConfig2.word = 0; 1726 NicConfig2.word = 0;
1727#endif
1216 if ((NicConfig2.word & 0x00ff) == 0xff) 1728 if ((NicConfig2.word & 0x00ff) == 0xff)
1217 { 1729 {
1218 NicConfig2.word &= 0xff00; 1730 NicConfig2.word &= 0xff00;
@@ -1405,6 +1917,14 @@ VOID NICReadEEPROMParameters(
1405 1917
1406 RTMPReadTxPwrPerRate(pAd); 1918 RTMPReadTxPwrPerRate(pAd);
1407 1919
1920#ifdef RT30xx
1921 if (IS_RT30xx(pAd))
1922 {
1923 eFusePhysicalReadRegisters(pAd, EFUSE_TAG, 2, &value);
1924 pAd->EFuseTag = (value & 0xff);
1925 }
1926#endif // RT30xx //
1927
1408 DBGPRINT(RT_DEBUG_TRACE, ("<-- NICReadEEPROMParameters\n")); 1928 DBGPRINT(RT_DEBUG_TRACE, ("<-- NICReadEEPROMParameters\n"));
1409} 1929}
1410 1930
@@ -1449,16 +1969,49 @@ VOID NICInitAsicFromEEPROM(
1449 } 1969 }
1450 } 1970 }
1451 1971
1972#ifndef RT30xx
1452 Antenna.word = pAd->Antenna.word; 1973 Antenna.word = pAd->Antenna.word;
1974#endif
1975#ifdef RT30xx
1976 Antenna.word = pAd->EEPROMDefaultValue[0];
1977 if (Antenna.word == 0xFFFF)
1978 {
1979 DBGPRINT(RT_DEBUG_ERROR, ("E2PROM error, hard code as 0x%04x\n", Antenna.word));
1980 BUG_ON(Antenna.word == 0xFFFF);
1981 }
1982#endif
1453 pAd->Mlme.RealRxPath = (UCHAR) Antenna.field.RxPath; 1983 pAd->Mlme.RealRxPath = (UCHAR) Antenna.field.RxPath;
1454 pAd->RfIcType = (UCHAR) Antenna.field.RfIcType; 1984 pAd->RfIcType = (UCHAR) Antenna.field.RfIcType;
1455 1985
1986#ifdef RT30xx
1987 DBGPRINT(RT_DEBUG_WARN, ("pAd->RfIcType = %d, RealRxPath=%d, TxPath = %d\n", pAd->RfIcType, pAd->Mlme.RealRxPath,Antenna.field.TxPath));
1988
1989 // Save the antenna for future use
1990 pAd->Antenna.word = Antenna.word;
1991#endif
1456 NicConfig2.word = pAd->EEPROMDefaultValue[1]; 1992 NicConfig2.word = pAd->EEPROMDefaultValue[1];
1457 1993
1994#ifdef RT30xx
1995 {
1996 if ((NicConfig2.word & 0x00ff) == 0xff)
1997 {
1998 NicConfig2.word &= 0xff00;
1999 }
1458 2000
2001 if ((NicConfig2.word >> 8) == 0xff)
2002 {
2003 NicConfig2.word &= 0x00ff;
2004 }
2005 }
2006#endif
1459 // Save the antenna for future use 2007 // Save the antenna for future use
1460 pAd->NicConfig2.word = NicConfig2.word; 2008 pAd->NicConfig2.word = NicConfig2.word;
1461 2009
2010#ifdef RT30xx
2011 // set default antenna as main
2012 if (pAd->RfIcType == RFIC_3020)
2013 AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
2014#endif
1462 // 2015 //
1463 // Send LED Setting to MCU. 2016 // Send LED Setting to MCU.
1464 // 2017 //
@@ -1467,7 +2020,13 @@ VOID NICInitAsicFromEEPROM(
1467 pAd->LedCntl.word = 0x01; 2020 pAd->LedCntl.word = 0x01;
1468 pAd->Led1 = 0x5555; 2021 pAd->Led1 = 0x5555;
1469 pAd->Led2 = 0x2221; 2022 pAd->Led2 = 0x2221;
2023#ifdef RT2860
1470 pAd->Led3 = 0xA9F8; 2024 pAd->Led3 = 0xA9F8;
2025#endif
2026
2027#ifdef RT2870
2028 pAd->Led3 = 0x5627;
2029#endif // RT2870 //
1471 } 2030 }
1472 2031
1473 AsicSendCommandToMcu(pAd, 0x52, 0xff, (UCHAR)pAd->Led1, (UCHAR)(pAd->Led1 >> 8)); 2032 AsicSendCommandToMcu(pAd, 0x52, 0xff, (UCHAR)pAd->Led1, (UCHAR)(pAd->Led1 >> 8));
@@ -1501,10 +2060,12 @@ VOID NICInitAsicFromEEPROM(
1501 else 2060 else
1502 { 2061 {
1503 RTMPSetLED(pAd, LED_RADIO_ON); 2062 RTMPSetLED(pAd, LED_RADIO_ON);
2063#ifdef RT2860
1504 AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x02); 2064 AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x02);
1505 AsicSendCommandToMcu(pAd, 0x31, PowerWakeCID, 0x00, 0x00); 2065 AsicSendCommandToMcu(pAd, 0x31, PowerWakeCID, 0x00, 0x00);
1506 // 2-1. wait command ok. 2066 // 2-1. wait command ok.
1507 AsicCheckCommanOk(pAd, PowerWakeCID); 2067 AsicCheckCommanOk(pAd, PowerWakeCID);
2068#endif
1508 } 2069 }
1509 } 2070 }
1510 2071
@@ -1579,8 +2140,10 @@ NDIS_STATUS NICInitializeAdapter(
1579{ 2140{
1580 NDIS_STATUS Status = NDIS_STATUS_SUCCESS; 2141 NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
1581 WPDMA_GLO_CFG_STRUC GloCfg; 2142 WPDMA_GLO_CFG_STRUC GloCfg;
2143#ifdef RT2860
1582 UINT32 Value; 2144 UINT32 Value;
1583 DELAY_INT_CFG_STRUC IntCfg; 2145 DELAY_INT_CFG_STRUC IntCfg;
2146#endif
1584 ULONG i =0, j=0; 2147 ULONG i =0, j=0;
1585 AC_TXOP_CSR0_STRUC csr0; 2148 AC_TXOP_CSR0_STRUC csr0;
1586 2149
@@ -1619,9 +2182,11 @@ retry:
1619 2182
1620 // asic simulation sequence put this ahead before loading firmware. 2183 // asic simulation sequence put this ahead before loading firmware.
1621 // pbf hardware reset 2184 // pbf hardware reset
2185#ifdef RT2860
1622 RTMP_IO_WRITE32(pAd, WPDMA_RST_IDX, 0x1003f); // 0x10000 for reset rx, 0x3f resets all 6 tx rings. 2186 RTMP_IO_WRITE32(pAd, WPDMA_RST_IDX, 0x1003f); // 0x10000 for reset rx, 0x3f resets all 6 tx rings.
1623 RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0xe1f); 2187 RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0xe1f);
1624 RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0xe00); 2188 RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0xe00);
2189#endif
1625 2190
1626 // Initialze ASIC for TX & Rx operation 2191 // Initialze ASIC for TX & Rx operation
1627 if (NICInitializeAsic(pAd , bHardReset) != NDIS_STATUS_SUCCESS) 2192 if (NICInitializeAsic(pAd , bHardReset) != NDIS_STATUS_SUCCESS)
@@ -1635,6 +2200,7 @@ retry:
1635 } 2200 }
1636 2201
1637 2202
2203#ifdef RT2860
1638 // Write AC_BK base address register 2204 // Write AC_BK base address register
1639 Value = RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_BK].Cell[0].AllocPa); 2205 Value = RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_BK].Cell[0].AllocPa);
1640 RTMP_IO_WRITE32(pAd, TX_BASE_PTR1, Value); 2206 RTMP_IO_WRITE32(pAd, TX_BASE_PTR1, Value);
@@ -1707,6 +2273,7 @@ retry:
1707 // Write RX_RING_CSR register 2273 // Write RX_RING_CSR register
1708 Value = RX_RING_SIZE; 2274 Value = RX_RING_SIZE;
1709 RTMP_IO_WRITE32(pAd, RX_MAX_CNT, Value); 2275 RTMP_IO_WRITE32(pAd, RX_MAX_CNT, Value);
2276#endif /* RT2860 */
1710 2277
1711 2278
1712 // WMM parameter 2279 // WMM parameter
@@ -1725,6 +2292,7 @@ retry:
1725 RTMP_IO_WRITE32(pAd, WMM_TXOP1_CFG, csr0.word); 2292 RTMP_IO_WRITE32(pAd, WMM_TXOP1_CFG, csr0.word);
1726 2293
1727 2294
2295#ifdef RT2860
1728 // 3. Set DMA global configuration except TX_DMA_EN and RX_DMA_EN bits: 2296 // 3. Set DMA global configuration except TX_DMA_EN and RX_DMA_EN bits:
1729 i = 0; 2297 i = 0;
1730 do 2298 do
@@ -1743,6 +2311,7 @@ retry:
1743 2311
1744 IntCfg.word = 0; 2312 IntCfg.word = 0;
1745 RTMP_IO_WRITE32(pAd, DELAY_INT_CFG, IntCfg.word); 2313 RTMP_IO_WRITE32(pAd, DELAY_INT_CFG, IntCfg.word);
2314#endif
1746 2315
1747 2316
1748 // reset action 2317 // reset action
@@ -1778,33 +2347,134 @@ NDIS_STATUS NICInitializeAsic(
1778 ULONG Index = 0; 2347 ULONG Index = 0;
1779 UCHAR R0 = 0xff; 2348 UCHAR R0 = 0xff;
1780 UINT32 MacCsr12 = 0, Counter = 0; 2349 UINT32 MacCsr12 = 0, Counter = 0;
2350#ifdef RT2870
2351 UINT32 MacCsr0 = 0;
2352 NTSTATUS Status;
2353 UCHAR Value = 0xff;
2354#endif // RT2870 //
2355#ifdef RT30xx
2356 UINT32 eFuseCtrl;
2357#endif // RT30xx //
1781 USHORT KeyIdx; 2358 USHORT KeyIdx;
1782 INT i,apidx; 2359 INT i,apidx;
1783 2360
1784 DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitializeAsic\n")); 2361 DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitializeAsic\n"));
1785 2362
2363#ifdef RT2860
1786 if (bHardReset == TRUE) 2364 if (bHardReset == TRUE)
1787 { 2365 {
1788 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x3); 2366 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x3);
1789 } 2367 }
1790 else 2368 else
1791 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x1); 2369 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x1);
2370#endif
2371#ifdef RT2870
2372 //
2373 // Make sure MAC gets ready after NICLoadFirmware().
2374 //
2375 Index = 0;
2376
2377 //To avoid hang-on issue when interface up in kernel 2.4,
2378 //we use a local variable "MacCsr0" instead of using "pAd->MACVersion" directly.
2379 do
2380 {
2381 RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0);
2382
2383 if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF))
2384 break;
2385
2386 RTMPusecDelay(10);
2387 } while (Index++ < 100);
2388
2389 pAd->MACVersion = MacCsr0;
2390 DBGPRINT(RT_DEBUG_TRACE, ("MAC_CSR0 [ Ver:Rev=0x%08x]\n", pAd->MACVersion));
2391 // turn on bit13 (set to zero) after rt2860D. This is to solve high-current issue.
2392 RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &MacCsr12);
2393 MacCsr12 &= (~0x2000);
2394 RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, MacCsr12);
2395
2396 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x3);
2397 RTMP_IO_WRITE32(pAd, USB_DMA_CFG, 0x0);
2398 Status = RTUSBVenderReset(pAd);
2399#endif
1792 2400
1793 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0); 2401 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0);
2402
1794 // Initialize MAC register to default value 2403 // Initialize MAC register to default value
2404#ifdef RT2860
1795 for (Index = 0; Index < NUM_MAC_REG_PARMS; Index++) 2405 for (Index = 0; Index < NUM_MAC_REG_PARMS; Index++)
1796 { 2406 {
1797 RTMP_IO_WRITE32(pAd, MACRegTable[Index].Register, MACRegTable[Index].Value); 2407 RTMP_IO_WRITE32(pAd, MACRegTable[Index].Register, MACRegTable[Index].Value);
1798 } 2408 }
2409#endif
2410#ifdef RT2870
2411 for(Index=0; Index<NUM_MAC_REG_PARMS; Index++)
2412 {
2413#ifdef RT3070
2414 if ((MACRegTable[Index].Register == TX_SW_CFG0) && (IS_RT3070(pAd) || IS_RT3071(pAd)))
2415 {
2416 MACRegTable[Index].Value = 0x00000400;
2417 }
2418#endif // RT3070 //
2419 RTMP_IO_WRITE32(pAd, (USHORT)MACRegTable[Index].Register, MACRegTable[Index].Value);
2420 }
2421
2422#ifndef RT30xx
2423 if(IS_RT3070(pAd))
2424 {
2425 // According to Frank Hsu (from Gary Tsao)
2426 RTMP_IO_WRITE32(pAd, (USHORT)TX_SW_CFG0, 0x00000400);
2427
2428 // Initialize RT3070 serial MAC registers which is different from RT2870 serial
2429 RTUSBWriteMACRegister(pAd, TX_SW_CFG1, 0);
2430 RTUSBWriteMACRegister(pAd, TX_SW_CFG2, 0);
2431 }
2432#endif
2433#endif // RT2870 //
1799 2434
1800 2435
1801 { 2436 {
1802 for (Index = 0; Index < NUM_STA_MAC_REG_PARMS; Index++) 2437 for (Index = 0; Index < NUM_STA_MAC_REG_PARMS; Index++)
1803 { 2438 {
2439#ifdef RT2860
1804 RTMP_IO_WRITE32(pAd, STAMACRegTable[Index].Register, STAMACRegTable[Index].Value); 2440 RTMP_IO_WRITE32(pAd, STAMACRegTable[Index].Register, STAMACRegTable[Index].Value);
2441#endif
2442#ifdef RT2870
2443 RTMP_IO_WRITE32(pAd, (USHORT)STAMACRegTable[Index].Register, STAMACRegTable[Index].Value);
2444#endif
1805 } 2445 }
1806 } 2446 }
1807 2447
2448#ifdef RT30xx
2449 // Initialize RT3070 serial MAc registers which is different from RT2870 serial
2450 if (IS_RT3090(pAd))
2451 {
2452 RTMP_IO_WRITE32(pAd, TX_SW_CFG1, 0);
2453
2454 // RT3071 version E has fixed this issue
2455 if ((pAd->MACVersion & 0xffff) < 0x0211)
2456 {
2457 if (pAd->NicConfig2.field.DACTestBit == 1)
2458 {
2459 RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x1F); // To fix throughput drop drastically
2460 }
2461 else
2462 {
2463 RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0F); // To fix throughput drop drastically
2464 }
2465 }
2466 else
2467 {
2468 RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0);
2469 }
2470 }
2471 else if (IS_RT3070(pAd))
2472 {
2473 RTMP_IO_WRITE32(pAd, TX_SW_CFG1, 0);
2474 RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x1F); // To fix throughput drop drastically
2475 }
2476#endif // RT30xx //
2477
1808 // 2478 //
1809 // Before program BBP, we need to wait BBP/RF get wake up. 2479 // Before program BBP, we need to wait BBP/RF get wake up.
1810 // 2480 //
@@ -1844,11 +2514,69 @@ NDIS_STATUS NICInitializeAsic(
1844 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBPRegTable[Index].Register, BBPRegTable[Index].Value); 2514 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBPRegTable[Index].Register, BBPRegTable[Index].Value);
1845 } 2515 }
1846 2516
2517#ifndef RT30xx
1847 // for rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT. 2518 // for rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT.
1848 if ((pAd->MACVersion&0xffff) != 0x0101) 2519 if ((pAd->MACVersion&0xffff) != 0x0101)
1849 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19); 2520 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19);
1850 2521
2522#ifdef RT2870
2523 //write RT3070 BBP wchich different with 2870 after write RT2870 BBP
2524 if (IS_RT3070(pAd))
2525 {
2526 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0a);
2527 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x99);
2528 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R105, 0x05);
2529 }
2530#endif // RT2870 //
2531#endif
2532#ifdef RT30xx
2533 // for rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT.
2534 // RT3090 should not program BBP R84 to 0x19, otherwise TX will block.
2535 if (((pAd->MACVersion&0xffff) != 0x0101) && (!IS_RT30xx(pAd)))
2536 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19);
2537
2538// add by johnli, RF power sequence setup
2539 if (IS_RT30xx(pAd))
2540 { //update for RT3070/71/72/90/91/92.
2541 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R79, 0x13);
2542 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R80, 0x05);
2543 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R81, 0x33);
2544 }
2545
2546 if (IS_RT3090(pAd))
2547 {
2548 UCHAR bbpreg=0;
2549
2550 // enable DC filter
2551 if ((pAd->MACVersion & 0xffff) >= 0x0211)
2552 {
2553 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R103, 0xc0);
2554 }
1851 2555
2556 // improve power consumption
2557 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R138, &bbpreg);
2558 if (pAd->Antenna.field.TxPath == 1)
2559 {
2560 // turn off tx DAC_1
2561 bbpreg = (bbpreg | 0x20);
2562 }
2563
2564 if (pAd->Antenna.field.RxPath == 1)
2565 {
2566 // turn off tx ADC_1
2567 bbpreg &= (~0x2);
2568 }
2569 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R138, bbpreg);
2570
2571 // improve power consumption in RT3071 Ver.E
2572 if ((pAd->MACVersion & 0xffff) >= 0x0211)
2573 {
2574 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R31, &bbpreg);
2575 bbpreg &= (~0x3);
2576 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R31, bbpreg);
2577 }
2578 }
2579#endif
1852 if (pAd->MACVersion == 0x28600100) 2580 if (pAd->MACVersion == 0x28600100)
1853 { 2581 {
1854 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16); 2582 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
@@ -1865,6 +2593,18 @@ NDIS_STATUS NICInitializeAsic(
1865 RTMP_IO_WRITE32(pAd, MAX_LEN_CFG, csr); 2593 RTMP_IO_WRITE32(pAd, MAX_LEN_CFG, csr);
1866 } 2594 }
1867 2595
2596#ifdef RT2870
2597{
2598 UCHAR MAC_Value[]={0xff,0xff,0xff,0xff,0xff,0xff,0xff,0,0};
2599
2600 //Initialize WCID table
2601 Value = 0xff;
2602 for(Index =0 ;Index < 254;Index++)
2603 {
2604 RTUSBMultiWrite(pAd, (USHORT)(MAC_WCID_BASE + Index * 8), MAC_Value, 8);
2605 }
2606}
2607#endif // RT2870 //
1868 2608
1869 // Add radio off control 2609 // Add radio off control
1870 { 2610 {
@@ -1912,6 +2652,35 @@ NDIS_STATUS NICInitializeAsic(
1912 RTMP_IO_WRITE32(pAd, pAd->BeaconOffset[apidx] + i, 0x00); 2652 RTMP_IO_WRITE32(pAd, pAd->BeaconOffset[apidx] + i, 0x00);
1913 } 2653 }
1914 } 2654 }
2655#ifdef RT2870
2656 AsicDisableSync(pAd);
2657 // Clear raw counters
2658 RTMP_IO_READ32(pAd, RX_STA_CNT0, &Counter);
2659 RTMP_IO_READ32(pAd, RX_STA_CNT1, &Counter);
2660 RTMP_IO_READ32(pAd, RX_STA_CNT2, &Counter);
2661 RTMP_IO_READ32(pAd, TX_STA_CNT0, &Counter);
2662 RTMP_IO_READ32(pAd, TX_STA_CNT1, &Counter);
2663 RTMP_IO_READ32(pAd, TX_STA_CNT2, &Counter);
2664 // Default PCI clock cycle per ms is different as default setting, which is based on PCI.
2665 RTMP_IO_READ32(pAd, USB_CYC_CFG, &Counter);
2666 Counter&=0xffffff00;
2667 Counter|=0x000001e;
2668 RTMP_IO_WRITE32(pAd, USB_CYC_CFG, Counter);
2669#endif // RT2870 //
2670#ifdef RT30xx
2671 pAd->bUseEfuse=FALSE;
2672 RTMP_IO_READ32(pAd, EFUSE_CTRL, &eFuseCtrl);
2673 pAd->bUseEfuse = ( (eFuseCtrl & 0x80000000) == 0x80000000) ? 1 : 0;
2674 if(pAd->bUseEfuse)
2675 {
2676 DBGPRINT(RT_DEBUG_TRACE, ("NVM is Efuse\n"));
2677 }
2678 else
2679 {
2680 DBGPRINT(RT_DEBUG_TRACE, ("NVM is EEPROM\n"));
2681
2682 }
2683#endif // RT30xx //
1915 2684
1916 { 2685 {
1917 // for rt2860E and after, init TXOP_CTRL_CFG with 0x583f. This is for extension channel overlapping IOT. 2686 // for rt2860E and after, init TXOP_CTRL_CFG with 0x583f. This is for extension channel overlapping IOT.
@@ -1924,6 +2693,7 @@ NDIS_STATUS NICInitializeAsic(
1924} 2693}
1925 2694
1926 2695
2696#ifdef RT2860
1927VOID NICRestoreBBPValue( 2697VOID NICRestoreBBPValue(
1928 IN PRTMP_ADAPTER pAd) 2698 IN PRTMP_ADAPTER pAd)
1929{ 2699{
@@ -2047,6 +2817,7 @@ VOID NICRestoreBBPValue(
2047 2817
2048 DBGPRINT(RT_DEBUG_TRACE, ("<--- NICRestoreBBPValue !!!!!!!!!!!!!!!!!!!!!!! \n")); 2818 DBGPRINT(RT_DEBUG_TRACE, ("<--- NICRestoreBBPValue !!!!!!!!!!!!!!!!!!!!!!! \n"));
2049} 2819}
2820#endif /* RT2860 */
2050 2821
2051/* 2822/*
2052 ======================================================================== 2823 ========================================================================
@@ -2299,6 +3070,22 @@ VOID NICUpdateRawCounters(
2299 // Update RX Overflow counter 3070 // Update RX Overflow counter
2300 pAd->Counters8023.RxNoBuffer += (RxStaCnt2.field.RxFifoOverflowCount); 3071 pAd->Counters8023.RxNoBuffer += (RxStaCnt2.field.RxFifoOverflowCount);
2301 3072
3073#ifdef RT2870
3074 if (pAd->RalinkCounters.RxCount != pAd->watchDogRxCnt)
3075 {
3076 pAd->watchDogRxCnt = pAd->RalinkCounters.RxCount;
3077 pAd->watchDogRxOverFlowCnt = 0;
3078 }
3079 else
3080 {
3081 if (RxStaCnt2.field.RxFifoOverflowCount)
3082 pAd->watchDogRxOverFlowCnt++;
3083 else
3084 pAd->watchDogRxOverFlowCnt = 0;
3085 }
3086#endif // RT2870 //
3087
3088
2302 if (!pAd->bUpdateBcnCntDone) 3089 if (!pAd->bUpdateBcnCntDone)
2303 { 3090 {
2304 // Update BEACON sent count 3091 // Update BEACON sent count
@@ -2531,9 +3318,40 @@ NDIS_STATUS NICLoadFirmware(
2531 ULONG FileLength, Index; 3318 ULONG FileLength, Index;
2532 //ULONG firm; 3319 //ULONG firm;
2533 UINT32 MacReg = 0; 3320 UINT32 MacReg = 0;
3321#ifdef RT2870
3322 UINT32 Version = (pAd->MACVersion >> 16);
3323#endif // RT2870 //
2534 3324
2535 pFirmwareImage = FirmwareImage; 3325 pFirmwareImage = FirmwareImage;
2536 FileLength = sizeof(FirmwareImage); 3326 FileLength = sizeof(FirmwareImage);
3327#ifdef RT2870
3328 // New 8k byte firmware size for RT3071/RT3072
3329 //printk("Usb Chip\n");
3330 if (FIRMWAREIMAGE_LENGTH == FIRMWAREIMAGE_MAX_LENGTH)
3331 //The firmware image consists of two parts. One is the origianl and the other is the new.
3332 //Use Second Part
3333 {
3334 if ((Version != 0x2860) && (Version != 0x2872) && (Version != 0x3070))
3335 { // Use Firmware V2.
3336 //printk("KH:Use New Version,part2\n");
3337 pFirmwareImage = (PUCHAR)&FirmwareImage[FIRMWAREIMAGEV1_LENGTH];
3338 FileLength = FIRMWAREIMAGEV2_LENGTH;
3339 }
3340 else
3341 {
3342 //printk("KH:Use New Version,part1\n");
3343 pFirmwareImage = FirmwareImage;
3344 FileLength = FIRMWAREIMAGEV1_LENGTH;
3345 }
3346 }
3347 else
3348 {
3349 DBGPRINT(RT_DEBUG_ERROR, ("KH: bin file should be 8KB.\n"));
3350 Status = NDIS_STATUS_FAILURE;
3351 }
3352
3353#endif // RT2870 //
3354
2537 RT28XX_WRITE_FIRMWARE(pAd, pFirmwareImage, FileLength); 3355 RT28XX_WRITE_FIRMWARE(pAd, pFirmwareImage, FileLength);
2538 3356
2539 /* check if MCU is ready */ 3357 /* check if MCU is ready */
@@ -2799,6 +3617,31 @@ VOID UserCfgInit(
2799 // 3617 //
2800 // part I. intialize common configuration 3618 // part I. intialize common configuration
2801 // 3619 //
3620#ifdef RT2870
3621 pAd->BulkOutReq = 0;
3622
3623 pAd->BulkOutComplete = 0;
3624 pAd->BulkOutCompleteOther = 0;
3625 pAd->BulkOutCompleteCancel = 0;
3626 pAd->BulkInReq = 0;
3627 pAd->BulkInComplete = 0;
3628 pAd->BulkInCompleteFail = 0;
3629
3630 //pAd->QuickTimerP = 100;
3631 //pAd->TurnAggrBulkInCount = 0;
3632 pAd->bUsbTxBulkAggre = 0;
3633
3634 // init as unsed value to ensure driver will set to MCU once.
3635 pAd->LedIndicatorStregth = 0xFF;
3636
3637 pAd->CommonCfg.MaxPktOneTxBulk = 2;
3638 pAd->CommonCfg.TxBulkFactor = 1;
3639 pAd->CommonCfg.RxBulkFactor =1;
3640
3641 pAd->CommonCfg.TxPower = 100; //mW
3642
3643 NdisZeroMemory(&pAd->CommonCfg.IOTestParm, sizeof(pAd->CommonCfg.IOTestParm));
3644#endif // RT2870 //
2802 3645
2803 for(key_index=0; key_index<SHARE_KEY_NUM; key_index++) 3646 for(key_index=0; key_index<SHARE_KEY_NUM; key_index++)
2804 { 3647 {
@@ -2809,14 +3652,19 @@ VOID UserCfgInit(
2809 } 3652 }
2810 } 3653 }
2811 3654
3655#ifdef RT30xx
3656 pAd->EepromAccess = FALSE;
3657#endif
2812 pAd->Antenna.word = 0; 3658 pAd->Antenna.word = 0;
2813 pAd->CommonCfg.BBPCurrentBW = BW_20; 3659 pAd->CommonCfg.BBPCurrentBW = BW_20;
2814 3660
2815 pAd->LedCntl.word = 0; 3661 pAd->LedCntl.word = 0;
3662#ifdef RT2860
2816 pAd->LedIndicatorStregth = 0; 3663 pAd->LedIndicatorStregth = 0;
2817 pAd->RLnkCtrlOffset = 0; 3664 pAd->RLnkCtrlOffset = 0;
2818 pAd->HostLnkCtrlOffset = 0; 3665 pAd->HostLnkCtrlOffset = 0;
2819 pAd->CheckDmaBusyCount = 0; 3666 pAd->CheckDmaBusyCount = 0;
3667#endif
2820 3668
2821 pAd->bAutoTxAgcA = FALSE; // Default is OFF 3669 pAd->bAutoTxAgcA = FALSE; // Default is OFF
2822 pAd->bAutoTxAgcG = FALSE; // Default is OFF 3670 pAd->bAutoTxAgcG = FALSE; // Default is OFF
@@ -3020,9 +3868,11 @@ VOID UserCfgInit(
3020 NdisAllocateSpinLock(&pAd->MacTabLock); 3868 NdisAllocateSpinLock(&pAd->MacTabLock);
3021 3869
3022 pAd->CommonCfg.bWiFiTest = FALSE; 3870 pAd->CommonCfg.bWiFiTest = FALSE;
3871#ifdef RT2860
3023 pAd->bPCIclkOff = FALSE; 3872 pAd->bPCIclkOff = FALSE;
3024 3873
3025 RTMP_SET_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP); 3874 RTMP_SET_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP);
3875#endif
3026 DBGPRINT(RT_DEBUG_TRACE, ("<-- UserCfgInit\n")); 3876 DBGPRINT(RT_DEBUG_TRACE, ("<-- UserCfgInit\n"));
3027} 3877}
3028 3878
@@ -3124,6 +3974,9 @@ VOID RTMPInitTimer(
3124 pTimer->State = FALSE; 3974 pTimer->State = FALSE;
3125 pTimer->cookie = (ULONG) pData; 3975 pTimer->cookie = (ULONG) pData;
3126 3976
3977#ifdef RT2870
3978 pTimer->pAd = pAd;
3979#endif // RT2870 //
3127 3980
3128 RTMP_OS_Init_Timer(pAd, &pTimer->TimerObj, pTimerFunc, (PVOID) pTimer); 3981 RTMP_OS_Init_Timer(pAd, &pTimer->TimerObj, pTimerFunc, (PVOID) pTimer);
3129} 3982}
@@ -3250,6 +4103,12 @@ VOID RTMPCancelTimer(
3250 if (*pCancelled == TRUE) 4103 if (*pCancelled == TRUE)
3251 pTimer->State = TRUE; 4104 pTimer->State = TRUE;
3252 4105
4106#ifdef RT2870
4107 // We need to go-through the TimerQ to findout this timer handler and remove it if
4108 // it's still waiting for execution.
4109
4110 RT2870_TimerQ_Remove(pTimer->pAd, pTimer);
4111#endif // RT2870 //
3253 } 4112 }
3254 else 4113 else
3255 { 4114 {
diff --git a/drivers/staging/rt2860/common/spectrum.c b/drivers/staging/rt2860/common/spectrum.c
index c658bf3082c3..101c2923ca37 100644
--- a/drivers/staging/rt2860/common/spectrum.c
+++ b/drivers/staging/rt2860/common/spectrum.c
@@ -1570,7 +1570,12 @@ static VOID PeerMeasureReportAction(
1570 1570
1571 if ((pMeasureReportInfo = kmalloc(sizeof(MEASURE_RPI_REPORT), GFP_ATOMIC)) == NULL) 1571 if ((pMeasureReportInfo = kmalloc(sizeof(MEASURE_RPI_REPORT), GFP_ATOMIC)) == NULL)
1572 { 1572 {
1573#ifndef RT30xx
1573 DBGPRINT(RT_DEBUG_ERROR, ("%s unable to alloc memory for measure report buffer (size=%zu).\n", __func__, sizeof(MEASURE_RPI_REPORT))); 1574 DBGPRINT(RT_DEBUG_ERROR, ("%s unable to alloc memory for measure report buffer (size=%zu).\n", __func__, sizeof(MEASURE_RPI_REPORT)));
1575#endif
1576#ifdef RT30xx
1577 DBGPRINT(RT_DEBUG_ERROR, ("%s unable to alloc memory for measure report buffer (size=%d).\n", __func__, sizeof(MEASURE_RPI_REPORT)));
1578#endif
1574 return; 1579 return;
1575 } 1580 }
1576 1581
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 14:43:18 -0500