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authorDavid Woodhouse <David.Woodhouse@intel.com>2009-07-01 14:30:28 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2009-07-01 14:43:37 -0400
commit206a73c102fc480ba072a9388bc2142c303113aa (patch)
tree0b946089436df51a4444ef23069a9037853d5e61 /drivers
parentc85994e4771025ef2a66533eb1a4c6c2217b9cda (diff)
intel-iommu: Kill superfluous mapping_lock
Since we're using cmpxchg64() anyway (because that's the only way to do an atomic 64-bit store on i386), we might as well ditch the extra locking and just use cmpxchg64() to ensure that we don't add the page twice. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/intel-iommu.c12
1 files changed, 2 insertions, 10 deletions
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c
index eea1006c860a..02223e2e27d4 100644
--- a/drivers/pci/intel-iommu.c
+++ b/drivers/pci/intel-iommu.c
@@ -267,7 +267,6 @@ struct dmar_domain {
267 struct iova_domain iovad; /* iova's that belong to this domain */ 267 struct iova_domain iovad; /* iova's that belong to this domain */
268 268
269 struct dma_pte *pgd; /* virtual address */ 269 struct dma_pte *pgd; /* virtual address */
270 spinlock_t mapping_lock; /* page table lock */
271 int gaw; /* max guest address width */ 270 int gaw; /* max guest address width */
272 271
273 /* adjusted guest address width, 0 is level 2 30-bit */ 272 /* adjusted guest address width, 0 is level 2 30-bit */
@@ -701,13 +700,11 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
701 struct dma_pte *parent, *pte = NULL; 700 struct dma_pte *parent, *pte = NULL;
702 int level = agaw_to_level(domain->agaw); 701 int level = agaw_to_level(domain->agaw);
703 int offset; 702 int offset;
704 unsigned long flags;
705 703
706 BUG_ON(!domain->pgd); 704 BUG_ON(!domain->pgd);
707 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width); 705 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
708 parent = domain->pgd; 706 parent = domain->pgd;
709 707
710 spin_lock_irqsave(&domain->mapping_lock, flags);
711 while (level > 0) { 708 while (level > 0) {
712 void *tmp_page; 709 void *tmp_page;
713 710
@@ -721,11 +718,9 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
721 718
722 tmp_page = alloc_pgtable_page(); 719 tmp_page = alloc_pgtable_page();
723 720
724 if (!tmp_page) { 721 if (!tmp_page)
725 spin_unlock_irqrestore(&domain->mapping_lock,
726 flags);
727 return NULL; 722 return NULL;
728 } 723
729 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); 724 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
730 pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; 725 pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
731 if (cmpxchg64(&pte->val, 0ULL, pteval)) { 726 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
@@ -740,7 +735,6 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
740 level--; 735 level--;
741 } 736 }
742 737
743 spin_unlock_irqrestore(&domain->mapping_lock, flags);
744 return pte; 738 return pte;
745} 739}
746 740
@@ -1375,7 +1369,6 @@ static int domain_init(struct dmar_domain *domain, int guest_width)
1375 unsigned long sagaw; 1369 unsigned long sagaw;
1376 1370
1377 init_iova_domain(&domain->iovad, DMA_32BIT_PFN); 1371 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1378 spin_lock_init(&domain->mapping_lock);
1379 spin_lock_init(&domain->iommu_lock); 1372 spin_lock_init(&domain->iommu_lock);
1380 1373
1381 domain_reserve_special_ranges(domain); 1374 domain_reserve_special_ranges(domain);
@@ -3336,7 +3329,6 @@ static int md_domain_init(struct dmar_domain *domain, int guest_width)
3336 int adjust_width; 3329 int adjust_width;
3337 3330
3338 init_iova_domain(&domain->iovad, DMA_32BIT_PFN); 3331 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3339 spin_lock_init(&domain->mapping_lock);
3340 spin_lock_init(&domain->iommu_lock); 3332 spin_lock_init(&domain->iommu_lock);
3341 3333
3342 domain_reserve_special_ranges(domain); 3334 domain_reserve_special_ranges(domain);