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authorArnd Bergmann <arnd@arndb.de>2014-02-25 11:50:08 -0500
committerArnd Bergmann <arnd@arndb.de>2014-02-25 11:50:14 -0500
commit1e7bdf82abf210577228d36a098588b49e46b9a9 (patch)
tree4c5f490622a806be8d8677d272e2c7ee4c1c7a2b /drivers/watchdog
parent96f9d40db89fbf59f0f115877ab90d94bb66f503 (diff)
parent59416745bb8cbe32daf805f768418353168b0664 (diff)
Merge tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu into next/drivers
mvebu watchdog driver changes for v3.15 - orion watchdog - cleanup and extend driver to support Armada 370 and Armada XP Depends: - tags/irqchip-mvebu-fixes-3.14 (already pulled by tglx) - both are based on v3.14-rc1 * tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu: watchdog: orion: Enable the build on ARCH_MVEBU watchdog: orion: Add support for Armada 370 and Armada XP SoC watchdog: orion: Add per-compatible watchdog start implementation watchdog: orion: Add per-compatible clock initialization watchdog: orion: Introduce per-compatible of_device_id data watchdog: orion: Introduce an orion_watchdog device structure watchdog: orion: Remove unneeded BRIDGE_CAUSE clear watchdog: orion: Make RSTOUT register a separate resource watchdog: orion: Handle the interrupt so it's properly acked watchdog: orion: Make sure the watchdog is initially stopped watchdog: orion: Remove unused macros watchdog: orion: Use atomic access for shared registers watchdog: orion: Add clock error handling Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/watchdog')
-rw-r--r--drivers/watchdog/Kconfig2
-rw-r--r--drivers/watchdog/orion_wdt.c381
2 files changed, 303 insertions, 80 deletions
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 79d25894343a..f1ff408c4b17 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -292,7 +292,7 @@ config DAVINCI_WATCHDOG
292 292
293config ORION_WATCHDOG 293config ORION_WATCHDOG
294 tristate "Orion watchdog" 294 tristate "Orion watchdog"
295 depends on ARCH_ORION5X || ARCH_KIRKWOOD || ARCH_DOVE 295 depends on ARCH_ORION5X || ARCH_KIRKWOOD || ARCH_DOVE || ARCH_MVEBU
296 select WATCHDOG_CORE 296 select WATCHDOG_CORE
297 help 297 help
298 Say Y here if to include support for the watchdog timer 298 Say Y here if to include support for the watchdog timer
diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
index f7722a424676..15321aa0bb94 100644
--- a/drivers/watchdog/orion_wdt.c
+++ b/drivers/watchdog/orion_wdt.c
@@ -19,101 +19,204 @@
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/watchdog.h> 20#include <linux/watchdog.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/interrupt.h>
22#include <linux/io.h> 23#include <linux/io.h>
23#include <linux/spinlock.h>
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/err.h> 25#include <linux/err.h>
26#include <linux/of.h> 26#include <linux/of.h>
27#include <mach/bridge-regs.h> 27#include <linux/of_device.h>
28
29/* RSTOUT mask register physical address for Orion5x, Kirkwood and Dove */
30#define ORION_RSTOUT_MASK_OFFSET 0x20108
31
32/* Internal registers can be configured at any 1 MiB aligned address */
33#define INTERNAL_REGS_MASK ~(SZ_1M - 1)
28 34
29/* 35/*
30 * Watchdog timer block registers. 36 * Watchdog timer block registers.
31 */ 37 */
32#define TIMER_CTRL 0x0000 38#define TIMER_CTRL 0x0000
33#define WDT_EN 0x0010 39#define TIMER_A370_STATUS 0x04
34#define WDT_VAL 0x0024
35 40
36#define WDT_MAX_CYCLE_COUNT 0xffffffff 41#define WDT_MAX_CYCLE_COUNT 0xffffffff
37#define WDT_IN_USE 0
38#define WDT_OK_TO_CLOSE 1
39 42
40#define WDT_RESET_OUT_EN BIT(1) 43#define WDT_A370_RATIO_MASK(v) ((v) << 16)
41#define WDT_INT_REQ BIT(3) 44#define WDT_A370_RATIO_SHIFT 5
45#define WDT_A370_RATIO (1 << WDT_A370_RATIO_SHIFT)
46
47#define WDT_AXP_FIXED_ENABLE_BIT BIT(10)
48#define WDT_A370_EXPIRED BIT(31)
42 49
43static bool nowayout = WATCHDOG_NOWAYOUT; 50static bool nowayout = WATCHDOG_NOWAYOUT;
44static int heartbeat = -1; /* module parameter (seconds) */ 51static int heartbeat = -1; /* module parameter (seconds) */
45static unsigned int wdt_max_duration; /* (seconds) */
46static struct clk *clk;
47static unsigned int wdt_tclk;
48static void __iomem *wdt_reg;
49static DEFINE_SPINLOCK(wdt_lock);
50 52
51static int orion_wdt_ping(struct watchdog_device *wdt_dev) 53struct orion_watchdog;
54
55struct orion_watchdog_data {
56 int wdt_counter_offset;
57 int wdt_enable_bit;
58 int rstout_enable_bit;
59 int (*clock_init)(struct platform_device *,
60 struct orion_watchdog *);
61 int (*start)(struct watchdog_device *);
62};
63
64struct orion_watchdog {
65 struct watchdog_device wdt;
66 void __iomem *reg;
67 void __iomem *rstout;
68 unsigned long clk_rate;
69 struct clk *clk;
70 const struct orion_watchdog_data *data;
71};
72
73static int orion_wdt_clock_init(struct platform_device *pdev,
74 struct orion_watchdog *dev)
52{ 75{
53 spin_lock(&wdt_lock); 76 int ret;
54 77
55 /* Reload watchdog duration */ 78 dev->clk = clk_get(&pdev->dev, NULL);
56 writel(wdt_tclk * wdt_dev->timeout, wdt_reg + WDT_VAL); 79 if (IS_ERR(dev->clk))
80 return PTR_ERR(dev->clk);
81 ret = clk_prepare_enable(dev->clk);
82 if (ret) {
83 clk_put(dev->clk);
84 return ret;
85 }
57 86
58 spin_unlock(&wdt_lock); 87 dev->clk_rate = clk_get_rate(dev->clk);
59 return 0; 88 return 0;
60} 89}
61 90
62static int orion_wdt_start(struct watchdog_device *wdt_dev) 91static int armada370_wdt_clock_init(struct platform_device *pdev,
92 struct orion_watchdog *dev)
63{ 93{
64 u32 reg; 94 int ret;
65 95
66 spin_lock(&wdt_lock); 96 dev->clk = clk_get(&pdev->dev, NULL);
97 if (IS_ERR(dev->clk))
98 return PTR_ERR(dev->clk);
99 ret = clk_prepare_enable(dev->clk);
100 if (ret) {
101 clk_put(dev->clk);
102 return ret;
103 }
104
105 /* Setup watchdog input clock */
106 atomic_io_modify(dev->reg + TIMER_CTRL,
107 WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT),
108 WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT));
109
110 dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO;
111 return 0;
112}
113
114static int armadaxp_wdt_clock_init(struct platform_device *pdev,
115 struct orion_watchdog *dev)
116{
117 int ret;
118
119 dev->clk = of_clk_get_by_name(pdev->dev.of_node, "fixed");
120 if (IS_ERR(dev->clk))
121 return PTR_ERR(dev->clk);
122 ret = clk_prepare_enable(dev->clk);
123 if (ret) {
124 clk_put(dev->clk);
125 return ret;
126 }
127
128 /* Enable the fixed watchdog clock input */
129 atomic_io_modify(dev->reg + TIMER_CTRL,
130 WDT_AXP_FIXED_ENABLE_BIT,
131 WDT_AXP_FIXED_ENABLE_BIT);
132
133 dev->clk_rate = clk_get_rate(dev->clk);
134 return 0;
135}
136
137static int orion_wdt_ping(struct watchdog_device *wdt_dev)
138{
139 struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
140 /* Reload watchdog duration */
141 writel(dev->clk_rate * wdt_dev->timeout,
142 dev->reg + dev->data->wdt_counter_offset);
143 return 0;
144}
145
146static int armada370_start(struct watchdog_device *wdt_dev)
147{
148 struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
67 149
68 /* Set watchdog duration */ 150 /* Set watchdog duration */
69 writel(wdt_tclk * wdt_dev->timeout, wdt_reg + WDT_VAL); 151 writel(dev->clk_rate * wdt_dev->timeout,
152 dev->reg + dev->data->wdt_counter_offset);
70 153
71 /* Clear watchdog timer interrupt */ 154 /* Clear the watchdog expiration bit */
72 writel(~WDT_INT_REQ, BRIDGE_CAUSE); 155 atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0);
73 156
74 /* Enable watchdog timer */ 157 /* Enable watchdog timer */
75 reg = readl(wdt_reg + TIMER_CTRL); 158 atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit,
76 reg |= WDT_EN; 159 dev->data->wdt_enable_bit);
77 writel(reg, wdt_reg + TIMER_CTRL); 160
161 atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit,
162 dev->data->rstout_enable_bit);
163 return 0;
164}
165
166static int orion_start(struct watchdog_device *wdt_dev)
167{
168 struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
169
170 /* Set watchdog duration */
171 writel(dev->clk_rate * wdt_dev->timeout,
172 dev->reg + dev->data->wdt_counter_offset);
173
174 /* Enable watchdog timer */
175 atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit,
176 dev->data->wdt_enable_bit);
78 177
79 /* Enable reset on watchdog */ 178 /* Enable reset on watchdog */
80 reg = readl(RSTOUTn_MASK); 179 atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit,
81 reg |= WDT_RESET_OUT_EN; 180 dev->data->rstout_enable_bit);
82 writel(reg, RSTOUTn_MASK);
83 181
84 spin_unlock(&wdt_lock);
85 return 0; 182 return 0;
86} 183}
87 184
88static int orion_wdt_stop(struct watchdog_device *wdt_dev) 185static int orion_wdt_start(struct watchdog_device *wdt_dev)
89{ 186{
90 u32 reg; 187 struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
91 188
92 spin_lock(&wdt_lock); 189 /* There are some per-SoC quirks to handle */
190 return dev->data->start(wdt_dev);
191}
192
193static int orion_wdt_stop(struct watchdog_device *wdt_dev)
194{
195 struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
93 196
94 /* Disable reset on watchdog */ 197 /* Disable reset on watchdog */
95 reg = readl(RSTOUTn_MASK); 198 atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit, 0);
96 reg &= ~WDT_RESET_OUT_EN;
97 writel(reg, RSTOUTn_MASK);
98 199
99 /* Disable watchdog timer */ 200 /* Disable watchdog timer */
100 reg = readl(wdt_reg + TIMER_CTRL); 201 atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0);
101 reg &= ~WDT_EN;
102 writel(reg, wdt_reg + TIMER_CTRL);
103 202
104 spin_unlock(&wdt_lock);
105 return 0; 203 return 0;
106} 204}
107 205
108static unsigned int orion_wdt_get_timeleft(struct watchdog_device *wdt_dev) 206static int orion_wdt_enabled(struct orion_watchdog *dev)
109{ 207{
110 unsigned int time_left; 208 bool enabled, running;
209
210 enabled = readl(dev->rstout) & dev->data->rstout_enable_bit;
211 running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit;
111 212
112 spin_lock(&wdt_lock); 213 return enabled && running;
113 time_left = readl(wdt_reg + WDT_VAL) / wdt_tclk; 214}
114 spin_unlock(&wdt_lock);
115 215
116 return time_left; 216static unsigned int orion_wdt_get_timeleft(struct watchdog_device *wdt_dev)
217{
218 struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
219 return readl(dev->reg + dev->data->wdt_counter_offset) / dev->clk_rate;
117} 220}
118 221
119static int orion_wdt_set_timeout(struct watchdog_device *wdt_dev, 222static int orion_wdt_set_timeout(struct watchdog_device *wdt_dev,
@@ -137,68 +240,188 @@ static const struct watchdog_ops orion_wdt_ops = {
137 .get_timeleft = orion_wdt_get_timeleft, 240 .get_timeleft = orion_wdt_get_timeleft,
138}; 241};
139 242
140static struct watchdog_device orion_wdt = { 243static irqreturn_t orion_wdt_irq(int irq, void *devid)
141 .info = &orion_wdt_info, 244{
142 .ops = &orion_wdt_ops, 245 panic("Watchdog Timeout");
143 .min_timeout = 1, 246 return IRQ_HANDLED;
247}
248
249/*
250 * The original devicetree binding for this driver specified only
251 * one memory resource, so in order to keep DT backwards compatibility
252 * we try to fallback to a hardcoded register address, if the resource
253 * is missing from the devicetree.
254 */
255static void __iomem *orion_wdt_ioremap_rstout(struct platform_device *pdev,
256 phys_addr_t internal_regs)
257{
258 struct resource *res;
259 phys_addr_t rstout;
260
261 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
262 if (res)
263 return devm_ioremap(&pdev->dev, res->start,
264 resource_size(res));
265
266 /* This workaround works only for "orion-wdt", DT-enabled */
267 if (!of_device_is_compatible(pdev->dev.of_node, "marvell,orion-wdt"))
268 return NULL;
269
270 rstout = internal_regs + ORION_RSTOUT_MASK_OFFSET;
271
272 WARN(1, FW_BUG "falling back to harcoded RSTOUT reg 0x%x\n", rstout);
273 return devm_ioremap(&pdev->dev, rstout, 0x4);
274}
275
276static const struct orion_watchdog_data orion_data = {
277 .rstout_enable_bit = BIT(1),
278 .wdt_enable_bit = BIT(4),
279 .wdt_counter_offset = 0x24,
280 .clock_init = orion_wdt_clock_init,
281 .start = orion_start,
282};
283
284static const struct orion_watchdog_data armada370_data = {
285 .rstout_enable_bit = BIT(8),
286 .wdt_enable_bit = BIT(8),
287 .wdt_counter_offset = 0x34,
288 .clock_init = armada370_wdt_clock_init,
289 .start = armada370_start,
144}; 290};
145 291
292static const struct orion_watchdog_data armadaxp_data = {
293 .rstout_enable_bit = BIT(8),
294 .wdt_enable_bit = BIT(8),
295 .wdt_counter_offset = 0x34,
296 .clock_init = armadaxp_wdt_clock_init,
297 .start = armada370_start,
298};
299
300static const struct of_device_id orion_wdt_of_match_table[] = {
301 {
302 .compatible = "marvell,orion-wdt",
303 .data = &orion_data,
304 },
305 {
306 .compatible = "marvell,armada-370-wdt",
307 .data = &armada370_data,
308 },
309 {
310 .compatible = "marvell,armada-xp-wdt",
311 .data = &armadaxp_data,
312 },
313 {},
314};
315MODULE_DEVICE_TABLE(of, orion_wdt_of_match_table);
316
146static int orion_wdt_probe(struct platform_device *pdev) 317static int orion_wdt_probe(struct platform_device *pdev)
147{ 318{
319 struct orion_watchdog *dev;
320 const struct of_device_id *match;
321 unsigned int wdt_max_duration; /* (seconds) */
148 struct resource *res; 322 struct resource *res;
149 int ret; 323 int ret, irq;
150 324
151 clk = devm_clk_get(&pdev->dev, NULL); 325 dev = devm_kzalloc(&pdev->dev, sizeof(struct orion_watchdog),
152 if (IS_ERR(clk)) { 326 GFP_KERNEL);
153 dev_err(&pdev->dev, "Orion Watchdog missing clock\n"); 327 if (!dev)
154 return -ENODEV; 328 return -ENOMEM;
155 } 329
156 clk_prepare_enable(clk); 330 match = of_match_device(orion_wdt_of_match_table, &pdev->dev);
157 wdt_tclk = clk_get_rate(clk); 331 if (!match)
332 /* Default legacy match */
333 match = &orion_wdt_of_match_table[0];
334
335 dev->wdt.info = &orion_wdt_info;
336 dev->wdt.ops = &orion_wdt_ops;
337 dev->wdt.min_timeout = 1;
338 dev->data = match->data;
158 339
159 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 340 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
160 if (!res) 341 if (!res)
161 return -ENODEV; 342 return -ENODEV;
162 wdt_reg = devm_ioremap(&pdev->dev, res->start, resource_size(res));
163 if (!wdt_reg)
164 return -ENOMEM;
165 343
166 wdt_max_duration = WDT_MAX_CYCLE_COUNT / wdt_tclk; 344 dev->reg = devm_ioremap(&pdev->dev, res->start,
345 resource_size(res));
346 if (!dev->reg)
347 return -ENOMEM;
167 348
168 orion_wdt.timeout = wdt_max_duration; 349 dev->rstout = orion_wdt_ioremap_rstout(pdev, res->start &
169 orion_wdt.max_timeout = wdt_max_duration; 350 INTERNAL_REGS_MASK);
170 watchdog_init_timeout(&orion_wdt, heartbeat, &pdev->dev); 351 if (!dev->rstout)
352 return -ENODEV;
171 353
172 watchdog_set_nowayout(&orion_wdt, nowayout); 354 ret = dev->data->clock_init(pdev, dev);
173 ret = watchdog_register_device(&orion_wdt);
174 if (ret) { 355 if (ret) {
175 clk_disable_unprepare(clk); 356 dev_err(&pdev->dev, "cannot initialize clock\n");
176 return ret; 357 return ret;
177 } 358 }
178 359
360 wdt_max_duration = WDT_MAX_CYCLE_COUNT / dev->clk_rate;
361
362 dev->wdt.timeout = wdt_max_duration;
363 dev->wdt.max_timeout = wdt_max_duration;
364 watchdog_init_timeout(&dev->wdt, heartbeat, &pdev->dev);
365
366 platform_set_drvdata(pdev, &dev->wdt);
367 watchdog_set_drvdata(&dev->wdt, dev);
368
369 /*
370 * Let's make sure the watchdog is fully stopped, unless it's
371 * explicitly enabled. This may be the case if the module was
372 * removed and re-insterted, or if the bootloader explicitly
373 * set a running watchdog before booting the kernel.
374 */
375 if (!orion_wdt_enabled(dev))
376 orion_wdt_stop(&dev->wdt);
377
378 /* Request the IRQ only after the watchdog is disabled */
379 irq = platform_get_irq(pdev, 0);
380 if (irq > 0) {
381 /*
382 * Not all supported platforms specify an interrupt for the
383 * watchdog, so let's make it optional.
384 */
385 ret = devm_request_irq(&pdev->dev, irq, orion_wdt_irq, 0,
386 pdev->name, dev);
387 if (ret < 0) {
388 dev_err(&pdev->dev, "failed to request IRQ\n");
389 goto disable_clk;
390 }
391 }
392
393 watchdog_set_nowayout(&dev->wdt, nowayout);
394 ret = watchdog_register_device(&dev->wdt);
395 if (ret)
396 goto disable_clk;
397
179 pr_info("Initial timeout %d sec%s\n", 398 pr_info("Initial timeout %d sec%s\n",
180 orion_wdt.timeout, nowayout ? ", nowayout" : ""); 399 dev->wdt.timeout, nowayout ? ", nowayout" : "");
181 return 0; 400 return 0;
401
402disable_clk:
403 clk_disable_unprepare(dev->clk);
404 clk_put(dev->clk);
405 return ret;
182} 406}
183 407
184static int orion_wdt_remove(struct platform_device *pdev) 408static int orion_wdt_remove(struct platform_device *pdev)
185{ 409{
186 watchdog_unregister_device(&orion_wdt); 410 struct watchdog_device *wdt_dev = platform_get_drvdata(pdev);
187 clk_disable_unprepare(clk); 411 struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
412
413 watchdog_unregister_device(wdt_dev);
414 clk_disable_unprepare(dev->clk);
415 clk_put(dev->clk);
188 return 0; 416 return 0;
189} 417}
190 418
191static void orion_wdt_shutdown(struct platform_device *pdev) 419static void orion_wdt_shutdown(struct platform_device *pdev)
192{ 420{
193 orion_wdt_stop(&orion_wdt); 421 struct watchdog_device *wdt_dev = platform_get_drvdata(pdev);
422 orion_wdt_stop(wdt_dev);
194} 423}
195 424
196static const struct of_device_id orion_wdt_of_match_table[] = {
197 { .compatible = "marvell,orion-wdt", },
198 {},
199};
200MODULE_DEVICE_TABLE(of, orion_wdt_of_match_table);
201
202static struct platform_driver orion_wdt_driver = { 425static struct platform_driver orion_wdt_driver = {
203 .probe = orion_wdt_probe, 426 .probe = orion_wdt_probe,
204 .remove = orion_wdt_remove, 427 .remove = orion_wdt_remove,