diff options
author | Ingo Molnar <mingo@elte.hu> | 2009-09-02 02:17:56 -0400 |
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committer | Ingo Molnar <mingo@elte.hu> | 2009-09-02 02:17:56 -0400 |
commit | 936e894a976dd3b0f07f1f6f43c17b77b7e6146d (patch) | |
tree | 5ed5c1f6735dcd26550594df23c8f7fe2aa21a15 /drivers/watchdog/coh901327_wdt.c | |
parent | 69575d388603365f2afbf4166df93152df59b165 (diff) | |
parent | 326ba5010a5429a5a528b268b36a5900d4ab0eba (diff) |
Merge commit 'v2.6.31-rc8' into x86/txt
Conflicts:
arch/x86/kernel/reboot.c
security/Kconfig
Merge reason: resolve the conflicts, bump up from rc3 to rc8.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'drivers/watchdog/coh901327_wdt.c')
-rw-r--r-- | drivers/watchdog/coh901327_wdt.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/watchdog/coh901327_wdt.c b/drivers/watchdog/coh901327_wdt.c index fecb307d28e9..aec7cefdef21 100644 --- a/drivers/watchdog/coh901327_wdt.c +++ b/drivers/watchdog/coh901327_wdt.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/bitops.h> | 18 | #include <linux/bitops.h> |
19 | #include <linux/uaccess.h> | 19 | #include <linux/uaccess.h> |
20 | #include <linux/clk.h> | 20 | #include <linux/clk.h> |
21 | #include <linux/delay.h> | ||
21 | 22 | ||
22 | #define DRV_NAME "WDOG COH 901 327" | 23 | #define DRV_NAME "WDOG COH 901 327" |
23 | 24 | ||
@@ -92,6 +93,8 @@ static struct clk *clk; | |||
92 | static void coh901327_enable(u16 timeout) | 93 | static void coh901327_enable(u16 timeout) |
93 | { | 94 | { |
94 | u16 val; | 95 | u16 val; |
96 | unsigned long freq; | ||
97 | unsigned long delay_ns; | ||
95 | 98 | ||
96 | clk_enable(clk); | 99 | clk_enable(clk); |
97 | /* Restart timer if it is disabled */ | 100 | /* Restart timer if it is disabled */ |
@@ -102,6 +105,14 @@ static void coh901327_enable(u16 timeout) | |||
102 | /* Acknowledge any pending interrupt so it doesn't just fire off */ | 105 | /* Acknowledge any pending interrupt so it doesn't just fire off */ |
103 | writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE, | 106 | writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE, |
104 | virtbase + U300_WDOG_IER); | 107 | virtbase + U300_WDOG_IER); |
108 | /* | ||
109 | * The interrupt is cleared in the 32 kHz clock domain. | ||
110 | * Wait 3 32 kHz cycles for it to take effect | ||
111 | */ | ||
112 | freq = clk_get_rate(clk); | ||
113 | delay_ns = (1000000000 + freq - 1) / freq; /* Freq to ns and round up */ | ||
114 | delay_ns = 3 * delay_ns; /* Wait 3 cycles */ | ||
115 | ndelay(delay_ns); | ||
105 | /* Enable the watchdog interrupt */ | 116 | /* Enable the watchdog interrupt */ |
106 | writew(U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE, virtbase + U300_WDOG_IMR); | 117 | writew(U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE, virtbase + U300_WDOG_IMR); |
107 | /* Activate the watchdog timer */ | 118 | /* Activate the watchdog timer */ |