diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-11-01 13:43:31 -0400 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-11-28 09:50:39 -0500 |
| commit | c1c30a29df7e47310caa979dc48f715ae478de5f (patch) | |
| tree | bea09972cee59473033064e55a649105e86525a7 /drivers/watchdog/at91sam9_wdt.h | |
| parent | f22deee523e0ff49c3be01dd6f979d374230725a (diff) | |
ARM: at91: make watchdog drivers soc independent
switch the watchdog drivers to resource and pass it via platform_device
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'drivers/watchdog/at91sam9_wdt.h')
| -rw-r--r-- | drivers/watchdog/at91sam9_wdt.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/watchdog/at91sam9_wdt.h b/drivers/watchdog/at91sam9_wdt.h index 757f9cab5c82..c6fbb2e6c41b 100644 --- a/drivers/watchdog/at91sam9_wdt.h +++ b/drivers/watchdog/at91sam9_wdt.h | |||
| @@ -16,11 +16,11 @@ | |||
| 16 | #ifndef AT91_WDT_H | 16 | #ifndef AT91_WDT_H |
| 17 | #define AT91_WDT_H | 17 | #define AT91_WDT_H |
| 18 | 18 | ||
| 19 | #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ | 19 | #define AT91_WDT_CR 0x00 /* Watchdog Control Register */ |
| 20 | #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ | 20 | #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ |
| 21 | #define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ | 21 | #define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ |
| 22 | 22 | ||
| 23 | #define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ | 23 | #define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ |
| 24 | #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ | 24 | #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ |
| 25 | #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ | 25 | #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ |
| 26 | #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ | 26 | #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ |
| @@ -30,7 +30,7 @@ | |||
| 30 | #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ | 30 | #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ |
| 31 | #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ | 31 | #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ |
| 32 | 32 | ||
| 33 | #define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ | 33 | #define AT91_WDT_SR 0x08 /* Watchdog Status Register */ |
| 34 | #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ | 34 | #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ |
| 35 | #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ | 35 | #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ |
| 36 | 36 | ||