WATCHDOG: Add watchdog driver for OCTEON SOCs

The OCTEON is a MIPS64 based SOC family with an on chip watchdog unit.

The driver is split into two source files one for the C code and one
for assembly.  Assembly is needed to handle the NMI and then print the
machine state before the reboot is triggered.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: Wim Van Sebroeck <wim@iguana.be>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Marc Zyngier <maz@misterjones.org>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Sam Ravnborg <sam@ravnborg.org>
To: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org,
Patchwork: https://patchwork.linux-mips.org/patch/1503/
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

 create mode 100644 drivers/watchdog/octeon-wdt-main.c
 create mode 100644 drivers/watchdog/octeon-wdt-nmi.S

1 files changed, 18 insertions, 0 deletions

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index afcfacc9bbe2..b04b18468932 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -875,6 +875,24 @@ config TXX9_WDT
         help
           Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
 
+config OCTEON_WDT
+        tristate "Cavium OCTEON SOC family Watchdog Timer"
+        depends on CPU_CAVIUM_OCTEON
+        default y
+        select EXPORT_UASM if OCTEON_WDT = m
+        help
+          Hardware driver for OCTEON's on chip watchdog timer.
+          Enables the watchdog for all cores running Linux. It
+          installs a NMI handler and pokes the watchdog based on an
+          interrupt.  On first expiration of the watchdog, the
+          interrupt handler pokes it.  The second expiration causes an
+          NMI that prints a message. The third expiration causes a
+          global soft reset.
+
+          When userspace has /dev/watchdog open, no poking is done
+          from the first interrupt, it is then only poked when the
+          device is written.
+
 # PARISC Architecture
 
 # POWERPC Architecture