aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/video
diff options
context:
space:
mode:
authorArchit Taneja <archit@ti.com>2011-01-31 11:27:44 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-03-11 08:46:22 -0500
commit6af9cd1431db952a7f9f8931497c9989a48b07df (patch)
treeb2149896379347185e80b75585a44078a805f7a9 /drivers/video
parent872462cdfc74e7b93c09870128d9bb436d4e9804 (diff)
OMAP2PLUS: DSS2: Generalize naming of PRCM related clock enums in DSS driver
enum dss_clock structure is replaced with generic names that could be used across OMAP2420, 2430, 3xxx, 44xx platforms. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/omap2/dss/core.c4
-rw-r--r--drivers/video/omap2/dss/dispc.c10
-rw-r--r--drivers/video/omap2/dss/dpi.c16
-rw-r--r--drivers/video/omap2/dss/dsi.c18
-rw-r--r--drivers/video/omap2/dss/dss.c62
-rw-r--r--drivers/video/omap2/dss/dss.h10
-rw-r--r--drivers/video/omap2/dss/manager.c4
-rw-r--r--drivers/video/omap2/dss/overlay.c4
-rw-r--r--drivers/video/omap2/dss/rfbi.c10
-rw-r--r--drivers/video/omap2/dss/sdi.c8
-rw-r--r--drivers/video/omap2/dss/venc.c8
11 files changed, 77 insertions, 77 deletions
diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
index 3f7a5fcd1142..f56ee64f5b58 100644
--- a/drivers/video/omap2/dss/core.c
+++ b/drivers/video/omap2/dss/core.c
@@ -184,7 +184,7 @@ static int omap_dss_probe(struct platform_device *pdev)
184 } 184 }
185 185
186 /* keep clocks enabled to prevent context saves/restores during init */ 186 /* keep clocks enabled to prevent context saves/restores during init */
187 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 187 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
188 188
189 r = rfbi_init_platform_driver(); 189 r = rfbi_init_platform_driver();
190 if (r) { 190 if (r) {
@@ -251,7 +251,7 @@ static int omap_dss_probe(struct platform_device *pdev)
251 pdata->default_device = dssdev; 251 pdata->default_device = dssdev;
252 } 252 }
253 253
254 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 254 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
255 255
256 return 0; 256 return 0;
257 257
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 96e37f8e75dc..dc4518c4b0e4 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -551,9 +551,9 @@ void dispc_restore_context(void)
551static inline void enable_clocks(bool enable) 551static inline void enable_clocks(bool enable)
552{ 552{
553 if (enable) 553 if (enable)
554 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 554 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
555 else 555 else
556 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 556 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
557} 557}
558 558
559bool dispc_go_busy(enum omap_channel channel) 559bool dispc_go_busy(enum omap_channel channel)
@@ -2311,7 +2311,7 @@ unsigned long dispc_fclk_rate(void)
2311 unsigned long r = 0; 2311 unsigned long r = 0;
2312 2312
2313 if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) 2313 if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
2314 r = dss_clk_get_rate(DSS_CLK_FCK1); 2314 r = dss_clk_get_rate(DSS_CLK_FCK);
2315 else 2315 else
2316#ifdef CONFIG_OMAP2_DSS_DSI 2316#ifdef CONFIG_OMAP2_DSS_DSI
2317 r = dsi_get_dsi1_pll_rate(); 2317 r = dsi_get_dsi1_pll_rate();
@@ -2439,7 +2439,7 @@ void dispc_dump_regs(struct seq_file *s)
2439{ 2439{
2440#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r)) 2440#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2441 2441
2442 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 2442 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
2443 2443
2444 DUMPREG(DISPC_REVISION); 2444 DUMPREG(DISPC_REVISION);
2445 DUMPREG(DISPC_SYSCONFIG); 2445 DUMPREG(DISPC_SYSCONFIG);
@@ -2596,7 +2596,7 @@ void dispc_dump_regs(struct seq_file *s)
2596 DUMPREG(DISPC_VID_PRELOAD(0)); 2596 DUMPREG(DISPC_VID_PRELOAD(0));
2597 DUMPREG(DISPC_VID_PRELOAD(1)); 2597 DUMPREG(DISPC_VID_PRELOAD(1));
2598 2598
2599 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 2599 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
2600#undef DUMPREG 2600#undef DUMPREG
2601} 2601}
2602 2602
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 75fb0a515430..746f1b6dd897 100644
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -107,7 +107,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
107 bool is_tft; 107 bool is_tft;
108 int r = 0; 108 int r = 0;
109 109
110 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 110 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
111 111
112 dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config, 112 dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
113 dssdev->panel.acbi, dssdev->panel.acb); 113 dssdev->panel.acbi, dssdev->panel.acb);
@@ -137,7 +137,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
137 dispc_set_lcd_timings(dssdev->manager->id, t); 137 dispc_set_lcd_timings(dssdev->manager->id, t);
138 138
139err0: 139err0:
140 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 140 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
141 return r; 141 return r;
142} 142}
143 143
@@ -173,14 +173,14 @@ int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
173 goto err1; 173 goto err1;
174 } 174 }
175 175
176 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 176 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
177 177
178 r = dpi_basic_init(dssdev); 178 r = dpi_basic_init(dssdev);
179 if (r) 179 if (r)
180 goto err2; 180 goto err2;
181 181
182#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL 182#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
183 dss_clk_enable(DSS_CLK_FCK2); 183 dss_clk_enable(DSS_CLK_SYSCK);
184 r = dsi_pll_init(dssdev, 0, 1); 184 r = dsi_pll_init(dssdev, 0, 1);
185 if (r) 185 if (r)
186 goto err3; 186 goto err3;
@@ -199,10 +199,10 @@ err4:
199#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL 199#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
200 dsi_pll_uninit(); 200 dsi_pll_uninit();
201err3: 201err3:
202 dss_clk_disable(DSS_CLK_FCK2); 202 dss_clk_disable(DSS_CLK_SYSCK);
203#endif 203#endif
204err2: 204err2:
205 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 205 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
206 if (cpu_is_omap34xx()) 206 if (cpu_is_omap34xx())
207 regulator_disable(dpi.vdds_dsi_reg); 207 regulator_disable(dpi.vdds_dsi_reg);
208err1: 208err1:
@@ -219,10 +219,10 @@ void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
219#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL 219#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
220 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); 220 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
221 dsi_pll_uninit(); 221 dsi_pll_uninit();
222 dss_clk_disable(DSS_CLK_FCK2); 222 dss_clk_disable(DSS_CLK_SYSCK);
223#endif 223#endif
224 224
225 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 225 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
226 226
227 if (cpu_is_omap34xx()) 227 if (cpu_is_omap34xx())
228 regulator_disable(dpi.vdds_dsi_reg); 228 regulator_disable(dpi.vdds_dsi_reg);
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index c42acae10af0..c7b5382e1a6b 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -654,18 +654,18 @@ static void dsi_vc_disable_bta_irq(int channel)
654static inline void enable_clocks(bool enable) 654static inline void enable_clocks(bool enable)
655{ 655{
656 if (enable) 656 if (enable)
657 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 657 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
658 else 658 else
659 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 659 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
660} 660}
661 661
662/* source clock for DSI PLL. this could also be PCLKFREE */ 662/* source clock for DSI PLL. this could also be PCLKFREE */
663static inline void dsi_enable_pll_clock(bool enable) 663static inline void dsi_enable_pll_clock(bool enable)
664{ 664{
665 if (enable) 665 if (enable)
666 dss_clk_enable(DSS_CLK_FCK2); 666 dss_clk_enable(DSS_CLK_SYSCK);
667 else 667 else
668 dss_clk_disable(DSS_CLK_FCK2); 668 dss_clk_disable(DSS_CLK_SYSCK);
669 669
670 if (enable && dsi.pll_locked) { 670 if (enable && dsi.pll_locked) {
671 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) 671 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
@@ -741,7 +741,7 @@ static unsigned long dsi_fclk_rate(void)
741 741
742 if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) { 742 if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
743 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */ 743 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
744 r = dss_clk_get_rate(DSS_CLK_FCK1); 744 r = dss_clk_get_rate(DSS_CLK_FCK);
745 } else { 745 } else {
746 /* DSI FCLK source is DSI2_PLL_FCLK */ 746 /* DSI FCLK source is DSI2_PLL_FCLK */
747 r = dsi_get_dsi2_pll_rate(); 747 r = dsi_get_dsi2_pll_rate();
@@ -821,7 +821,7 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
821 return -EINVAL; 821 return -EINVAL;
822 822
823 if (cinfo->use_dss2_fck) { 823 if (cinfo->use_dss2_fck) {
824 cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2); 824 cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK);
825 /* XXX it is unclear if highfreq should be used 825 /* XXX it is unclear if highfreq should be used
826 * with DSS2_FCK source also */ 826 * with DSS2_FCK source also */
827 cinfo->highfreq = 0; 827 cinfo->highfreq = 0;
@@ -867,7 +867,7 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
867 int match = 0; 867 int match = 0;
868 unsigned long dss_clk_fck2; 868 unsigned long dss_clk_fck2;
869 869
870 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2); 870 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK);
871 871
872 if (req_pck == dsi.cache_req_pck && 872 if (req_pck == dsi.cache_req_pck &&
873 dsi.cache_cinfo.clkin == dss_clk_fck2) { 873 dsi.cache_cinfo.clkin == dss_clk_fck2) {
@@ -1319,7 +1319,7 @@ void dsi_dump_regs(struct seq_file *s)
1319{ 1319{
1320#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r)) 1320#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1321 1321
1322 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 1322 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
1323 1323
1324 DUMPREG(DSI_REVISION); 1324 DUMPREG(DSI_REVISION);
1325 DUMPREG(DSI_SYSCONFIG); 1325 DUMPREG(DSI_SYSCONFIG);
@@ -1391,7 +1391,7 @@ void dsi_dump_regs(struct seq_file *s)
1391 DUMPREG(DSI_PLL_CONFIGURATION1); 1391 DUMPREG(DSI_PLL_CONFIGURATION1);
1392 DUMPREG(DSI_PLL_CONFIGURATION2); 1392 DUMPREG(DSI_PLL_CONFIGURATION2);
1393 1393
1394 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 1394 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
1395#undef DUMPREG 1395#undef DUMPREG
1396} 1396}
1397 1397
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 56d37bfefd4d..0372befbb692 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -227,7 +227,7 @@ void dss_dump_clocks(struct seq_file *s)
227 unsigned long dpll4_ck_rate; 227 unsigned long dpll4_ck_rate;
228 unsigned long dpll4_m4_ck_rate; 228 unsigned long dpll4_m4_ck_rate;
229 229
230 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 230 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
231 231
232 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); 232 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
233 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); 233 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
@@ -240,21 +240,21 @@ void dss_dump_clocks(struct seq_file *s)
240 seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n", 240 seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n",
241 dpll4_ck_rate, 241 dpll4_ck_rate,
242 dpll4_ck_rate / dpll4_m4_ck_rate, 242 dpll4_ck_rate / dpll4_m4_ck_rate,
243 dss_clk_get_rate(DSS_CLK_FCK1)); 243 dss_clk_get_rate(DSS_CLK_FCK));
244 else 244 else
245 seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n", 245 seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
246 dpll4_ck_rate, 246 dpll4_ck_rate,
247 dpll4_ck_rate / dpll4_m4_ck_rate, 247 dpll4_ck_rate / dpll4_m4_ck_rate,
248 dss_clk_get_rate(DSS_CLK_FCK1)); 248 dss_clk_get_rate(DSS_CLK_FCK));
249 249
250 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 250 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
251} 251}
252 252
253void dss_dump_regs(struct seq_file *s) 253void dss_dump_regs(struct seq_file *s)
254{ 254{
255#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) 255#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
256 256
257 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 257 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
258 258
259 DUMPREG(DSS_REVISION); 259 DUMPREG(DSS_REVISION);
260 DUMPREG(DSS_SYSCONFIG); 260 DUMPREG(DSS_SYSCONFIG);
@@ -265,7 +265,7 @@ void dss_dump_regs(struct seq_file *s)
265 DUMPREG(DSS_PLL_CONTROL); 265 DUMPREG(DSS_PLL_CONTROL);
266 DUMPREG(DSS_SDI_STATUS); 266 DUMPREG(DSS_SDI_STATUS);
267 267
268 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 268 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
269#undef DUMPREG 269#undef DUMPREG
270} 270}
271 271
@@ -350,7 +350,7 @@ int dss_set_clock_div(struct dss_clock_info *cinfo)
350 350
351int dss_get_clock_div(struct dss_clock_info *cinfo) 351int dss_get_clock_div(struct dss_clock_info *cinfo)
352{ 352{
353 cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1); 353 cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
354 354
355 if (cpu_is_omap34xx()) { 355 if (cpu_is_omap34xx()) {
356 unsigned long prate; 356 unsigned long prate;
@@ -391,7 +391,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
391 391
392 prate = dss_get_dpll4_rate(); 392 prate = dss_get_dpll4_rate();
393 393
394 fck = dss_clk_get_rate(DSS_CLK_FCK1); 394 fck = dss_clk_get_rate(DSS_CLK_FCK);
395 if (req_pck == dss.cache_req_pck && 395 if (req_pck == dss.cache_req_pck &&
396 ((cpu_is_omap34xx() && prate == dss.cache_prate) || 396 ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
397 dss.cache_dss_cinfo.fck == fck)) { 397 dss.cache_dss_cinfo.fck == fck)) {
@@ -418,7 +418,7 @@ retry:
418 if (cpu_is_omap24xx()) { 418 if (cpu_is_omap24xx()) {
419 struct dispc_clock_info cur_dispc; 419 struct dispc_clock_info cur_dispc;
420 /* XXX can we change the clock on omap2? */ 420 /* XXX can we change the clock on omap2? */
421 fck = dss_clk_get_rate(DSS_CLK_FCK1); 421 fck = dss_clk_get_rate(DSS_CLK_FCK);
422 fck_div = 1; 422 fck_div = 1;
423 423
424 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); 424 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
@@ -701,7 +701,7 @@ static void save_all_ctx(void)
701{ 701{
702 DSSDBG("save context\n"); 702 DSSDBG("save context\n");
703 703
704 dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); 704 dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
705 705
706 dss_save_context(); 706 dss_save_context();
707 dispc_save_context(); 707 dispc_save_context();
@@ -709,7 +709,7 @@ static void save_all_ctx(void)
709 dsi_save_context(); 709 dsi_save_context();
710#endif 710#endif
711 711
712 dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); 712 dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
713} 713}
714 714
715static void restore_all_ctx(void) 715static void restore_all_ctx(void)
@@ -807,13 +807,13 @@ unsigned long dss_clk_get_rate(enum dss_clock clk)
807 switch (clk) { 807 switch (clk) {
808 case DSS_CLK_ICK: 808 case DSS_CLK_ICK:
809 return clk_get_rate(dss.dss_ick); 809 return clk_get_rate(dss.dss_ick);
810 case DSS_CLK_FCK1: 810 case DSS_CLK_FCK:
811 return clk_get_rate(dss.dss1_fck); 811 return clk_get_rate(dss.dss1_fck);
812 case DSS_CLK_FCK2: 812 case DSS_CLK_SYSCK:
813 return clk_get_rate(dss.dss2_fck); 813 return clk_get_rate(dss.dss2_fck);
814 case DSS_CLK_54M: 814 case DSS_CLK_TVFCK:
815 return clk_get_rate(dss.dss_54m_fck); 815 return clk_get_rate(dss.dss_54m_fck);
816 case DSS_CLK_96M: 816 case DSS_CLK_VIDFCK:
817 return clk_get_rate(dss.dss_96m_fck); 817 return clk_get_rate(dss.dss_96m_fck);
818 } 818 }
819 819
@@ -827,13 +827,13 @@ static unsigned count_clk_bits(enum dss_clock clks)
827 827
828 if (clks & DSS_CLK_ICK) 828 if (clks & DSS_CLK_ICK)
829 ++num_clks; 829 ++num_clks;
830 if (clks & DSS_CLK_FCK1) 830 if (clks & DSS_CLK_FCK)
831 ++num_clks; 831 ++num_clks;
832 if (clks & DSS_CLK_FCK2) 832 if (clks & DSS_CLK_SYSCK)
833 ++num_clks; 833 ++num_clks;
834 if (clks & DSS_CLK_54M) 834 if (clks & DSS_CLK_TVFCK)
835 ++num_clks; 835 ++num_clks;
836 if (clks & DSS_CLK_96M) 836 if (clks & DSS_CLK_VIDFCK)
837 ++num_clks; 837 ++num_clks;
838 838
839 return num_clks; 839 return num_clks;
@@ -845,13 +845,13 @@ static void dss_clk_enable_no_ctx(enum dss_clock clks)
845 845
846 if (clks & DSS_CLK_ICK) 846 if (clks & DSS_CLK_ICK)
847 clk_enable(dss.dss_ick); 847 clk_enable(dss.dss_ick);
848 if (clks & DSS_CLK_FCK1) 848 if (clks & DSS_CLK_FCK)
849 clk_enable(dss.dss1_fck); 849 clk_enable(dss.dss1_fck);
850 if (clks & DSS_CLK_FCK2) 850 if (clks & DSS_CLK_SYSCK)
851 clk_enable(dss.dss2_fck); 851 clk_enable(dss.dss2_fck);
852 if (clks & DSS_CLK_54M) 852 if (clks & DSS_CLK_TVFCK)
853 clk_enable(dss.dss_54m_fck); 853 clk_enable(dss.dss_54m_fck);
854 if (clks & DSS_CLK_96M) 854 if (clks & DSS_CLK_VIDFCK)
855 clk_enable(dss.dss_96m_fck); 855 clk_enable(dss.dss_96m_fck);
856 856
857 dss.num_clks_enabled += num_clks; 857 dss.num_clks_enabled += num_clks;
@@ -873,13 +873,13 @@ static void dss_clk_disable_no_ctx(enum dss_clock clks)
873 873
874 if (clks & DSS_CLK_ICK) 874 if (clks & DSS_CLK_ICK)
875 clk_disable(dss.dss_ick); 875 clk_disable(dss.dss_ick);
876 if (clks & DSS_CLK_FCK1) 876 if (clks & DSS_CLK_FCK)
877 clk_disable(dss.dss1_fck); 877 clk_disable(dss.dss1_fck);
878 if (clks & DSS_CLK_FCK2) 878 if (clks & DSS_CLK_SYSCK)
879 clk_disable(dss.dss2_fck); 879 clk_disable(dss.dss2_fck);
880 if (clks & DSS_CLK_54M) 880 if (clks & DSS_CLK_TVFCK)
881 clk_disable(dss.dss_54m_fck); 881 clk_disable(dss.dss_54m_fck);
882 if (clks & DSS_CLK_96M) 882 if (clks & DSS_CLK_VIDFCK)
883 clk_disable(dss.dss_96m_fck); 883 clk_disable(dss.dss_96m_fck);
884 884
885 dss.num_clks_enabled -= num_clks; 885 dss.num_clks_enabled -= num_clks;
@@ -903,9 +903,9 @@ static void dss_clk_enable_all_no_ctx(void)
903{ 903{
904 enum dss_clock clks; 904 enum dss_clock clks;
905 905
906 clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; 906 clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
907 if (cpu_is_omap34xx()) 907 if (cpu_is_omap34xx())
908 clks |= DSS_CLK_96M; 908 clks |= DSS_CLK_VIDFCK;
909 dss_clk_enable_no_ctx(clks); 909 dss_clk_enable_no_ctx(clks);
910} 910}
911 911
@@ -913,9 +913,9 @@ static void dss_clk_disable_all_no_ctx(void)
913{ 913{
914 enum dss_clock clks; 914 enum dss_clock clks;
915 915
916 clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; 916 clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
917 if (cpu_is_omap34xx()) 917 if (cpu_is_omap34xx())
918 clks |= DSS_CLK_96M; 918 clks |= DSS_CLK_VIDFCK;
919 dss_clk_disable_no_ctx(clks); 919 dss_clk_disable_no_ctx(clks);
920} 920}
921 921
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 981d247c30f2..4b02e079f20e 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -112,11 +112,11 @@ enum omap_parallel_interface_mode {
112}; 112};
113 113
114enum dss_clock { 114enum dss_clock {
115 DSS_CLK_ICK = 1 << 0, 115 DSS_CLK_ICK = 1 << 0, /* DSS_L3_ICLK and DSS_L4_ICLK */
116 DSS_CLK_FCK1 = 1 << 1, 116 DSS_CLK_FCK = 1 << 1, /* DSS1_ALWON_FCLK */
117 DSS_CLK_FCK2 = 1 << 2, 117 DSS_CLK_SYSCK = 1 << 2, /* DSS2_ALWON_FCLK */
118 DSS_CLK_54M = 1 << 3, 118 DSS_CLK_TVFCK = 1 << 3, /* DSS_TV_FCLK */
119 DSS_CLK_96M = 1 << 4, 119 DSS_CLK_VIDFCK = 1 << 4, /* DSS_96M_FCLK*/
120}; 120};
121 121
122enum dss_clk_source { 122enum dss_clk_source {
diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
index 172d4e697309..1f53bf20b6cb 100644
--- a/drivers/video/omap2/dss/manager.c
+++ b/drivers/video/omap2/dss/manager.c
@@ -1394,7 +1394,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
1394 } 1394 }
1395 1395
1396 r = 0; 1396 r = 0;
1397 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 1397 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
1398 if (!dss_cache.irq_enabled) { 1398 if (!dss_cache.irq_enabled) {
1399 u32 mask; 1399 u32 mask;
1400 1400
@@ -1407,7 +1407,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
1407 dss_cache.irq_enabled = true; 1407 dss_cache.irq_enabled = true;
1408 } 1408 }
1409 configure_dispc(); 1409 configure_dispc();
1410 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 1410 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
1411 1411
1412 spin_unlock_irqrestore(&dss_cache.lock, flags); 1412 spin_unlock_irqrestore(&dss_cache.lock, flags);
1413 1413
diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
index 456efef03c20..996e9a4f6771 100644
--- a/drivers/video/omap2/dss/overlay.c
+++ b/drivers/video/omap2/dss/overlay.c
@@ -490,7 +490,7 @@ static int omap_dss_set_manager(struct omap_overlay *ovl,
490 490
491 ovl->manager = mgr; 491 ovl->manager = mgr;
492 492
493 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 493 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
494 /* XXX: on manual update display, in auto update mode, a bug happens 494 /* XXX: on manual update display, in auto update mode, a bug happens
495 * here. When an overlay is first enabled on LCD, then it's disabled, 495 * here. When an overlay is first enabled on LCD, then it's disabled,
496 * and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT 496 * and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT
@@ -499,7 +499,7 @@ static int omap_dss_set_manager(struct omap_overlay *ovl,
499 * but I don't understand how or why. */ 499 * but I don't understand how or why. */
500 msleep(40); 500 msleep(40);
501 dispc_set_channel_out(ovl->id, mgr->id); 501 dispc_set_channel_out(ovl->id, mgr->id);
502 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 502 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
503 503
504 return 0; 504 return 0;
505} 505}
diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
index 6dbb95d557f8..5ea17f49c611 100644
--- a/drivers/video/omap2/dss/rfbi.c
+++ b/drivers/video/omap2/dss/rfbi.c
@@ -141,9 +141,9 @@ static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
141static void rfbi_enable_clocks(bool enable) 141static void rfbi_enable_clocks(bool enable)
142{ 142{
143 if (enable) 143 if (enable)
144 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 144 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
145 else 145 else
146 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 146 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
147} 147}
148 148
149void omap_rfbi_write_command(const void *buf, u32 len) 149void omap_rfbi_write_command(const void *buf, u32 len)
@@ -496,7 +496,7 @@ unsigned long rfbi_get_max_tx_rate(void)
496 }; 496 };
497 497
498 l4_rate = rfbi.l4_khz / 1000; 498 l4_rate = rfbi.l4_khz / 1000;
499 dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000; 499 dss1_rate = dss_clk_get_rate(DSS_CLK_FCK) / 1000000;
500 500
501 for (i = 0; i < ARRAY_SIZE(ftab); i++) { 501 for (i = 0; i < ARRAY_SIZE(ftab); i++) {
502 /* Use a window instead of an exact match, to account 502 /* Use a window instead of an exact match, to account
@@ -921,7 +921,7 @@ void rfbi_dump_regs(struct seq_file *s)
921{ 921{
922#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r)) 922#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
923 923
924 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 924 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
925 925
926 DUMPREG(RFBI_REVISION); 926 DUMPREG(RFBI_REVISION);
927 DUMPREG(RFBI_SYSCONFIG); 927 DUMPREG(RFBI_SYSCONFIG);
@@ -952,7 +952,7 @@ void rfbi_dump_regs(struct seq_file *s)
952 DUMPREG(RFBI_VSYNC_WIDTH); 952 DUMPREG(RFBI_VSYNC_WIDTH);
953 DUMPREG(RFBI_HSYNC_WIDTH); 953 DUMPREG(RFBI_HSYNC_WIDTH);
954 954
955 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 955 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
956#undef DUMPREG 956#undef DUMPREG
957} 957}
958 958
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
index b64adf7dfc88..8272fc1f3279 100644
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@ -70,7 +70,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
70 70
71 /* In case of skip_init sdi_init has already enabled the clocks */ 71 /* In case of skip_init sdi_init has already enabled the clocks */
72 if (!sdi.skip_init) 72 if (!sdi.skip_init)
73 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 73 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
74 74
75 sdi_basic_init(dssdev); 75 sdi_basic_init(dssdev);
76 76
@@ -130,7 +130,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
130 130
131 return 0; 131 return 0;
132err2: 132err2:
133 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 133 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
134 regulator_disable(sdi.vdds_sdi_reg); 134 regulator_disable(sdi.vdds_sdi_reg);
135err1: 135err1:
136 omap_dss_stop_device(dssdev); 136 omap_dss_stop_device(dssdev);
@@ -145,7 +145,7 @@ void omapdss_sdi_display_disable(struct omap_dss_device *dssdev)
145 145
146 dss_sdi_disable(); 146 dss_sdi_disable();
147 147
148 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 148 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
149 149
150 regulator_disable(sdi.vdds_sdi_reg); 150 regulator_disable(sdi.vdds_sdi_reg);
151 151
@@ -175,7 +175,7 @@ int sdi_init(bool skip_init)
175 * of them until sdi_display_enable is called. 175 * of them until sdi_display_enable is called.
176 */ 176 */
177 if (skip_init) 177 if (skip_init)
178 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 178 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
179 return 0; 179 return 0;
180} 180}
181 181
diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
index ef36811f6ac8..1aadceb76e1d 100644
--- a/drivers/video/omap2/dss/venc.c
+++ b/drivers/video/omap2/dss/venc.c
@@ -391,11 +391,11 @@ static void venc_reset(void)
391static void venc_enable_clocks(int enable) 391static void venc_enable_clocks(int enable)
392{ 392{
393 if (enable) 393 if (enable)
394 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | 394 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK |
395 DSS_CLK_96M); 395 DSS_CLK_VIDFCK);
396 else 396 else
397 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | 397 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK |
398 DSS_CLK_96M); 398 DSS_CLK_VIDFCK);
399} 399}
400 400
401static const struct venc_config *venc_timings_to_config( 401static const struct venc_config *venc_timings_to_config(
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-11 21:00:00 -0500