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authorArchit Taneja <archit@ti.com>2012-09-22 03:08:19 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2012-09-26 07:58:50 -0400
commitd9ac773cd0f285c6df45ac35c52d47d8e6fa7c13 (patch)
treedf99be82950e912811f0870fd9d38835a27397f3 /drivers/video
parent2a5561b1f7a2c12db912b0d3c5fc830817d413a9 (diff)
OMAPDSS: DISPC: Add function to set channel in for writeback
Writeback can take input from either one of the overlays, or one of the overlay managers. Add an enum which represents the channel_in for writeback, and maps to the register field programming. Add a function to configure channel in for writeback. This will be used later in APPLY. Signed-off-by: Archit Taneja <archit@ti.com>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/omap2/dss/dispc.c7
-rw-r--r--drivers/video/omap2/dss/dss.h13
2 files changed, 20 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index d46cf29a90aa..f0796bafa74e 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -983,6 +983,13 @@ static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
983 return channel; 983 return channel;
984} 984}
985 985
986void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
987{
988 enum omap_plane plane = OMAP_DSS_WB;
989
990 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
991}
992
986static void dispc_ovl_set_burst_size(enum omap_plane plane, 993static void dispc_ovl_set_burst_size(enum omap_plane plane,
987 enum omap_burst_size burst_size) 994 enum omap_burst_size burst_size)
988{ 995{
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 322a2be7b4c6..379e0782eefb 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -113,6 +113,17 @@ enum dss_dsi_content_type {
113 DSS_DSI_CONTENT_GENERIC, 113 DSS_DSI_CONTENT_GENERIC,
114}; 114};
115 115
116enum dss_writeback_channel {
117 DSS_WB_LCD1_MGR = 0,
118 DSS_WB_LCD2_MGR = 1,
119 DSS_WB_TV_MGR = 2,
120 DSS_WB_OVL0 = 3,
121 DSS_WB_OVL1 = 4,
122 DSS_WB_OVL2 = 5,
123 DSS_WB_OVL3 = 6,
124 DSS_WB_LCD3_MGR = 7,
125};
126
116struct dss_clock_info { 127struct dss_clock_info {
117 /* rates that we get with dividers below */ 128 /* rates that we get with dividers below */
118 unsigned long fck; 129 unsigned long fck;
@@ -475,6 +486,8 @@ int dispc_mgr_get_clock_div(enum omap_channel channel,
475void dispc_mgr_setup(enum omap_channel channel, 486void dispc_mgr_setup(enum omap_channel channel,
476 struct omap_overlay_manager_info *info); 487 struct omap_overlay_manager_info *info);
477 488
489void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
490
478/* VENC */ 491/* VENC */
479#ifdef CONFIG_OMAP2_DSS_VENC 492#ifdef CONFIG_OMAP2_DSS_VENC
480int venc_init_platform_driver(void) __init; 493int venc_init_platform_driver(void) __init;