[ARM] pxafb: allow better platform configurable smart panel timing

For smart panels (LCD panel with internal framebuffer), the following
LCCR3 register bits have different meanings than the parallel one:

  LCCR3_PCP - controls the L_PCLK_WR polarity
  LCCR3_HSP - controls the L_LCLK_A0 polarity
  LCCR3_VSP - controls the L_FCLK_RD polarity

To keep minimum change to the original parallel timing, the .lcd_conn
flags and 'pxafb_mode_info.sync' are re-used to reflect this:

  LCD_PCLK_EDGE_{RISE,FALL} - configures LCCR3_PCP
  sync & FB_SYNC_{HOR,VERT}_HIGH_ACT - configures LCCR3_{HSP,VSP}

Signed-off-by: Eric Miao <eric.miao@marvell.com>

1 files changed, 3 insertions, 1 deletions

diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index 62d2dd0c1fa1..d6de84b42036 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -760,7 +760,9 @@ static void setup_smart_timing(struct pxafb_info *fbi,
                 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
 
         fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
-        fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk));
+        fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
+        fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
+        fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
 
         /* FIXME: make this configurable */
         fbi->reg_cmdcr = 1;