diff options
author | David Miller <davem@davemloft.net> | 2011-01-11 18:52:57 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2011-03-22 02:47:31 -0400 |
commit | f8645933513c65ac55f23c63b2649097289795c6 (patch) | |
tree | c4e3dade31d625e948e170231be01168ff300563 /drivers/video | |
parent | c5e04633b3b765a06986008e577930555e0f544b (diff) |
s3fb: Pass par->state.vgabase to vga_*() calls.
Instead of just plain NULL.
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/video')
-rw-r--r-- | drivers/video/s3fb.c | 102 |
1 files changed, 52 insertions, 50 deletions
diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index 23e4724bd439..262490a74bb7 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c | |||
@@ -348,26 +348,26 @@ static void s3_set_pixclock(struct fb_info *info, u32 pixclock) | |||
348 | } | 348 | } |
349 | 349 | ||
350 | /* Set VGA misc register */ | 350 | /* Set VGA misc register */ |
351 | regval = vga_r(NULL, VGA_MIS_R); | 351 | regval = vga_r(par->state.vgabase, VGA_MIS_R); |
352 | vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); | 352 | vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); |
353 | 353 | ||
354 | /* Set S3 clock registers */ | 354 | /* Set S3 clock registers */ |
355 | if (par->chip == CHIP_360_TRIO3D_1X || | 355 | if (par->chip == CHIP_360_TRIO3D_1X || |
356 | par->chip == CHIP_362_TRIO3D_2X || | 356 | par->chip == CHIP_362_TRIO3D_2X || |
357 | par->chip == CHIP_368_TRIO3D_2X) { | 357 | par->chip == CHIP_368_TRIO3D_2X) { |
358 | vga_wseq(NULL, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ | 358 | vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ |
359 | vga_wseq(NULL, 0x29, r >> 2); /* remaining highest bit of r */ | 359 | vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ |
360 | } else | 360 | } else |
361 | vga_wseq(NULL, 0x12, (n - 2) | (r << 5)); | 361 | vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); |
362 | vga_wseq(NULL, 0x13, m - 2); | 362 | vga_wseq(par->state.vgabase, 0x13, m - 2); |
363 | 363 | ||
364 | udelay(1000); | 364 | udelay(1000); |
365 | 365 | ||
366 | /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ | 366 | /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ |
367 | regval = vga_rseq (NULL, 0x15); /* | 0x80; */ | 367 | regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ |
368 | vga_wseq(NULL, 0x15, regval & ~(1<<5)); | 368 | vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); |
369 | vga_wseq(NULL, 0x15, regval | (1<<5)); | 369 | vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); |
370 | vga_wseq(NULL, 0x15, regval & ~(1<<5)); | 370 | vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); |
371 | } | 371 | } |
372 | 372 | ||
373 | 373 | ||
@@ -511,9 +511,9 @@ static int s3fb_set_par(struct fb_info *info) | |||
511 | info->var.activate = FB_ACTIVATE_NOW; | 511 | info->var.activate = FB_ACTIVATE_NOW; |
512 | 512 | ||
513 | /* Unlock registers */ | 513 | /* Unlock registers */ |
514 | vga_wcrt(NULL, 0x38, 0x48); | 514 | vga_wcrt(par->state.vgabase, 0x38, 0x48); |
515 | vga_wcrt(NULL, 0x39, 0xA5); | 515 | vga_wcrt(par->state.vgabase, 0x39, 0xA5); |
516 | vga_wseq(NULL, 0x08, 0x06); | 516 | vga_wseq(par->state.vgabase, 0x08, 0x06); |
517 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); | 517 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); |
518 | 518 | ||
519 | /* Blank screen and turn off sync */ | 519 | /* Blank screen and turn off sync */ |
@@ -552,13 +552,13 @@ static int s3fb_set_par(struct fb_info *info) | |||
552 | if (par->chip != CHIP_360_TRIO3D_1X && | 552 | if (par->chip != CHIP_360_TRIO3D_1X && |
553 | par->chip != CHIP_362_TRIO3D_2X && | 553 | par->chip != CHIP_362_TRIO3D_2X && |
554 | par->chip != CHIP_368_TRIO3D_2X) { | 554 | par->chip != CHIP_368_TRIO3D_2X) { |
555 | vga_wcrt(NULL, 0x54, 0x18); /* M parameter */ | 555 | vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ |
556 | vga_wcrt(NULL, 0x60, 0xff); /* N parameter */ | 556 | vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ |
557 | vga_wcrt(NULL, 0x61, 0xff); /* L parameter */ | 557 | vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ |
558 | vga_wcrt(NULL, 0x62, 0xff); /* L parameter */ | 558 | vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ |
559 | } | 559 | } |
560 | 560 | ||
561 | vga_wcrt(NULL, 0x3A, 0x35); | 561 | vga_wcrt(par->state.vgabase, 0x3A, 0x35); |
562 | svga_wattr(par->state.vgabase, 0x33, 0x00); | 562 | svga_wattr(par->state.vgabase, 0x33, 0x00); |
563 | 563 | ||
564 | if (info->var.vmode & FB_VMODE_DOUBLE) | 564 | if (info->var.vmode & FB_VMODE_DOUBLE) |
@@ -580,27 +580,27 @@ static int s3fb_set_par(struct fb_info *info) | |||
580 | 580 | ||
581 | /* S3 virge DX hack */ | 581 | /* S3 virge DX hack */ |
582 | if (par->chip == CHIP_375_VIRGE_DX) { | 582 | if (par->chip == CHIP_375_VIRGE_DX) { |
583 | vga_wcrt(NULL, 0x86, 0x80); | 583 | vga_wcrt(par->state.vgabase, 0x86, 0x80); |
584 | vga_wcrt(NULL, 0x90, 0x00); | 584 | vga_wcrt(par->state.vgabase, 0x90, 0x00); |
585 | } | 585 | } |
586 | 586 | ||
587 | /* S3 virge VX hack */ | 587 | /* S3 virge VX hack */ |
588 | if (par->chip == CHIP_988_VIRGE_VX) { | 588 | if (par->chip == CHIP_988_VIRGE_VX) { |
589 | vga_wcrt(NULL, 0x50, 0x00); | 589 | vga_wcrt(par->state.vgabase, 0x50, 0x00); |
590 | vga_wcrt(NULL, 0x67, 0x50); | 590 | vga_wcrt(par->state.vgabase, 0x67, 0x50); |
591 | 591 | ||
592 | vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09); | 592 | vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); |
593 | vga_wcrt(NULL, 0x66, 0x90); | 593 | vga_wcrt(par->state.vgabase, 0x66, 0x90); |
594 | } | 594 | } |
595 | 595 | ||
596 | if (par->chip == CHIP_360_TRIO3D_1X || | 596 | if (par->chip == CHIP_360_TRIO3D_1X || |
597 | par->chip == CHIP_362_TRIO3D_2X || | 597 | par->chip == CHIP_362_TRIO3D_2X || |
598 | par->chip == CHIP_368_TRIO3D_2X) { | 598 | par->chip == CHIP_368_TRIO3D_2X) { |
599 | dbytes = info->var.xres * ((bpp+7)/8); | 599 | dbytes = info->var.xres * ((bpp+7)/8); |
600 | vga_wcrt(NULL, 0x91, (dbytes + 7) / 8); | 600 | vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); |
601 | vga_wcrt(NULL, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); | 601 | vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); |
602 | 602 | ||
603 | vga_wcrt(NULL, 0x66, 0x81); | 603 | vga_wcrt(par->state.vgabase, 0x66, 0x81); |
604 | } | 604 | } |
605 | 605 | ||
606 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); | 606 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); |
@@ -627,7 +627,7 @@ static int s3fb_set_par(struct fb_info *info) | |||
627 | break; | 627 | break; |
628 | case 1: | 628 | case 1: |
629 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); | 629 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); |
630 | vga_wgfx(NULL, VGA_GFX_MODE, 0x40); | 630 | vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); |
631 | 631 | ||
632 | /* Set additional registers like in 8-bit mode */ | 632 | /* Set additional registers like in 8-bit mode */ |
633 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); | 633 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
@@ -720,7 +720,7 @@ static int s3fb_set_par(struct fb_info *info) | |||
720 | /* Set interlaced mode start/end register */ | 720 | /* Set interlaced mode start/end register */ |
721 | value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; | 721 | value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; |
722 | value = ((value * hmul) / 8) - 5; | 722 | value = ((value * hmul) / 8) - 5; |
723 | vga_wcrt(NULL, 0x3C, (value + 1) / 2); | 723 | vga_wcrt(par->state.vgabase, 0x3C, (value + 1) / 2); |
724 | 724 | ||
725 | memset_io(info->screen_base, 0x00, screen_size); | 725 | memset_io(info->screen_base, 0x00, screen_size); |
726 | /* Device and screen back on */ | 726 | /* Device and screen back on */ |
@@ -873,12 +873,14 @@ static struct fb_ops s3fb_ops = { | |||
873 | 873 | ||
874 | /* ------------------------------------------------------------------------- */ | 874 | /* ------------------------------------------------------------------------- */ |
875 | 875 | ||
876 | static int __devinit s3_identification(int chip) | 876 | static int __devinit s3_identification(struct s3fb_info *par) |
877 | { | 877 | { |
878 | int chip = par->chip; | ||
879 | |||
878 | if (chip == CHIP_XXX_TRIO) { | 880 | if (chip == CHIP_XXX_TRIO) { |
879 | u8 cr30 = vga_rcrt(NULL, 0x30); | 881 | u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); |
880 | u8 cr2e = vga_rcrt(NULL, 0x2e); | 882 | u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); |
881 | u8 cr2f = vga_rcrt(NULL, 0x2f); | 883 | u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); |
882 | 884 | ||
883 | if ((cr30 == 0xE0) || (cr30 == 0xE1)) { | 885 | if ((cr30 == 0xE0) || (cr30 == 0xE1)) { |
884 | if (cr2e == 0x10) | 886 | if (cr2e == 0x10) |
@@ -893,7 +895,7 @@ static int __devinit s3_identification(int chip) | |||
893 | } | 895 | } |
894 | 896 | ||
895 | if (chip == CHIP_XXX_TRIO64V2_DXGX) { | 897 | if (chip == CHIP_XXX_TRIO64V2_DXGX) { |
896 | u8 cr6f = vga_rcrt(NULL, 0x6f); | 898 | u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); |
897 | 899 | ||
898 | if (! (cr6f & 0x01)) | 900 | if (! (cr6f & 0x01)) |
899 | return CHIP_775_TRIO64V2_DX; | 901 | return CHIP_775_TRIO64V2_DX; |
@@ -902,7 +904,7 @@ static int __devinit s3_identification(int chip) | |||
902 | } | 904 | } |
903 | 905 | ||
904 | if (chip == CHIP_XXX_VIRGE_DXGX) { | 906 | if (chip == CHIP_XXX_VIRGE_DXGX) { |
905 | u8 cr6f = vga_rcrt(NULL, 0x6f); | 907 | u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); |
906 | 908 | ||
907 | if (! (cr6f & 0x01)) | 909 | if (! (cr6f & 0x01)) |
908 | return CHIP_375_VIRGE_DX; | 910 | return CHIP_375_VIRGE_DX; |
@@ -911,7 +913,7 @@ static int __devinit s3_identification(int chip) | |||
911 | } | 913 | } |
912 | 914 | ||
913 | if (chip == CHIP_36X_TRIO3D_1X_2X) { | 915 | if (chip == CHIP_36X_TRIO3D_1X_2X) { |
914 | switch (vga_rcrt(NULL, 0x2f)) { | 916 | switch (vga_rcrt(par->state.vgabase, 0x2f)) { |
915 | case 0x00: | 917 | case 0x00: |
916 | return CHIP_360_TRIO3D_1X; | 918 | return CHIP_360_TRIO3D_1X; |
917 | case 0x01: | 919 | case 0x01: |
@@ -979,21 +981,21 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i | |||
979 | } | 981 | } |
980 | 982 | ||
981 | /* Unlock regs */ | 983 | /* Unlock regs */ |
982 | cr38 = vga_rcrt(NULL, 0x38); | 984 | cr38 = vga_rcrt(par->state.vgabase, 0x38); |
983 | cr39 = vga_rcrt(NULL, 0x39); | 985 | cr39 = vga_rcrt(par->state.vgabase, 0x39); |
984 | vga_wseq(NULL, 0x08, 0x06); | 986 | vga_wseq(par->state.vgabase, 0x08, 0x06); |
985 | vga_wcrt(NULL, 0x38, 0x48); | 987 | vga_wcrt(par->state.vgabase, 0x38, 0x48); |
986 | vga_wcrt(NULL, 0x39, 0xA5); | 988 | vga_wcrt(par->state.vgabase, 0x39, 0xA5); |
987 | 989 | ||
988 | /* Identify chip type */ | 990 | /* Identify chip type */ |
989 | par->chip = id->driver_data & CHIP_MASK; | 991 | par->chip = id->driver_data & CHIP_MASK; |
990 | par->rev = vga_rcrt(NULL, 0x2f); | 992 | par->rev = vga_rcrt(par->state.vgabase, 0x2f); |
991 | if (par->chip & CHIP_UNDECIDED_FLAG) | 993 | if (par->chip & CHIP_UNDECIDED_FLAG) |
992 | par->chip = s3_identification(par->chip); | 994 | par->chip = s3_identification(par); |
993 | 995 | ||
994 | /* Find how many physical memory there is on card */ | 996 | /* Find how many physical memory there is on card */ |
995 | /* 0x36 register is accessible even if other registers are locked */ | 997 | /* 0x36 register is accessible even if other registers are locked */ |
996 | regval = vga_rcrt(NULL, 0x36); | 998 | regval = vga_rcrt(par->state.vgabase, 0x36); |
997 | if (par->chip == CHIP_360_TRIO3D_1X || | 999 | if (par->chip == CHIP_360_TRIO3D_1X || |
998 | par->chip == CHIP_362_TRIO3D_2X || | 1000 | par->chip == CHIP_362_TRIO3D_2X || |
999 | par->chip == CHIP_368_TRIO3D_2X) { | 1001 | par->chip == CHIP_368_TRIO3D_2X) { |
@@ -1012,13 +1014,13 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i | |||
1012 | info->fix.smem_len = info->screen_size; | 1014 | info->fix.smem_len = info->screen_size; |
1013 | 1015 | ||
1014 | /* Find MCLK frequency */ | 1016 | /* Find MCLK frequency */ |
1015 | regval = vga_rseq(NULL, 0x10); | 1017 | regval = vga_rseq(par->state.vgabase, 0x10); |
1016 | par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); | 1018 | par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); |
1017 | par->mclk_freq = par->mclk_freq >> (regval >> 5); | 1019 | par->mclk_freq = par->mclk_freq >> (regval >> 5); |
1018 | 1020 | ||
1019 | /* Restore locks */ | 1021 | /* Restore locks */ |
1020 | vga_wcrt(NULL, 0x38, cr38); | 1022 | vga_wcrt(par->state.vgabase, 0x38, cr38); |
1021 | vga_wcrt(NULL, 0x39, cr39); | 1023 | vga_wcrt(par->state.vgabase, 0x39, cr39); |
1022 | 1024 | ||
1023 | strcpy(info->fix.id, s3_names [par->chip]); | 1025 | strcpy(info->fix.id, s3_names [par->chip]); |
1024 | info->fix.mmio_start = 0; | 1026 | info->fix.mmio_start = 0; |
@@ -1054,8 +1056,8 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i | |||
1054 | 1056 | ||
1055 | if (par->chip == CHIP_UNKNOWN) | 1057 | if (par->chip == CHIP_UNKNOWN) |
1056 | printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", | 1058 | printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", |
1057 | info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e), | 1059 | info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e), |
1058 | vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30)); | 1060 | vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30)); |
1059 | 1061 | ||
1060 | /* Record a reference to the driver data */ | 1062 | /* Record a reference to the driver data */ |
1061 | pci_set_drvdata(dev, info); | 1063 | pci_set_drvdata(dev, info); |