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authorGuoqing Li <ligq@marvell.com>2013-02-21 19:42:15 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-02-21 20:22:17 -0500
commitd63028c389058ab47455baf2e232c25ce0765a04 (patch)
tree4f9d2078162f0432b6747f235a3dd0ede36cdb6d /drivers/video
parent24cb87a761284407007984416e44e7d819cb0efd (diff)
video: mmp display controller support
Marvell mmp series display controller support in mmpdisp subsystem. This driver focus on implementation of hardware operations of path/overlay, which is defined in mmp display subsystem interface. This driver registers all pathes to mmp display framework. Signed-off-by: Guoqing Li <ligq@marvell.com> Signed-off-by: Lisa Du <cldu@marvell.com> Signed-off-by: Zhou Zhu <zzhu3@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/mmp/Kconfig1
-rw-r--r--drivers/video/mmp/Makefile2
-rw-r--r--drivers/video/mmp/hw/Kconfig12
-rw-r--r--drivers/video/mmp/hw/Makefile1
-rw-r--r--drivers/video/mmp/hw/mmp_ctrl.c585
-rw-r--r--drivers/video/mmp/hw/mmp_ctrl.h1970
6 files changed, 2570 insertions, 1 deletions
diff --git a/drivers/video/mmp/Kconfig b/drivers/video/mmp/Kconfig
index 6a0b0566ed32..ed51d15467c0 100644
--- a/drivers/video/mmp/Kconfig
+++ b/drivers/video/mmp/Kconfig
@@ -5,5 +5,6 @@ menuconfig MMP_DISP
5 Marvell Display Subsystem support. 5 Marvell Display Subsystem support.
6 6
7if MMP_DISP 7if MMP_DISP
8source "drivers/video/mmp/hw/Kconfig"
8source "drivers/video/mmp/fb/Kconfig" 9source "drivers/video/mmp/fb/Kconfig"
9endif 10endif
diff --git a/drivers/video/mmp/Makefile b/drivers/video/mmp/Makefile
index fdcd833150bd..6999a0917e19 100644
--- a/drivers/video/mmp/Makefile
+++ b/drivers/video/mmp/Makefile
@@ -1 +1 @@
obj-y += core.o fb/ obj-y += core.o hw/ fb/
diff --git a/drivers/video/mmp/hw/Kconfig b/drivers/video/mmp/hw/Kconfig
new file mode 100644
index 000000000000..6c1dd34e8cf9
--- /dev/null
+++ b/drivers/video/mmp/hw/Kconfig
@@ -0,0 +1,12 @@
1if MMP_DISP
2
3config MMP_DISP_CONTROLLER
4 bool "mmp display controller hw support"
5 depends on CPU_PXA910 || CPU_MMP2 || CPU_MMP3 || CPU_PXA988
6 default n
7 help
8 Marvell MMP display hw controller support
9 this controller is used on Marvell PXA910,
10 MMP2, MMP3, PXA988 chips
11
12endif
diff --git a/drivers/video/mmp/hw/Makefile b/drivers/video/mmp/hw/Makefile
new file mode 100644
index 000000000000..f34ace82888e
--- /dev/null
+++ b/drivers/video/mmp/hw/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_MMP_DISP_CONTROLLER) += mmp_ctrl.o
diff --git a/drivers/video/mmp/hw/mmp_ctrl.c b/drivers/video/mmp/hw/mmp_ctrl.c
new file mode 100644
index 000000000000..1b5d29992313
--- /dev/null
+++ b/drivers/video/mmp/hw/mmp_ctrl.c
@@ -0,0 +1,585 @@
1/*
2 * linux/drivers/video/mmp/hw/mmp_ctrl.c
3 * Marvell MMP series Display Controller support
4 *
5 * Copyright (C) 2012 Marvell Technology Group Ltd.
6 * Authors: Guoqing Li <ligq@marvell.com>
7 * Lisa Du <cldu@marvell.com>
8 * Zhou Zhu <zzhu3@marvell.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
22 *
23 */
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/kernel.h>
27#include <linux/errno.h>
28#include <linux/string.h>
29#include <linux/interrupt.h>
30#include <linux/slab.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/dma-mapping.h>
34#include <linux/clk.h>
35#include <linux/err.h>
36#include <linux/vmalloc.h>
37#include <linux/uaccess.h>
38#include <linux/kthread.h>
39#include <linux/io.h>
40
41#include "mmp_ctrl.h"
42
43static irqreturn_t ctrl_handle_irq(int irq, void *dev_id)
44{
45 struct mmphw_ctrl *ctrl = (struct mmphw_ctrl *)dev_id;
46 u32 isr, imask, tmp;
47
48 isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
49 imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
50
51 do {
52 /* clear clock only */
53 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
54 if (tmp & isr)
55 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR);
56 } while ((isr = readl(ctrl->reg_base + SPU_IRQ_ISR)) & imask);
57
58 return IRQ_HANDLED;
59}
60
61static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt)
62{
63 u32 link_config = path_to_path_plat(overlay->path)->link_config;
64 u32 rbswap, uvswap = 0, yuvswap = 0,
65 csc_en = 0, val = 0,
66 vid = overlay_is_vid(overlay);
67
68 switch (pix_fmt) {
69 case PIXFMT_RGB565:
70 case PIXFMT_RGB1555:
71 case PIXFMT_RGB888PACK:
72 case PIXFMT_RGB888UNPACK:
73 case PIXFMT_RGBA888:
74 rbswap = !(link_config & 0x1);
75 break;
76 case PIXFMT_VYUY:
77 case PIXFMT_YVU422P:
78 case PIXFMT_YVU420P:
79 rbswap = link_config & 0x1;
80 uvswap = 1;
81 break;
82 case PIXFMT_YUYV:
83 rbswap = link_config & 0x1;
84 yuvswap = 1;
85 break;
86 default:
87 rbswap = link_config & 0x1;
88 break;
89 }
90
91 switch (pix_fmt) {
92 case PIXFMT_RGB565:
93 case PIXFMT_BGR565:
94 val = 0;
95 break;
96 case PIXFMT_RGB1555:
97 case PIXFMT_BGR1555:
98 val = 0x1;
99 break;
100 case PIXFMT_RGB888PACK:
101 case PIXFMT_BGR888PACK:
102 val = 0x2;
103 break;
104 case PIXFMT_RGB888UNPACK:
105 case PIXFMT_BGR888UNPACK:
106 val = 0x3;
107 break;
108 case PIXFMT_RGBA888:
109 case PIXFMT_BGRA888:
110 val = 0x4;
111 break;
112 case PIXFMT_UYVY:
113 case PIXFMT_VYUY:
114 case PIXFMT_YUYV:
115 val = 0x5;
116 csc_en = 1;
117 break;
118 case PIXFMT_YUV422P:
119 case PIXFMT_YVU422P:
120 val = 0x6;
121 csc_en = 1;
122 break;
123 case PIXFMT_YUV420P:
124 case PIXFMT_YVU420P:
125 val = 0x7;
126 csc_en = 1;
127 break;
128 default:
129 break;
130 }
131
132 return (dma_palette(0) | dma_fmt(vid, val) |
133 dma_swaprb(vid, rbswap) | dma_swapuv(vid, uvswap) |
134 dma_swapyuv(vid, yuvswap) | dma_csc(vid, csc_en));
135}
136
137static void dmafetch_set_fmt(struct mmp_overlay *overlay)
138{
139 u32 tmp;
140 struct mmp_path *path = overlay->path;
141 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
142 tmp &= ~dma_mask(overlay_is_vid(overlay));
143 tmp |= fmt_to_reg(overlay, overlay->win.pix_fmt);
144 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
145}
146
147static void overlay_set_win(struct mmp_overlay *overlay, struct mmp_win *win)
148{
149 struct lcd_regs *regs = path_regs(overlay->path);
150 u32 pitch;
151
152 /* assert win supported */
153 memcpy(&overlay->win, win, sizeof(struct mmp_win));
154
155 mutex_lock(&overlay->access_ok);
156 pitch = win->xsrc * pixfmt_to_stride(win->pix_fmt);
157 writel_relaxed(pitch, &regs->g_pitch);
158 writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->g_size);
159 writel_relaxed((win->ydst << 16) | win->xdst, &regs->g_size_z);
160 writel_relaxed(0, &regs->g_start);
161
162 dmafetch_set_fmt(overlay);
163 mutex_unlock(&overlay->access_ok);
164}
165
166static void dmafetch_onoff(struct mmp_overlay *overlay, int on)
167{
168 u32 mask = overlay_is_vid(overlay) ? CFG_GRA_ENA_MASK :
169 CFG_DMA_ENA_MASK;
170 u32 enable = overlay_is_vid(overlay) ? CFG_GRA_ENA(1) : CFG_DMA_ENA(1);
171 u32 tmp;
172 struct mmp_path *path = overlay->path;
173
174 mutex_lock(&overlay->access_ok);
175 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
176 tmp &= ~mask;
177 tmp |= (on ? enable : 0);
178 writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
179 mutex_unlock(&overlay->access_ok);
180}
181
182static void path_enabledisable(struct mmp_path *path, int on)
183{
184 u32 tmp;
185 mutex_lock(&path->access_ok);
186 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
187 if (on)
188 tmp &= ~SCLK_DISABLE;
189 else
190 tmp |= SCLK_DISABLE;
191 writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
192 mutex_unlock(&path->access_ok);
193}
194
195static void path_onoff(struct mmp_path *path, int on)
196{
197 if (path->status == on) {
198 dev_info(path->dev, "path %s is already %s\n",
199 path->name, stat_name(path->status));
200 return;
201 }
202
203 if (on) {
204 path_enabledisable(path, 1);
205
206 if (path->panel && path->panel->set_onoff)
207 path->panel->set_onoff(path->panel, 1);
208 } else {
209 if (path->panel && path->panel->set_onoff)
210 path->panel->set_onoff(path->panel, 0);
211
212 path_enabledisable(path, 0);
213 }
214 path->status = on;
215}
216
217static void overlay_set_onoff(struct mmp_overlay *overlay, int on)
218{
219 if (overlay->status == on) {
220 dev_info(overlay_to_ctrl(overlay)->dev, "overlay %s is already %s\n",
221 overlay->path->name, stat_name(overlay->status));
222 return;
223 }
224 overlay->status = on;
225 dmafetch_onoff(overlay, on);
226 if (overlay->path->ops.check_status(overlay->path)
227 != overlay->path->status)
228 path_onoff(overlay->path, on);
229}
230
231static void overlay_set_fetch(struct mmp_overlay *overlay, int fetch_id)
232{
233 overlay->dmafetch_id = fetch_id;
234}
235
236static int overlay_set_addr(struct mmp_overlay *overlay, struct mmp_addr *addr)
237{
238 struct lcd_regs *regs = path_regs(overlay->path);
239
240 /* FIXME: assert addr supported */
241 memcpy(&overlay->addr, addr, sizeof(struct mmp_win));
242 writel(addr->phys[0], &regs->g_0);
243
244 return overlay->addr.phys[0];
245}
246
247static void path_set_mode(struct mmp_path *path, struct mmp_mode *mode)
248{
249 struct lcd_regs *regs = path_regs(path);
250 u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div,
251 link_config = path_to_path_plat(path)->link_config;
252
253 /* FIXME: assert videomode supported */
254 memcpy(&path->mode, mode, sizeof(struct mmp_mode));
255
256 mutex_lock(&path->access_ok);
257
258 /* polarity of timing signals */
259 tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1;
260 tmp |= mode->vsync_invert ? 0 : 0x8;
261 tmp |= mode->hsync_invert ? 0 : 0x4;
262 tmp |= link_config & CFG_DUMBMODE_MASK;
263 tmp |= CFG_DUMB_ENA(1);
264 writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));
265
266 writel_relaxed((mode->yres << 16) | mode->xres, &regs->screen_active);
267 writel_relaxed((mode->left_margin << 16) | mode->right_margin,
268 &regs->screen_h_porch);
269 writel_relaxed((mode->upper_margin << 16) | mode->lower_margin,
270 &regs->screen_v_porch);
271 total_x = mode->xres + mode->left_margin + mode->right_margin +
272 mode->hsync_len;
273 total_y = mode->yres + mode->upper_margin + mode->lower_margin +
274 mode->vsync_len;
275 writel_relaxed((total_y << 16) | total_x, &regs->screen_size);
276
277 /* vsync ctrl */
278 if (path->output_type == PATH_OUT_DSI)
279 vsync_ctrl = 0x01330133;
280 else
281 vsync_ctrl = ((mode->xres + mode->right_margin) << 16)
282 | (mode->xres + mode->right_margin);
283 writel_relaxed(vsync_ctrl, &regs->vsync_ctrl);
284
285 /* set pixclock div */
286 sclk_src = clk_get_rate(path_to_ctrl(path)->clk);
287 sclk_div = sclk_src / mode->pixclock_freq;
288 if (sclk_div * mode->pixclock_freq < sclk_src)
289 sclk_div++;
290
291 dev_info(path->dev, "%s sclk_src %d sclk_div 0x%x pclk %d\n",
292 __func__, sclk_src, sclk_div, mode->pixclock_freq);
293
294 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
295 tmp &= ~CLK_INT_DIV_MASK;
296 tmp |= sclk_div;
297 writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
298
299 mutex_unlock(&path->access_ok);
300}
301
302static struct mmp_overlay_ops mmphw_overlay_ops = {
303 .set_fetch = overlay_set_fetch,
304 .set_onoff = overlay_set_onoff,
305 .set_win = overlay_set_win,
306 .set_addr = overlay_set_addr,
307};
308
309static void ctrl_set_default(struct mmphw_ctrl *ctrl)
310{
311 u32 tmp, irq_mask;
312
313 /*
314 * LCD Global control(LCD_TOP_CTRL) should be configed before
315 * any other LCD registers read/write, or there maybe issues.
316 */
317 tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL);
318 tmp |= 0xfff0;
319 writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL);
320
321
322 /* disable all interrupts */
323 irq_mask = path_imasks(0) | err_imask(0) |
324 path_imasks(1) | err_imask(1);
325 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
326 tmp &= ~irq_mask;
327 tmp |= irq_mask;
328 writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA);
329}
330
331static void path_set_default(struct mmp_path *path)
332{
333 struct lcd_regs *regs = path_regs(path);
334 u32 dma_ctrl1, mask, tmp, path_config;
335
336 path_config = path_to_path_plat(path)->path_config;
337
338 /* Configure IOPAD: should be parallel only */
339 if (PATH_OUT_PARALLEL == path->output_type) {
340 mask = CFG_IOPADMODE_MASK | CFG_BURST_MASK | CFG_BOUNDARY_MASK;
341 tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL);
342 tmp &= ~mask;
343 tmp |= path_config;
344 writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);
345 }
346
347 /* Select path clock source */
348 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
349 tmp &= ~SCLK_SRC_SEL_MASK;
350 tmp |= path_config;
351 writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
352
353 /*
354 * Configure default bits: vsync triggers DMA,
355 * power save enable, configure alpha registers to
356 * display 100% graphics, and set pixel command.
357 */
358 dma_ctrl1 = 0x2032ff81;
359
360 dma_ctrl1 |= CFG_VSYNC_INV_MASK;
361 writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));
362
363 /* Configure default register values */
364 writel_relaxed(0x00000000, &regs->blank_color);
365 writel_relaxed(0x00000000, &regs->g_1);
366 writel_relaxed(0x00000000, &regs->g_start);
367
368 /*
369 * 1.enable multiple burst request in DMA AXI
370 * bus arbiter for faster read if not tv path;
371 * 2.enable horizontal smooth filter;
372 */
373 if (PATH_PN == path->id) {
374 mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK
375 | CFG_ARBFAST_ENA(1);
376 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
377 tmp |= mask;
378 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
379 } else if (PATH_TV == path->id) {
380 mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK
381 | CFG_ARBFAST_ENA(1);
382 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
383 tmp &= ~mask;
384 tmp |= CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK;
385 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
386 }
387}
388
389static int path_init(struct mmphw_path_plat *path_plat,
390 struct mmp_mach_path_config *config)
391{
392 struct mmphw_ctrl *ctrl = path_plat->ctrl;
393 struct mmp_path_info *path_info;
394 struct mmp_path *path = NULL;
395
396 dev_info(ctrl->dev, "%s: %s\n", __func__, config->name);
397
398 /* init driver data */
399 path_info = kzalloc(sizeof(struct mmp_path_info), GFP_KERNEL);
400 if (!path_info) {
401 dev_err(ctrl->dev, "%s: unable to alloc path_info for %s\n",
402 __func__, config->name);
403 return 0;
404 }
405 path_info->name = config->name;
406 path_info->id = path_plat->id;
407 path_info->dev = ctrl->dev;
408 path_info->overlay_num = config->overlay_num;
409 path_info->overlay_ops = &mmphw_overlay_ops;
410 path_info->set_mode = path_set_mode;
411 path_info->plat_data = path_plat;
412
413 /* create/register platform device */
414 path = mmp_register_path(path_info);
415 if (!path) {
416 kfree(path_info);
417 return 0;
418 }
419 path_plat->path = path;
420 path_plat->path_config = config->path_config;
421 path_plat->link_config = config->link_config;
422 path_set_default(path);
423
424 kfree(path_info);
425 return 1;
426}
427
428static void path_deinit(struct mmphw_path_plat *path_plat)
429{
430 if (!path_plat)
431 return;
432
433 if (path_plat->path)
434 mmp_unregister_path(path_plat->path);
435}
436
437static int mmphw_probe(struct platform_device *pdev)
438{
439 struct mmp_mach_plat_info *mi;
440 struct resource *res;
441 int ret, i, size, irq;
442 struct mmphw_path_plat *path_plat;
443 struct mmphw_ctrl *ctrl = NULL;
444
445 /* get resources from platform data */
446 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
447 if (res == NULL) {
448 dev_err(&pdev->dev, "%s: no IO memory defined\n", __func__);
449 ret = -ENOENT;
450 goto failed;
451 }
452
453 irq = platform_get_irq(pdev, 0);
454 if (irq < 0) {
455 dev_err(&pdev->dev, "%s: no IRQ defined\n", __func__);
456 ret = -ENOENT;
457 goto failed;
458 }
459
460 /* get configs from platform data */
461 mi = pdev->dev.platform_data;
462 if (mi == NULL || !mi->path_num || !mi->paths) {
463 dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
464 ret = -EINVAL;
465 goto failed;
466 }
467
468 /* allocate */
469 size = sizeof(struct mmphw_ctrl) + sizeof(struct mmphw_path_plat) *
470 mi->path_num;
471 ctrl = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
472 if (!ctrl) {
473 ret = -ENOMEM;
474 goto failed;
475 }
476
477 ctrl->name = mi->name;
478 ctrl->path_num = mi->path_num;
479 ctrl->dev = &pdev->dev;
480 ctrl->irq = irq;
481 platform_set_drvdata(pdev, ctrl);
482 mutex_init(&ctrl->access_ok);
483
484 /* map registers.*/
485 if (!devm_request_mem_region(ctrl->dev, res->start,
486 resource_size(res), ctrl->name)) {
487 dev_err(ctrl->dev,
488 "can't request region for resource %pR\n", res);
489 ret = -EINVAL;
490 goto failed;
491 }
492
493 ctrl->reg_base = devm_ioremap_nocache(ctrl->dev,
494 res->start, resource_size(res));
495 if (ctrl->reg_base == NULL) {
496 dev_err(ctrl->dev, "%s: res %x - %x map failed\n", __func__,
497 res->start, res->end);
498 ret = -ENOMEM;
499 goto failed;
500 }
501
502 /* request irq */
503 ret = devm_request_irq(ctrl->dev, ctrl->irq, ctrl_handle_irq,
504 IRQF_SHARED, "lcd_controller", ctrl);
505 if (ret < 0) {
506 dev_err(ctrl->dev, "%s unable to request IRQ %d\n",
507 __func__, ctrl->irq);
508 ret = -ENXIO;
509 goto failed;
510 }
511
512 /* get clock */
513 ctrl->clk = devm_clk_get(ctrl->dev, mi->clk_name);
514 if (IS_ERR(ctrl->clk)) {
515 dev_err(ctrl->dev, "unable to get clk %s\n", mi->clk_name);
516 ret = -ENOENT;
517 goto failed_get_clk;
518 }
519 clk_prepare_enable(ctrl->clk);
520
521 /* init global regs */
522 ctrl_set_default(ctrl);
523
524 /* init pathes from machine info and register them */
525 for (i = 0; i < ctrl->path_num; i++) {
526 /* get from config and machine info */
527 path_plat = &ctrl->path_plats[i];
528 path_plat->id = i;
529 path_plat->ctrl = ctrl;
530
531 /* path init */
532 if (!path_init(path_plat, &mi->paths[i])) {
533 ret = -EINVAL;
534 goto failed_path_init;
535 }
536 }
537
538 dev_info(ctrl->dev, "device init done\n");
539
540 return 0;
541
542failed_path_init:
543 for (i = 0; i < ctrl->path_num; i++) {
544 path_plat = &ctrl->path_plats[i];
545 path_deinit(path_plat);
546 }
547
548 if (ctrl->clk) {
549 devm_clk_put(ctrl->dev, ctrl->clk);
550 clk_disable_unprepare(ctrl->clk);
551 }
552failed_get_clk:
553 devm_free_irq(ctrl->dev, ctrl->irq, ctrl);
554failed:
555 if (ctrl) {
556 if (ctrl->reg_base)
557 devm_iounmap(ctrl->dev, ctrl->reg_base);
558 devm_release_mem_region(ctrl->dev, res->start,
559 resource_size(res));
560 devm_kfree(ctrl->dev, ctrl);
561 }
562
563 platform_set_drvdata(pdev, NULL);
564 dev_err(&pdev->dev, "device init failed\n");
565
566 return ret;
567}
568
569static struct platform_driver mmphw_driver = {
570 .driver = {
571 .name = "mmp-disp",
572 .owner = THIS_MODULE,
573 },
574 .probe = mmphw_probe,
575};
576
577static int mmphw_init(void)
578{
579 return platform_driver_register(&mmphw_driver);
580}
581module_init(mmphw_init);
582
583MODULE_AUTHOR("Li Guoqing<ligq@marvell.com>");
584MODULE_DESCRIPTION("Framebuffer driver for mmp");
585MODULE_LICENSE("GPL");
diff --git a/drivers/video/mmp/hw/mmp_ctrl.h b/drivers/video/mmp/hw/mmp_ctrl.h
new file mode 100644
index 000000000000..b125f53336fa
--- /dev/null
+++ b/drivers/video/mmp/hw/mmp_ctrl.h
@@ -0,0 +1,1970 @@
1/*
2 * drivers/video/mmp/hw/mmp_ctrl.h
3 *
4 *
5 * Copyright (C) 2012 Marvell Technology Group Ltd.
6 * Authors: Guoqing Li <ligq@marvell.com>
7 * Lisa Du <cldu@marvell.com>
8 * Zhou Zhu <zzhu3@marvell.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
22 *
23 */
24
25#ifndef _MMP_CTRL_H_
26#define _MMP_CTRL_H_
27
28#include <video/mmp_disp.h>
29
30/* ------------< LCD register >------------ */
31struct lcd_regs {
32/* TV patch register for MMP2 */
33/* 32 bit TV Video Frame0 Y Starting Address */
34#define LCD_TVD_START_ADDR_Y0 (0x0000)
35/* 32 bit TV Video Frame0 U Starting Address */
36#define LCD_TVD_START_ADDR_U0 (0x0004)
37/* 32 bit TV Video Frame0 V Starting Address */
38#define LCD_TVD_START_ADDR_V0 (0x0008)
39/* 32 bit TV Video Frame0 Command Starting Address */
40#define LCD_TVD_START_ADDR_C0 (0x000C)
41/* 32 bit TV Video Frame1 Y Starting Address Register*/
42#define LCD_TVD_START_ADDR_Y1 (0x0010)
43/* 32 bit TV Video Frame1 U Starting Address Register*/
44#define LCD_TVD_START_ADDR_U1 (0x0014)
45/* 32 bit TV Video Frame1 V Starting Address Register*/
46#define LCD_TVD_START_ADDR_V1 (0x0018)
47/* 32 bit TV Video Frame1 Command Starting Address Register*/
48#define LCD_TVD_START_ADDR_C1 (0x001C)
49/* 32 bit TV Video Y andC Line Length(Pitch)Register*/
50#define LCD_TVD_PITCH_YC (0x0020)
51/* 32 bit TV Video U andV Line Length(Pitch)Register*/
52#define LCD_TVD_PITCH_UV (0x0024)
53/* 32 bit TV Video Starting Point on Screen Register*/
54#define LCD_TVD_OVSA_HPXL_VLN (0x0028)
55/* 32 bit TV Video Source Size Register*/
56#define LCD_TVD_HPXL_VLN (0x002C)
57/* 32 bit TV Video Destination Size (After Zooming)Register*/
58#define LCD_TVDZM_HPXL_VLN (0x0030)
59 u32 v_y0;
60 u32 v_u0;
61 u32 v_v0;
62 u32 v_c0;
63 u32 v_y1;
64 u32 v_u1;
65 u32 v_v1;
66 u32 v_c1;
67 u32 v_pitch_yc; /* Video Y and C Line Length (Pitch) */
68 u32 v_pitch_uv; /* Video U and V Line Length (Pitch) */
69 u32 v_start; /* Video Starting Point on Screen */
70 u32 v_size; /* Video Source Size */
71 u32 v_size_z; /* Video Destination Size (After Zooming) */
72
73/* 32 bit TV Graphic Frame 0 Starting Address Register*/
74#define LCD_TVG_START_ADDR0 (0x0034)
75/* 32 bit TV Graphic Frame 1 Starting Address Register*/
76#define LCD_TVG_START_ADDR1 (0x0038)
77/* 32 bit TV Graphic Line Length(Pitch)Register*/
78#define LCD_TVG_PITCH (0x003C)
79/* 32 bit TV Graphic Starting Point on Screen Register*/
80#define LCD_TVG_OVSA_HPXL_VLN (0x0040)
81/* 32 bit TV Graphic Source Size Register*/
82#define LCD_TVG_HPXL_VLN (0x0044)
83/* 32 bit TV Graphic Destination size (after Zooming)Register*/
84#define LCD_TVGZM_HPXL_VLN (0x0048)
85 u32 g_0; /* Graphic Frame 0/1 Starting Address */
86 u32 g_1;
87 u32 g_pitch; /* Graphic Line Length (Pitch) */
88 u32 g_start; /* Graphic Starting Point on Screen */
89 u32 g_size; /* Graphic Source Size */
90 u32 g_size_z; /* Graphic Destination Size (After Zooming) */
91
92/* 32 bit TV Hardware Cursor Starting Point on screen Register*/
93#define LCD_TVC_OVSA_HPXL_VLN (0x004C)
94/* 32 bit TV Hardware Cursor Size Register */
95#define LCD_TVC_HPXL_VLN (0x0050)
96 u32 hc_start; /* Hardware Cursor */
97 u32 hc_size; /* Hardware Cursor */
98
99/* 32 bit TV Total Screen Size Register*/
100#define LCD_TV_V_H_TOTAL (0x0054)
101/* 32 bit TV Screen Active Size Register*/
102#define LCD_TV_V_H_ACTIVE (0x0058)
103/* 32 bit TV Screen Horizontal Porch Register*/
104#define LCD_TV_H_PORCH (0x005C)
105/* 32 bit TV Screen Vertical Porch Register*/
106#define LCD_TV_V_PORCH (0x0060)
107 u32 screen_size; /* Screen Total Size */
108 u32 screen_active; /* Screen Active Size */
109 u32 screen_h_porch; /* Screen Horizontal Porch */
110 u32 screen_v_porch; /* Screen Vertical Porch */
111
112/* 32 bit TV Screen Blank Color Register*/
113#define LCD_TV_BLANKCOLOR (0x0064)
114/* 32 bit TV Hardware Cursor Color1 Register*/
115#define LCD_TV_ALPHA_COLOR1 (0x0068)
116/* 32 bit TV Hardware Cursor Color2 Register*/
117#define LCD_TV_ALPHA_COLOR2 (0x006C)
118 u32 blank_color; /* Screen Blank Color */
119 u32 hc_Alpha_color1; /* Hardware Cursor Color1 */
120 u32 hc_Alpha_color2; /* Hardware Cursor Color2 */
121
122/* 32 bit TV Video Y Color Key Control*/
123#define LCD_TV_COLORKEY_Y (0x0070)
124/* 32 bit TV Video U Color Key Control*/
125#define LCD_TV_COLORKEY_U (0x0074)
126/* 32 bit TV Video V Color Key Control*/
127#define LCD_TV_COLORKEY_V (0x0078)
128 u32 v_colorkey_y; /* Video Y Color Key Control */
129 u32 v_colorkey_u; /* Video U Color Key Control */
130 u32 v_colorkey_v; /* Video V Color Key Control */
131
132/* 32 bit TV VSYNC PulsePixel Edge Control Register*/
133#define LCD_TV_SEPXLCNT (0x007C)
134 u32 vsync_ctrl; /* VSYNC PulsePixel Edge Control */
135};
136
137#define intf_ctrl(id) ((id) ? (((id) & 1) ? LCD_TVIF_CTRL : \
138 LCD_DUMB2_CTRL) : LCD_SPU_DUMB_CTRL)
139#define dma_ctrl0(id) ((id) ? (((id) & 1) ? LCD_TV_CTRL0 : \
140 LCD_PN2_CTRL0) : LCD_SPU_DMA_CTRL0)
141#define dma_ctrl1(id) ((id) ? (((id) & 1) ? LCD_TV_CTRL1 : \
142 LCD_PN2_CTRL1) : LCD_SPU_DMA_CTRL1)
143#define dma_ctrl(ctrl1, id) (ctrl1 ? dma_ctrl1(id) : dma_ctrl0(id))
144
145/* 32 bit TV Path DMA Control 0*/
146#define LCD_TV_CTRL0 (0x0080)
147/* 32 bit TV Path DMA Control 1*/
148#define LCD_TV_CTRL1 (0x0084)
149/* 32 bit TV Path Video Contrast*/
150#define LCD_TV_CONTRAST (0x0088)
151/* 32 bit TV Path Video Saturation*/
152#define LCD_TV_SATURATION (0x008C)
153/* 32 bit TV Path Video Hue Adjust*/
154#define LCD_TV_CBSH_HUE (0x0090)
155/* 32 bit TV Path TVIF Control Register */
156#define LCD_TVIF_CTRL (0x0094)
157#define TV_VBLNK_VALID_EN (1 << 12)
158
159/* 32 bit TV Path I/O Pad Control*/
160#define LCD_TVIOPAD_CTRL (0x0098)
161/* 32 bit TV Path Cloc Divider */
162#define LCD_TCLK_DIV (0x009C)
163
164#define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
165 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
166
167/* dither configure */
168#ifdef CONFIG_CPU_PXA988
169#define LCD_DITHER_CTRL (0x01EC)
170#else
171#define LCD_DITHER_CTRL (0x00A0)
172#endif
173
174#define DITHER_TBL_INDEX_SEL(s) ((s) << 16)
175#define DITHER_MODE2(m) ((m) << 12)
176#define DITHER_MODE2_SHIFT (12)
177#define DITHER_4X8_EN2 (1 << 9)
178#define DITHER_4X8_EN2_SHIFT (9)
179#define DITHER_EN2 (1 << 8)
180#define DITHER_MODE1(m) ((m) << 4)
181#define DITHER_MODE1_SHIFT (4)
182#define DITHER_4X8_EN1 (1 << 1)
183#define DITHER_4X8_EN1_SHIFT (1)
184#define DITHER_EN1 (1)
185
186/* dither table data was fixed by video bpp of input and output*/
187#ifdef CONFIG_CPU_PXA988
188#define DITHER_TB_4X4_INDEX0 (0x6e4ca280)
189#define DITHER_TB_4X4_INDEX1 (0x5d7f91b3)
190#define DITHER_TB_4X8_INDEX0 (0xb391a280)
191#define DITHER_TB_4X8_INDEX1 (0x7f5d6e4c)
192#define DITHER_TB_4X8_INDEX2 (0x80a291b3)
193#define DITHER_TB_4X8_INDEX3 (0x4c6e5d7f)
194#define LCD_DITHER_TBL_DATA (0x01F0)
195#else
196#define DITHER_TB_4X4_INDEX0 (0x3b19f7d5)
197#define DITHER_TB_4X4_INDEX1 (0x082ac4e6)
198#define DITHER_TB_4X8_INDEX0 (0xf7d508e6)
199#define DITHER_TB_4X8_INDEX1 (0x3b194c2a)
200#define DITHER_TB_4X8_INDEX2 (0xc4e6d5f7)
201#define DITHER_TB_4X8_INDEX3 (0x082a193b)
202#define LCD_DITHER_TBL_DATA (0x00A4)
203#endif
204
205/* Video Frame 0&1 start address registers */
206#define LCD_SPU_DMA_START_ADDR_Y0 0x00C0
207#define LCD_SPU_DMA_START_ADDR_U0 0x00C4
208#define LCD_SPU_DMA_START_ADDR_V0 0x00C8
209#define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */
210#define LCD_SPU_DMA_START_ADDR_Y1 0x00D0
211#define LCD_SPU_DMA_START_ADDR_U1 0x00D4
212#define LCD_SPU_DMA_START_ADDR_V1 0x00D8
213#define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */
214
215/* YC & UV Pitch */
216#define LCD_SPU_DMA_PITCH_YC 0x00E0
217#define SPU_DMA_PITCH_C(c) ((c)<<16)
218#define SPU_DMA_PITCH_Y(y) (y)
219#define LCD_SPU_DMA_PITCH_UV 0x00E4
220#define SPU_DMA_PITCH_V(v) ((v)<<16)
221#define SPU_DMA_PITCH_U(u) (u)
222
223/* Video Starting Point on Screen Register */
224#define LCD_SPUT_DMA_OVSA_HPXL_VLN 0x00E8
225#define CFG_DMA_OVSA_VLN(y) ((y)<<16) /* 0~0xfff */
226#define CFG_DMA_OVSA_HPXL(x) (x) /* 0~0xfff */
227
228/* Video Size Register */
229#define LCD_SPU_DMA_HPXL_VLN 0x00EC
230#define CFG_DMA_VLN(y) ((y)<<16)
231#define CFG_DMA_HPXL(x) (x)
232
233/* Video Size After zooming Register */
234#define LCD_SPU_DZM_HPXL_VLN 0x00F0
235#define CFG_DZM_VLN(y) ((y)<<16)
236#define CFG_DZM_HPXL(x) (x)
237
238/* Graphic Frame 0&1 Starting Address Register */
239#define LCD_CFG_GRA_START_ADDR0 0x00F4
240#define LCD_CFG_GRA_START_ADDR1 0x00F8
241
242/* Graphic Frame Pitch */
243#define LCD_CFG_GRA_PITCH 0x00FC
244
245/* Graphic Starting Point on Screen Register */
246#define LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100
247#define CFG_GRA_OVSA_VLN(y) ((y)<<16)
248#define CFG_GRA_OVSA_HPXL(x) (x)
249
250/* Graphic Size Register */
251#define LCD_SPU_GRA_HPXL_VLN 0x0104
252#define CFG_GRA_VLN(y) ((y)<<16)
253#define CFG_GRA_HPXL(x) (x)
254
255/* Graphic Size after Zooming Register */
256#define LCD_SPU_GZM_HPXL_VLN 0x0108
257#define CFG_GZM_VLN(y) ((y)<<16)
258#define CFG_GZM_HPXL(x) (x)
259
260/* HW Cursor Starting Point on Screen Register */
261#define LCD_SPU_HWC_OVSA_HPXL_VLN 0x010C
262#define CFG_HWC_OVSA_VLN(y) ((y)<<16)
263#define CFG_HWC_OVSA_HPXL(x) (x)
264
265/* HW Cursor Size */
266#define LCD_SPU_HWC_HPXL_VLN 0x0110
267#define CFG_HWC_VLN(y) ((y)<<16)
268#define CFG_HWC_HPXL(x) (x)
269
270/* Total Screen Size Register */
271#define LCD_SPUT_V_H_TOTAL 0x0114
272#define CFG_V_TOTAL(y) ((y)<<16)
273#define CFG_H_TOTAL(x) (x)
274
275/* Total Screen Active Size Register */
276#define LCD_SPU_V_H_ACTIVE 0x0118
277#define CFG_V_ACTIVE(y) ((y)<<16)
278#define CFG_H_ACTIVE(x) (x)
279
280/* Screen H&V Porch Register */
281#define LCD_SPU_H_PORCH 0x011C
282#define CFG_H_BACK_PORCH(b) ((b)<<16)
283#define CFG_H_FRONT_PORCH(f) (f)
284#define LCD_SPU_V_PORCH 0x0120
285#define CFG_V_BACK_PORCH(b) ((b)<<16)
286#define CFG_V_FRONT_PORCH(f) (f)
287
288/* Screen Blank Color Register */
289#define LCD_SPU_BLANKCOLOR 0x0124
290#define CFG_BLANKCOLOR_MASK 0x00FFFFFF
291#define CFG_BLANKCOLOR_R_MASK 0x000000FF
292#define CFG_BLANKCOLOR_G_MASK 0x0000FF00
293#define CFG_BLANKCOLOR_B_MASK 0x00FF0000
294
295/* HW Cursor Color 1&2 Register */
296#define LCD_SPU_ALPHA_COLOR1 0x0128
297#define CFG_HWC_COLOR1 0x00FFFFFF
298#define CFG_HWC_COLOR1_R(red) ((red)<<16)
299#define CFG_HWC_COLOR1_G(green) ((green)<<8)
300#define CFG_HWC_COLOR1_B(blue) (blue)
301#define CFG_HWC_COLOR1_R_MASK 0x000000FF
302#define CFG_HWC_COLOR1_G_MASK 0x0000FF00
303#define CFG_HWC_COLOR1_B_MASK 0x00FF0000
304#define LCD_SPU_ALPHA_COLOR2 0x012C
305#define CFG_HWC_COLOR2 0x00FFFFFF
306#define CFG_HWC_COLOR2_R_MASK 0x000000FF
307#define CFG_HWC_COLOR2_G_MASK 0x0000FF00
308#define CFG_HWC_COLOR2_B_MASK 0x00FF0000
309
310/* Video YUV Color Key Control */
311#define LCD_SPU_COLORKEY_Y 0x0130
312#define CFG_CKEY_Y2(y2) ((y2)<<24)
313#define CFG_CKEY_Y2_MASK 0xFF000000
314#define CFG_CKEY_Y1(y1) ((y1)<<16)
315#define CFG_CKEY_Y1_MASK 0x00FF0000
316#define CFG_CKEY_Y(y) ((y)<<8)
317#define CFG_CKEY_Y_MASK 0x0000FF00
318#define CFG_ALPHA_Y(y) (y)
319#define CFG_ALPHA_Y_MASK 0x000000FF
320#define LCD_SPU_COLORKEY_U 0x0134
321#define CFG_CKEY_U2(u2) ((u2)<<24)
322#define CFG_CKEY_U2_MASK 0xFF000000
323#define CFG_CKEY_U1(u1) ((u1)<<16)
324#define CFG_CKEY_U1_MASK 0x00FF0000
325#define CFG_CKEY_U(u) ((u)<<8)
326#define CFG_CKEY_U_MASK 0x0000FF00
327#define CFG_ALPHA_U(u) (u)
328#define CFG_ALPHA_U_MASK 0x000000FF
329#define LCD_SPU_COLORKEY_V 0x0138
330#define CFG_CKEY_V2(v2) ((v2)<<24)
331#define CFG_CKEY_V2_MASK 0xFF000000
332#define CFG_CKEY_V1(v1) ((v1)<<16)
333#define CFG_CKEY_V1_MASK 0x00FF0000
334#define CFG_CKEY_V(v) ((v)<<8)
335#define CFG_CKEY_V_MASK 0x0000FF00
336#define CFG_ALPHA_V(v) (v)
337#define CFG_ALPHA_V_MASK 0x000000FF
338
339/* Graphics/Video DMA color key enable bits in LCD_TV_CTRL1 */
340#define CFG_CKEY_GRA 0x2
341#define CFG_CKEY_DMA 0x1
342
343/* Interlace mode enable bits in LCD_TV_CTRL1 */
344#define CFG_TV_INTERLACE_EN (1 << 22)
345#define CFG_TV_NIB (1 << 0)
346
347#define LCD_PN_SEPXLCNT 0x013c /* MMP2 */
348
349/* SPI Read Data Register */
350#define LCD_SPU_SPI_RXDATA 0x0140
351
352/* Smart Panel Read Data Register */
353#define LCD_SPU_ISA_RSDATA 0x0144
354#define ISA_RXDATA_16BIT_1_DATA_MASK 0x000000FF
355#define ISA_RXDATA_16BIT_2_DATA_MASK 0x0000FF00
356#define ISA_RXDATA_16BIT_3_DATA_MASK 0x00FF0000
357#define ISA_RXDATA_16BIT_4_DATA_MASK 0xFF000000
358#define ISA_RXDATA_32BIT_1_DATA_MASK 0x00FFFFFF
359
360#define LCD_SPU_DBG_ISA (0x0148) /* TTC */
361#define LCD_SPU_DMAVLD_YC (0x014C)
362#define LCD_SPU_DMAVLD_UV (0x0150)
363#define LCD_SPU_DMAVLD_UVSPU_GRAVLD (0x0154)
364
365#define LCD_READ_IOPAD (0x0148) /* MMP2*/
366#define LCD_DMAVLD_YC (0x014C)
367#define LCD_DMAVLD_UV (0x0150)
368#define LCD_TVGGRAVLD_HLEN (0x0154)
369
370/* HWC SRAM Read Data Register */
371#define LCD_SPU_HWC_RDDAT 0x0158
372
373/* Gamma Table SRAM Read Data Register */
374#define LCD_SPU_GAMMA_RDDAT 0x015c
375#define CFG_GAMMA_RDDAT_MASK 0x000000FF
376
377/* Palette Table SRAM Read Data Register */
378#define LCD_SPU_PALETTE_RDDAT 0x0160
379#define CFG_PALETTE_RDDAT_MASK 0x00FFFFFF
380
381#define LCD_SPU_DBG_DMATOP (0x0164) /* TTC */
382#define LCD_SPU_DBG_GRATOP (0x0168)
383#define LCD_SPU_DBG_TXCTRL (0x016C)
384#define LCD_SPU_DBG_SLVTOP (0x0170)
385#define LCD_SPU_DBG_MUXTOP (0x0174)
386
387#define LCD_SLV_DBG (0x0164) /* MMP2 */
388#define LCD_TVDVLD_YC (0x0168)
389#define LCD_TVDVLD_UV (0x016C)
390#define LCD_TVC_RDDAT (0x0170)
391#define LCD_TV_GAMMA_RDDAT (0x0174)
392
393/* I/O Pads Input Read Only Register */
394#define LCD_SPU_IOPAD_IN 0x0178
395#define CFG_IOPAD_IN_MASK 0x0FFFFFFF
396
397#define LCD_TV_PALETTE_RDDAT (0x0178) /* MMP2 */
398
399/* Reserved Read Only Registers */
400#define LCD_CFG_RDREG5F 0x017C
401#define IRE_FRAME_CNT_MASK 0x000000C0
402#define IPE_FRAME_CNT_MASK 0x00000030
403#define GRA_FRAME_CNT_MASK 0x0000000C /* Graphic */
404#define DMA_FRAME_CNT_MASK 0x00000003 /* Video */
405
406#define LCD_FRAME_CNT (0x017C) /* MMP2 */
407
408/* SPI Control Register. */
409#define LCD_SPU_SPI_CTRL 0x0180
410#define CFG_SCLKCNT(div) ((div)<<24) /* 0xFF~0x2 */
411#define CFG_SCLKCNT_MASK 0xFF000000
412#define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */
413#define CFG_RXBITS_MASK 0x00FF0000
414#define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */
415#define CFG_TXBITS_MASK 0x0000FF00
416#define CFG_CLKINV(clk) ((clk)<<7)
417#define CFG_CLKINV_MASK 0x00000080
418#define CFG_KEEPXFER(transfer) ((transfer)<<6)
419#define CFG_KEEPXFER_MASK 0x00000040
420#define CFG_RXBITSTO0(rx) ((rx)<<5)
421#define CFG_RXBITSTO0_MASK 0x00000020
422#define CFG_TXBITSTO0(tx) ((tx)<<4)
423#define CFG_TXBITSTO0_MASK 0x00000010
424#define CFG_SPI_ENA(spi) ((spi)<<3)
425#define CFG_SPI_ENA_MASK 0x00000008
426#define CFG_SPI_SEL(spi) ((spi)<<2)
427#define CFG_SPI_SEL_MASK 0x00000004
428#define CFG_SPI_3W4WB(wire) ((wire)<<1)
429#define CFG_SPI_3W4WB_MASK 0x00000002
430#define CFG_SPI_START(start) (start)
431#define CFG_SPI_START_MASK 0x00000001
432
433/* SPI Tx Data Register */
434#define LCD_SPU_SPI_TXDATA 0x0184
435
436/*
437 1. Smart Pannel 8-bit Bus Control Register.
438 2. AHB Slave Path Data Port Register
439*/
440#define LCD_SPU_SMPN_CTRL 0x0188
441
442/* DMA Control 0 Register */
443#define LCD_SPU_DMA_CTRL0 0x0190
444#define CFG_NOBLENDING(nb) ((nb)<<31)
445#define CFG_NOBLENDING_MASK 0x80000000
446#define CFG_GAMMA_ENA(gn) ((gn)<<30)
447#define CFG_GAMMA_ENA_MASK 0x40000000
448#define CFG_CBSH_ENA(cn) ((cn)<<29)
449#define CFG_CBSH_ENA_MASK 0x20000000
450#define CFG_PALETTE_ENA(pn) ((pn)<<28)
451#define CFG_PALETTE_ENA_MASK 0x10000000
452#define CFG_ARBFAST_ENA(an) ((an)<<27)
453#define CFG_ARBFAST_ENA_MASK 0x08000000
454#define CFG_HWC_1BITMOD(mode) ((mode)<<26)
455#define CFG_HWC_1BITMOD_MASK 0x04000000
456#define CFG_HWC_1BITENA(mn) ((mn)<<25)
457#define CFG_HWC_1BITENA_MASK 0x02000000
458#define CFG_HWC_ENA(cn) ((cn)<<24)
459#define CFG_HWC_ENA_MASK 0x01000000
460#define CFG_DMAFORMAT(dmaformat) ((dmaformat)<<20)
461#define CFG_DMAFORMAT_MASK 0x00F00000
462#define CFG_GRAFORMAT(graformat) ((graformat)<<16)
463#define CFG_GRAFORMAT_MASK 0x000F0000
464/* for graphic part */
465#define CFG_GRA_FTOGGLE(toggle) ((toggle)<<15)
466#define CFG_GRA_FTOGGLE_MASK 0x00008000
467#define CFG_GRA_HSMOOTH(smooth) ((smooth)<<14)
468#define CFG_GRA_HSMOOTH_MASK 0x00004000
469#define CFG_GRA_TSTMODE(test) ((test)<<13)
470#define CFG_GRA_TSTMODE_MASK 0x00002000
471#define CFG_GRA_SWAPRB(swap) ((swap)<<12)
472#define CFG_GRA_SWAPRB_MASK 0x00001000
473#define CFG_GRA_SWAPUV(swap) ((swap)<<11)
474#define CFG_GRA_SWAPUV_MASK 0x00000800
475#define CFG_GRA_SWAPYU(swap) ((swap)<<10)
476#define CFG_GRA_SWAPYU_MASK 0x00000400
477#define CFG_GRA_SWAP_MASK 0x00001C00
478#define CFG_YUV2RGB_GRA(cvrt) ((cvrt)<<9)
479#define CFG_YUV2RGB_GRA_MASK 0x00000200
480#define CFG_GRA_ENA(gra) ((gra)<<8)
481#define CFG_GRA_ENA_MASK 0x00000100
482#define dma0_gfx_masks (CFG_GRAFORMAT_MASK | CFG_GRA_FTOGGLE_MASK | \
483 CFG_GRA_HSMOOTH_MASK | CFG_GRA_TSTMODE_MASK | CFG_GRA_SWAP_MASK | \
484 CFG_YUV2RGB_GRA_MASK | CFG_GRA_ENA_MASK)
485/* for video part */
486#define CFG_DMA_FTOGGLE(toggle) ((toggle)<<7)
487#define CFG_DMA_FTOGGLE_MASK 0x00000080
488#define CFG_DMA_HSMOOTH(smooth) ((smooth)<<6)
489#define CFG_DMA_HSMOOTH_MASK 0x00000040
490#define CFG_DMA_TSTMODE(test) ((test)<<5)
491#define CFG_DMA_TSTMODE_MASK 0x00000020
492#define CFG_DMA_SWAPRB(swap) ((swap)<<4)
493#define CFG_DMA_SWAPRB_MASK 0x00000010
494#define CFG_DMA_SWAPUV(swap) ((swap)<<3)
495#define CFG_DMA_SWAPUV_MASK 0x00000008
496#define CFG_DMA_SWAPYU(swap) ((swap)<<2)
497#define CFG_DMA_SWAPYU_MASK 0x00000004
498#define CFG_DMA_SWAP_MASK 0x0000001C
499#define CFG_YUV2RGB_DMA(cvrt) ((cvrt)<<1)
500#define CFG_YUV2RGB_DMA_MASK 0x00000002
501#define CFG_DMA_ENA(video) (video)
502#define CFG_DMA_ENA_MASK 0x00000001
503#define dma0_vid_masks (CFG_DMAFORMAT_MASK | CFG_DMA_FTOGGLE_MASK | \
504 CFG_DMA_HSMOOTH_MASK | CFG_DMA_TSTMODE_MASK | CFG_DMA_SWAP_MASK | \
505 CFG_YUV2RGB_DMA_MASK | CFG_DMA_ENA_MASK)
506#define dma_palette(val) ((val ? 1 : 0) << 28)
507#define dma_fmt(vid, val) ((val & 0xf) << ((vid) ? 20 : 16))
508#define dma_swaprb(vid, val) ((val ? 1 : 0) << ((vid) ? 4 : 12))
509#define dma_swapuv(vid, val) ((val ? 1 : 0) << ((vid) ? 3 : 11))
510#define dma_swapyuv(vid, val) ((val ? 1 : 0) << ((vid) ? 2 : 10))
511#define dma_csc(vid, val) ((val ? 1 : 0) << ((vid) ? 1 : 9))
512#define dma_hsmooth(vid, val) ((val ? 1 : 0) << ((vid) ? 6 : 14))
513#define dma_mask(vid) (dma_palette(1) | dma_fmt(vid, 0xf) | dma_csc(vid, 1) \
514 | dma_swaprb(vid, 1) | dma_swapuv(vid, 1) | dma_swapyuv(vid, 1))
515
516/* DMA Control 1 Register */
517#define LCD_SPU_DMA_CTRL1 0x0194
518#define CFG_FRAME_TRIG(trig) ((trig)<<31)
519#define CFG_FRAME_TRIG_MASK 0x80000000
520#define CFG_VSYNC_TRIG(trig) ((trig)<<28)
521#define CFG_VSYNC_TRIG_MASK 0x70000000
522#define CFG_VSYNC_INV(inv) ((inv)<<27)
523#define CFG_VSYNC_INV_MASK 0x08000000
524#define CFG_COLOR_KEY_MODE(cmode) ((cmode)<<24)
525#define CFG_COLOR_KEY_MASK 0x07000000
526#define CFG_CARRY(carry) ((carry)<<23)
527#define CFG_CARRY_MASK 0x00800000
528#define CFG_LNBUF_ENA(lnbuf) ((lnbuf)<<22)
529#define CFG_LNBUF_ENA_MASK 0x00400000
530#define CFG_GATED_ENA(gated) ((gated)<<21)
531#define CFG_GATED_ENA_MASK 0x00200000
532#define CFG_PWRDN_ENA(power) ((power)<<20)
533#define CFG_PWRDN_ENA_MASK 0x00100000
534#define CFG_DSCALE(dscale) ((dscale)<<18)
535#define CFG_DSCALE_MASK 0x000C0000
536#define CFG_ALPHA_MODE(amode) ((amode)<<16)
537#define CFG_ALPHA_MODE_MASK 0x00030000
538#define CFG_ALPHA(alpha) ((alpha)<<8)
539#define CFG_ALPHA_MASK 0x0000FF00
540#define CFG_PXLCMD(pxlcmd) (pxlcmd)
541#define CFG_PXLCMD_MASK 0x000000FF
542
543/* SRAM Control Register */
544#define LCD_SPU_SRAM_CTRL 0x0198
545#define CFG_SRAM_INIT_WR_RD(mode) ((mode)<<14)
546#define CFG_SRAM_INIT_WR_RD_MASK 0x0000C000
547#define CFG_SRAM_ADDR_LCDID(id) ((id)<<8)
548#define CFG_SRAM_ADDR_LCDID_MASK 0x00000F00
549#define CFG_SRAM_ADDR(addr) (addr)
550#define CFG_SRAM_ADDR_MASK 0x000000FF
551
552/* SRAM Write Data Register */
553#define LCD_SPU_SRAM_WRDAT 0x019C
554
555/* SRAM RTC/WTC Control Register */
556#define LCD_SPU_SRAM_PARA0 0x01A0
557
558/* SRAM Power Down Control Register */
559#define LCD_SPU_SRAM_PARA1 0x01A4
560#define CFG_CSB_256x32(hwc) ((hwc)<<15) /* HWC */
561#define CFG_CSB_256x32_MASK 0x00008000
562#define CFG_CSB_256x24(palette) ((palette)<<14) /* Palette */
563#define CFG_CSB_256x24_MASK 0x00004000
564#define CFG_CSB_256x8(gamma) ((gamma)<<13) /* Gamma */
565#define CFG_CSB_256x8_MASK 0x00002000
566#define CFG_PDWN256x32(pdwn) ((pdwn)<<7) /* HWC */
567#define CFG_PDWN256x32_MASK 0x00000080
568#define CFG_PDWN256x24(pdwn) ((pdwn)<<6) /* Palette */
569#define CFG_PDWN256x24_MASK 0x00000040
570#define CFG_PDWN256x8(pdwn) ((pdwn)<<5) /* Gamma */
571#define CFG_PDWN256x8_MASK 0x00000020
572#define CFG_PDWN32x32(pdwn) ((pdwn)<<3)
573#define CFG_PDWN32x32_MASK 0x00000008
574#define CFG_PDWN16x66(pdwn) ((pdwn)<<2)
575#define CFG_PDWN16x66_MASK 0x00000004
576#define CFG_PDWN32x66(pdwn) ((pdwn)<<1)
577#define CFG_PDWN32x66_MASK 0x00000002
578#define CFG_PDWN64x66(pdwn) (pdwn)
579#define CFG_PDWN64x66_MASK 0x00000001
580
581/* Smart or Dumb Panel Clock Divider */
582#define LCD_CFG_SCLK_DIV 0x01A8
583#define SCLK_SRC_SEL(src) ((src)<<31)
584#define SCLK_SRC_SEL_MASK 0x80000000
585#define SCLK_DISABLE (1<<28)
586#define CLK_FRACDIV(frac) ((frac)<<16)
587#define CLK_FRACDIV_MASK 0x0FFF0000
588#define DSI1_BITCLK_DIV(div) (div<<8)
589#define DSI1_BITCLK_DIV_MASK 0x00000F00
590#define CLK_INT_DIV(div) (div)
591#define CLK_INT_DIV_MASK 0x000000FF
592
593/* Video Contrast Register */
594#define LCD_SPU_CONTRAST 0x01AC
595#define CFG_BRIGHTNESS(bright) ((bright)<<16)
596#define CFG_BRIGHTNESS_MASK 0xFFFF0000
597#define CFG_CONTRAST(contrast) (contrast)
598#define CFG_CONTRAST_MASK 0x0000FFFF
599
600/* Video Saturation Register */
601#define LCD_SPU_SATURATION 0x01B0
602#define CFG_C_MULTS(mult) ((mult)<<16)
603#define CFG_C_MULTS_MASK 0xFFFF0000
604#define CFG_SATURATION(sat) (sat)
605#define CFG_SATURATION_MASK 0x0000FFFF
606
607/* Video Hue Adjust Register */
608#define LCD_SPU_CBSH_HUE 0x01B4
609#define CFG_SIN0(sin0) ((sin0)<<16)
610#define CFG_SIN0_MASK 0xFFFF0000
611#define CFG_COS0(con0) (con0)
612#define CFG_COS0_MASK 0x0000FFFF
613
614/* Dump LCD Panel Control Register */
615#define LCD_SPU_DUMB_CTRL 0x01B8
616#define CFG_DUMBMODE(mode) ((mode)<<28)
617#define CFG_DUMBMODE_MASK 0xF0000000
618#define CFG_LCDGPIO_O(data) ((data)<<20)
619#define CFG_LCDGPIO_O_MASK 0x0FF00000
620#define CFG_LCDGPIO_ENA(gpio) ((gpio)<<12)
621#define CFG_LCDGPIO_ENA_MASK 0x000FF000
622#define CFG_BIAS_OUT(bias) ((bias)<<8)
623#define CFG_BIAS_OUT_MASK 0x00000100
624#define CFG_REVERSE_RGB(RGB) ((RGB)<<7)
625#define CFG_REVERSE_RGB_MASK 0x00000080
626#define CFG_INV_COMPBLANK(blank) ((blank)<<6)
627#define CFG_INV_COMPBLANK_MASK 0x00000040
628#define CFG_INV_COMPSYNC(sync) ((sync)<<5)
629#define CFG_INV_COMPSYNC_MASK 0x00000020
630#define CFG_INV_HENA(hena) ((hena)<<4)
631#define CFG_INV_HENA_MASK 0x00000010
632#define CFG_INV_VSYNC(vsync) ((vsync)<<3)
633#define CFG_INV_VSYNC_MASK 0x00000008
634#define CFG_INV_HSYNC(hsync) ((hsync)<<2)
635#define CFG_INV_HSYNC_MASK 0x00000004
636#define CFG_INV_PCLK(pclk) ((pclk)<<1)
637#define CFG_INV_PCLK_MASK 0x00000002
638#define CFG_DUMB_ENA(dumb) (dumb)
639#define CFG_DUMB_ENA_MASK 0x00000001
640
641/* LCD I/O Pads Control Register */
642#define SPU_IOPAD_CONTROL 0x01BC
643#define CFG_GRA_VM_ENA(vm) ((vm)<<15)
644#define CFG_GRA_VM_ENA_MASK 0x00008000
645#define CFG_DMA_VM_ENA(vm) ((vm)<<13)
646#define CFG_DMA_VM_ENA_MASK 0x00002000
647#define CFG_CMD_VM_ENA(vm) ((vm)<<12)
648#define CFG_CMD_VM_ENA_MASK 0x00001000
649#define CFG_CSC(csc) ((csc)<<8)
650#define CFG_CSC_MASK 0x00000300
651#define CFG_BOUNDARY(size) ((size)<<5)
652#define CFG_BOUNDARY_MASK 0x00000020
653#define CFG_BURST(len) ((len)<<4)
654#define CFG_BURST_MASK 0x00000010
655#define CFG_IOPADMODE(iopad) (iopad)
656#define CFG_IOPADMODE_MASK 0x0000000F
657
658/* LCD Interrupt Control Register */
659#define SPU_IRQ_ENA 0x01C0
660#define DMA_FRAME_IRQ0_ENA(irq) ((irq)<<31)
661#define DMA_FRAME_IRQ0_ENA_MASK 0x80000000
662#define DMA_FRAME_IRQ1_ENA(irq) ((irq)<<30)
663#define DMA_FRAME_IRQ1_ENA_MASK 0x40000000
664#define DMA_FF_UNDERFLOW_ENA(ff) ((ff)<<29)
665#define DMA_FF_UNDERFLOW_ENA_MASK 0x20000000
666#define AXI_BUS_ERROR_IRQ_ENA(irq) ((irq)<<28)
667#define AXI_BUS_ERROR_IRQ_ENA_MASK 0x10000000
668#define GRA_FRAME_IRQ0_ENA(irq) ((irq)<<27)
669#define GRA_FRAME_IRQ0_ENA_MASK 0x08000000
670#define GRA_FRAME_IRQ1_ENA(irq) ((irq)<<26)
671#define GRA_FRAME_IRQ1_ENA_MASK 0x04000000
672#define GRA_FF_UNDERFLOW_ENA(ff) ((ff)<<25)
673#define GRA_FF_UNDERFLOW_ENA_MASK 0x02000000
674#define VSYNC_IRQ_ENA(vsync_irq) ((vsync_irq)<<23)
675#define VSYNC_IRQ_ENA_MASK 0x00800000
676#define DUMB_FRAMEDONE_ENA(fdone) ((fdone)<<22)
677#define DUMB_FRAMEDONE_ENA_MASK 0x00400000
678#define TWC_FRAMEDONE_ENA(fdone) ((fdone)<<21)
679#define TWC_FRAMEDONE_ENA_MASK 0x00200000
680#define HWC_FRAMEDONE_ENA(fdone) ((fdone)<<20)
681#define HWC_FRAMEDONE_ENA_MASK 0x00100000
682#define SLV_IRQ_ENA(irq) ((irq)<<19)
683#define SLV_IRQ_ENA_MASK 0x00080000
684#define SPI_IRQ_ENA(irq) ((irq)<<18)
685#define SPI_IRQ_ENA_MASK 0x00040000
686#define PWRDN_IRQ_ENA(irq) ((irq)<<17)
687#define PWRDN_IRQ_ENA_MASK 0x00020000
688#define AXI_LATENCY_TOO_LONG_IRQ_ENA(irq) ((irq)<<16)
689#define AXI_LATENCY_TOO_LONG_IRQ_ENA_MASK 0x00010000
690#define CLEAN_SPU_IRQ_ISR(irq) (irq)
691#define CLEAN_SPU_IRQ_ISR_MASK 0x0000FFFF
692#define TV_DMA_FRAME_IRQ0_ENA(irq) ((irq)<<15)
693#define TV_DMA_FRAME_IRQ0_ENA_MASK 0x00008000
694#define TV_DMA_FRAME_IRQ1_ENA(irq) ((irq)<<14)
695#define TV_DMA_FRAME_IRQ1_ENA_MASK 0x00004000
696#define TV_DMA_FF_UNDERFLOW_ENA(unerrun) ((unerrun)<<13)
697#define TV_DMA_FF_UNDERFLOW_ENA_MASK 0x00002000
698#define TVSYNC_IRQ_ENA(irq) ((irq)<<12)
699#define TVSYNC_IRQ_ENA_MASK 0x00001000
700#define TV_FRAME_IRQ0_ENA(irq) ((irq)<<11)
701#define TV_FRAME_IRQ0_ENA_MASK 0x00000800
702#define TV_FRAME_IRQ1_ENA(irq) ((irq)<<10)
703#define TV_FRAME_IRQ1_ENA_MASK 0x00000400
704#define TV_GRA_FF_UNDERFLOW_ENA(unerrun) ((unerrun)<<9)
705#define TV_GRA_FF_UNDERFLOW_ENA_MASK 0x00000200
706#define TV_FRAMEDONE_ENA(irq) ((irq)<<8)
707#define TV_FRAMEDONE_ENA_MASK 0x00000100
708
709/* FIXME - JUST GUESS */
710#define PN2_DMA_FRAME_IRQ0_ENA(irq) ((irq)<<7)
711#define PN2_DMA_FRAME_IRQ0_ENA_MASK 0x00000080
712#define PN2_DMA_FRAME_IRQ1_ENA(irq) ((irq)<<6)
713#define PN2_DMA_FRAME_IRQ1_ENA_MASK 0x00000040
714#define PN2_DMA_FF_UNDERFLOW_ENA(ff) ((ff)<<5)
715#define PN2_DMA_FF_UNDERFLOW_ENA_MASK 0x00000020
716#define PN2_GRA_FRAME_IRQ0_ENA(irq) ((irq)<<3)
717#define PN2_GRA_FRAME_IRQ0_ENA_MASK 0x00000008
718#define PN2_GRA_FRAME_IRQ1_ENA(irq) ((irq)<<2)
719#define PN2_GRA_FRAME_IRQ1_ENA_MASK 0x04000004
720#define PN2_GRA_FF_UNDERFLOW_ENA(ff) ((ff)<<1)
721#define PN2_GRA_FF_UNDERFLOW_ENA_MASK 0x00000002
722#define PN2_VSYNC_IRQ_ENA(irq) ((irq)<<0)
723#define PN2_SYNC_IRQ_ENA_MASK 0x00000001
724
725#define gf0_imask(id) ((id) ? (((id) & 1) ? TV_FRAME_IRQ0_ENA_MASK \
726 : PN2_GRA_FRAME_IRQ0_ENA_MASK) : GRA_FRAME_IRQ0_ENA_MASK)
727#define gf1_imask(id) ((id) ? (((id) & 1) ? TV_FRAME_IRQ1_ENA_MASK \
728 : PN2_GRA_FRAME_IRQ1_ENA_MASK) : GRA_FRAME_IRQ1_ENA_MASK)
729#define vsync_imask(id) ((id) ? (((id) & 1) ? TVSYNC_IRQ_ENA_MASK \
730 : PN2_SYNC_IRQ_ENA_MASK) : VSYNC_IRQ_ENA_MASK)
731#define vsync_imasks (vsync_imask(0) | vsync_imask(1))
732
733#define display_done_imask(id) ((id) ? (((id) & 1) ? TV_FRAMEDONE_ENA_MASK\
734 : (PN2_DMA_FRAME_IRQ0_ENA_MASK | PN2_DMA_FRAME_IRQ1_ENA_MASK))\
735 : DUMB_FRAMEDONE_ENA_MASK)
736
737#define display_done_imasks (display_done_imask(0) | display_done_imask(1))
738
739#define vf0_imask(id) ((id) ? (((id) & 1) ? TV_DMA_FRAME_IRQ0_ENA_MASK \
740 : PN2_DMA_FRAME_IRQ0_ENA_MASK) : DMA_FRAME_IRQ0_ENA_MASK)
741#define vf1_imask(id) ((id) ? (((id) & 1) ? TV_DMA_FRAME_IRQ1_ENA_MASK \
742 : PN2_DMA_FRAME_IRQ1_ENA_MASK) : DMA_FRAME_IRQ1_ENA_MASK)
743
744#define gfx_imasks (gf0_imask(0) | gf1_imask(0) | gf0_imask(1) | \
745 gf1_imask(1))
746#define vid_imasks (vf0_imask(0) | vf1_imask(0) | vf0_imask(1) | \
747 vf1_imask(1))
748#define vid_imask(id) (display_done_imask(id))
749
750#define pn1_imasks (gf0_imask(0) | gf1_imask(0) | vsync_imask(0) | \
751 display_done_imask(0) | vf0_imask(0) | vf1_imask(0))
752#define tv_imasks (gf0_imask(1) | gf1_imask(1) | vsync_imask(1) | \
753 display_done_imask(1) | vf0_imask(1) | vf1_imask(1))
754#define path_imasks(id) ((id) ? (tv_imasks) : (pn1_imasks))
755
756/* error indications */
757#define vid_udflow_imask(id) ((id) ? (((id) & 1) ? \
758 (TV_DMA_FF_UNDERFLOW_ENA_MASK) : (PN2_DMA_FF_UNDERFLOW_ENA_MASK)) : \
759 (DMA_FF_UNDERFLOW_ENA_MASK))
760#define gfx_udflow_imask(id) ((id) ? (((id) & 1) ? \
761 (TV_GRA_FF_UNDERFLOW_ENA_MASK) : (PN2_GRA_FF_UNDERFLOW_ENA_MASK)) : \
762 (GRA_FF_UNDERFLOW_ENA_MASK))
763
764#define err_imask(id) (vid_udflow_imask(id) | gfx_udflow_imask(id) | \
765 AXI_BUS_ERROR_IRQ_ENA_MASK | AXI_LATENCY_TOO_LONG_IRQ_ENA_MASK)
766#define err_imasks (err_imask(0) | err_imask(1) | err_imask(2))
767/* LCD Interrupt Status Register */
768#define SPU_IRQ_ISR 0x01C4
769#define DMA_FRAME_IRQ0(irq) ((irq)<<31)
770#define DMA_FRAME_IRQ0_MASK 0x80000000
771#define DMA_FRAME_IRQ1(irq) ((irq)<<30)
772#define DMA_FRAME_IRQ1_MASK 0x40000000
773#define DMA_FF_UNDERFLOW(ff) ((ff)<<29)
774#define DMA_FF_UNDERFLOW_MASK 0x20000000
775#define AXI_BUS_ERROR_IRQ(irq) ((irq)<<28)
776#define AXI_BUS_ERROR_IRQ_MASK 0x10000000
777#define GRA_FRAME_IRQ0(irq) ((irq)<<27)
778#define GRA_FRAME_IRQ0_MASK 0x08000000
779#define GRA_FRAME_IRQ1(irq) ((irq)<<26)
780#define GRA_FRAME_IRQ1_MASK 0x04000000
781#define GRA_FF_UNDERFLOW(ff) ((ff)<<25)
782#define GRA_FF_UNDERFLOW_MASK 0x02000000
783#define VSYNC_IRQ(vsync_irq) ((vsync_irq)<<23)
784#define VSYNC_IRQ_MASK 0x00800000
785#define DUMB_FRAMEDONE(fdone) ((fdone)<<22)
786#define DUMB_FRAMEDONE_MASK 0x00400000
787#define TWC_FRAMEDONE(fdone) ((fdone)<<21)
788#define TWC_FRAMEDONE_MASK 0x00200000
789#define HWC_FRAMEDONE(fdone) ((fdone)<<20)
790#define HWC_FRAMEDONE_MASK 0x00100000
791#define SLV_IRQ(irq) ((irq)<<19)
792#define SLV_IRQ_MASK 0x00080000
793#define SPI_IRQ(irq) ((irq)<<18)
794#define SPI_IRQ_MASK 0x00040000
795#define PWRDN_IRQ(irq) ((irq)<<17)
796#define PWRDN_IRQ_MASK 0x00020000
797#define AXI_LATENCY_TOO_LONGR_IRQ(irq) ((irq)<<16)
798#define AXI_LATENCY_TOO_LONGR_IRQ_MASK 0x00010000
799#define TV_DMA_FRAME_IRQ0(irq) ((irq)<<15)
800#define TV_DMA_FRAME_IRQ0_MASK 0x00008000
801#define TV_DMA_FRAME_IRQ1(irq) ((irq)<<14)
802#define TV_DMA_FRAME_IRQ1_MASK 0x00004000
803#define TV_DMA_FF_UNDERFLOW(unerrun) ((unerrun)<<13)
804#define TV_DMA_FF_UNDERFLOW_MASK 0x00002000
805#define TVSYNC_IRQ(irq) ((irq)<<12)
806#define TVSYNC_IRQ_MASK 0x00001000
807#define TV_FRAME_IRQ0(irq) ((irq)<<11)
808#define TV_FRAME_IRQ0_MASK 0x00000800
809#define TV_FRAME_IRQ1(irq) ((irq)<<10)
810#define TV_FRAME_IRQ1_MASK 0x00000400
811#define TV_GRA_FF_UNDERFLOW(unerrun) ((unerrun)<<9)
812#define TV_GRA_FF_UNDERFLOW_MASK 0x00000200
813#define PN2_DMA_FRAME_IRQ0(irq) ((irq)<<7)
814#define PN2_DMA_FRAME_IRQ0_MASK 0x00000080
815#define PN2_DMA_FRAME_IRQ1(irq) ((irq)<<6)
816#define PN2_DMA_FRAME_IRQ1_MASK 0x00000040
817#define PN2_DMA_FF_UNDERFLOW(ff) ((ff)<<5)
818#define PN2_DMA_FF_UNDERFLOW_MASK 0x00000020
819#define PN2_GRA_FRAME_IRQ0(irq) ((irq)<<3)
820#define PN2_GRA_FRAME_IRQ0_MASK 0x00000008
821#define PN2_GRA_FRAME_IRQ1(irq) ((irq)<<2)
822#define PN2_GRA_FRAME_IRQ1_MASK 0x04000004
823#define PN2_GRA_FF_UNDERFLOW(ff) ((ff)<<1)
824#define PN2_GRA_FF_UNDERFLOW_MASK 0x00000002
825#define PN2_VSYNC_IRQ(irq) ((irq)<<0)
826#define PN2_SYNC_IRQ_MASK 0x00000001
827
828/* LCD FIFO Depth register */
829#define LCD_FIFO_DEPTH 0x01c8
830#define VIDEO_FIFO(fi) ((fi) << 0)
831#define VIDEO_FIFO_MASK 0x00000003
832#define GRAPHIC_FIFO(fi) ((fi) << 2)
833#define GRAPHIC_FIFO_MASK 0x0000000c
834
835/* read-only */
836#define DMA_FRAME_IRQ0_LEVEL_MASK 0x00008000
837#define DMA_FRAME_IRQ1_LEVEL_MASK 0x00004000
838#define DMA_FRAME_CNT_ISR_MASK 0x00003000
839#define GRA_FRAME_IRQ0_LEVEL_MASK 0x00000800
840#define GRA_FRAME_IRQ1_LEVEL_MASK 0x00000400
841#define GRA_FRAME_CNT_ISR_MASK 0x00000300
842#define VSYNC_IRQ_LEVEL_MASK 0x00000080
843#define DUMB_FRAMEDONE_LEVEL_MASK 0x00000040
844#define TWC_FRAMEDONE_LEVEL_MASK 0x00000020
845#define HWC_FRAMEDONE_LEVEL_MASK 0x00000010
846#define SLV_FF_EMPTY_MASK 0x00000008
847#define DMA_FF_ALLEMPTY_MASK 0x00000004
848#define GRA_FF_ALLEMPTY_MASK 0x00000002
849#define PWRDN_IRQ_LEVEL_MASK 0x00000001
850
851/* 32 bit LCD Interrupt Reset Status*/
852#define SPU_IRQ_RSR (0x01C8)
853/* 32 bit Panel Path Graphic Partial Display Horizontal Control Register*/
854#define LCD_GRA_CUTHPXL (0x01CC)
855/* 32 bit Panel Path Graphic Partial Display Vertical Control Register*/
856#define LCD_GRA_CUTVLN (0x01D0)
857/* 32 bit TV Path Graphic Partial Display Horizontal Control Register*/
858#define LCD_TVG_CUTHPXL (0x01D4)
859/* 32 bit TV Path Graphic Partial Display Vertical Control Register*/
860#define LCD_TVG_CUTVLN (0x01D8)
861/* 32 bit LCD Global Control Register*/
862#define LCD_TOP_CTRL (0x01DC)
863/* 32 bit LCD SQU Line Buffer Control Register 1*/
864#define LCD_SQULN1_CTRL (0x01E0)
865/* 32 bit LCD SQU Line Buffer Control Register 2*/
866#define LCD_SQULN2_CTRL (0x01E4)
867#define squln_ctrl(id) ((id) ? (((id) & 1) ? LCD_SQULN2_CTRL : \
868 LCD_PN2_SQULN1_CTRL) : LCD_SQULN1_CTRL)
869
870/* 32 bit LCD Mixed Overlay Control Register */
871#define LCD_AFA_ALL2ONE (0x01E8)
872
873#define LCD_PN2_SCLK_DIV (0x01EC)
874#define LCD_PN2_TCLK_DIV (0x01F0)
875#define LCD_LVDS_SCLK_DIV_WR (0x01F4)
876#define LCD_LVDS_SCLK_DIV_RD (0x01FC)
877#define PN2_LCD_DMA_START_ADDR_Y0 (0x0200)
878#define PN2_LCD_DMA_START_ADDR_U0 (0x0204)
879#define PN2_LCD_DMA_START_ADDR_V0 (0x0208)
880#define PN2_LCD_DMA_START_ADDR_C0 (0x020C)
881#define PN2_LCD_DMA_START_ADDR_Y1 (0x0210)
882#define PN2_LCD_DMA_START_ADDR_U1 (0x0214)
883#define PN2_LCD_DMA_START_ADDR_V1 (0x0218)
884#define PN2_LCD_DMA_START_ADDR_C1 (0x021C)
885#define PN2_LCD_DMA_PITCH_YC (0x0220)
886#define PN2_LCD_DMA_PITCH_UV (0x0224)
887#define PN2_LCD_DMA_OVSA_HPXL_VLN (0x0228)
888#define PN2_LCD_DMA_HPXL_VLN (0x022C)
889#define PN2_LCD_DMAZM_HPXL_VLN (0x0230)
890#define PN2_LCD_GRA_START_ADDR0 (0x0234)
891#define PN2_LCD_GRA_START_ADDR1 (0x0238)
892#define PN2_LCD_GRA_PITCH (0x023C)
893#define PN2_LCD_GRA_OVSA_HPXL_VLN (0x0240)
894#define PN2_LCD_GRA_HPXL_VLN (0x0244)
895#define PN2_LCD_GRAZM_HPXL_VLN (0x0248)
896#define PN2_LCD_HWC_OVSA_HPXL_VLN (0x024C)
897#define PN2_LCD_HWC_HPXL_VLN (0x0250)
898#define LCD_PN2_V_H_TOTAL (0x0254)
899#define LCD_PN2_V_H_ACTIVE (0x0258)
900#define LCD_PN2_H_PORCH (0x025C)
901#define LCD_PN2_V_PORCH (0x0260)
902#define LCD_PN2_BLANKCOLOR (0x0264)
903#define LCD_PN2_ALPHA_COLOR1 (0x0268)
904#define LCD_PN2_ALPHA_COLOR2 (0x026C)
905#define LCD_PN2_COLORKEY_Y (0x0270)
906#define LCD_PN2_COLORKEY_U (0x0274)
907#define LCD_PN2_COLORKEY_V (0x0278)
908#define LCD_PN2_SEPXLCNT (0x027C)
909#define LCD_TV_V_H_TOTAL_FLD (0x0280)
910#define LCD_TV_V_PORCH_FLD (0x0284)
911#define LCD_TV_SEPXLCNT_FLD (0x0288)
912
913#define LCD_2ND_ALPHA (0x0294)
914#define LCD_PN2_CONTRAST (0x0298)
915#define LCD_PN2_SATURATION (0x029c)
916#define LCD_PN2_CBSH_HUE (0x02a0)
917#define LCD_TIMING_EXT (0x02C0)
918#define LCD_PN2_LAYER_ALPHA_SEL1 (0x02c4)
919#define LCD_PN2_CTRL0 (0x02C8)
920#define TV_LAYER_ALPHA_SEL1 (0x02cc)
921#define LCD_SMPN2_CTRL (0x02D0)
922#define LCD_IO_OVERL_MAP_CTRL (0x02D4)
923#define LCD_DUMB2_CTRL (0x02d8)
924#define LCD_PN2_CTRL1 (0x02DC)
925#define PN2_IOPAD_CONTROL (0x02E0)
926#define LCD_PN2_SQULN1_CTRL (0x02E4)
927#define PN2_LCD_GRA_CUTHPXL (0x02e8)
928#define PN2_LCD_GRA_CUTVLN (0x02ec)
929#define LCD_PN2_SQULN2_CTRL (0x02F0)
930#define ALL_LAYER_ALPHA_SEL (0x02F4)
931
932/* pxa988 has different MASTER_CTRL from MMP3/MMP2 */
933#ifdef CONFIG_CPU_PXA988
934#define TIMING_MASTER_CONTROL (0x01F4)
935#define MASTER_ENH(id) (1 << ((id) + 5))
936#define MASTER_ENV(id) (1 << ((id) + 6))
937#else
938#define TIMING_MASTER_CONTROL (0x02F8)
939#define MASTER_ENH(id) (1 << (id))
940#define MASTER_ENV(id) (1 << ((id) + 4))
941#endif
942
943#define DSI_START_SEL_SHIFT(id) (((id) << 1) + 8)
944#define timing_master_config(path, dsi_id, lcd_id) \
945 (MASTER_ENH(path) | MASTER_ENV(path) | \
946 (((lcd_id) + ((dsi_id) << 1)) << DSI_START_SEL_SHIFT(path)))
947
948#define LCD_2ND_BLD_CTL (0x02Fc)
949#define LVDS_SRC_MASK (3 << 30)
950#define LVDS_SRC_SHIFT (30)
951#define LVDS_FMT_MASK (1 << 28)
952#define LVDS_FMT_SHIFT (28)
953
954#define CLK_SCLK (1 << 0)
955#define CLK_LVDS_RD (1 << 1)
956#define CLK_LVDS_WR (1 << 2)
957
958#define gra_partdisp_ctrl_hor(id) ((id) ? (((id) & 1) ? \
959 LCD_TVG_CUTHPXL : PN2_LCD_GRA_CUTHPXL) : LCD_GRA_CUTHPXL)
960#define gra_partdisp_ctrl_ver(id) ((id) ? (((id) & 1) ? \
961 LCD_TVG_CUTVLN : PN2_LCD_GRA_CUTVLN) : LCD_GRA_CUTVLN)
962
963/*
964 * defined Video Memory Color format for DMA control 0 register
965 * DMA0 bit[23:20]
966 */
967#define VMODE_RGB565 0x0
968#define VMODE_RGB1555 0x1
969#define VMODE_RGB888PACKED 0x2
970#define VMODE_RGB888UNPACKED 0x3
971#define VMODE_RGBA888 0x4
972#define VMODE_YUV422PACKED 0x5
973#define VMODE_YUV422PLANAR 0x6
974#define VMODE_YUV420PLANAR 0x7
975#define VMODE_SMPNCMD 0x8
976#define VMODE_PALETTE4BIT 0x9
977#define VMODE_PALETTE8BIT 0xa
978#define VMODE_RESERVED 0xb
979
980/*
981 * defined Graphic Memory Color format for DMA control 0 register
982 * DMA0 bit[19:16]
983 */
984#define GMODE_RGB565 0x0
985#define GMODE_RGB1555 0x1
986#define GMODE_RGB888PACKED 0x2
987#define GMODE_RGB888UNPACKED 0x3
988#define GMODE_RGBA888 0x4
989#define GMODE_YUV422PACKED 0x5
990#define GMODE_YUV422PLANAR 0x6
991#define GMODE_YUV420PLANAR 0x7
992#define GMODE_SMPNCMD 0x8
993#define GMODE_PALETTE4BIT 0x9
994#define GMODE_PALETTE8BIT 0xa
995#define GMODE_RESERVED 0xb
996
997/*
998 * define for DMA control 1 register
999 */
1000#define DMA1_FRAME_TRIG 31 /* bit location */
1001#define DMA1_VSYNC_MODE 28
1002#define DMA1_VSYNC_INV 27
1003#define DMA1_CKEY 24
1004#define DMA1_CARRY 23
1005#define DMA1_LNBUF_ENA 22
1006#define DMA1_GATED_ENA 21
1007#define DMA1_PWRDN_ENA 20
1008#define DMA1_DSCALE 18
1009#define DMA1_ALPHA_MODE 16
1010#define DMA1_ALPHA 08
1011#define DMA1_PXLCMD 00
1012
1013/*
1014 * defined for Configure Dumb Mode
1015 * DUMB LCD Panel bit[31:28]
1016 */
1017#define DUMB16_RGB565_0 0x0
1018#define DUMB16_RGB565_1 0x1
1019#define DUMB18_RGB666_0 0x2
1020#define DUMB18_RGB666_1 0x3
1021#define DUMB12_RGB444_0 0x4
1022#define DUMB12_RGB444_1 0x5
1023#define DUMB24_RGB888_0 0x6
1024#define DUMB_BLANK 0x7
1025
1026/*
1027 * defined for Configure I/O Pin Allocation Mode
1028 * LCD LCD I/O Pads control register bit[3:0]
1029 */
1030#define IOPAD_DUMB24 0x0
1031#define IOPAD_DUMB18SPI 0x1
1032#define IOPAD_DUMB18GPIO 0x2
1033#define IOPAD_DUMB16SPI 0x3
1034#define IOPAD_DUMB16GPIO 0x4
1035#define IOPAD_DUMB12 0x5
1036#define IOPAD_SMART18SPI 0x6
1037#define IOPAD_SMART16SPI 0x7
1038#define IOPAD_SMART8BOTH 0x8
1039#define IOPAD_DUMB18_SMART8 0x9
1040#define IOPAD_DUMB16_SMART8SPI 0xa
1041#define IOPAD_DUMB16_SMART8GPIO 0xb
1042#define IOPAD_DUMB16_DUMB16 0xc
1043#define IOPAD_SMART8_SMART8 0xc
1044
1045/*
1046 *defined for indicating boundary and cycle burst length
1047 */
1048#define CFG_BOUNDARY_1KB (1<<5)
1049#define CFG_BOUNDARY_4KB (0<<5)
1050#define CFG_CYC_BURST_LEN16 (1<<4)
1051#define CFG_CYC_BURST_LEN8 (0<<4)
1052
1053/*
1054 * defined Dumb Panel Clock Divider register
1055 * SCLK_Source bit[31]
1056 */
1057 /* 0: PLL clock select*/
1058#define AXI_BUS_SEL 0x80000000
1059#define CCD_CLK_SEL 0x40000000
1060#define DCON_CLK_SEL 0x20000000
1061#define ENA_CLK_INT_DIV CONFIG_FB_DOVE_CLCD_SCLK_DIV
1062#define IDLE_CLK_INT_DIV 0x1 /* idle Integer Divider */
1063#define DIS_CLK_INT_DIV 0x0 /* Disable Integer Divider */
1064
1065/* SRAM ID */
1066#define SRAMID_GAMMA_YR 0x0
1067#define SRAMID_GAMMA_UG 0x1
1068#define SRAMID_GAMMA_VB 0x2
1069#define SRAMID_PALATTE 0x3
1070#define SRAMID_HWC 0xf
1071
1072/* SRAM INIT Read/Write */
1073#define SRAMID_INIT_READ 0x0
1074#define SRAMID_INIT_WRITE 0x2
1075#define SRAMID_INIT_DEFAULT 0x3
1076
1077/*
1078 * defined VSYNC selection mode for DMA control 1 register
1079 * DMA1 bit[30:28]
1080 */
1081#define VMODE_SMPN 0x0
1082#define VMODE_SMPNIRQ 0x1
1083#define VMODE_DUMB 0x2
1084#define VMODE_IPE 0x3
1085#define VMODE_IRE 0x4
1086
1087/*
1088 * defined Configure Alpha and Alpha mode for DMA control 1 register
1089 * DMA1 bit[15:08](alpha) / bit[17:16](alpha mode)
1090 */
1091/* ALPHA mode */
1092#define MODE_ALPHA_DMA 0x0
1093#define MODE_ALPHA_GRA 0x1
1094#define MODE_ALPHA_CFG 0x2
1095
1096/* alpha value */
1097#define ALPHA_NOGRAPHIC 0xFF /* all video, no graphic */
1098#define ALPHA_NOVIDEO 0x00 /* all graphic, no video */
1099#define ALPHA_GRAPHNVIDEO 0x0F /* Selects graphic & video */
1100
1101/*
1102 * defined Pixel Command for DMA control 1 register
1103 * DMA1 bit[07:00]
1104 */
1105#define PIXEL_CMD 0x81
1106
1107/* DSI */
1108/* DSI1 - 4 Lane Controller base */
1109#define DSI1_REGS_PHYSICAL_BASE 0xD420B800
1110/* DSI2 - 3 Lane Controller base */
1111#define DSI2_REGS_PHYSICAL_BASE 0xD420BA00
1112
1113/* DSI Controller Registers */
1114struct dsi_lcd_regs {
1115#define DSI_LCD1_CTRL_0 0x100 /* DSI Active Panel 1 Control register 0 */
1116#define DSI_LCD1_CTRL_1 0x104 /* DSI Active Panel 1 Control register 1 */
1117 u32 ctrl0;
1118 u32 ctrl1;
1119 u32 reserved1[2];
1120
1121#define DSI_LCD1_TIMING_0 0x110 /* Timing register 0 */
1122#define DSI_LCD1_TIMING_1 0x114 /* Timing register 1 */
1123#define DSI_LCD1_TIMING_2 0x118 /* Timing register 2 */
1124#define DSI_LCD1_TIMING_3 0x11C /* Timing register 3 */
1125#define DSI_LCD1_WC_0 0x120 /* Word Count register 0 */
1126#define DSI_LCD1_WC_1 0x124 /* Word Count register 1 */
1127#define DSI_LCD1_WC_2 0x128 /* Word Count register 2 */
1128 u32 timing0;
1129 u32 timing1;
1130 u32 timing2;
1131 u32 timing3;
1132 u32 wc0;
1133 u32 wc1;
1134 u32 wc2;
1135 u32 reserved2[1];
1136 u32 slot_cnt0;
1137 u32 slot_cnt1;
1138 u32 reserved3[2];
1139 u32 status_0;
1140 u32 status_1;
1141 u32 status_2;
1142 u32 status_3;
1143 u32 status_4;
1144};
1145
1146struct dsi_regs {
1147#define DSI_CTRL_0 0x000 /* DSI control register 0 */
1148#define DSI_CTRL_1 0x004 /* DSI control register 1 */
1149 u32 ctrl0;
1150 u32 ctrl1;
1151 u32 reserved1[2];
1152 u32 irq_status;
1153 u32 irq_mask;
1154 u32 reserved2[2];
1155
1156#define DSI_CPU_CMD_0 0x020 /* DSI CPU packet command register 0 */
1157#define DSI_CPU_CMD_1 0x024 /* DSU CPU Packet Command Register 1 */
1158#define DSI_CPU_CMD_3 0x02C /* DSU CPU Packet Command Register 3 */
1159#define DSI_CPU_WDAT_0 0x030 /* DSI CUP */
1160 u32 cmd0;
1161 u32 cmd1;
1162 u32 cmd2;
1163 u32 cmd3;
1164 u32 dat0;
1165 u32 status0;
1166 u32 status1;
1167 u32 status2;
1168 u32 status3;
1169 u32 status4;
1170 u32 reserved3[2];
1171
1172 u32 smt_cmd;
1173 u32 smt_ctrl0;
1174 u32 smt_ctrl1;
1175 u32 reserved4[1];
1176
1177 u32 rx0_status;
1178
1179/* Rx Packet Header - data from slave device */
1180#define DSI_RX_PKT_HDR_0 0x064
1181 u32 rx0_header;
1182 u32 rx1_status;
1183 u32 rx1_header;
1184 u32 rx_ctrl;
1185 u32 rx_ctrl1;
1186 u32 rx2_status;
1187 u32 rx2_header;
1188 u32 reserved5[1];
1189
1190 u32 phy_ctrl1;
1191#define DSI_PHY_CTRL_2 0x088 /* DSI DPHI Control Register 2 */
1192#define DSI_PHY_CTRL_3 0x08C /* DPHY Control Register 3 */
1193 u32 phy_ctrl2;
1194 u32 phy_ctrl3;
1195 u32 phy_status0;
1196 u32 phy_status1;
1197 u32 reserved6[5];
1198 u32 phy_status2;
1199
1200#define DSI_PHY_RCOMP_0 0x0B0 /* DPHY Rcomp Control Register */
1201 u32 phy_rcomp0;
1202 u32 reserved7[3];
1203#define DSI_PHY_TIME_0 0x0C0 /* DPHY Timing Control Register 0 */
1204#define DSI_PHY_TIME_1 0x0C4 /* DPHY Timing Control Register 1 */
1205#define DSI_PHY_TIME_2 0x0C8 /* DPHY Timing Control Register 2 */
1206#define DSI_PHY_TIME_3 0x0CC /* DPHY Timing Control Register 3 */
1207#define DSI_PHY_TIME_4 0x0D0 /* DPHY Timing Control Register 4 */
1208#define DSI_PHY_TIME_5 0x0D4 /* DPHY Timing Control Register 5 */
1209 u32 phy_timing0;
1210 u32 phy_timing1;
1211 u32 phy_timing2;
1212 u32 phy_timing3;
1213 u32 phy_code_0;
1214 u32 phy_code_1;
1215 u32 reserved8[2];
1216 u32 mem_ctrl;
1217 u32 tx_timer;
1218 u32 rx_timer;
1219 u32 turn_timer;
1220 u32 reserved9[4];
1221
1222#define DSI_LCD1_CTRL_0 0x100 /* DSI Active Panel 1 Control register 0 */
1223#define DSI_LCD1_CTRL_1 0x104 /* DSI Active Panel 1 Control register 1 */
1224#define DSI_LCD1_TIMING_0 0x110 /* Timing register 0 */
1225#define DSI_LCD1_TIMING_1 0x114 /* Timing register 1 */
1226#define DSI_LCD1_TIMING_2 0x118 /* Timing register 2 */
1227#define DSI_LCD1_TIMING_3 0x11C /* Timing register 3 */
1228#define DSI_LCD1_WC_0 0x120 /* Word Count register 0 */
1229#define DSI_LCD1_WC_1 0x124 /* Word Count register 1 */
1230#define DSI_LCD1_WC_2 0x128 /* Word Count register 2 */
1231 struct dsi_lcd_regs lcd1;
1232 u32 reserved10[11];
1233 struct dsi_lcd_regs lcd2;
1234};
1235
1236#define DSI_LCD2_CTRL_0 0x180 /* DSI Active Panel 2 Control register 0 */
1237#define DSI_LCD2_CTRL_1 0x184 /* DSI Active Panel 2 Control register 1 */
1238#define DSI_LCD2_TIMING_0 0x190 /* Timing register 0 */
1239#define DSI_LCD2_TIMING_1 0x194 /* Timing register 1 */
1240#define DSI_LCD2_TIMING_2 0x198 /* Timing register 2 */
1241#define DSI_LCD2_TIMING_3 0x19C /* Timing register 3 */
1242#define DSI_LCD2_WC_0 0x1A0 /* Word Count register 0 */
1243#define DSI_LCD2_WC_1 0x1A4 /* Word Count register 1 */
1244#define DSI_LCD2_WC_2 0x1A8 /* Word Count register 2 */
1245
1246/* DSI_CTRL_0 0x0000 DSI Control Register 0 */
1247#define DSI_CTRL_0_CFG_SOFT_RST (1<<31)
1248#define DSI_CTRL_0_CFG_SOFT_RST_REG (1<<30)
1249#define DSI_CTRL_0_CFG_LCD1_TX_EN (1<<8)
1250#define DSI_CTRL_0_CFG_LCD1_SLV (1<<4)
1251#define DSI_CTRL_0_CFG_LCD1_EN (1<<0)
1252
1253/* DSI_CTRL_1 0x0004 DSI Control Register 1 */
1254#define DSI_CTRL_1_CFG_EOTP (1<<8)
1255#define DSI_CTRL_1_CFG_RSVD (2<<4)
1256#define DSI_CTRL_1_CFG_LCD2_VCH_NO_MASK (3<<2)
1257#define DSI_CTRL_1_CFG_LCD2_VCH_NO_SHIFT 2
1258#define DSI_CTRL_1_CFG_LCD1_VCH_NO_MASK (3<<0)
1259#define DSI_CTRL_1_CFG_LCD1_VCH_NO_SHIFT 0
1260
1261/* DSI_LCD1_CTRL_1 0x0104 DSI Active Panel 1 Control Register 1 */
1262/* LCD 1 Vsync Reset Enable */
1263#define DSI_LCD1_CTRL_1_CFG_L1_VSYNC_RST_EN (1<<31)
1264/* LCD 1 2K Pixel Buffer Mode Enable */
1265#define DSI_LCD1_CTRL_1_CFG_L1_M2K_EN (1<<30)
1266/* Bit(s) DSI_LCD1_CTRL_1_RSRV_29_23 reserved */
1267/* Long Blanking Packet Enable */
1268#define DSI_LCD1_CTRL_1_CFG_L1_HLP_PKT_EN (1<<22)
1269/* Extra Long Blanking Packet Enable */
1270#define DSI_LCD1_CTRL_1_CFG_L1_HEX_PKT_EN (1<<21)
1271/* Front Porch Packet Enable */
1272#define DSI_LCD1_CTRL_1_CFG_L1_HFP_PKT_EN (1<<20)
1273/* hact Packet Enable */
1274#define DSI_LCD1_CTRL_1_CFG_L1_HACT_PKT_EN (1<<19)
1275/* Back Porch Packet Enable */
1276#define DSI_LCD1_CTRL_1_CFG_L1_HBP_PKT_EN (1<<18)
1277/* hse Packet Enable */
1278#define DSI_LCD1_CTRL_1_CFG_L1_HSE_PKT_EN (1<<17)
1279/* hsa Packet Enable */
1280#define DSI_LCD1_CTRL_1_CFG_L1_HSA_PKT_EN (1<<16)
1281/* All Item Enable after Pixel Data */
1282#define DSI_LCD1_CTRL_1_CFG_L1_ALL_SLOT_EN (1<<15)
1283/* Extra Long Packet Enable after Pixel Data */
1284#define DSI_LCD1_CTRL_1_CFG_L1_HEX_SLOT_EN (1<<14)
1285/* Bit(s) DSI_LCD1_CTRL_1_RSRV_13_11 reserved */
1286/* Turn Around Bus at Last h Line */
1287#define DSI_LCD1_CTRL_1_CFG_L1_LAST_LINE_TURN (1<<10)
1288/* Go to Low Power Every Frame */
1289#define DSI_LCD1_CTRL_1_CFG_L1_LPM_FRAME_EN (1<<9)
1290/* Go to Low Power Every Line */
1291#define DSI_LCD1_CTRL_1_CFG_L1_LPM_LINE_EN (1<<8)
1292/* Bit(s) DSI_LCD1_CTRL_1_RSRV_7_4 reserved */
1293/* DSI Transmission Mode for LCD 1 */
1294#define DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_SHIFT 2
1295#define DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_MASK (3<<2)
1296/* LCD 1 Input Data RGB Mode for LCD 1 */
1297#define DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_SHIFT 0
1298#define DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_MASK (3<<2)
1299
1300/* DSI_PHY_CTRL_2 0x0088 DPHY Control Register 2 */
1301/* Bit(s) DSI_PHY_CTRL_2_RSRV_31_12 reserved */
1302/* DPHY LP Receiver Enable */
1303#define DSI_PHY_CTRL_2_CFG_CSR_LANE_RESC_EN_MASK (0xf<<8)
1304#define DSI_PHY_CTRL_2_CFG_CSR_LANE_RESC_EN_SHIFT 8
1305/* DPHY Data Lane Enable */
1306#define DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_MASK (0xf<<4)
1307#define DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_SHIFT 4
1308/* DPHY Bus Turn Around */
1309#define DSI_PHY_CTRL_2_CFG_CSR_LANE_TURN_MASK (0xf)
1310#define DSI_PHY_CTRL_2_CFG_CSR_LANE_TURN_SHIFT 0
1311
1312/* DSI_CPU_CMD_1 0x0024 DSI CPU Packet Command Register 1 */
1313/* Bit(s) DSI_CPU_CMD_1_RSRV_31_24 reserved */
1314/* LPDT TX Enable */
1315#define DSI_CPU_CMD_1_CFG_TXLP_LPDT_MASK (0xf<<20)
1316#define DSI_CPU_CMD_1_CFG_TXLP_LPDT_SHIFT 20
1317/* ULPS TX Enable */
1318#define DSI_CPU_CMD_1_CFG_TXLP_ULPS_MASK (0xf<<16)
1319#define DSI_CPU_CMD_1_CFG_TXLP_ULPS_SHIFT 16
1320/* Low Power TX Trigger Code */
1321#define DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_MASK (0xffff)
1322#define DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_SHIFT 0
1323
1324/* DSI_PHY_TIME_0 0x00c0 DPHY Timing Control Register 0 */
1325/* Length of HS Exit Period in tx_clk_esc Cycles */
1326#define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_MASK (0xff<<24)
1327#define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_SHIFT 24
1328/* DPHY HS Trail Period Length */
1329#define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_MASK (0xff<<16)
1330#define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_SHIFT 16
1331/* DPHY HS Zero State Length */
1332#define DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_MASK (0xff<<8)
1333#define DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_SHIFT 8
1334/* DPHY HS Prepare State Length */
1335#define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_PREP_MASK (0xff)
1336#define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_PREP_SHIFT 0
1337
1338/* DSI_PHY_TIME_1 0x00c4 DPHY Timing Control Register 1 */
1339/* Time to Drive LP-00 by New Transmitter */
1340#define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_MASK (0xff<<24)
1341#define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_SHIFT 24
1342/* Time to Drive LP-00 after Turn Request */
1343#define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_MASK (0xff<<16)
1344#define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_SHIFT 16
1345/* DPHY HS Wakeup Period Length */
1346#define DSI_PHY_TIME_1_CFG_CSR_TIME_WAKEUP_MASK (0xffff)
1347#define DSI_PHY_TIME_1_CFG_CSR_TIME_WAKEUP_SHIFT 0
1348
1349/* DSI_PHY_TIME_2 0x00c8 DPHY Timing Control Register 2 */
1350/* DPHY CLK Exit Period Length */
1351#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_MASK (0xff<<24)
1352#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_SHIFT 24
1353/* DPHY CLK Trail Period Length */
1354#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_MASK (0xff<<16)
1355#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_SHIFT 16
1356/* DPHY CLK Zero State Length */
1357#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_MASK (0xff<<8)
1358#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_SHIFT 8
1359/* DPHY CLK LP Length */
1360#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_LPX_MASK (0xff)
1361#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_LPX_SHIFT 0
1362
1363/* DSI_PHY_TIME_3 0x00cc DPHY Timing Control Register 3 */
1364/* Bit(s) DSI_PHY_TIME_3_RSRV_31_16 reserved */
1365/* DPHY LP Length */
1366#define DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_MASK (0xff<<8)
1367#define DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_SHIFT 8
1368/* DPHY HS req to rdy Length */
1369#define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_MASK (0xff)
1370#define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_SHIFT 0
1371
1372/*
1373 * DSI timings
1374 * PXA988 has diffrent ESC CLK with MMP2/MMP3
1375 * it will be used in dsi_set_dphy() in pxa688_phy.c
1376 * as low power mode clock.
1377 */
1378#ifdef CONFIG_CPU_PXA988
1379#define DSI_ESC_CLK 52 /* Unit: Mhz */
1380#define DSI_ESC_CLK_T 19 /* Unit: ns */
1381#else
1382#define DSI_ESC_CLK 66 /* Unit: Mhz */
1383#define DSI_ESC_CLK_T 15 /* Unit: ns */
1384#endif
1385
1386/* LVDS */
1387/* LVDS_PHY_CTRL */
1388#define LVDS_PHY_CTL 0x2A4
1389#define LVDS_PLL_LOCK (1 << 31)
1390#define LVDS_PHY_EXT_MASK (7 << 28)
1391#define LVDS_PHY_EXT_SHIFT (28)
1392#define LVDS_CLK_PHASE_MASK (0x7f << 16)
1393#define LVDS_CLK_PHASE_SHIFT (16)
1394#define LVDS_SSC_RESET_EXT (1 << 13)
1395#define LVDS_SSC_MODE_DOWN_SPREAD (1 << 12)
1396#define LVDS_SSC_EN (1 << 11)
1397#define LVDS_PU_PLL (1 << 10)
1398#define LVDS_PU_TX (1 << 9)
1399#define LVDS_PU_IVREF (1 << 8)
1400#define LVDS_CLK_SEL (1 << 7)
1401#define LVDS_CLK_SEL_LVDS_PCLK (1 << 7)
1402#define LVDS_PD_CH_MASK (0x3f << 1)
1403#define LVDS_PD_CH(ch) ((ch) << 1)
1404#define LVDS_RST (1 << 0)
1405
1406#define LVDS_PHY_CTL_EXT 0x2A8
1407
1408/* LVDS_PHY_CTRL_EXT1 */
1409#define LVDS_SSC_RNGE_MASK (0x7ff << 16)
1410#define LVDS_SSC_RNGE_SHIFT (16)
1411#define LVDS_RESERVE_IN_MASK (0xf << 12)
1412#define LVDS_RESERVE_IN_SHIFT (12)
1413#define LVDS_TEST_MON_MASK (0x7 << 8)
1414#define LVDS_TEST_MON_SHIFT (8)
1415#define LVDS_POL_SWAP_MASK (0x3f << 0)
1416#define LVDS_POL_SWAP_SHIFT (0)
1417
1418/* LVDS_PHY_CTRL_EXT2 */
1419#define LVDS_TX_DIF_AMP_MASK (0xf << 24)
1420#define LVDS_TX_DIF_AMP_SHIFT (24)
1421#define LVDS_TX_DIF_CM_MASK (0x3 << 22)
1422#define LVDS_TX_DIF_CM_SHIFT (22)
1423#define LVDS_SELLV_TXCLK_MASK (0x1f << 16)
1424#define LVDS_SELLV_TXCLK_SHIFT (16)
1425#define LVDS_TX_CMFB_EN (0x1 << 15)
1426#define LVDS_TX_TERM_EN (0x1 << 14)
1427#define LVDS_SELLV_TXDATA_MASK (0x1f << 8)
1428#define LVDS_SELLV_TXDATA_SHIFT (8)
1429#define LVDS_SELLV_OP7_MASK (0x3 << 6)
1430#define LVDS_SELLV_OP7_SHIFT (6)
1431#define LVDS_SELLV_OP6_MASK (0x3 << 4)
1432#define LVDS_SELLV_OP6_SHIFT (4)
1433#define LVDS_SELLV_OP9_MASK (0x3 << 2)
1434#define LVDS_SELLV_OP9_SHIFT (2)
1435#define LVDS_STRESSTST_EN (0x1 << 0)
1436
1437/* LVDS_PHY_CTRL_EXT3 */
1438#define LVDS_KVCO_MASK (0xf << 28)
1439#define LVDS_KVCO_SHIFT (28)
1440#define LVDS_CTUNE_MASK (0x3 << 26)
1441#define LVDS_CTUNE_SHIFT (26)
1442#define LVDS_VREG_IVREF_MASK (0x3 << 24)
1443#define LVDS_VREG_IVREF_SHIFT (24)
1444#define LVDS_VDDL_MASK (0xf << 20)
1445#define LVDS_VDDL_SHIFT (20)
1446#define LVDS_VDDM_MASK (0x3 << 18)
1447#define LVDS_VDDM_SHIFT (18)
1448#define LVDS_FBDIV_MASK (0xf << 8)
1449#define LVDS_FBDIV_SHIFT (8)
1450#define LVDS_REFDIV_MASK (0x7f << 0)
1451#define LVDS_REFDIV_SHIFT (0)
1452
1453/* LVDS_PHY_CTRL_EXT4 */
1454#define LVDS_SSC_FREQ_DIV_MASK (0xffff << 16)
1455#define LVDS_SSC_FREQ_DIV_SHIFT (16)
1456#define LVDS_INTPI_MASK (0xf << 12)
1457#define LVDS_INTPI_SHIFT (12)
1458#define LVDS_VCODIV_SEL_SE_MASK (0xf << 8)
1459#define LVDS_VCODIV_SEL_SE_SHIFT (8)
1460#define LVDS_RESET_INTP_EXT (0x1 << 7)
1461#define LVDS_VCO_VRNG_MASK (0x7 << 4)
1462#define LVDS_VCO_VRNG_SHIFT (4)
1463#define LVDS_PI_EN (0x1 << 3)
1464#define LVDS_ICP_MASK (0x7 << 0)
1465#define LVDS_ICP_SHIFT (0)
1466
1467/* LVDS_PHY_CTRL_EXT5 */
1468#define LVDS_FREQ_OFFSET_MASK (0x1ffff << 15)
1469#define LVDS_FREQ_OFFSET_SHIFT (15)
1470#define LVDS_FREQ_OFFSET_VALID (0x1 << 2)
1471#define LVDS_FREQ_OFFSET_MODE_CK_DIV4_OUT (0x1 << 1)
1472#define LVDS_FREQ_OFFSET_MODE_EN (0x1 << 0)
1473
1474/* VDMA */
1475struct vdma_ch_regs {
1476#define VDMA_DC_SADDR_1 0x320
1477#define VDMA_DC_SADDR_2 0x3A0
1478#define VDMA_DC_SZ_1 0x324
1479#define VDMA_DC_SZ_2 0x3A4
1480#define VDMA_CTRL_1 0x328
1481#define VDMA_CTRL_2 0x3A8
1482#define VDMA_SRC_SZ_1 0x32C
1483#define VDMA_SRC_SZ_2 0x3AC
1484#define VDMA_SA_1 0x330
1485#define VDMA_SA_2 0x3B0
1486#define VDMA_DA_1 0x334
1487#define VDMA_DA_2 0x3B4
1488#define VDMA_SZ_1 0x338
1489#define VDMA_SZ_2 0x3B8
1490 u32 dc_saddr;
1491 u32 dc_size;
1492 u32 ctrl;
1493 u32 src_size;
1494 u32 src_addr;
1495 u32 dst_addr;
1496 u32 dst_size;
1497#define VDMA_PITCH_1 0x33C
1498#define VDMA_PITCH_2 0x3BC
1499#define VDMA_ROT_CTRL_1 0x340
1500#define VDMA_ROT_CTRL_2 0x3C0
1501#define VDMA_RAM_CTRL0_1 0x344
1502#define VDMA_RAM_CTRL0_2 0x3C4
1503#define VDMA_RAM_CTRL1_1 0x348
1504#define VDMA_RAM_CTRL1_2 0x3C8
1505 u32 pitch;
1506 u32 rot_ctrl;
1507 u32 ram_ctrl0;
1508 u32 ram_ctrl1;
1509
1510};
1511struct vdma_regs {
1512#define VDMA_ARBR_CTRL 0x300
1513#define VDMA_IRQR 0x304
1514#define VDMA_IRQM 0x308
1515#define VDMA_IRQS 0x30C
1516#define VDMA_MDMA_ARBR_CTRL 0x310
1517 u32 arbr_ctr;
1518 u32 irq_raw;
1519 u32 irq_mask;
1520 u32 irq_status;
1521 u32 mdma_arbr_ctrl;
1522 u32 reserved[3];
1523
1524 struct vdma_ch_regs ch1;
1525 u32 reserved2[21];
1526 struct vdma_ch_regs ch2;
1527};
1528
1529/* CMU */
1530#define CMU_PIP_DE_H_CFG 0x0008
1531#define CMU_PRI1_H_CFG 0x000C
1532#define CMU_PRI2_H_CFG 0x0010
1533#define CMU_ACE_MAIN_DE1_H_CFG 0x0014
1534#define CMU_ACE_MAIN_DE2_H_CFG 0x0018
1535#define CMU_ACE_PIP_DE1_H_CFG 0x001C
1536#define CMU_ACE_PIP_DE2_H_CFG 0x0020
1537#define CMU_PIP_DE_V_CFG 0x0024
1538#define CMU_PRI_V_CFG 0x0028
1539#define CMU_ACE_MAIN_DE_V_CFG 0x002C
1540#define CMU_ACE_PIP_DE_V_CFG 0x0030
1541#define CMU_BAR_0_CFG 0x0034
1542#define CMU_BAR_1_CFG 0x0038
1543#define CMU_BAR_2_CFG 0x003C
1544#define CMU_BAR_3_CFG 0x0040
1545#define CMU_BAR_4_CFG 0x0044
1546#define CMU_BAR_5_CFG 0x0048
1547#define CMU_BAR_6_CFG 0x004C
1548#define CMU_BAR_7_CFG 0x0050
1549#define CMU_BAR_8_CFG 0x0054
1550#define CMU_BAR_9_CFG 0x0058
1551#define CMU_BAR_10_CFG 0x005C
1552#define CMU_BAR_11_CFG 0x0060
1553#define CMU_BAR_12_CFG 0x0064
1554#define CMU_BAR_13_CFG 0x0068
1555#define CMU_BAR_14_CFG 0x006C
1556#define CMU_BAR_15_CFG 0x0070
1557#define CMU_BAR_CTRL 0x0074
1558#define PATTERN_TOTAL 0x0078
1559#define PATTERN_ACTIVE 0x007C
1560#define PATTERN_FRONT_PORCH 0x0080
1561#define PATTERN_BACK_PORCH 0x0084
1562#define CMU_CLK_CTRL 0x0088
1563
1564#define CMU_ICSC_M_C0_L 0x0900
1565#define CMU_ICSC_M_C0_H 0x0901
1566#define CMU_ICSC_M_C1_L 0x0902
1567#define CMU_ICSC_M_C1_H 0x0903
1568#define CMU_ICSC_M_C2_L 0x0904
1569#define CMU_ICSC_M_C2_H 0x0905
1570#define CMU_ICSC_M_C3_L 0x0906
1571#define CMU_ICSC_M_C3_H 0x0907
1572#define CMU_ICSC_M_C4_L 0x0908
1573#define CMU_ICSC_M_C4_H 0x0909
1574#define CMU_ICSC_M_C5_L 0x090A
1575#define CMU_ICSC_M_C5_H 0x090B
1576#define CMU_ICSC_M_C6_L 0x090C
1577#define CMU_ICSC_M_C6_H 0x090D
1578#define CMU_ICSC_M_C7_L 0x090E
1579#define CMU_ICSC_M_C7_H 0x090F
1580#define CMU_ICSC_M_C8_L 0x0910
1581#define CMU_ICSC_M_C8_H 0x0911
1582#define CMU_ICSC_M_O1_0 0x0914
1583#define CMU_ICSC_M_O1_1 0x0915
1584#define CMU_ICSC_M_O1_2 0x0916
1585#define CMU_ICSC_M_O2_0 0x0918
1586#define CMU_ICSC_M_O2_1 0x0919
1587#define CMU_ICSC_M_O2_2 0x091A
1588#define CMU_ICSC_M_O3_0 0x091C
1589#define CMU_ICSC_M_O3_1 0x091D
1590#define CMU_ICSC_M_O3_2 0x091E
1591#define CMU_ICSC_P_C0_L 0x0920
1592#define CMU_ICSC_P_C0_H 0x0921
1593#define CMU_ICSC_P_C1_L 0x0922
1594#define CMU_ICSC_P_C1_H 0x0923
1595#define CMU_ICSC_P_C2_L 0x0924
1596#define CMU_ICSC_P_C2_H 0x0925
1597#define CMU_ICSC_P_C3_L 0x0926
1598#define CMU_ICSC_P_C3_H 0x0927
1599#define CMU_ICSC_P_C4_L 0x0928
1600#define CMU_ICSC_P_C4_H 0x0929
1601#define CMU_ICSC_P_C5_L 0x092A
1602#define CMU_ICSC_P_C5_H 0x092B
1603#define CMU_ICSC_P_C6_L 0x092C
1604#define CMU_ICSC_P_C6_H 0x092D
1605#define CMU_ICSC_P_C7_L 0x092E
1606#define CMU_ICSC_P_C7_H 0x092F
1607#define CMU_ICSC_P_C8_L 0x0930
1608#define CMU_ICSC_P_C8_H 0x0931
1609#define CMU_ICSC_P_O1_0 0x0934
1610#define CMU_ICSC_P_O1_1 0x0935
1611#define CMU_ICSC_P_O1_2 0x0936
1612#define CMU_ICSC_P_O2_0 0x0938
1613#define CMU_ICSC_P_O2_1 0x0939
1614#define CMU_ICSC_P_O2_2 0x093A
1615#define CMU_ICSC_P_O3_0 0x093C
1616#define CMU_ICSC_P_O3_1 0x093D
1617#define CMU_ICSC_P_O3_2 0x093E
1618#define CMU_BR_M_EN 0x0940
1619#define CMU_BR_M_TH1_L 0x0942
1620#define CMU_BR_M_TH1_H 0x0943
1621#define CMU_BR_M_TH2_L 0x0944
1622#define CMU_BR_M_TH2_H 0x0945
1623#define CMU_ACE_M_EN 0x0950
1624#define CMU_ACE_M_WFG1 0x0951
1625#define CMU_ACE_M_WFG2 0x0952
1626#define CMU_ACE_M_WFG3 0x0953
1627#define CMU_ACE_M_TH0 0x0954
1628#define CMU_ACE_M_TH1 0x0955
1629#define CMU_ACE_M_TH2 0x0956
1630#define CMU_ACE_M_TH3 0x0957
1631#define CMU_ACE_M_TH4 0x0958
1632#define CMU_ACE_M_TH5 0x0959
1633#define CMU_ACE_M_OP0_L 0x095A
1634#define CMU_ACE_M_OP0_H 0x095B
1635#define CMU_ACE_M_OP5_L 0x095C
1636#define CMU_ACE_M_OP5_H 0x095D
1637#define CMU_ACE_M_GB2 0x095E
1638#define CMU_ACE_M_GB3 0x095F
1639#define CMU_ACE_M_MS1 0x0960
1640#define CMU_ACE_M_MS2 0x0961
1641#define CMU_ACE_M_MS3 0x0962
1642#define CMU_BR_P_EN 0x0970
1643#define CMU_BR_P_TH1_L 0x0972
1644#define CMU_BR_P_TH1_H 0x0973
1645#define CMU_BR_P_TH2_L 0x0974
1646#define CMU_BR_P_TH2_H 0x0975
1647#define CMU_ACE_P_EN 0x0980
1648#define CMU_ACE_P_WFG1 0x0981
1649#define CMU_ACE_P_WFG2 0x0982
1650#define CMU_ACE_P_WFG3 0x0983
1651#define CMU_ACE_P_TH0 0x0984
1652#define CMU_ACE_P_TH1 0x0985
1653#define CMU_ACE_P_TH2 0x0986
1654#define CMU_ACE_P_TH3 0x0987
1655#define CMU_ACE_P_TH4 0x0988
1656#define CMU_ACE_P_TH5 0x0989
1657#define CMU_ACE_P_OP0_L 0x098A
1658#define CMU_ACE_P_OP0_H 0x098B
1659#define CMU_ACE_P_OP5_L 0x098C
1660#define CMU_ACE_P_OP5_H 0x098D
1661#define CMU_ACE_P_GB2 0x098E
1662#define CMU_ACE_P_GB3 0x098F
1663#define CMU_ACE_P_MS1 0x0990
1664#define CMU_ACE_P_MS2 0x0991
1665#define CMU_ACE_P_MS3 0x0992
1666#define CMU_FTDC_M_EN 0x09A0
1667#define CMU_FTDC_P_EN 0x09A1
1668#define CMU_FTDC_INLOW_L 0x09A2
1669#define CMU_FTDC_INLOW_H 0x09A3
1670#define CMU_FTDC_INHIGH_L 0x09A4
1671#define CMU_FTDC_INHIGH_H 0x09A5
1672#define CMU_FTDC_OUTLOW_L 0x09A6
1673#define CMU_FTDC_OUTLOW_H 0x09A7
1674#define CMU_FTDC_OUTHIGH_L 0x09A8
1675#define CMU_FTDC_OUTHIGH_H 0x09A9
1676#define CMU_FTDC_YLOW 0x09AA
1677#define CMU_FTDC_YHIGH 0x09AB
1678#define CMU_FTDC_CH1 0x09AC
1679#define CMU_FTDC_CH2_L 0x09AE
1680#define CMU_FTDC_CH2_H 0x09AF
1681#define CMU_FTDC_CH3_L 0x09B0
1682#define CMU_FTDC_CH3_H 0x09B1
1683#define CMU_FTDC_1_C00_6 0x09B2
1684#define CMU_FTDC_1_C01_6 0x09B8
1685#define CMU_FTDC_1_C11_6 0x09BE
1686#define CMU_FTDC_1_C10_6 0x09C4
1687#define CMU_FTDC_1_OFF00_6 0x09CA
1688#define CMU_FTDC_1_OFF10_6 0x09D0
1689#define CMU_HS_M_EN 0x0A00
1690#define CMU_HS_M_AX1_L 0x0A02
1691#define CMU_HS_M_AX1_H 0x0A03
1692#define CMU_HS_M_AX2_L 0x0A04
1693#define CMU_HS_M_AX2_H 0x0A05
1694#define CMU_HS_M_AX3_L 0x0A06
1695#define CMU_HS_M_AX3_H 0x0A07
1696#define CMU_HS_M_AX4_L 0x0A08
1697#define CMU_HS_M_AX4_H 0x0A09
1698#define CMU_HS_M_AX5_L 0x0A0A
1699#define CMU_HS_M_AX5_H 0x0A0B
1700#define CMU_HS_M_AX6_L 0x0A0C
1701#define CMU_HS_M_AX6_H 0x0A0D
1702#define CMU_HS_M_AX7_L 0x0A0E
1703#define CMU_HS_M_AX7_H 0x0A0F
1704#define CMU_HS_M_AX8_L 0x0A10
1705#define CMU_HS_M_AX8_H 0x0A11
1706#define CMU_HS_M_AX9_L 0x0A12
1707#define CMU_HS_M_AX9_H 0x0A13
1708#define CMU_HS_M_AX10_L 0x0A14
1709#define CMU_HS_M_AX10_H 0x0A15
1710#define CMU_HS_M_AX11_L 0x0A16
1711#define CMU_HS_M_AX11_H 0x0A17
1712#define CMU_HS_M_AX12_L 0x0A18
1713#define CMU_HS_M_AX12_H 0x0A19
1714#define CMU_HS_M_AX13_L 0x0A1A
1715#define CMU_HS_M_AX13_H 0x0A1B
1716#define CMU_HS_M_AX14_L 0x0A1C
1717#define CMU_HS_M_AX14_H 0x0A1D
1718#define CMU_HS_M_H1_H14 0x0A1E
1719#define CMU_HS_M_S1_S14 0x0A2C
1720#define CMU_HS_M_GL 0x0A3A
1721#define CMU_HS_M_MAXSAT_RGB_Y_L 0x0A3C
1722#define CMU_HS_M_MAXSAT_RGB_Y_H 0x0A3D
1723#define CMU_HS_M_MAXSAT_RCR_L 0x0A3E
1724#define CMU_HS_M_MAXSAT_RCR_H 0x0A3F
1725#define CMU_HS_M_MAXSAT_RCB_L 0x0A40
1726#define CMU_HS_M_MAXSAT_RCB_H 0x0A41
1727#define CMU_HS_M_MAXSAT_GCR_L 0x0A42
1728#define CMU_HS_M_MAXSAT_GCR_H 0x0A43
1729#define CMU_HS_M_MAXSAT_GCB_L 0x0A44
1730#define CMU_HS_M_MAXSAT_GCB_H 0x0A45
1731#define CMU_HS_M_MAXSAT_BCR_L 0x0A46
1732#define CMU_HS_M_MAXSAT_BCR_H 0x0A47
1733#define CMU_HS_M_MAXSAT_BCB_L 0x0A48
1734#define CMU_HS_M_MAXSAT_BCB_H 0x0A49
1735#define CMU_HS_M_ROFF_L 0x0A4A
1736#define CMU_HS_M_ROFF_H 0x0A4B
1737#define CMU_HS_M_GOFF_L 0x0A4C
1738#define CMU_HS_M_GOFF_H 0x0A4D
1739#define CMU_HS_M_BOFF_L 0x0A4E
1740#define CMU_HS_M_BOFF_H 0x0A4F
1741#define CMU_HS_P_EN 0x0A50
1742#define CMU_HS_P_AX1_L 0x0A52
1743#define CMU_HS_P_AX1_H 0x0A53
1744#define CMU_HS_P_AX2_L 0x0A54
1745#define CMU_HS_P_AX2_H 0x0A55
1746#define CMU_HS_P_AX3_L 0x0A56
1747#define CMU_HS_P_AX3_H 0x0A57
1748#define CMU_HS_P_AX4_L 0x0A58
1749#define CMU_HS_P_AX4_H 0x0A59
1750#define CMU_HS_P_AX5_L 0x0A5A
1751#define CMU_HS_P_AX5_H 0x0A5B
1752#define CMU_HS_P_AX6_L 0x0A5C
1753#define CMU_HS_P_AX6_H 0x0A5D
1754#define CMU_HS_P_AX7_L 0x0A5E
1755#define CMU_HS_P_AX7_H 0x0A5F
1756#define CMU_HS_P_AX8_L 0x0A60
1757#define CMU_HS_P_AX8_H 0x0A61
1758#define CMU_HS_P_AX9_L 0x0A62
1759#define CMU_HS_P_AX9_H 0x0A63
1760#define CMU_HS_P_AX10_L 0x0A64
1761#define CMU_HS_P_AX10_H 0x0A65
1762#define CMU_HS_P_AX11_L 0x0A66
1763#define CMU_HS_P_AX11_H 0x0A67
1764#define CMU_HS_P_AX12_L 0x0A68
1765#define CMU_HS_P_AX12_H 0x0A69
1766#define CMU_HS_P_AX13_L 0x0A6A
1767#define CMU_HS_P_AX13_H 0x0A6B
1768#define CMU_HS_P_AX14_L 0x0A6C
1769#define CMU_HS_P_AX14_H 0x0A6D
1770#define CMU_HS_P_H1_H14 0x0A6E
1771#define CMU_HS_P_S1_S14 0x0A7C
1772#define CMU_HS_P_GL 0x0A8A
1773#define CMU_HS_P_MAXSAT_RGB_Y_L 0x0A8C
1774#define CMU_HS_P_MAXSAT_RGB_Y_H 0x0A8D
1775#define CMU_HS_P_MAXSAT_RCR_L 0x0A8E
1776#define CMU_HS_P_MAXSAT_RCR_H 0x0A8F
1777#define CMU_HS_P_MAXSAT_RCB_L 0x0A90
1778#define CMU_HS_P_MAXSAT_RCB_H 0x0A91
1779#define CMU_HS_P_MAXSAT_GCR_L 0x0A92
1780#define CMU_HS_P_MAXSAT_GCR_H 0x0A93
1781#define CMU_HS_P_MAXSAT_GCB_L 0x0A94
1782#define CMU_HS_P_MAXSAT_GCB_H 0x0A95
1783#define CMU_HS_P_MAXSAT_BCR_L 0x0A96
1784#define CMU_HS_P_MAXSAT_BCR_H 0x0A97
1785#define CMU_HS_P_MAXSAT_BCB_L 0x0A98
1786#define CMU_HS_P_MAXSAT_BCB_H 0x0A99
1787#define CMU_HS_P_ROFF_L 0x0A9A
1788#define CMU_HS_P_ROFF_H 0x0A9B
1789#define CMU_HS_P_GOFF_L 0x0A9C
1790#define CMU_HS_P_GOFF_H 0x0A9D
1791#define CMU_HS_P_BOFF_L 0x0A9E
1792#define CMU_HS_P_BOFF_H 0x0A9F
1793#define CMU_GLCSC_M_C0_L 0x0AA0
1794#define CMU_GLCSC_M_C0_H 0x0AA1
1795#define CMU_GLCSC_M_C1_L 0x0AA2
1796#define CMU_GLCSC_M_C1_H 0x0AA3
1797#define CMU_GLCSC_M_C2_L 0x0AA4
1798#define CMU_GLCSC_M_C2_H 0x0AA5
1799#define CMU_GLCSC_M_C3_L 0x0AA6
1800#define CMU_GLCSC_M_C3_H 0x0AA7
1801#define CMU_GLCSC_M_C4_L 0x0AA8
1802#define CMU_GLCSC_M_C4_H 0x0AA9
1803#define CMU_GLCSC_M_C5_L 0x0AAA
1804#define CMU_GLCSC_M_C5_H 0x0AAB
1805#define CMU_GLCSC_M_C6_L 0x0AAC
1806#define CMU_GLCSC_M_C6_H 0x0AAD
1807#define CMU_GLCSC_M_C7_L 0x0AAE
1808#define CMU_GLCSC_M_C7_H 0x0AAF
1809#define CMU_GLCSC_M_C8_L 0x0AB0
1810#define CMU_GLCSC_M_C8_H 0x0AB1
1811#define CMU_GLCSC_M_O1_1 0x0AB4
1812#define CMU_GLCSC_M_O1_2 0x0AB5
1813#define CMU_GLCSC_M_O1_3 0x0AB6
1814#define CMU_GLCSC_M_O2_1 0x0AB8
1815#define CMU_GLCSC_M_O2_2 0x0AB9
1816#define CMU_GLCSC_M_O2_3 0x0ABA
1817#define CMU_GLCSC_M_O3_1 0x0ABC
1818#define CMU_GLCSC_M_O3_2 0x0ABD
1819#define CMU_GLCSC_M_O3_3 0x0ABE
1820#define CMU_GLCSC_P_C0_L 0x0AC0
1821#define CMU_GLCSC_P_C0_H 0x0AC1
1822#define CMU_GLCSC_P_C1_L 0x0AC2
1823#define CMU_GLCSC_P_C1_H 0x0AC3
1824#define CMU_GLCSC_P_C2_L 0x0AC4
1825#define CMU_GLCSC_P_C2_H 0x0AC5
1826#define CMU_GLCSC_P_C3_L 0x0AC6
1827#define CMU_GLCSC_P_C3_H 0x0AC7
1828#define CMU_GLCSC_P_C4_L 0x0AC8
1829#define CMU_GLCSC_P_C4_H 0x0AC9
1830#define CMU_GLCSC_P_C5_L 0x0ACA
1831#define CMU_GLCSC_P_C5_H 0x0ACB
1832#define CMU_GLCSC_P_C6_L 0x0ACC
1833#define CMU_GLCSC_P_C6_H 0x0ACD
1834#define CMU_GLCSC_P_C7_L 0x0ACE
1835#define CMU_GLCSC_P_C7_H 0x0ACF
1836#define CMU_GLCSC_P_C8_L 0x0AD0
1837#define CMU_GLCSC_P_C8_H 0x0AD1
1838#define CMU_GLCSC_P_O1_1 0x0AD4
1839#define CMU_GLCSC_P_O1_2 0x0AD5
1840#define CMU_GLCSC_P_O1_3 0x0AD6
1841#define CMU_GLCSC_P_O2_1 0x0AD8
1842#define CMU_GLCSC_P_O2_2 0x0AD9
1843#define CMU_GLCSC_P_O2_3 0x0ADA
1844#define CMU_GLCSC_P_O3_1 0x0ADC
1845#define CMU_GLCSC_P_O3_2 0x0ADD
1846#define CMU_GLCSC_P_O3_3 0x0ADE
1847#define CMU_PIXVAL_M_EN 0x0AE0
1848#define CMU_PIXVAL_P_EN 0x0AE1
1849
1850#define CMU_CLK_CTRL_TCLK 0x0
1851#define CMU_CLK_CTRL_SCLK 0x2
1852#define CMU_CLK_CTRL_MSK 0x2
1853#define CMU_CLK_CTRL_ENABLE 0x1
1854
1855#define LCD_TOP_CTRL_TV 0x2
1856#define LCD_TOP_CTRL_PN 0x0
1857#define LCD_TOP_CTRL_SEL_MSK 0x2
1858#define LCD_IO_CMU_IN_SEL_MSK (0x3 << 20)
1859#define LCD_IO_CMU_IN_SEL_TV 0
1860#define LCD_IO_CMU_IN_SEL_PN 1
1861#define LCD_IO_CMU_IN_SEL_PN2 2
1862#define LCD_IO_TV_OUT_SEL_MSK (0x3 << 26)
1863#define LCD_IO_PN_OUT_SEL_MSK (0x3 << 24)
1864#define LCD_IO_PN2_OUT_SEL_MSK (0x3 << 28)
1865#define LCD_IO_TV_OUT_SEL_NON 3
1866#define LCD_IO_PN_OUT_SEL_NON 3
1867#define LCD_IO_PN2_OUT_SEL_NON 3
1868#define LCD_TOP_CTRL_CMU_ENABLE 0x1
1869#define LCD_IO_OVERL_MSK 0xC00000
1870#define LCD_IO_OVERL_TV 0x0
1871#define LCD_IO_OVERL_LCD1 0x400000
1872#define LCD_IO_OVERL_LCD2 0xC00000
1873#define HINVERT_MSK 0x4
1874#define VINVERT_MSK 0x8
1875#define HINVERT_LEN 0x2
1876#define VINVERT_LEN 0x3
1877
1878#define CMU_CTRL 0x88
1879#define CMU_CTRL_A0_MSK 0x6
1880#define CMU_CTRL_A0_TV 0x0
1881#define CMU_CTRL_A0_LCD1 0x1
1882#define CMU_CTRL_A0_LCD2 0x2
1883#define CMU_CTRL_A0_HDMI 0x3
1884
1885#define ICR_DRV_ROUTE_OFF 0x0
1886#define ICR_DRV_ROUTE_TV 0x1
1887#define ICR_DRV_ROUTE_LCD1 0x2
1888#define ICR_DRV_ROUTE_LCD2 0x3
1889
1890enum {
1891 PATH_PN = 0,
1892 PATH_TV,
1893 PATH_P2,
1894};
1895
1896/*
1897 * mmp path describes part of mmp path related info:
1898 * which is hiden in display driver and not exported to buffer driver
1899 */
1900struct mmphw_ctrl;
1901struct mmphw_path_plat {
1902 int id;
1903 struct mmphw_ctrl *ctrl;
1904 struct mmp_path *path;
1905 u32 path_config;
1906 u32 link_config;
1907};
1908
1909/* mmp ctrl describes mmp controller related info */
1910struct mmphw_ctrl {
1911 /* platform related, get from config */
1912 const char *name;
1913 int irq;
1914 void *reg_base;
1915 struct clk *clk;
1916
1917 /* sys info */
1918 struct device *dev;
1919
1920 /* state */
1921 int open_count;
1922 int status;
1923 struct mutex access_ok;
1924
1925 /*pathes*/
1926 int path_num;
1927 struct mmphw_path_plat path_plats[0];
1928};
1929
1930static inline int overlay_is_vid(struct mmp_overlay *overlay)
1931{
1932 return overlay->dmafetch_id & 1;
1933}
1934
1935static inline struct mmphw_path_plat *path_to_path_plat(struct mmp_path *path)
1936{
1937 return (struct mmphw_path_plat *)path->plat_data;
1938}
1939
1940static inline struct mmphw_ctrl *path_to_ctrl(struct mmp_path *path)
1941{
1942 return path_to_path_plat(path)->ctrl;
1943}
1944
1945static inline struct mmphw_ctrl *overlay_to_ctrl(struct mmp_overlay *overlay)
1946{
1947 return path_to_ctrl(overlay->path);
1948}
1949
1950static inline void *ctrl_regs(struct mmp_path *path)
1951{
1952 return path_to_ctrl(path)->reg_base;
1953}
1954
1955/* path regs, for regs symmetrical for both pathes */
1956static inline struct lcd_regs *path_regs(struct mmp_path *path)
1957{
1958 if (path->id == PATH_PN)
1959 return (struct lcd_regs *)(ctrl_regs(path) + 0xc0);
1960 else if (path->id == PATH_TV)
1961 return (struct lcd_regs *)ctrl_regs(path);
1962 else if (path->id == PATH_P2)
1963 return (struct lcd_regs *)(ctrl_regs(path) + 0x200);
1964 else {
1965 dev_err(path->dev, "path id %d invalid\n", path->id);
1966 BUG_ON(1);
1967 return NULL;
1968 }
1969}
1970#endif /* _MMP_CTRL_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 19:14:26 -0500