aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/video
diff options
context:
space:
mode:
authorAnatolij Gustschin <agust@denx.de>2011-05-13 08:12:15 -0400
committerAnatolij Gustschin <agust@denx.de>2011-05-24 10:28:51 -0400
commit3cadf9455c31de340ed77394dfad330caeb66b58 (patch)
tree4523ca559a55147e6a90b275c06eeb14d8ced1a4 /drivers/video
parentdcdf2f7e7e154957f913e5468e3715e1a0401138 (diff)
video: mb862xxfb: use pre-initialized configuration for PCI GDCs
If the bootloader has already initialized the display controller, do not re-initialize it in the driver. Take over the bootloader's configuration instead. This is already supported for non PCI GDCs Lime and Mint. Add this functionality for PCI GDCs Coral-P and Coral-PA. It is useful to avoid flicker and also avoids unneeded init delays while booting. Signed-off-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/mb862xx/mb862xxfb.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/video/mb862xx/mb862xxfb.c b/drivers/video/mb862xx/mb862xxfb.c
index 825795894daa..a1b81e73394c 100644
--- a/drivers/video/mb862xx/mb862xxfb.c
+++ b/drivers/video/mb862xx/mb862xxfb.c
@@ -746,13 +746,21 @@ static int coralp_init(struct mb862xxfb_par *par)
746 cn = (ver & GC_CID_CNAME_MSK) >> 8; 746 cn = (ver & GC_CID_CNAME_MSK) >> 8;
747 ver = ver & GC_CID_VERSION_MSK; 747 ver = ver & GC_CID_VERSION_MSK;
748 if (cn == 3) { 748 if (cn == 3) {
749 unsigned long reg;
750
749 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\ 751 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
750 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?", 752 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
751 par->pdev->revision); 753 par->pdev->revision);
752 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133); 754 reg = inreg(disp, GC_DCM1);
753 udelay(200); 755 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
754 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL); 756 par->pre_init = 1;
755 udelay(10); 757
758 if (!par->pre_init) {
759 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
760 udelay(200);
761 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
762 udelay(10);
763 }
756 /* Clear interrupt status */ 764 /* Clear interrupt status */
757 outreg(host, GC_IST, 0); 765 outreg(host, GC_IST, 0);
758 } else { 766 } else {