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authorMythri P K <mythripk@ti.com>2011-09-08 09:36:23 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-09-30 09:16:32 -0400
commit7d983f39ecc463a4fb94bc1fd7204be46e35d5e0 (patch)
treec11bcd5d4cb61d44f64d42449d394e6cf6ce3a5e /drivers/video
parent7c1f1ecac9240663db357ae0f30761a7ee7c8463 (diff)
OMAP4: DSS2: HDMI: Split the current HDMI driver to move
Split the current HDMI driver to move the HDMI IP dependent ( PLL/PHY/Core configuration code) to a new IP file (ti_hdmi_4xxx_ip.c. This is to separate IP dependent OMAP agnostic code from OMAP specific DSS dependent code. Signed-off-by: Mythri P K <mythripk@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/omap2/dss/Makefile2
-rw-r--r--drivers/video/omap2/dss/hdmi.c734
-rw-r--r--drivers/video/omap2/dss/ti_hdmi.h7
-rw-r--r--drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c767
-rw-r--r--drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h (renamed from drivers/video/omap2/dss/hdmi.h)9
5 files changed, 780 insertions, 739 deletions
diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile
index 10d9d3bb3e24..962782927243 100644
--- a/drivers/video/omap2/dss/Makefile
+++ b/drivers/video/omap2/dss/Makefile
@@ -6,4 +6,4 @@ omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
6omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o 6omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
7omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o 7omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
8omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o \ 8omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o \
9 hdmi_omap4_panel.o 9 hdmi_omap4_panel.o ti_hdmi_4xxx_ip.o
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index 96a0ac941126..b6d63c63c9fd 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -41,7 +41,6 @@
41 41
42#include "ti_hdmi.h" 42#include "ti_hdmi.h"
43#include "dss.h" 43#include "dss.h"
44#include "hdmi.h"
45#include "dss_features.h" 44#include "dss_features.h"
46 45
47#define HDMI_WP 0x0 46#define HDMI_WP 0x0
@@ -161,56 +160,6 @@ static const int code_vesa[85] = {
161 160
162static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0}; 161static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0};
163 162
164static inline void hdmi_write_reg(void __iomem *base_addr,
165 const struct hdmi_reg idx, u32 val)
166{
167 __raw_writel(val, base_addr + idx.idx);
168}
169
170static inline u32 hdmi_read_reg(void __iomem *base_addr,
171 const struct hdmi_reg idx)
172{
173 return __raw_readl(base_addr + idx.idx);
174}
175
176static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
177{
178 return ip_data->base_wp;
179}
180
181static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
182{
183 return ip_data->base_wp + ip_data->phy_offset;
184}
185
186static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
187{
188 return ip_data->base_wp + ip_data->pll_offset;
189}
190
191static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
192{
193 return ip_data->base_wp + ip_data->core_av_offset;
194}
195
196static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
197{
198 return ip_data->base_wp + ip_data->core_sys_offset;
199}
200
201static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
202 const struct hdmi_reg idx,
203 int b2, int b1, u32 val)
204{
205 u32 t = 0;
206 while (val != REG_GET(base_addr, idx, b2, b1)) {
207 udelay(1);
208 if (t++ > 10000)
209 return !val;
210 }
211 return val;
212}
213
214static int hdmi_runtime_get(void) 163static int hdmi_runtime_get(void)
215{ 164{
216 int r; 165 int r;
@@ -239,312 +188,6 @@ int hdmi_init_display(struct omap_dss_device *dssdev)
239 return 0; 188 return 0;
240} 189}
241 190
242static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
243{
244 u32 r;
245 void __iomem *pll_base = hdmi_pll_base(ip_data);
246 struct hdmi_pll_info *fmt = &ip_data->pll_data;
247
248 /* PLL start always use manual mode */
249 REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
250
251 r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
252 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
253 r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */
254
255 hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
256
257 r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
258
259 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
260 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
261 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
262 r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
263
264 if (fmt->dcofreq) {
265 /* divider programming for frequency beyond 1000Mhz */
266 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
267 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
268 } else {
269 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
270 }
271
272 hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
273
274 r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
275 r = FLD_MOD(r, fmt->regm2, 24, 18);
276 r = FLD_MOD(r, fmt->regmf, 17, 0);
277
278 hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
279
280 /* go now */
281 REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
282
283 /* wait for bit change */
284 if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
285 0, 0, 1) != 1) {
286 DSSERR("PLL GO bit not set\n");
287 return -ETIMEDOUT;
288 }
289
290 /* Wait till the lock bit is set in PLL status */
291 if (hdmi_wait_for_bit_change(pll_base,
292 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
293 DSSWARN("cannot lock PLL\n");
294 DSSWARN("CFG1 0x%x\n",
295 hdmi_read_reg(pll_base, PLLCTRL_CFG1));
296 DSSWARN("CFG2 0x%x\n",
297 hdmi_read_reg(pll_base, PLLCTRL_CFG2));
298 DSSWARN("CFG4 0x%x\n",
299 hdmi_read_reg(pll_base, PLLCTRL_CFG4));
300 return -ETIMEDOUT;
301 }
302
303 DSSDBG("PLL locked!\n");
304
305 return 0;
306}
307
308/* PHY_PWR_CMD */
309static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
310{
311 /* Command for power control of HDMI PHY */
312 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
313
314 /* Status of the power control of HDMI PHY */
315 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
316 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
317 DSSERR("Failed to set PHY power mode to %d\n", val);
318 return -ETIMEDOUT;
319 }
320
321 return 0;
322}
323
324/* PLL_PWR_CMD */
325int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
326{
327 /* Command for power control of HDMI PLL */
328 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
329
330 /* wait till PHY_PWR_STATUS is set */
331 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
332 1, 0, val) != val) {
333 DSSERR("Failed to set PHY_PWR_STATUS\n");
334 return -ETIMEDOUT;
335 }
336
337 return 0;
338}
339
340static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
341{
342 /* SYSRESET controlled by power FSM */
343 REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
344
345 /* READ 0x0 reset is in progress */
346 if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
347 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
348 DSSERR("Failed to sysreset PLL\n");
349 return -ETIMEDOUT;
350 }
351
352 return 0;
353}
354
355static int hdmi_phy_init(struct hdmi_ip_data *ip_data)
356{
357 u16 r = 0;
358 void __iomem *phy_base = hdmi_phy_base(ip_data);
359
360 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
361 if (r)
362 return r;
363
364 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
365 if (r)
366 return r;
367
368 /*
369 * Read address 0 in order to get the SCP reset done completed
370 * Dummy access performed to make sure reset is done
371 */
372 hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
373
374 /*
375 * Write to phy address 0 to configure the clock
376 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
377 */
378 REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
379
380 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
381 hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
382
383 /* Setup max LDO voltage */
384 REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
385
386 /* Write to phy address 3 to change the polarity control */
387 REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
388
389 return 0;
390}
391
392static int hdmi_pll_program(struct hdmi_ip_data *ip_data)
393{
394 u16 r = 0;
395
396 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
397 if (r)
398 return r;
399
400 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
401 if (r)
402 return r;
403
404 r = hdmi_pll_reset(ip_data);
405 if (r)
406 return r;
407
408 r = hdmi_pll_init(ip_data);
409 if (r)
410 return r;
411
412 return 0;
413}
414
415static void hdmi_phy_off(struct hdmi_ip_data *ip_data)
416{
417 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
418}
419
420static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
421 u8 *pedid, int ext)
422{
423 u32 i, j;
424 char checksum = 0;
425 u32 offset = 0;
426 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
427
428 /* Turn on CLK for DDC */
429 REG_FLD_MOD(hdmi_av_base(ip_data), HDMI_CORE_AV_DPD, 0x7, 2, 0);
430
431 /*
432 * SW HACK : Without the Delay DDC(i2c bus) reads 0 values /
433 * right shifted values( The behavior is not consistent and seen only
434 * with some TV's)
435 */
436 usleep_range(800, 1000);
437
438 if (!ext) {
439 /* Clk SCL Devices */
440 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
441
442 /* HDMI_CORE_DDC_STATUS_IN_PROG */
443 if (hdmi_wait_for_bit_change(core_sys_base,
444 HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) {
445 DSSERR("Failed to program DDC\n");
446 return -ETIMEDOUT;
447 }
448
449 /* Clear FIFO */
450 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
451
452 /* HDMI_CORE_DDC_STATUS_IN_PROG */
453 if (hdmi_wait_for_bit_change(core_sys_base,
454 HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) {
455 DSSERR("Failed to program DDC\n");
456 return -ETIMEDOUT;
457 }
458
459 } else {
460 if (ext % 2 != 0)
461 offset = 0x80;
462 }
463
464 /* Load Segment Address Register */
465 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_SEGM, ext/2, 7, 0);
466
467 /* Load Slave Address Register */
468 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
469
470 /* Load Offset Address Register */
471 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
472
473 /* Load Byte Count */
474 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
475 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
476
477 /* Set DDC_CMD */
478 if (ext)
479 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
480 else
481 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
482
483 /* HDMI_CORE_DDC_STATUS_BUS_LOW */
484 if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
485 DSSWARN("I2C Bus Low?\n");
486 return -EIO;
487 }
488 /* HDMI_CORE_DDC_STATUS_NO_ACK */
489 if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
490 DSSWARN("I2C No Ack\n");
491 return -EIO;
492 }
493
494 i = ext * 128;
495 j = 0;
496 while (((REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) ||
497 (REG_GET(core_sys_base,
498 HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && j < 128) {
499
500 if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 2, 2) == 0) {
501 /* FIFO not empty */
502 pedid[i++] = REG_GET(core_sys_base,
503 HDMI_CORE_DDC_DATA, 7, 0);
504 j++;
505 }
506 }
507
508 for (j = 0; j < 128; j++)
509 checksum += pedid[j];
510
511 if (checksum != 0) {
512 DSSERR("E-EDID checksum failed!!\n");
513 return -EIO;
514 }
515
516 return 0;
517}
518
519static int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length)
520{
521 int r = 0, n = 0, i = 0;
522 int max_ext_blocks = (max_length / 128) - 1;
523
524 r = hdmi_core_ddc_edid(ip_data, pedid, 0);
525 if (r) {
526 return r;
527 } else {
528 n = pedid[0x7e];
529
530 /*
531 * README: need to comply with max_length set by the caller.
532 * Better implementation should be to allocate necessary
533 * memory to store EDID according to nb_block field found
534 * in first block
535 */
536 if (n > max_ext_blocks)
537 n = max_ext_blocks;
538
539 for (i = 1; i <= n; i++) {
540 r = hdmi_core_ddc_edid(ip_data, pedid, i);
541 if (r)
542 return r;
543 }
544 }
545 return 0;
546}
547
548static void copy_hdmi_to_dss_timings( 191static void copy_hdmi_to_dss_timings(
549 const struct hdmi_video_timings *hdmi_timings, 192 const struct hdmi_video_timings *hdmi_timings,
550 struct omap_video_timings *timings) 193 struct omap_video_timings *timings)
@@ -746,383 +389,6 @@ static void hdmi_read_edid(struct omap_video_timings *dp)
746 389
747} 390}
748 391
749static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
750 struct hdmi_core_infoframe_avi *avi_cfg,
751 struct hdmi_core_packet_enable_repeat *repeat_cfg)
752{
753 DSSDBG("Enter hdmi_core_init\n");
754
755 /* video core */
756 video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
757 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
758 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
759 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
760 video_cfg->hdmi_dvi = HDMI_DVI;
761 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
762
763 /* info frame */
764 avi_cfg->db1_format = 0;
765 avi_cfg->db1_active_info = 0;
766 avi_cfg->db1_bar_info_dv = 0;
767 avi_cfg->db1_scan_info = 0;
768 avi_cfg->db2_colorimetry = 0;
769 avi_cfg->db2_aspect_ratio = 0;
770 avi_cfg->db2_active_fmt_ar = 0;
771 avi_cfg->db3_itc = 0;
772 avi_cfg->db3_ec = 0;
773 avi_cfg->db3_q_range = 0;
774 avi_cfg->db3_nup_scaling = 0;
775 avi_cfg->db4_videocode = 0;
776 avi_cfg->db5_pixel_repeat = 0;
777 avi_cfg->db6_7_line_eoftop = 0 ;
778 avi_cfg->db8_9_line_sofbottom = 0;
779 avi_cfg->db10_11_pixel_eofleft = 0;
780 avi_cfg->db12_13_pixel_sofright = 0;
781
782 /* packet enable and repeat */
783 repeat_cfg->audio_pkt = 0;
784 repeat_cfg->audio_pkt_repeat = 0;
785 repeat_cfg->avi_infoframe = 0;
786 repeat_cfg->avi_infoframe_repeat = 0;
787 repeat_cfg->gen_cntrl_pkt = 0;
788 repeat_cfg->gen_cntrl_pkt_repeat = 0;
789 repeat_cfg->generic_pkt = 0;
790 repeat_cfg->generic_pkt_repeat = 0;
791}
792
793static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
794{
795 DSSDBG("Enter hdmi_core_powerdown_disable\n");
796 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
797}
798
799static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
800{
801 DSSDBG("Enter hdmi_core_swreset_release\n");
802 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
803}
804
805static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
806{
807 DSSDBG("Enter hdmi_core_swreset_assert\n");
808 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
809}
810
811/* HDMI_CORE_VIDEO_CONFIG */
812static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
813 struct hdmi_core_video_config *cfg)
814{
815 u32 r = 0;
816 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
817
818 /* sys_ctrl1 default configuration not tunable */
819 r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
820 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
821 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
822 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
823 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
824 hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
825
826 REG_FLD_MOD(core_sys_base,
827 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
828
829 /* Vid_Mode */
830 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
831
832 /* dither truncation configuration */
833 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
834 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
835 r = FLD_MOD(r, 1, 5, 5);
836 } else {
837 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
838 r = FLD_MOD(r, 0, 5, 5);
839 }
840 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
841
842 /* HDMI_Ctrl */
843 r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
844 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
845 r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
846 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
847 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
848
849 /* TMDS_CTRL */
850 REG_FLD_MOD(core_sys_base,
851 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
852}
853
854static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data,
855 struct hdmi_core_infoframe_avi info_avi)
856{
857 u32 val;
858 char sum = 0, checksum = 0;
859 void __iomem *av_base = hdmi_av_base(ip_data);
860
861 sum += 0x82 + 0x002 + 0x00D;
862 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
863 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
864 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
865
866 val = (info_avi.db1_format << 5) |
867 (info_avi.db1_active_info << 4) |
868 (info_avi.db1_bar_info_dv << 2) |
869 (info_avi.db1_scan_info);
870 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
871 sum += val;
872
873 val = (info_avi.db2_colorimetry << 6) |
874 (info_avi.db2_aspect_ratio << 4) |
875 (info_avi.db2_active_fmt_ar);
876 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
877 sum += val;
878
879 val = (info_avi.db3_itc << 7) |
880 (info_avi.db3_ec << 4) |
881 (info_avi.db3_q_range << 2) |
882 (info_avi.db3_nup_scaling);
883 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
884 sum += val;
885
886 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
887 info_avi.db4_videocode);
888 sum += info_avi.db4_videocode;
889
890 val = info_avi.db5_pixel_repeat;
891 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
892 sum += val;
893
894 val = info_avi.db6_7_line_eoftop & 0x00FF;
895 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
896 sum += val;
897
898 val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
899 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
900 sum += val;
901
902 val = info_avi.db8_9_line_sofbottom & 0x00FF;
903 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
904 sum += val;
905
906 val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
907 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
908 sum += val;
909
910 val = info_avi.db10_11_pixel_eofleft & 0x00FF;
911 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
912 sum += val;
913
914 val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
915 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
916 sum += val;
917
918 val = info_avi.db12_13_pixel_sofright & 0x00FF;
919 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
920 sum += val;
921
922 val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
923 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
924 sum += val;
925
926 checksum = 0x100 - sum;
927 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
928}
929
930static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
931 struct hdmi_core_packet_enable_repeat repeat_cfg)
932{
933 /* enable/repeat the infoframe */
934 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
935 (repeat_cfg.audio_pkt << 5) |
936 (repeat_cfg.audio_pkt_repeat << 4) |
937 (repeat_cfg.avi_infoframe << 1) |
938 (repeat_cfg.avi_infoframe_repeat));
939
940 /* enable/repeat the packet */
941 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
942 (repeat_cfg.gen_cntrl_pkt << 3) |
943 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
944 (repeat_cfg.generic_pkt << 1) |
945 (repeat_cfg.generic_pkt_repeat));
946}
947
948static void hdmi_wp_init(struct omap_video_timings *timings,
949 struct hdmi_video_format *video_fmt,
950 struct hdmi_video_interface *video_int)
951{
952 DSSDBG("Enter hdmi_wp_init\n");
953
954 timings->hbp = 0;
955 timings->hfp = 0;
956 timings->hsw = 0;
957 timings->vbp = 0;
958 timings->vfp = 0;
959 timings->vsw = 0;
960
961 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
962 video_fmt->y_res = 0;
963 video_fmt->x_res = 0;
964
965 video_int->vsp = 0;
966 video_int->hsp = 0;
967
968 video_int->interlacing = 0;
969 video_int->tm = 0; /* HDMI_TIMING_SLAVE */
970
971}
972
973static void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start)
974{
975 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31);
976}
977
978static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
979 struct omap_video_timings *timings, struct hdmi_config *param)
980{
981 DSSDBG("Enter hdmi_wp_video_init_format\n");
982
983 video_fmt->y_res = param->timings.timings.y_res;
984 video_fmt->x_res = param->timings.timings.x_res;
985
986 timings->hbp = param->timings.timings.hbp;
987 timings->hfp = param->timings.timings.hfp;
988 timings->hsw = param->timings.timings.hsw;
989 timings->vbp = param->timings.timings.vbp;
990 timings->vfp = param->timings.timings.vfp;
991 timings->vsw = param->timings.timings.vsw;
992}
993
994static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
995 struct hdmi_video_format *video_fmt)
996{
997 u32 l = 0;
998
999 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
1000 video_fmt->packing_mode, 10, 8);
1001
1002 l |= FLD_VAL(video_fmt->y_res, 31, 16);
1003 l |= FLD_VAL(video_fmt->x_res, 15, 0);
1004 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
1005}
1006
1007static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data,
1008 struct hdmi_video_interface *video_int)
1009{
1010 u32 r;
1011 DSSDBG("Enter hdmi_wp_video_config_interface\n");
1012
1013 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
1014 r = FLD_MOD(r, video_int->vsp, 7, 7);
1015 r = FLD_MOD(r, video_int->hsp, 6, 6);
1016 r = FLD_MOD(r, video_int->interlacing, 3, 3);
1017 r = FLD_MOD(r, video_int->tm, 1, 0);
1018 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
1019}
1020
1021static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
1022 struct omap_video_timings *timings)
1023{
1024 u32 timing_h = 0;
1025 u32 timing_v = 0;
1026
1027 DSSDBG("Enter hdmi_wp_video_config_timing\n");
1028
1029 timing_h |= FLD_VAL(timings->hbp, 31, 20);
1030 timing_h |= FLD_VAL(timings->hfp, 19, 8);
1031 timing_h |= FLD_VAL(timings->hsw, 7, 0);
1032 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
1033
1034 timing_v |= FLD_VAL(timings->vbp, 31, 20);
1035 timing_v |= FLD_VAL(timings->vfp, 19, 8);
1036 timing_v |= FLD_VAL(timings->vsw, 7, 0);
1037 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
1038}
1039
1040static void hdmi_basic_configure(struct hdmi_ip_data *ip_data)
1041{
1042 /* HDMI */
1043 struct omap_video_timings video_timing;
1044 struct hdmi_video_format video_format;
1045 struct hdmi_video_interface video_interface;
1046 /* HDMI core */
1047 struct hdmi_core_infoframe_avi avi_cfg;
1048 struct hdmi_core_video_config v_core_cfg;
1049 struct hdmi_core_packet_enable_repeat repeat_cfg;
1050 struct hdmi_config *cfg = &ip_data->cfg;
1051
1052 hdmi_wp_init(&video_timing, &video_format,
1053 &video_interface);
1054
1055 hdmi_core_init(&v_core_cfg,
1056 &avi_cfg,
1057 &repeat_cfg);
1058
1059 hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
1060
1061 hdmi_wp_video_config_timing(ip_data, &video_timing);
1062
1063 /* video config */
1064 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
1065
1066 hdmi_wp_video_config_format(ip_data, &video_format);
1067
1068 video_interface.vsp = cfg->timings.vsync_pol;
1069 video_interface.hsp = cfg->timings.hsync_pol;
1070 video_interface.interlacing = cfg->interlace;
1071 video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */
1072
1073 hdmi_wp_video_config_interface(ip_data, &video_interface);
1074
1075 /*
1076 * configure core video part
1077 * set software reset in the core
1078 */
1079 hdmi_core_swreset_assert(ip_data);
1080
1081 /* power down off */
1082 hdmi_core_powerdown_disable(ip_data);
1083
1084 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
1085 v_core_cfg.hdmi_dvi = cfg->cm.mode;
1086
1087 hdmi_core_video_config(ip_data, &v_core_cfg);
1088
1089 /* release software reset in the core */
1090 hdmi_core_swreset_release(ip_data);
1091
1092 /*
1093 * configure packet
1094 * info frame video see doc CEA861-D page 65
1095 */
1096 avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
1097 avi_cfg.db1_active_info =
1098 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
1099 avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
1100 avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
1101 avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
1102 avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
1103 avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
1104 avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
1105 avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
1106 avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
1107 avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
1108 avi_cfg.db4_videocode = cfg->cm.code;
1109 avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
1110 avi_cfg.db6_7_line_eoftop = 0;
1111 avi_cfg.db8_9_line_sofbottom = 0;
1112 avi_cfg.db10_11_pixel_eofleft = 0;
1113 avi_cfg.db12_13_pixel_sofright = 0;
1114
1115 hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg);
1116
1117 /* enable/repeat the infoframe */
1118 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
1119 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
1120 /* wakeup */
1121 repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
1122 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
1123 hdmi_core_av_packet_config(ip_data, repeat_cfg);
1124}
1125
1126static void update_hdmi_timings(struct hdmi_config *cfg, 392static void update_hdmi_timings(struct hdmi_config *cfg,
1127 struct omap_video_timings *timings, int code) 393 struct omap_video_timings *timings, int code)
1128{ 394{
diff --git a/drivers/video/omap2/dss/ti_hdmi.h b/drivers/video/omap2/dss/ti_hdmi.h
index f0e508ec28d1..7c630984767d 100644
--- a/drivers/video/omap2/dss/ti_hdmi.h
+++ b/drivers/video/omap2/dss/ti_hdmi.h
@@ -91,4 +91,11 @@ struct hdmi_ip_data {
91 struct hdmi_config cfg; 91 struct hdmi_config cfg;
92 struct hdmi_pll_info pll_data; 92 struct hdmi_pll_info pll_data;
93}; 93};
94int hdmi_phy_init(struct hdmi_ip_data *ip_data);
95void hdmi_phy_off(struct hdmi_ip_data *ip_data);
96int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length);
97void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start);
98int hdmi_pll_program(struct hdmi_ip_data *ip_data);
99int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val);
100void hdmi_basic_configure(struct hdmi_ip_data *ip_data);
94#endif 101#endif
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
new file mode 100644
index 000000000000..b97a3c029584
--- /dev/null
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -0,0 +1,767 @@
1/*
2 * ti_hdmi_4xxx_ip.c
3 *
4 * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/interrupt.h>
27#include <linux/mutex.h>
28#include <linux/delay.h>
29#include <linux/string.h>
30
31#include "ti_hdmi_4xxx_ip.h"
32#include "dss.h"
33
34static inline void hdmi_write_reg(void __iomem *base_addr,
35 const struct hdmi_reg idx, u32 val)
36{
37 __raw_writel(val, base_addr + idx.idx);
38}
39
40static inline u32 hdmi_read_reg(void __iomem *base_addr,
41 const struct hdmi_reg idx)
42{
43 return __raw_readl(base_addr + idx.idx);
44}
45
46static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
47{
48 return ip_data->base_wp;
49}
50
51static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
52{
53 return ip_data->base_wp + ip_data->phy_offset;
54}
55
56static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
57{
58 return ip_data->base_wp + ip_data->pll_offset;
59}
60
61static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
62{
63 return ip_data->base_wp + ip_data->core_av_offset;
64}
65
66static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
67{
68 return ip_data->base_wp + ip_data->core_sys_offset;
69}
70
71static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
72 const struct hdmi_reg idx,
73 int b2, int b1, u32 val)
74{
75 u32 t = 0;
76 while (val != REG_GET(base_addr, idx, b2, b1)) {
77 udelay(1);
78 if (t++ > 10000)
79 return !val;
80 }
81 return val;
82}
83
84static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
85{
86 u32 r;
87 void __iomem *pll_base = hdmi_pll_base(ip_data);
88 struct hdmi_pll_info *fmt = &ip_data->pll_data;
89
90 /* PLL start always use manual mode */
91 REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
92
93 r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
94 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
95 r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */
96
97 hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
98
99 r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
100
101 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
102 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
103 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
104 r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
105
106 if (fmt->dcofreq) {
107 /* divider programming for frequency beyond 1000Mhz */
108 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
109 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
110 } else {
111 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
112 }
113
114 hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
115
116 r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
117 r = FLD_MOD(r, fmt->regm2, 24, 18);
118 r = FLD_MOD(r, fmt->regmf, 17, 0);
119
120 hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
121
122 /* go now */
123 REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
124
125 /* wait for bit change */
126 if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
127 0, 0, 1) != 1) {
128 pr_err("PLL GO bit not set\n");
129 return -ETIMEDOUT;
130 }
131
132 /* Wait till the lock bit is set in PLL status */
133 if (hdmi_wait_for_bit_change(pll_base,
134 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
135 pr_err("cannot lock PLL\n");
136 pr_err("CFG1 0x%x\n",
137 hdmi_read_reg(pll_base, PLLCTRL_CFG1));
138 pr_err("CFG2 0x%x\n",
139 hdmi_read_reg(pll_base, PLLCTRL_CFG2));
140 pr_err("CFG4 0x%x\n",
141 hdmi_read_reg(pll_base, PLLCTRL_CFG4));
142 return -ETIMEDOUT;
143 }
144
145 pr_debug("PLL locked!\n");
146
147 return 0;
148}
149
150/* PHY_PWR_CMD */
151static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
152{
153 /* Command for power control of HDMI PHY */
154 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
155
156 /* Status of the power control of HDMI PHY */
157 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
158 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
159 pr_err("Failed to set PHY power mode to %d\n", val);
160 return -ETIMEDOUT;
161 }
162
163 return 0;
164}
165
166/* PLL_PWR_CMD */
167int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
168{
169 /* Command for power control of HDMI PLL */
170 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
171
172 /* wait till PHY_PWR_STATUS is set */
173 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
174 1, 0, val) != val) {
175 pr_err("Failed to set PLL_PWR_STATUS\n");
176 return -ETIMEDOUT;
177 }
178
179 return 0;
180}
181
182static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
183{
184 /* SYSRESET controlled by power FSM */
185 REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
186
187 /* READ 0x0 reset is in progress */
188 if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
189 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
190 pr_err("Failed to sysreset PLL\n");
191 return -ETIMEDOUT;
192 }
193
194 return 0;
195}
196
197int hdmi_pll_program(struct hdmi_ip_data *ip_data)
198{
199 u16 r = 0;
200
201 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
202 if (r)
203 return r;
204
205 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
206 if (r)
207 return r;
208
209 r = hdmi_pll_reset(ip_data);
210 if (r)
211 return r;
212
213 r = hdmi_pll_init(ip_data);
214 if (r)
215 return r;
216
217 return 0;
218}
219
220int hdmi_phy_init(struct hdmi_ip_data *ip_data)
221{
222 u16 r = 0;
223 void __iomem *phy_base = hdmi_phy_base(ip_data);
224
225 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
226 if (r)
227 return r;
228
229 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
230 if (r)
231 return r;
232
233 /*
234 * Read address 0 in order to get the SCP reset done completed
235 * Dummy access performed to make sure reset is done
236 */
237 hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
238
239 /*
240 * Write to phy address 0 to configure the clock
241 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
242 */
243 REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
244
245 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
246 hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
247
248 /* Setup max LDO voltage */
249 REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
250
251 /* Write to phy address 3 to change the polarity control */
252 REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
253
254 return 0;
255}
256
257void hdmi_phy_off(struct hdmi_ip_data *ip_data)
258{
259 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
260}
261
262static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
263 u8 *pedid, int ext)
264{
265 u32 i, j;
266 char checksum = 0;
267 u32 offset = 0;
268 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
269
270 /* Turn on CLK for DDC */
271 REG_FLD_MOD(hdmi_av_base(ip_data), HDMI_CORE_AV_DPD, 0x7, 2, 0);
272
273 /*
274 * SW HACK : Without the Delay DDC(i2c bus) reads 0 values /
275 * right shifted values( The behavior is not consistent and seen only
276 * with some TV's)
277 */
278 usleep_range(800, 1000);
279
280 if (!ext) {
281 /* Clk SCL Devices */
282 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
283
284 /* HDMI_CORE_DDC_STATUS_IN_PROG */
285 if (hdmi_wait_for_bit_change(core_sys_base,
286 HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) {
287 pr_err("Failed to program DDC\n");
288 return -ETIMEDOUT;
289 }
290
291 /* Clear FIFO */
292 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
293
294 /* HDMI_CORE_DDC_STATUS_IN_PROG */
295 if (hdmi_wait_for_bit_change(core_sys_base,
296 HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) {
297 pr_err("Failed to program DDC\n");
298 return -ETIMEDOUT;
299 }
300
301 } else {
302 if (ext % 2 != 0)
303 offset = 0x80;
304 }
305
306 /* Load Segment Address Register */
307 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_SEGM, ext/2, 7, 0);
308
309 /* Load Slave Address Register */
310 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
311
312 /* Load Offset Address Register */
313 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
314
315 /* Load Byte Count */
316 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
317 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
318
319 /* Set DDC_CMD */
320 if (ext)
321 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
322 else
323 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
324
325 /* HDMI_CORE_DDC_STATUS_BUS_LOW */
326 if (REG_GET(core_sys_base,
327 HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
328 pr_err("I2C Bus Low?\n");
329 return -EIO;
330 }
331 /* HDMI_CORE_DDC_STATUS_NO_ACK */
332 if (REG_GET(core_sys_base,
333 HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
334 pr_err("I2C No Ack\n");
335 return -EIO;
336 }
337
338 i = ext * 128;
339 j = 0;
340 while (((REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) ||
341 (REG_GET(core_sys_base,
342 HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && j < 128) {
343
344 if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 2, 2) == 0) {
345 /* FIFO not empty */
346 pedid[i++] = REG_GET(core_sys_base,
347 HDMI_CORE_DDC_DATA, 7, 0);
348 j++;
349 }
350 }
351
352 for (j = 0; j < 128; j++)
353 checksum += pedid[j];
354
355 if (checksum != 0) {
356 pr_err("E-EDID checksum failed!!\n");
357 return -EIO;
358 }
359
360 return 0;
361}
362
363int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length)
364{
365 int r = 0, n = 0, i = 0;
366 int max_ext_blocks = (max_length / 128) - 1;
367
368 r = hdmi_core_ddc_edid(ip_data, pedid, 0);
369 if (r) {
370 return r;
371 } else {
372 n = pedid[0x7e];
373
374 /*
375 * README: need to comply with max_length set by the caller.
376 * Better implementation should be to allocate necessary
377 * memory to store EDID according to nb_block field found
378 * in first block
379 */
380 if (n > max_ext_blocks)
381 n = max_ext_blocks;
382
383 for (i = 1; i <= n; i++) {
384 r = hdmi_core_ddc_edid(ip_data, pedid, i);
385 if (r)
386 return r;
387 }
388 }
389 return 0;
390}
391
392static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
393 struct hdmi_core_infoframe_avi *avi_cfg,
394 struct hdmi_core_packet_enable_repeat *repeat_cfg)
395{
396 pr_debug("Enter hdmi_core_init\n");
397
398 /* video core */
399 video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
400 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
401 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
402 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
403 video_cfg->hdmi_dvi = HDMI_DVI;
404 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
405
406 /* info frame */
407 avi_cfg->db1_format = 0;
408 avi_cfg->db1_active_info = 0;
409 avi_cfg->db1_bar_info_dv = 0;
410 avi_cfg->db1_scan_info = 0;
411 avi_cfg->db2_colorimetry = 0;
412 avi_cfg->db2_aspect_ratio = 0;
413 avi_cfg->db2_active_fmt_ar = 0;
414 avi_cfg->db3_itc = 0;
415 avi_cfg->db3_ec = 0;
416 avi_cfg->db3_q_range = 0;
417 avi_cfg->db3_nup_scaling = 0;
418 avi_cfg->db4_videocode = 0;
419 avi_cfg->db5_pixel_repeat = 0;
420 avi_cfg->db6_7_line_eoftop = 0 ;
421 avi_cfg->db8_9_line_sofbottom = 0;
422 avi_cfg->db10_11_pixel_eofleft = 0;
423 avi_cfg->db12_13_pixel_sofright = 0;
424
425 /* packet enable and repeat */
426 repeat_cfg->audio_pkt = 0;
427 repeat_cfg->audio_pkt_repeat = 0;
428 repeat_cfg->avi_infoframe = 0;
429 repeat_cfg->avi_infoframe_repeat = 0;
430 repeat_cfg->gen_cntrl_pkt = 0;
431 repeat_cfg->gen_cntrl_pkt_repeat = 0;
432 repeat_cfg->generic_pkt = 0;
433 repeat_cfg->generic_pkt_repeat = 0;
434}
435
436static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
437{
438 pr_debug("Enter hdmi_core_powerdown_disable\n");
439 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
440}
441
442static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
443{
444 pr_debug("Enter hdmi_core_swreset_release\n");
445 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
446}
447
448static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
449{
450 pr_debug("Enter hdmi_core_swreset_assert\n");
451 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
452}
453
454/* HDMI_CORE_VIDEO_CONFIG */
455static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
456 struct hdmi_core_video_config *cfg)
457{
458 u32 r = 0;
459 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
460
461 /* sys_ctrl1 default configuration not tunable */
462 r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
463 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
464 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
465 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
466 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
467 hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
468
469 REG_FLD_MOD(core_sys_base,
470 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
471
472 /* Vid_Mode */
473 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
474
475 /* dither truncation configuration */
476 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
477 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
478 r = FLD_MOD(r, 1, 5, 5);
479 } else {
480 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
481 r = FLD_MOD(r, 0, 5, 5);
482 }
483 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
484
485 /* HDMI_Ctrl */
486 r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
487 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
488 r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
489 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
490 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
491
492 /* TMDS_CTRL */
493 REG_FLD_MOD(core_sys_base,
494 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
495}
496
497static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data,
498 struct hdmi_core_infoframe_avi info_avi)
499{
500 u32 val;
501 char sum = 0, checksum = 0;
502 void __iomem *av_base = hdmi_av_base(ip_data);
503
504 sum += 0x82 + 0x002 + 0x00D;
505 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
506 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
507 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
508
509 val = (info_avi.db1_format << 5) |
510 (info_avi.db1_active_info << 4) |
511 (info_avi.db1_bar_info_dv << 2) |
512 (info_avi.db1_scan_info);
513 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
514 sum += val;
515
516 val = (info_avi.db2_colorimetry << 6) |
517 (info_avi.db2_aspect_ratio << 4) |
518 (info_avi.db2_active_fmt_ar);
519 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
520 sum += val;
521
522 val = (info_avi.db3_itc << 7) |
523 (info_avi.db3_ec << 4) |
524 (info_avi.db3_q_range << 2) |
525 (info_avi.db3_nup_scaling);
526 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
527 sum += val;
528
529 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
530 info_avi.db4_videocode);
531 sum += info_avi.db4_videocode;
532
533 val = info_avi.db5_pixel_repeat;
534 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
535 sum += val;
536
537 val = info_avi.db6_7_line_eoftop & 0x00FF;
538 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
539 sum += val;
540
541 val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
542 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
543 sum += val;
544
545 val = info_avi.db8_9_line_sofbottom & 0x00FF;
546 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
547 sum += val;
548
549 val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
550 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
551 sum += val;
552
553 val = info_avi.db10_11_pixel_eofleft & 0x00FF;
554 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
555 sum += val;
556
557 val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
558 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
559 sum += val;
560
561 val = info_avi.db12_13_pixel_sofright & 0x00FF;
562 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
563 sum += val;
564
565 val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
566 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
567 sum += val;
568
569 checksum = 0x100 - sum;
570 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
571}
572
573static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
574 struct hdmi_core_packet_enable_repeat repeat_cfg)
575{
576 /* enable/repeat the infoframe */
577 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
578 (repeat_cfg.audio_pkt << 5) |
579 (repeat_cfg.audio_pkt_repeat << 4) |
580 (repeat_cfg.avi_infoframe << 1) |
581 (repeat_cfg.avi_infoframe_repeat));
582
583 /* enable/repeat the packet */
584 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
585 (repeat_cfg.gen_cntrl_pkt << 3) |
586 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
587 (repeat_cfg.generic_pkt << 1) |
588 (repeat_cfg.generic_pkt_repeat));
589}
590
591static void hdmi_wp_init(struct omap_video_timings *timings,
592 struct hdmi_video_format *video_fmt,
593 struct hdmi_video_interface *video_int)
594{
595 pr_debug("Enter hdmi_wp_init\n");
596
597 timings->hbp = 0;
598 timings->hfp = 0;
599 timings->hsw = 0;
600 timings->vbp = 0;
601 timings->vfp = 0;
602 timings->vsw = 0;
603
604 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
605 video_fmt->y_res = 0;
606 video_fmt->x_res = 0;
607
608 video_int->vsp = 0;
609 video_int->hsp = 0;
610
611 video_int->interlacing = 0;
612 video_int->tm = 0; /* HDMI_TIMING_SLAVE */
613
614}
615
616void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start)
617{
618 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31);
619}
620
621static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
622 struct omap_video_timings *timings, struct hdmi_config *param)
623{
624 pr_debug("Enter hdmi_wp_video_init_format\n");
625
626 video_fmt->y_res = param->timings.timings.y_res;
627 video_fmt->x_res = param->timings.timings.x_res;
628
629 timings->hbp = param->timings.timings.hbp;
630 timings->hfp = param->timings.timings.hfp;
631 timings->hsw = param->timings.timings.hsw;
632 timings->vbp = param->timings.timings.vbp;
633 timings->vfp = param->timings.timings.vfp;
634 timings->vsw = param->timings.timings.vsw;
635}
636
637static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
638 struct hdmi_video_format *video_fmt)
639{
640 u32 l = 0;
641
642 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
643 video_fmt->packing_mode, 10, 8);
644
645 l |= FLD_VAL(video_fmt->y_res, 31, 16);
646 l |= FLD_VAL(video_fmt->x_res, 15, 0);
647 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
648}
649
650static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data,
651 struct hdmi_video_interface *video_int)
652{
653 u32 r;
654 pr_debug("Enter hdmi_wp_video_config_interface\n");
655
656 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
657 r = FLD_MOD(r, video_int->vsp, 7, 7);
658 r = FLD_MOD(r, video_int->hsp, 6, 6);
659 r = FLD_MOD(r, video_int->interlacing, 3, 3);
660 r = FLD_MOD(r, video_int->tm, 1, 0);
661 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
662}
663
664static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
665 struct omap_video_timings *timings)
666{
667 u32 timing_h = 0;
668 u32 timing_v = 0;
669
670 pr_debug("Enter hdmi_wp_video_config_timing\n");
671
672 timing_h |= FLD_VAL(timings->hbp, 31, 20);
673 timing_h |= FLD_VAL(timings->hfp, 19, 8);
674 timing_h |= FLD_VAL(timings->hsw, 7, 0);
675 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
676
677 timing_v |= FLD_VAL(timings->vbp, 31, 20);
678 timing_v |= FLD_VAL(timings->vfp, 19, 8);
679 timing_v |= FLD_VAL(timings->vsw, 7, 0);
680 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
681}
682
683void hdmi_basic_configure(struct hdmi_ip_data *ip_data)
684{
685 /* HDMI */
686 struct omap_video_timings video_timing;
687 struct hdmi_video_format video_format;
688 struct hdmi_video_interface video_interface;
689 /* HDMI core */
690 struct hdmi_core_infoframe_avi avi_cfg;
691 struct hdmi_core_video_config v_core_cfg;
692 struct hdmi_core_packet_enable_repeat repeat_cfg;
693 struct hdmi_config *cfg = &ip_data->cfg;
694
695 hdmi_wp_init(&video_timing, &video_format,
696 &video_interface);
697
698 hdmi_core_init(&v_core_cfg,
699 &avi_cfg,
700 &repeat_cfg);
701
702 hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
703
704 hdmi_wp_video_config_timing(ip_data, &video_timing);
705
706 /* video config */
707 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
708
709 hdmi_wp_video_config_format(ip_data, &video_format);
710
711 video_interface.vsp = cfg->timings.vsync_pol;
712 video_interface.hsp = cfg->timings.hsync_pol;
713 video_interface.interlacing = cfg->interlace;
714 video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */
715
716 hdmi_wp_video_config_interface(ip_data, &video_interface);
717
718 /*
719 * configure core video part
720 * set software reset in the core
721 */
722 hdmi_core_swreset_assert(ip_data);
723
724 /* power down off */
725 hdmi_core_powerdown_disable(ip_data);
726
727 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
728 v_core_cfg.hdmi_dvi = cfg->cm.mode;
729
730 hdmi_core_video_config(ip_data, &v_core_cfg);
731
732 /* release software reset in the core */
733 hdmi_core_swreset_release(ip_data);
734
735 /*
736 * configure packet
737 * info frame video see doc CEA861-D page 65
738 */
739 avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
740 avi_cfg.db1_active_info =
741 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
742 avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
743 avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
744 avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
745 avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
746 avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
747 avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
748 avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
749 avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
750 avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
751 avi_cfg.db4_videocode = cfg->cm.code;
752 avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
753 avi_cfg.db6_7_line_eoftop = 0;
754 avi_cfg.db8_9_line_sofbottom = 0;
755 avi_cfg.db10_11_pixel_eofleft = 0;
756 avi_cfg.db12_13_pixel_sofright = 0;
757
758 hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg);
759
760 /* enable/repeat the infoframe */
761 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
762 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
763 /* wakeup */
764 repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
765 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
766 hdmi_core_av_packet_config(ip_data, repeat_cfg);
767}
diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
index 2d4a22eca9c6..7feead1d50d2 100644
--- a/drivers/video/omap2/dss/hdmi.h
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * hdmi.h 2 * ti_hdmi_4xxx_ip.h
3 * 3 *
4 * HDMI driver definition for TI OMAP4 processors. 4 * HDMI header definition for DM81xx, DM38xx, TI OMAP4 etc processors.
5 * 5 *
6 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ 6 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
7 * 7 *
@@ -18,11 +18,12 @@
18 * this program. If not, see <http://www.gnu.org/licenses/>. 18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */ 19 */
20 20
21#ifndef _OMAP4_DSS_HDMI_H_ 21#ifndef _HDMI_TI_4xxx_H_
22#define _OMAP4_DSS_HDMI_H_ 22#define _HDMI_TI_4xxx_H_
23 23
24#include <linux/string.h> 24#include <linux/string.h>
25#include <video/omapdss.h> 25#include <video/omapdss.h>
26#include "ti_hdmi.h"
26 27
27struct hdmi_reg { u16 idx; }; 28struct hdmi_reg { u16 idx; };
28 29
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 23:41:57 -0500