aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/video
diff options
context:
space:
mode:
authorTomi Valkeinen <tomi.valkeinen@ti.com>2014-09-29 16:46:18 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2015-02-26 05:15:14 -0500
commitc64aa3a6600fa5ab25c3ff535d134c8f09add5aa (patch)
tree44a2f96a94a2a169d9366251bfe3adf7124a3390 /drivers/video
parent47fc469b3af5fc63d65a51e21acaa3ed06c288e7 (diff)
OMAPDSS: Add support for MFLAG
OMAP5 has support for MFLAG feature, which allows DSS to dynamically increase the priority of DISPC's DMA traffic. At the moment we don't have support for it. It was noticed that on DRA7 with high bandwidth use cases we see FIFO underflows. Implementing MFLAG support removed those underflows. Interestingly, on OMAP5 uEVM no such overflows were seen. This patch adds a simple MFLAG implementation, where we use a fixed MFLAG threshold value based on the FIFO size. The thresholds are set to 4/8 of fifo size for low threshold, and 5/8 of fifo size for high threshold. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/fbdev/omap2/dss/dispc.c50
1 files changed, 50 insertions, 0 deletions
diff --git a/drivers/video/fbdev/omap2/dss/dispc.c b/drivers/video/fbdev/omap2/dss/dispc.c
index 6296a3e5124f..6b056d0ce187 100644
--- a/drivers/video/fbdev/omap2/dss/dispc.c
+++ b/drivers/video/fbdev/omap2/dss/dispc.c
@@ -1305,6 +1305,53 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1305} 1305}
1306EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds); 1306EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
1307 1307
1308static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1309{
1310 int bit;
1311
1312 if (plane == OMAP_DSS_GFX)
1313 bit = 14;
1314 else
1315 bit = 23;
1316
1317 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1318}
1319
1320static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1321 int low, int high)
1322{
1323 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1324 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1325}
1326
1327static void dispc_init_mflag(void)
1328{
1329 int i;
1330
1331 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1332 (2 << 0) | /* MFLAG_CTRL = enable */
1333 (0 << 2)); /* MFLAG_START = disable */
1334
1335 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1336 u32 size = dispc_ovl_get_fifo_size(i);
1337 u32 unit = dss_feat_get_buffer_size_unit();
1338 u32 low, high;
1339
1340 dispc_ovl_set_mflag(i, true);
1341
1342 /*
1343 * Simulation team suggests below thesholds:
1344 * HT = fifosize * 5 / 8;
1345 * LT = fifosize * 4 / 8;
1346 */
1347
1348 low = size * 4 / 8 / unit;
1349 high = size * 5 / 8 / unit;
1350
1351 dispc_ovl_set_mflag_threshold(i, low, high);
1352 }
1353}
1354
1308static void dispc_ovl_set_fir(enum omap_plane plane, 1355static void dispc_ovl_set_fir(enum omap_plane plane,
1309 int hinc, int vinc, 1356 int hinc, int vinc,
1310 enum omap_color_component color_comp) 1357 enum omap_color_component color_comp)
@@ -3630,6 +3677,9 @@ static void _omap_dispc_initial_config(void)
3630 3677
3631 if (dispc.feat->mstandby_workaround) 3678 if (dispc.feat->mstandby_workaround)
3632 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); 3679 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3680
3681 if (dss_has_feature(FEAT_MFLAG))
3682 dispc_init_mflag();
3633} 3683}
3634 3684
3635static const struct dispc_features omap24xx_dispc_feats __initconst = { 3685static const struct dispc_features omap24xx_dispc_feats __initconst = {