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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-06-14 06:00:16 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-06-14 06:00:16 -0400
commit4c31791c3d9d38ac052dd5e2981df713d8f3dcc4 (patch)
treeb7f95922b2f1da5b36d95176e6d8f826151f3ee1 /drivers/video
parent98797a241e28b787b84d308b867ec4c5fe7bbdf8 (diff)
parent7517b3fbe40c231d79d36f31c1e9930cbb8c4be2 (diff)
Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/Kconfig10
-rw-r--r--drivers/video/Makefile1
-rw-r--r--drivers/video/pxa168fb.c803
-rw-r--r--drivers/video/pxa168fb.h558
4 files changed, 1372 insertions, 0 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 8083d862ebc5..b6c0239d8d29 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1759,6 +1759,16 @@ config FB_68328
1759 Say Y here if you want to support the built-in frame buffer of 1759 Say Y here if you want to support the built-in frame buffer of
1760 the Motorola 68328 CPU family. 1760 the Motorola 68328 CPU family.
1761 1761
1762config FB_PXA168
1763 tristate "PXA168/910 LCD framebuffer support"
1764 depends on FB && (CPU_PXA168 || CPU_PXA910)
1765 select FB_CFB_FILLRECT
1766 select FB_CFB_COPYAREA
1767 select FB_CFB_IMAGEBLIT
1768 ---help---
1769 Frame buffer driver for the built-in LCD controller in the Marvell
1770 MMP processor.
1771
1762config FB_PXA 1772config FB_PXA
1763 tristate "PXA LCD framebuffer support" 1773 tristate "PXA LCD framebuffer support"
1764 depends on FB && ARCH_PXA 1774 depends on FB && ARCH_PXA
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index d8d0be5151e3..01a819f47371 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -97,6 +97,7 @@ obj-$(CONFIG_FB_GBE) += gbefb.o
97obj-$(CONFIG_FB_CIRRUS) += cirrusfb.o 97obj-$(CONFIG_FB_CIRRUS) += cirrusfb.o
98obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o 98obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o
99obj-$(CONFIG_FB_PXA) += pxafb.o 99obj-$(CONFIG_FB_PXA) += pxafb.o
100obj-$(CONFIG_FB_PXA168) += pxa168fb.o
100obj-$(CONFIG_FB_W100) += w100fb.o 101obj-$(CONFIG_FB_W100) += w100fb.o
101obj-$(CONFIG_FB_TMIO) += tmiofb.o 102obj-$(CONFIG_FB_TMIO) += tmiofb.o
102obj-$(CONFIG_FB_AU1100) += au1100fb.o 103obj-$(CONFIG_FB_AU1100) += au1100fb.o
diff --git a/drivers/video/pxa168fb.c b/drivers/video/pxa168fb.c
new file mode 100644
index 000000000000..84d8327e47db
--- /dev/null
+++ b/drivers/video/pxa168fb.c
@@ -0,0 +1,803 @@
1/*
2 * linux/drivers/video/pxa168fb.c -- Marvell PXA168 LCD Controller
3 *
4 * Copyright (C) 2008 Marvell International Ltd.
5 * All rights reserved.
6 *
7 * 2009-02-16 adapted from original version for PXA168/910
8 * Jun Nie <njun@marvell.com>
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
12 * more details.
13 */
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/sched.h>
18#include <linux/string.h>
19#include <linux/interrupt.h>
20#include <linux/slab.h>
21#include <linux/fb.h>
22#include <linux/delay.h>
23#include <linux/init.h>
24#include <linux/ioport.h>
25#include <linux/platform_device.h>
26#include <linux/dma-mapping.h>
27#include <linux/clk.h>
28#include <linux/err.h>
29#include <linux/uaccess.h>
30#include <video/pxa168fb.h>
31
32#include "pxa168fb.h"
33
34#define DEFAULT_REFRESH 60 /* Hz */
35
36static int determine_best_pix_fmt(struct fb_var_screeninfo *var)
37{
38 /*
39 * Pseudocolor mode?
40 */
41 if (var->bits_per_pixel == 8)
42 return PIX_FMT_PSEUDOCOLOR;
43
44 /*
45 * Check for 565/1555.
46 */
47 if (var->bits_per_pixel == 16 && var->red.length <= 5 &&
48 var->green.length <= 6 && var->blue.length <= 5) {
49 if (var->transp.length == 0) {
50 if (var->red.offset >= var->blue.offset)
51 return PIX_FMT_RGB565;
52 else
53 return PIX_FMT_BGR565;
54 }
55
56 if (var->transp.length == 1 && var->green.length <= 5) {
57 if (var->red.offset >= var->blue.offset)
58 return PIX_FMT_RGB1555;
59 else
60 return PIX_FMT_BGR1555;
61 }
62
63 /* fall through */
64 }
65
66 /*
67 * Check for 888/A888.
68 */
69 if (var->bits_per_pixel <= 32 && var->red.length <= 8 &&
70 var->green.length <= 8 && var->blue.length <= 8) {
71 if (var->bits_per_pixel == 24 && var->transp.length == 0) {
72 if (var->red.offset >= var->blue.offset)
73 return PIX_FMT_RGB888PACK;
74 else
75 return PIX_FMT_BGR888PACK;
76 }
77
78 if (var->bits_per_pixel == 32 && var->transp.length == 8) {
79 if (var->red.offset >= var->blue.offset)
80 return PIX_FMT_RGBA888;
81 else
82 return PIX_FMT_BGRA888;
83 } else {
84 if (var->red.offset >= var->blue.offset)
85 return PIX_FMT_RGB888UNPACK;
86 else
87 return PIX_FMT_BGR888UNPACK;
88 }
89
90 /* fall through */
91 }
92
93 return -EINVAL;
94}
95
96static void set_pix_fmt(struct fb_var_screeninfo *var, int pix_fmt)
97{
98 switch (pix_fmt) {
99 case PIX_FMT_RGB565:
100 var->bits_per_pixel = 16;
101 var->red.offset = 11; var->red.length = 5;
102 var->green.offset = 5; var->green.length = 6;
103 var->blue.offset = 0; var->blue.length = 5;
104 var->transp.offset = 0; var->transp.length = 0;
105 break;
106 case PIX_FMT_BGR565:
107 var->bits_per_pixel = 16;
108 var->red.offset = 0; var->red.length = 5;
109 var->green.offset = 5; var->green.length = 6;
110 var->blue.offset = 11; var->blue.length = 5;
111 var->transp.offset = 0; var->transp.length = 0;
112 break;
113 case PIX_FMT_RGB1555:
114 var->bits_per_pixel = 16;
115 var->red.offset = 10; var->red.length = 5;
116 var->green.offset = 5; var->green.length = 5;
117 var->blue.offset = 0; var->blue.length = 5;
118 var->transp.offset = 15; var->transp.length = 1;
119 break;
120 case PIX_FMT_BGR1555:
121 var->bits_per_pixel = 16;
122 var->red.offset = 0; var->red.length = 5;
123 var->green.offset = 5; var->green.length = 5;
124 var->blue.offset = 10; var->blue.length = 5;
125 var->transp.offset = 15; var->transp.length = 1;
126 break;
127 case PIX_FMT_RGB888PACK:
128 var->bits_per_pixel = 24;
129 var->red.offset = 16; var->red.length = 8;
130 var->green.offset = 8; var->green.length = 8;
131 var->blue.offset = 0; var->blue.length = 8;
132 var->transp.offset = 0; var->transp.length = 0;
133 break;
134 case PIX_FMT_BGR888PACK:
135 var->bits_per_pixel = 24;
136 var->red.offset = 0; var->red.length = 8;
137 var->green.offset = 8; var->green.length = 8;
138 var->blue.offset = 16; var->blue.length = 8;
139 var->transp.offset = 0; var->transp.length = 0;
140 break;
141 case PIX_FMT_RGBA888:
142 var->bits_per_pixel = 32;
143 var->red.offset = 16; var->red.length = 8;
144 var->green.offset = 8; var->green.length = 8;
145 var->blue.offset = 0; var->blue.length = 8;
146 var->transp.offset = 24; var->transp.length = 8;
147 break;
148 case PIX_FMT_BGRA888:
149 var->bits_per_pixel = 32;
150 var->red.offset = 0; var->red.length = 8;
151 var->green.offset = 8; var->green.length = 8;
152 var->blue.offset = 16; var->blue.length = 8;
153 var->transp.offset = 24; var->transp.length = 8;
154 break;
155 case PIX_FMT_PSEUDOCOLOR:
156 var->bits_per_pixel = 8;
157 var->red.offset = 0; var->red.length = 8;
158 var->green.offset = 0; var->green.length = 8;
159 var->blue.offset = 0; var->blue.length = 8;
160 var->transp.offset = 0; var->transp.length = 0;
161 break;
162 }
163}
164
165static void set_mode(struct pxa168fb_info *fbi, struct fb_var_screeninfo *var,
166 struct fb_videomode *mode, int pix_fmt, int ystretch)
167{
168 struct fb_info *info = fbi->info;
169
170 set_pix_fmt(var, pix_fmt);
171
172 var->xres = mode->xres;
173 var->yres = mode->yres;
174 var->xres_virtual = max(var->xres, var->xres_virtual);
175 if (ystretch)
176 var->yres_virtual = info->fix.smem_len /
177 (var->xres_virtual * (var->bits_per_pixel >> 3));
178 else
179 var->yres_virtual = max(var->yres, var->yres_virtual);
180 var->grayscale = 0;
181 var->accel_flags = FB_ACCEL_NONE;
182 var->pixclock = mode->pixclock;
183 var->left_margin = mode->left_margin;
184 var->right_margin = mode->right_margin;
185 var->upper_margin = mode->upper_margin;
186 var->lower_margin = mode->lower_margin;
187 var->hsync_len = mode->hsync_len;
188 var->vsync_len = mode->vsync_len;
189 var->sync = mode->sync;
190 var->vmode = FB_VMODE_NONINTERLACED;
191 var->rotate = FB_ROTATE_UR;
192}
193
194static int pxa168fb_check_var(struct fb_var_screeninfo *var,
195 struct fb_info *info)
196{
197 struct pxa168fb_info *fbi = info->par;
198 int pix_fmt;
199
200 /*
201 * Determine which pixel format we're going to use.
202 */
203 pix_fmt = determine_best_pix_fmt(var);
204 if (pix_fmt < 0)
205 return pix_fmt;
206 set_pix_fmt(var, pix_fmt);
207 fbi->pix_fmt = pix_fmt;
208
209 /*
210 * Basic geometry sanity checks.
211 */
212 if (var->xoffset + var->xres > var->xres_virtual)
213 return -EINVAL;
214 if (var->yoffset + var->yres > var->yres_virtual)
215 return -EINVAL;
216 if (var->xres + var->right_margin +
217 var->hsync_len + var->left_margin > 2048)
218 return -EINVAL;
219 if (var->yres + var->lower_margin +
220 var->vsync_len + var->upper_margin > 2048)
221 return -EINVAL;
222
223 /*
224 * Check size of framebuffer.
225 */
226 if (var->xres_virtual * var->yres_virtual *
227 (var->bits_per_pixel >> 3) > info->fix.smem_len)
228 return -EINVAL;
229
230 return 0;
231}
232
233/*
234 * The hardware clock divider has an integer and a fractional
235 * stage:
236 *
237 * clk2 = clk_in / integer_divider
238 * clk_out = clk2 * (1 - (fractional_divider >> 12))
239 *
240 * Calculate integer and fractional divider for given clk_in
241 * and clk_out.
242 */
243static void set_clock_divider(struct pxa168fb_info *fbi,
244 const struct fb_videomode *m)
245{
246 int divider_int;
247 int needed_pixclk;
248 u64 div_result;
249 u32 x = 0;
250
251 /*
252 * Notice: The field pixclock is used by linux fb
253 * is in pixel second. E.g. struct fb_videomode &
254 * struct fb_var_screeninfo
255 */
256
257 /*
258 * Check input values.
259 */
260 if (!m || !m->pixclock || !m->refresh) {
261 dev_err(fbi->dev, "Input refresh or pixclock is wrong.\n");
262 return;
263 }
264
265 /*
266 * Using PLL/AXI clock.
267 */
268 x = 0x80000000;
269
270 /*
271 * Calc divider according to refresh rate.
272 */
273 div_result = 1000000000000ll;
274 do_div(div_result, m->pixclock);
275 needed_pixclk = (u32)div_result;
276
277 divider_int = clk_get_rate(fbi->clk) / needed_pixclk;
278
279 /* check whether divisor is too small. */
280 if (divider_int < 2) {
281 dev_warn(fbi->dev, "Warning: clock source is too slow."
282 "Try smaller resolution\n");
283 divider_int = 2;
284 }
285
286 /*
287 * Set setting to reg.
288 */
289 x |= divider_int;
290 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV);
291}
292
293static void set_dma_control0(struct pxa168fb_info *fbi)
294{
295 u32 x;
296
297 /*
298 * Set bit to enable graphics DMA.
299 */
300 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
301 x |= fbi->active ? 0x00000100 : 0;
302 fbi->active = 0;
303
304 /*
305 * If we are in a pseudo-color mode, we need to enable
306 * palette lookup.
307 */
308 if (fbi->pix_fmt == PIX_FMT_PSEUDOCOLOR)
309 x |= 0x10000000;
310
311 /*
312 * Configure hardware pixel format.
313 */
314 x &= ~(0xF << 16);
315 x |= (fbi->pix_fmt >> 1) << 16;
316
317 /*
318 * Check red and blue pixel swap.
319 * 1. source data swap
320 * 2. panel output data swap
321 */
322 x &= ~(1 << 12);
323 x |= ((fbi->pix_fmt & 1) ^ (fbi->panel_rbswap)) << 12;
324
325 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0);
326}
327
328static void set_dma_control1(struct pxa168fb_info *fbi, int sync)
329{
330 u32 x;
331
332 /*
333 * Configure default bits: vsync triggers DMA, gated clock
334 * enable, power save enable, configure alpha registers to
335 * display 100% graphics, and set pixel command.
336 */
337 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1);
338 x |= 0x2032ff81;
339
340 /*
341 * We trigger DMA on the falling edge of vsync if vsync is
342 * active low, or on the rising edge if vsync is active high.
343 */
344 if (!(sync & FB_SYNC_VERT_HIGH_ACT))
345 x |= 0x08000000;
346
347 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1);
348}
349
350static void set_graphics_start(struct fb_info *info, int xoffset, int yoffset)
351{
352 struct pxa168fb_info *fbi = info->par;
353 struct fb_var_screeninfo *var = &info->var;
354 int pixel_offset;
355 unsigned long addr;
356
357 pixel_offset = (yoffset * var->xres_virtual) + xoffset;
358
359 addr = fbi->fb_start_dma + (pixel_offset * (var->bits_per_pixel >> 3));
360 writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0);
361}
362
363static void set_dumb_panel_control(struct fb_info *info)
364{
365 struct pxa168fb_info *fbi = info->par;
366 struct pxa168fb_mach_info *mi = fbi->dev->platform_data;
367 u32 x;
368
369 /*
370 * Preserve enable flag.
371 */
372 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001;
373
374 x |= (fbi->is_blanked ? 0x7 : mi->dumb_mode) << 28;
375 x |= mi->gpio_output_data << 20;
376 x |= mi->gpio_output_mask << 12;
377 x |= mi->panel_rgb_reverse_lanes ? 0x00000080 : 0;
378 x |= mi->invert_composite_blank ? 0x00000040 : 0;
379 x |= (info->var.sync & FB_SYNC_COMP_HIGH_ACT) ? 0x00000020 : 0;
380 x |= mi->invert_pix_val_ena ? 0x00000010 : 0;
381 x |= (info->var.sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x00000008;
382 x |= (info->var.sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x00000004;
383 x |= mi->invert_pixclock ? 0x00000002 : 0;
384
385 writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL);
386}
387
388static void set_dumb_screen_dimensions(struct fb_info *info)
389{
390 struct pxa168fb_info *fbi = info->par;
391 struct fb_var_screeninfo *v = &info->var;
392 int x;
393 int y;
394
395 x = v->xres + v->right_margin + v->hsync_len + v->left_margin;
396 y = v->yres + v->lower_margin + v->vsync_len + v->upper_margin;
397
398 writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL);
399}
400
401static int pxa168fb_set_par(struct fb_info *info)
402{
403 struct pxa168fb_info *fbi = info->par;
404 struct fb_var_screeninfo *var = &info->var;
405 struct fb_videomode mode;
406 u32 x;
407 struct pxa168fb_mach_info *mi;
408
409 mi = fbi->dev->platform_data;
410
411 /*
412 * Set additional mode info.
413 */
414 if (fbi->pix_fmt == PIX_FMT_PSEUDOCOLOR)
415 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
416 else
417 info->fix.visual = FB_VISUAL_TRUECOLOR;
418 info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
419 info->fix.ypanstep = var->yres;
420
421 /*
422 * Disable panel output while we setup the display.
423 */
424 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL);
425 writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL);
426
427 /*
428 * Configure global panel parameters.
429 */
430 writel((var->yres << 16) | var->xres,
431 fbi->reg_base + LCD_SPU_V_H_ACTIVE);
432
433 /*
434 * convet var to video mode
435 */
436 fb_var_to_videomode(&mode, &info->var);
437
438 /* Calculate clock divisor. */
439 set_clock_divider(fbi, &mode);
440
441 /* Configure dma ctrl regs. */
442 set_dma_control0(fbi);
443 set_dma_control1(fbi, info->var.sync);
444
445 /*
446 * Configure graphics DMA parameters.
447 */
448 x = readl(fbi->reg_base + LCD_CFG_GRA_PITCH);
449 x = (x & ~0xFFFF) | ((var->xres_virtual * var->bits_per_pixel) >> 3);
450 writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH);
451 writel((var->yres << 16) | var->xres,
452 fbi->reg_base + LCD_SPU_GRA_HPXL_VLN);
453 writel((var->yres << 16) | var->xres,
454 fbi->reg_base + LCD_SPU_GZM_HPXL_VLN);
455
456 /*
457 * Configure dumb panel ctrl regs & timings.
458 */
459 set_dumb_panel_control(info);
460 set_dumb_screen_dimensions(info);
461
462 writel((var->left_margin << 16) | var->right_margin,
463 fbi->reg_base + LCD_SPU_H_PORCH);
464 writel((var->upper_margin << 16) | var->lower_margin,
465 fbi->reg_base + LCD_SPU_V_PORCH);
466
467 /*
468 * Re-enable panel output.
469 */
470 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL);
471 writel(x | 1, fbi->reg_base + LCD_SPU_DUMB_CTRL);
472
473 return 0;
474}
475
476static unsigned int chan_to_field(unsigned int chan, struct fb_bitfield *bf)
477{
478 return ((chan & 0xffff) >> (16 - bf->length)) << bf->offset;
479}
480
481static u32 to_rgb(u16 red, u16 green, u16 blue)
482{
483 red >>= 8;
484 green >>= 8;
485 blue >>= 8;
486
487 return (red << 16) | (green << 8) | blue;
488}
489
490static int
491pxa168fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
492 unsigned int blue, unsigned int trans, struct fb_info *info)
493{
494 struct pxa168fb_info *fbi = info->par;
495 u32 val;
496
497 if (info->var.grayscale)
498 red = green = blue = (19595 * red + 38470 * green +
499 7471 * blue) >> 16;
500
501 if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16) {
502 val = chan_to_field(red, &info->var.red);
503 val |= chan_to_field(green, &info->var.green);
504 val |= chan_to_field(blue , &info->var.blue);
505 fbi->pseudo_palette[regno] = val;
506 }
507
508 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
509 val = to_rgb(red, green, blue);
510 writel(val, fbi->reg_base + LCD_SPU_SRAM_WRDAT);
511 writel(0x8300 | regno, fbi->reg_base + LCD_SPU_SRAM_CTRL);
512 }
513
514 return 0;
515}
516
517static int pxa168fb_blank(int blank, struct fb_info *info)
518{
519 struct pxa168fb_info *fbi = info->par;
520
521 fbi->is_blanked = (blank == FB_BLANK_UNBLANK) ? 0 : 1;
522 set_dumb_panel_control(info);
523
524 return 0;
525}
526
527static int pxa168fb_pan_display(struct fb_var_screeninfo *var,
528 struct fb_info *info)
529{
530 set_graphics_start(info, var->xoffset, var->yoffset);
531
532 return 0;
533}
534
535static irqreturn_t pxa168fb_handle_irq(int irq, void *dev_id)
536{
537 struct pxa168fb_info *fbi = dev_id;
538 u32 isr = readl(fbi->reg_base + SPU_IRQ_ISR);
539
540 if ((isr & GRA_FRAME_IRQ0_ENA_MASK)) {
541
542 writel(isr & (~GRA_FRAME_IRQ0_ENA_MASK),
543 fbi->reg_base + SPU_IRQ_ISR);
544
545 return IRQ_HANDLED;
546 }
547 return IRQ_NONE;
548}
549
550static struct fb_ops pxa168fb_ops = {
551 .owner = THIS_MODULE,
552 .fb_check_var = pxa168fb_check_var,
553 .fb_set_par = pxa168fb_set_par,
554 .fb_setcolreg = pxa168fb_setcolreg,
555 .fb_blank = pxa168fb_blank,
556 .fb_pan_display = pxa168fb_pan_display,
557 .fb_fillrect = cfb_fillrect,
558 .fb_copyarea = cfb_copyarea,
559 .fb_imageblit = cfb_imageblit,
560};
561
562static int __init pxa168fb_init_mode(struct fb_info *info,
563 struct pxa168fb_mach_info *mi)
564{
565 struct pxa168fb_info *fbi = info->par;
566 struct fb_var_screeninfo *var = &info->var;
567 int ret = 0;
568 u32 total_w, total_h, refresh;
569 u64 div_result;
570 const struct fb_videomode *m;
571
572 /*
573 * Set default value
574 */
575 refresh = DEFAULT_REFRESH;
576
577 /* try to find best video mode. */
578 m = fb_find_best_mode(&info->var, &info->modelist);
579 if (m)
580 fb_videomode_to_var(&info->var, m);
581
582 /* Init settings. */
583 var->xres_virtual = var->xres;
584 var->yres_virtual = info->fix.smem_len /
585 (var->xres_virtual * (var->bits_per_pixel >> 3));
586 dev_dbg(fbi->dev, "pxa168fb: find best mode: res = %dx%d\n",
587 var->xres, var->yres);
588
589 /* correct pixclock. */
590 total_w = var->xres + var->left_margin + var->right_margin +
591 var->hsync_len;
592 total_h = var->yres + var->upper_margin + var->lower_margin +
593 var->vsync_len;
594
595 div_result = 1000000000000ll;
596 do_div(div_result, total_w * total_h * refresh);
597 var->pixclock = (u32)div_result;
598
599 return ret;
600}
601
602static int __init pxa168fb_probe(struct platform_device *pdev)
603{
604 struct pxa168fb_mach_info *mi;
605 struct fb_info *info = 0;
606 struct pxa168fb_info *fbi = 0;
607 struct resource *res;
608 struct clk *clk;
609 int irq, ret;
610
611 mi = pdev->dev.platform_data;
612 if (mi == NULL) {
613 dev_err(&pdev->dev, "no platform data defined\n");
614 return -EINVAL;
615 }
616
617 clk = clk_get(&pdev->dev, "LCDCLK");
618 if (IS_ERR(clk)) {
619 dev_err(&pdev->dev, "unable to get LCDCLK");
620 return PTR_ERR(clk);
621 }
622
623 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
624 if (res == NULL) {
625 dev_err(&pdev->dev, "no IO memory defined\n");
626 return -ENOENT;
627 }
628
629 irq = platform_get_irq(pdev, 0);
630 if (irq < 0) {
631 dev_err(&pdev->dev, "no IRQ defined\n");
632 return -ENOENT;
633 }
634
635 info = framebuffer_alloc(sizeof(struct pxa168fb_info), &pdev->dev);
636 if (info == NULL) {
637 clk_put(clk);
638 return -ENOMEM;
639 }
640
641 /* Initialize private data */
642 fbi = info->par;
643 fbi->info = info;
644 fbi->clk = clk;
645 fbi->dev = info->dev = &pdev->dev;
646 fbi->panel_rbswap = mi->panel_rbswap;
647 fbi->is_blanked = 0;
648 fbi->active = mi->active;
649
650 /*
651 * Initialise static fb parameters.
652 */
653 info->flags = FBINFO_DEFAULT | FBINFO_PARTIAL_PAN_OK |
654 FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
655 info->node = -1;
656 strlcpy(info->fix.id, mi->id, 16);
657 info->fix.type = FB_TYPE_PACKED_PIXELS;
658 info->fix.type_aux = 0;
659 info->fix.xpanstep = 0;
660 info->fix.ypanstep = 0;
661 info->fix.ywrapstep = 0;
662 info->fix.mmio_start = res->start;
663 info->fix.mmio_len = res->end - res->start + 1;
664 info->fix.accel = FB_ACCEL_NONE;
665 info->fbops = &pxa168fb_ops;
666 info->pseudo_palette = fbi->pseudo_palette;
667
668 /*
669 * Map LCD controller registers.
670 */
671 fbi->reg_base = ioremap_nocache(res->start, res->end - res->start);
672 if (fbi->reg_base == NULL) {
673 ret = -ENOMEM;
674 goto failed;
675 }
676
677 /*
678 * Allocate framebuffer memory.
679 */
680 info->fix.smem_len = PAGE_ALIGN(DEFAULT_FB_SIZE);
681
682 info->screen_base = dma_alloc_writecombine(fbi->dev, info->fix.smem_len,
683 &fbi->fb_start_dma, GFP_KERNEL);
684 if (info->screen_base == NULL) {
685 ret = -ENOMEM;
686 goto failed;
687 }
688
689 info->fix.smem_start = (unsigned long)fbi->fb_start_dma;
690
691 /*
692 * Set video mode according to platform data.
693 */
694 set_mode(fbi, &info->var, mi->modes, mi->pix_fmt, 1);
695
696 fb_videomode_to_modelist(mi->modes, mi->num_modes, &info->modelist);
697
698 /*
699 * init video mode data.
700 */
701 pxa168fb_init_mode(info, mi);
702
703 ret = pxa168fb_check_var(&info->var, info);
704 if (ret)
705 goto failed_free_fbmem;
706
707 /*
708 * Fill in sane defaults.
709 */
710 ret = pxa168fb_check_var(&info->var, info);
711 if (ret)
712 goto failed;
713
714 /*
715 * enable controller clock
716 */
717 clk_enable(fbi->clk);
718
719 pxa168fb_set_par(info);
720
721 /*
722 * Configure default register values.
723 */
724 writel(0, fbi->reg_base + LCD_SPU_BLANKCOLOR);
725 writel(mi->io_pin_allocation_mode, fbi->reg_base + SPU_IOPAD_CONTROL);
726 writel(0, fbi->reg_base + LCD_CFG_GRA_START_ADDR1);
727 writel(0, fbi->reg_base + LCD_SPU_GRA_OVSA_HPXL_VLN);
728 writel(0, fbi->reg_base + LCD_SPU_SRAM_PARA0);
729 writel(CFG_CSB_256x32(0x1)|CFG_CSB_256x24(0x1)|CFG_CSB_256x8(0x1),
730 fbi->reg_base + LCD_SPU_SRAM_PARA1);
731
732 /*
733 * Allocate color map.
734 */
735 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
736 ret = -ENOMEM;
737 goto failed_free_clk;
738 }
739
740 /*
741 * Register irq handler.
742 */
743 ret = request_irq(irq, pxa168fb_handle_irq, IRQF_SHARED,
744 info->fix.id, fbi);
745 if (ret < 0) {
746 dev_err(&pdev->dev, "unable to request IRQ\n");
747 ret = -ENXIO;
748 goto failed_free_cmap;
749 }
750
751 /*
752 * Enable GFX interrupt
753 */
754 writel(GRA_FRAME_IRQ0_ENA(0x1), fbi->reg_base + SPU_IRQ_ENA);
755
756 /*
757 * Register framebuffer.
758 */
759 ret = register_framebuffer(info);
760 if (ret < 0) {
761 dev_err(&pdev->dev, "Failed to register pxa168-fb: %d\n", ret);
762 ret = -ENXIO;
763 goto failed_free_irq;
764 }
765
766 platform_set_drvdata(pdev, fbi);
767 return 0;
768
769failed_free_irq:
770 free_irq(irq, fbi);
771failed_free_cmap:
772 fb_dealloc_cmap(&info->cmap);
773failed_free_clk:
774 clk_disable(fbi->clk);
775failed_free_fbmem:
776 dma_free_coherent(fbi->dev, info->fix.smem_len,
777 info->screen_base, fbi->fb_start_dma);
778failed:
779 kfree(info);
780 clk_put(clk);
781
782 dev_err(&pdev->dev, "frame buffer device init failed with %d\n", ret);
783 return ret;
784}
785
786static struct platform_driver pxa168fb_driver = {
787 .driver = {
788 .name = "pxa168-fb",
789 .owner = THIS_MODULE,
790 },
791 .probe = pxa168fb_probe,
792};
793
794static int __devinit pxa168fb_init(void)
795{
796 return platform_driver_register(&pxa168fb_driver);
797}
798module_init(pxa168fb_init);
799
800MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com> "
801 "Green Wan <gwan@marvell.com>");
802MODULE_DESCRIPTION("Framebuffer driver for PXA168/910");
803MODULE_LICENSE("GPL");
diff --git a/drivers/video/pxa168fb.h b/drivers/video/pxa168fb.h
new file mode 100644
index 000000000000..eee09279c524
--- /dev/null
+++ b/drivers/video/pxa168fb.h
@@ -0,0 +1,558 @@
1#ifndef __PXA168FB_H__
2#define __PXA168FB_H__
3
4/* ------------< LCD register >------------ */
5/* Video Frame 0&1 start address registers */
6#define LCD_SPU_DMA_START_ADDR_Y0 0x00C0
7#define LCD_SPU_DMA_START_ADDR_U0 0x00C4
8#define LCD_SPU_DMA_START_ADDR_V0 0x00C8
9#define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */
10#define LCD_SPU_DMA_START_ADDR_Y1 0x00D0
11#define LCD_SPU_DMA_START_ADDR_U1 0x00D4
12#define LCD_SPU_DMA_START_ADDR_V1 0x00D8
13#define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */
14
15/* YC & UV Pitch */
16#define LCD_SPU_DMA_PITCH_YC 0x00E0
17#define SPU_DMA_PITCH_C(c) ((c) << 16)
18#define SPU_DMA_PITCH_Y(y) (y)
19#define LCD_SPU_DMA_PITCH_UV 0x00E4
20#define SPU_DMA_PITCH_V(v) ((v) << 16)
21#define SPU_DMA_PITCH_U(u) (u)
22
23/* Video Starting Point on Screen Register */
24#define LCD_SPUT_DMA_OVSA_HPXL_VLN 0x00E8
25#define CFG_DMA_OVSA_VLN(y) ((y) << 16) /* 0~0xfff */
26#define CFG_DMA_OVSA_HPXL(x) (x) /* 0~0xfff */
27
28/* Video Size Register */
29#define LCD_SPU_DMA_HPXL_VLN 0x00EC
30#define CFG_DMA_VLN(y) ((y) << 16)
31#define CFG_DMA_HPXL(x) (x)
32
33/* Video Size After zooming Register */
34#define LCD_SPU_DZM_HPXL_VLN 0x00F0
35#define CFG_DZM_VLN(y) ((y) << 16)
36#define CFG_DZM_HPXL(x) (x)
37
38/* Graphic Frame 0&1 Starting Address Register */
39#define LCD_CFG_GRA_START_ADDR0 0x00F4
40#define LCD_CFG_GRA_START_ADDR1 0x00F8
41
42/* Graphic Frame Pitch */
43#define LCD_CFG_GRA_PITCH 0x00FC
44
45/* Graphic Starting Point on Screen Register */
46#define LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100
47#define CFG_GRA_OVSA_VLN(y) ((y) << 16)
48#define CFG_GRA_OVSA_HPXL(x) (x)
49
50/* Graphic Size Register */
51#define LCD_SPU_GRA_HPXL_VLN 0x0104
52#define CFG_GRA_VLN(y) ((y) << 16)
53#define CFG_GRA_HPXL(x) (x)
54
55/* Graphic Size after Zooming Register */
56#define LCD_SPU_GZM_HPXL_VLN 0x0108
57#define CFG_GZM_VLN(y) ((y) << 16)
58#define CFG_GZM_HPXL(x) (x)
59
60/* HW Cursor Starting Point on Screen Register */
61#define LCD_SPU_HWC_OVSA_HPXL_VLN 0x010C
62#define CFG_HWC_OVSA_VLN(y) ((y) << 16)
63#define CFG_HWC_OVSA_HPXL(x) (x)
64
65/* HW Cursor Size */
66#define LCD_SPU_HWC_HPXL_VLN 0x0110
67#define CFG_HWC_VLN(y) ((y) << 16)
68#define CFG_HWC_HPXL(x) (x)
69
70/* Total Screen Size Register */
71#define LCD_SPUT_V_H_TOTAL 0x0114
72#define CFG_V_TOTAL(y) ((y) << 16)
73#define CFG_H_TOTAL(x) (x)
74
75/* Total Screen Active Size Register */
76#define LCD_SPU_V_H_ACTIVE 0x0118
77#define CFG_V_ACTIVE(y) ((y) << 16)
78#define CFG_H_ACTIVE(x) (x)
79
80/* Screen H&V Porch Register */
81#define LCD_SPU_H_PORCH 0x011C
82#define CFG_H_BACK_PORCH(b) ((b) << 16)
83#define CFG_H_FRONT_PORCH(f) (f)
84#define LCD_SPU_V_PORCH 0x0120
85#define CFG_V_BACK_PORCH(b) ((b) << 16)
86#define CFG_V_FRONT_PORCH(f) (f)
87
88/* Screen Blank Color Register */
89#define LCD_SPU_BLANKCOLOR 0x0124
90#define CFG_BLANKCOLOR_MASK 0x00FFFFFF
91#define CFG_BLANKCOLOR_R_MASK 0x000000FF
92#define CFG_BLANKCOLOR_G_MASK 0x0000FF00
93#define CFG_BLANKCOLOR_B_MASK 0x00FF0000
94
95/* HW Cursor Color 1&2 Register */
96#define LCD_SPU_ALPHA_COLOR1 0x0128
97#define CFG_HWC_COLOR1 0x00FFFFFF
98#define CFG_HWC_COLOR1_R(red) ((red) << 16)
99#define CFG_HWC_COLOR1_G(green) ((green) << 8)
100#define CFG_HWC_COLOR1_B(blue) (blue)
101#define CFG_HWC_COLOR1_R_MASK 0x000000FF
102#define CFG_HWC_COLOR1_G_MASK 0x0000FF00
103#define CFG_HWC_COLOR1_B_MASK 0x00FF0000
104#define LCD_SPU_ALPHA_COLOR2 0x012C
105#define CFG_HWC_COLOR2 0x00FFFFFF
106#define CFG_HWC_COLOR2_R_MASK 0x000000FF
107#define CFG_HWC_COLOR2_G_MASK 0x0000FF00
108#define CFG_HWC_COLOR2_B_MASK 0x00FF0000
109
110/* Video YUV Color Key Control */
111#define LCD_SPU_COLORKEY_Y 0x0130
112#define CFG_CKEY_Y2(y2) ((y2) << 24)
113#define CFG_CKEY_Y2_MASK 0xFF000000
114#define CFG_CKEY_Y1(y1) ((y1) << 16)
115#define CFG_CKEY_Y1_MASK 0x00FF0000
116#define CFG_CKEY_Y(y) ((y) << 8)
117#define CFG_CKEY_Y_MASK 0x0000FF00
118#define CFG_ALPHA_Y(y) (y)
119#define CFG_ALPHA_Y_MASK 0x000000FF
120#define LCD_SPU_COLORKEY_U 0x0134
121#define CFG_CKEY_U2(u2) ((u2) << 24)
122#define CFG_CKEY_U2_MASK 0xFF000000
123#define CFG_CKEY_U1(u1) ((u1) << 16)
124#define CFG_CKEY_U1_MASK 0x00FF0000
125#define CFG_CKEY_U(u) ((u) << 8)
126#define CFG_CKEY_U_MASK 0x0000FF00
127#define CFG_ALPHA_U(u) (u)
128#define CFG_ALPHA_U_MASK 0x000000FF
129#define LCD_SPU_COLORKEY_V 0x0138
130#define CFG_CKEY_V2(v2) ((v2) << 24)
131#define CFG_CKEY_V2_MASK 0xFF000000
132#define CFG_CKEY_V1(v1) ((v1) << 16)
133#define CFG_CKEY_V1_MASK 0x00FF0000
134#define CFG_CKEY_V(v) ((v) << 8)
135#define CFG_CKEY_V_MASK 0x0000FF00
136#define CFG_ALPHA_V(v) (v)
137#define CFG_ALPHA_V_MASK 0x000000FF
138
139/* SPI Read Data Register */
140#define LCD_SPU_SPI_RXDATA 0x0140
141
142/* Smart Panel Read Data Register */
143#define LCD_SPU_ISA_RSDATA 0x0144
144#define ISA_RXDATA_16BIT_1_DATA_MASK 0x000000FF
145#define ISA_RXDATA_16BIT_2_DATA_MASK 0x0000FF00
146#define ISA_RXDATA_16BIT_3_DATA_MASK 0x00FF0000
147#define ISA_RXDATA_16BIT_4_DATA_MASK 0xFF000000
148#define ISA_RXDATA_32BIT_1_DATA_MASK 0x00FFFFFF
149
150/* HWC SRAM Read Data Register */
151#define LCD_SPU_HWC_RDDAT 0x0158
152
153/* Gamma Table SRAM Read Data Register */
154#define LCD_SPU_GAMMA_RDDAT 0x015c
155#define CFG_GAMMA_RDDAT_MASK 0x000000FF
156
157/* Palette Table SRAM Read Data Register */
158#define LCD_SPU_PALETTE_RDDAT 0x0160
159#define CFG_PALETTE_RDDAT_MASK 0x00FFFFFF
160
161/* I/O Pads Input Read Only Register */
162#define LCD_SPU_IOPAD_IN 0x0178
163#define CFG_IOPAD_IN_MASK 0x0FFFFFFF
164
165/* Reserved Read Only Registers */
166#define LCD_CFG_RDREG5F 0x017C
167#define IRE_FRAME_CNT_MASK 0x000000C0
168#define IPE_FRAME_CNT_MASK 0x00000030
169#define GRA_FRAME_CNT_MASK 0x0000000C /* Graphic */
170#define DMA_FRAME_CNT_MASK 0x00000003 /* Video */
171
172/* SPI Control Register. */
173#define LCD_SPU_SPI_CTRL 0x0180
174#define CFG_SCLKCNT(div) ((div) << 24) /* 0xFF~0x2 */
175#define CFG_SCLKCNT_MASK 0xFF000000
176#define CFG_RXBITS(rx) ((rx) << 16) /* 0x1F~0x1 */
177#define CFG_RXBITS_MASK 0x00FF0000
178#define CFG_TXBITS(tx) ((tx) << 8) /* 0x1F~0x1 */
179#define CFG_TXBITS_MASK 0x0000FF00
180#define CFG_CLKINV(clk) ((clk) << 7)
181#define CFG_CLKINV_MASK 0x00000080
182#define CFG_KEEPXFER(transfer) ((transfer) << 6)
183#define CFG_KEEPXFER_MASK 0x00000040
184#define CFG_RXBITSTO0(rx) ((rx) << 5)
185#define CFG_RXBITSTO0_MASK 0x00000020
186#define CFG_TXBITSTO0(tx) ((tx) << 4)
187#define CFG_TXBITSTO0_MASK 0x00000010
188#define CFG_SPI_ENA(spi) ((spi) << 3)
189#define CFG_SPI_ENA_MASK 0x00000008
190#define CFG_SPI_SEL(spi) ((spi) << 2)
191#define CFG_SPI_SEL_MASK 0x00000004
192#define CFG_SPI_3W4WB(wire) ((wire) << 1)
193#define CFG_SPI_3W4WB_MASK 0x00000002
194#define CFG_SPI_START(start) (start)
195#define CFG_SPI_START_MASK 0x00000001
196
197/* SPI Tx Data Register */
198#define LCD_SPU_SPI_TXDATA 0x0184
199
200/*
201 1. Smart Pannel 8-bit Bus Control Register.
202 2. AHB Slave Path Data Port Register
203*/
204#define LCD_SPU_SMPN_CTRL 0x0188
205
206/* DMA Control 0 Register */
207#define LCD_SPU_DMA_CTRL0 0x0190
208#define CFG_NOBLENDING(nb) ((nb) << 31)
209#define CFG_NOBLENDING_MASK 0x80000000
210#define CFG_GAMMA_ENA(gn) ((gn) << 30)
211#define CFG_GAMMA_ENA_MASK 0x40000000
212#define CFG_CBSH_ENA(cn) ((cn) << 29)
213#define CFG_CBSH_ENA_MASK 0x20000000
214#define CFG_PALETTE_ENA(pn) ((pn) << 28)
215#define CFG_PALETTE_ENA_MASK 0x10000000
216#define CFG_ARBFAST_ENA(an) ((an) << 27)
217#define CFG_ARBFAST_ENA_MASK 0x08000000
218#define CFG_HWC_1BITMOD(mode) ((mode) << 26)
219#define CFG_HWC_1BITMOD_MASK 0x04000000
220#define CFG_HWC_1BITENA(mn) ((mn) << 25)
221#define CFG_HWC_1BITENA_MASK 0x02000000
222#define CFG_HWC_ENA(cn) ((cn) << 24)
223#define CFG_HWC_ENA_MASK 0x01000000
224#define CFG_DMAFORMAT(dmaformat) ((dmaformat) << 20)
225#define CFG_DMAFORMAT_MASK 0x00F00000
226#define CFG_GRAFORMAT(graformat) ((graformat) << 16)
227#define CFG_GRAFORMAT_MASK 0x000F0000
228/* for graphic part */
229#define CFG_GRA_FTOGGLE(toggle) ((toggle) << 15)
230#define CFG_GRA_FTOGGLE_MASK 0x00008000
231#define CFG_GRA_HSMOOTH(smooth) ((smooth) << 14)
232#define CFG_GRA_HSMOOTH_MASK 0x00004000
233#define CFG_GRA_TSTMODE(test) ((test) << 13)
234#define CFG_GRA_TSTMODE_MASK 0x00002000
235#define CFG_GRA_SWAPRB(swap) ((swap) << 12)
236#define CFG_GRA_SWAPRB_MASK 0x00001000
237#define CFG_GRA_SWAPUV(swap) ((swap) << 11)
238#define CFG_GRA_SWAPUV_MASK 0x00000800
239#define CFG_GRA_SWAPYU(swap) ((swap) << 10)
240#define CFG_GRA_SWAPYU_MASK 0x00000400
241#define CFG_YUV2RGB_GRA(cvrt) ((cvrt) << 9)
242#define CFG_YUV2RGB_GRA_MASK 0x00000200
243#define CFG_GRA_ENA(gra) ((gra) << 8)
244#define CFG_GRA_ENA_MASK 0x00000100
245/* for video part */
246#define CFG_DMA_FTOGGLE(toggle) ((toggle) << 7)
247#define CFG_DMA_FTOGGLE_MASK 0x00000080
248#define CFG_DMA_HSMOOTH(smooth) ((smooth) << 6)
249#define CFG_DMA_HSMOOTH_MASK 0x00000040
250#define CFG_DMA_TSTMODE(test) ((test) << 5)
251#define CFG_DMA_TSTMODE_MASK 0x00000020
252#define CFG_DMA_SWAPRB(swap) ((swap) << 4)
253#define CFG_DMA_SWAPRB_MASK 0x00000010
254#define CFG_DMA_SWAPUV(swap) ((swap) << 3)
255#define CFG_DMA_SWAPUV_MASK 0x00000008
256#define CFG_DMA_SWAPYU(swap) ((swap) << 2)
257#define CFG_DMA_SWAPYU_MASK 0x00000004
258#define CFG_DMA_SWAP_MASK 0x0000001C
259#define CFG_YUV2RGB_DMA(cvrt) ((cvrt) << 1)
260#define CFG_YUV2RGB_DMA_MASK 0x00000002
261#define CFG_DMA_ENA(video) (video)
262#define CFG_DMA_ENA_MASK 0x00000001
263
264/* DMA Control 1 Register */
265#define LCD_SPU_DMA_CTRL1 0x0194
266#define CFG_FRAME_TRIG(trig) ((trig) << 31)
267#define CFG_FRAME_TRIG_MASK 0x80000000
268#define CFG_VSYNC_TRIG(trig) ((trig) << 28)
269#define CFG_VSYNC_TRIG_MASK 0x70000000
270#define CFG_VSYNC_INV(inv) ((inv) << 27)
271#define CFG_VSYNC_INV_MASK 0x08000000
272#define CFG_COLOR_KEY_MODE(cmode) ((cmode) << 24)
273#define CFG_COLOR_KEY_MASK 0x07000000
274#define CFG_CARRY(carry) ((carry) << 23)
275#define CFG_CARRY_MASK 0x00800000
276#define CFG_LNBUF_ENA(lnbuf) ((lnbuf) << 22)
277#define CFG_LNBUF_ENA_MASK 0x00400000
278#define CFG_GATED_ENA(gated) ((gated) << 21)
279#define CFG_GATED_ENA_MASK 0x00200000
280#define CFG_PWRDN_ENA(power) ((power) << 20)
281#define CFG_PWRDN_ENA_MASK 0x00100000
282#define CFG_DSCALE(dscale) ((dscale) << 18)
283#define CFG_DSCALE_MASK 0x000C0000
284#define CFG_ALPHA_MODE(amode) ((amode) << 16)
285#define CFG_ALPHA_MODE_MASK 0x00030000
286#define CFG_ALPHA(alpha) ((alpha) << 8)
287#define CFG_ALPHA_MASK 0x0000FF00
288#define CFG_PXLCMD(pxlcmd) (pxlcmd)
289#define CFG_PXLCMD_MASK 0x000000FF
290
291/* SRAM Control Register */
292#define LCD_SPU_SRAM_CTRL 0x0198
293#define CFG_SRAM_INIT_WR_RD(mode) ((mode) << 14)
294#define CFG_SRAM_INIT_WR_RD_MASK 0x0000C000
295#define CFG_SRAM_ADDR_LCDID(id) ((id) << 8)
296#define CFG_SRAM_ADDR_LCDID_MASK 0x00000F00
297#define CFG_SRAM_ADDR(addr) (addr)
298#define CFG_SRAM_ADDR_MASK 0x000000FF
299
300/* SRAM Write Data Register */
301#define LCD_SPU_SRAM_WRDAT 0x019C
302
303/* SRAM RTC/WTC Control Register */
304#define LCD_SPU_SRAM_PARA0 0x01A0
305
306/* SRAM Power Down Control Register */
307#define LCD_SPU_SRAM_PARA1 0x01A4
308#define CFG_CSB_256x32(hwc) ((hwc) << 15) /* HWC */
309#define CFG_CSB_256x32_MASK 0x00008000
310#define CFG_CSB_256x24(palette) ((palette) << 14) /* Palette */
311#define CFG_CSB_256x24_MASK 0x00004000
312#define CFG_CSB_256x8(gamma) ((gamma) << 13) /* Gamma */
313#define CFG_CSB_256x8_MASK 0x00002000
314#define CFG_PDWN256x32(pdwn) ((pdwn) << 7) /* HWC */
315#define CFG_PDWN256x32_MASK 0x00000080
316#define CFG_PDWN256x24(pdwn) ((pdwn) << 6) /* Palette */
317#define CFG_PDWN256x24_MASK 0x00000040
318#define CFG_PDWN256x8(pdwn) ((pdwn) << 5) /* Gamma */
319#define CFG_PDWN256x8_MASK 0x00000020
320#define CFG_PDWN32x32(pdwn) ((pdwn) << 3)
321#define CFG_PDWN32x32_MASK 0x00000008
322#define CFG_PDWN16x66(pdwn) ((pdwn) << 2)
323#define CFG_PDWN16x66_MASK 0x00000004
324#define CFG_PDWN32x66(pdwn) ((pdwn) << 1)
325#define CFG_PDWN32x66_MASK 0x00000002
326#define CFG_PDWN64x66(pdwn) (pdwn)
327#define CFG_PDWN64x66_MASK 0x00000001
328
329/* Smart or Dumb Panel Clock Divider */
330#define LCD_CFG_SCLK_DIV 0x01A8
331#define SCLK_SOURCE_SELECT(src) ((src) << 31)
332#define SCLK_SOURCE_SELECT_MASK 0x80000000
333#define CLK_FRACDIV(frac) ((frac) << 16)
334#define CLK_FRACDIV_MASK 0x0FFF0000
335#define CLK_INT_DIV(div) (div)
336#define CLK_INT_DIV_MASK 0x0000FFFF
337
338/* Video Contrast Register */
339#define LCD_SPU_CONTRAST 0x01AC
340#define CFG_BRIGHTNESS(bright) ((bright) << 16)
341#define CFG_BRIGHTNESS_MASK 0xFFFF0000
342#define CFG_CONTRAST(contrast) (contrast)
343#define CFG_CONTRAST_MASK 0x0000FFFF
344
345/* Video Saturation Register */
346#define LCD_SPU_SATURATION 0x01B0
347#define CFG_C_MULTS(mult) ((mult) << 16)
348#define CFG_C_MULTS_MASK 0xFFFF0000
349#define CFG_SATURATION(sat) (sat)
350#define CFG_SATURATION_MASK 0x0000FFFF
351
352/* Video Hue Adjust Register */
353#define LCD_SPU_CBSH_HUE 0x01B4
354#define CFG_SIN0(sin0) ((sin0) << 16)
355#define CFG_SIN0_MASK 0xFFFF0000
356#define CFG_COS0(con0) (con0)
357#define CFG_COS0_MASK 0x0000FFFF
358
359/* Dump LCD Panel Control Register */
360#define LCD_SPU_DUMB_CTRL 0x01B8
361#define CFG_DUMBMODE(mode) ((mode) << 28)
362#define CFG_DUMBMODE_MASK 0xF0000000
363#define CFG_LCDGPIO_O(data) ((data) << 20)
364#define CFG_LCDGPIO_O_MASK 0x0FF00000
365#define CFG_LCDGPIO_ENA(gpio) ((gpio) << 12)
366#define CFG_LCDGPIO_ENA_MASK 0x000FF000
367#define CFG_BIAS_OUT(bias) ((bias) << 8)
368#define CFG_BIAS_OUT_MASK 0x00000100
369#define CFG_REVERSE_RGB(rRGB) ((rRGB) << 7)
370#define CFG_REVERSE_RGB_MASK 0x00000080
371#define CFG_INV_COMPBLANK(blank) ((blank) << 6)
372#define CFG_INV_COMPBLANK_MASK 0x00000040
373#define CFG_INV_COMPSYNC(sync) ((sync) << 5)
374#define CFG_INV_COMPSYNC_MASK 0x00000020
375#define CFG_INV_HENA(hena) ((hena) << 4)
376#define CFG_INV_HENA_MASK 0x00000010
377#define CFG_INV_VSYNC(vsync) ((vsync) << 3)
378#define CFG_INV_VSYNC_MASK 0x00000008
379#define CFG_INV_HSYNC(hsync) ((hsync) << 2)
380#define CFG_INV_HSYNC_MASK 0x00000004
381#define CFG_INV_PCLK(pclk) ((pclk) << 1)
382#define CFG_INV_PCLK_MASK 0x00000002
383#define CFG_DUMB_ENA(dumb) (dumb)
384#define CFG_DUMB_ENA_MASK 0x00000001
385
386/* LCD I/O Pads Control Register */
387#define SPU_IOPAD_CONTROL 0x01BC
388#define CFG_GRA_VM_ENA(vm) ((vm) << 15) /* gfx */
389#define CFG_GRA_VM_ENA_MASK 0x00008000
390#define CFG_DMA_VM_ENA(vm) ((vm) << 13) /* video */
391#define CFG_DMA_VM_ENA_MASK 0x00002000
392#define CFG_CMD_VM_ENA(vm) ((vm) << 13)
393#define CFG_CMD_VM_ENA_MASK 0x00000800
394#define CFG_CSC(csc) ((csc) << 8) /* csc */
395#define CFG_CSC_MASK 0x00000300
396#define CFG_AXICTRL(axi) ((axi) << 4)
397#define CFG_AXICTRL_MASK 0x000000F0
398#define CFG_IOPADMODE(iopad) (iopad)
399#define CFG_IOPADMODE_MASK 0x0000000F
400
401/* LCD Interrupt Control Register */
402#define SPU_IRQ_ENA 0x01C0
403#define DMA_FRAME_IRQ0_ENA(irq) ((irq) << 31)
404#define DMA_FRAME_IRQ0_ENA_MASK 0x80000000
405#define DMA_FRAME_IRQ1_ENA(irq) ((irq) << 30)
406#define DMA_FRAME_IRQ1_ENA_MASK 0x40000000
407#define DMA_FF_UNDERFLOW_ENA(ff) ((ff) << 29)
408#define DMA_FF_UNDERFLOW_ENA_MASK 0x20000000
409#define GRA_FRAME_IRQ0_ENA(irq) ((irq) << 27)
410#define GRA_FRAME_IRQ0_ENA_MASK 0x08000000
411#define GRA_FRAME_IRQ1_ENA(irq) ((irq) << 26)
412#define GRA_FRAME_IRQ1_ENA_MASK 0x04000000
413#define GRA_FF_UNDERFLOW_ENA(ff) ((ff) << 25)
414#define GRA_FF_UNDERFLOW_ENA_MASK 0x02000000
415#define VSYNC_IRQ_ENA(vsync_irq) ((vsync_irq) << 23)
416#define VSYNC_IRQ_ENA_MASK 0x00800000
417#define DUMB_FRAMEDONE_ENA(fdone) ((fdone) << 22)
418#define DUMB_FRAMEDONE_ENA_MASK 0x00400000
419#define TWC_FRAMEDONE_ENA(fdone) ((fdone) << 21)
420#define TWC_FRAMEDONE_ENA_MASK 0x00200000
421#define HWC_FRAMEDONE_ENA(fdone) ((fdone) << 20)
422#define HWC_FRAMEDONE_ENA_MASK 0x00100000
423#define SLV_IRQ_ENA(irq) ((irq) << 19)
424#define SLV_IRQ_ENA_MASK 0x00080000
425#define SPI_IRQ_ENA(irq) ((irq) << 18)
426#define SPI_IRQ_ENA_MASK 0x00040000
427#define PWRDN_IRQ_ENA(irq) ((irq) << 17)
428#define PWRDN_IRQ_ENA_MASK 0x00020000
429#define ERR_IRQ_ENA(irq) ((irq) << 16)
430#define ERR_IRQ_ENA_MASK 0x00010000
431#define CLEAN_SPU_IRQ_ISR(irq) (irq)
432#define CLEAN_SPU_IRQ_ISR_MASK 0x0000FFFF
433
434/* LCD Interrupt Status Register */
435#define SPU_IRQ_ISR 0x01C4
436#define DMA_FRAME_IRQ0(irq) ((irq) << 31)
437#define DMA_FRAME_IRQ0_MASK 0x80000000
438#define DMA_FRAME_IRQ1(irq) ((irq) << 30)
439#define DMA_FRAME_IRQ1_MASK 0x40000000
440#define DMA_FF_UNDERFLOW(ff) ((ff) << 29)
441#define DMA_FF_UNDERFLOW_MASK 0x20000000
442#define GRA_FRAME_IRQ0(irq) ((irq) << 27)
443#define GRA_FRAME_IRQ0_MASK 0x08000000
444#define GRA_FRAME_IRQ1(irq) ((irq) << 26)
445#define GRA_FRAME_IRQ1_MASK 0x04000000
446#define GRA_FF_UNDERFLOW(ff) ((ff) << 25)
447#define GRA_FF_UNDERFLOW_MASK 0x02000000
448#define VSYNC_IRQ(vsync_irq) ((vsync_irq) << 23)
449#define VSYNC_IRQ_MASK 0x00800000
450#define DUMB_FRAMEDONE(fdone) ((fdone) << 22)
451#define DUMB_FRAMEDONE_MASK 0x00400000
452#define TWC_FRAMEDONE(fdone) ((fdone) << 21)
453#define TWC_FRAMEDONE_MASK 0x00200000
454#define HWC_FRAMEDONE(fdone) ((fdone) << 20)
455#define HWC_FRAMEDONE_MASK 0x00100000
456#define SLV_IRQ(irq) ((irq) << 19)
457#define SLV_IRQ_MASK 0x00080000
458#define SPI_IRQ(irq) ((irq) << 18)
459#define SPI_IRQ_MASK 0x00040000
460#define PWRDN_IRQ(irq) ((irq) << 17)
461#define PWRDN_IRQ_MASK 0x00020000
462#define ERR_IRQ(irq) ((irq) << 16)
463#define ERR_IRQ_MASK 0x00010000
464/* read-only */
465#define DMA_FRAME_IRQ0_LEVEL_MASK 0x00008000
466#define DMA_FRAME_IRQ1_LEVEL_MASK 0x00004000
467#define DMA_FRAME_CNT_ISR_MASK 0x00003000
468#define GRA_FRAME_IRQ0_LEVEL_MASK 0x00000800
469#define GRA_FRAME_IRQ1_LEVEL_MASK 0x00000400
470#define GRA_FRAME_CNT_ISR_MASK 0x00000300
471#define VSYNC_IRQ_LEVEL_MASK 0x00000080
472#define DUMB_FRAMEDONE_LEVEL_MASK 0x00000040
473#define TWC_FRAMEDONE_LEVEL_MASK 0x00000020
474#define HWC_FRAMEDONE_LEVEL_MASK 0x00000010
475#define SLV_FF_EMPTY_MASK 0x00000008
476#define DMA_FF_ALLEMPTY_MASK 0x00000004
477#define GRA_FF_ALLEMPTY_MASK 0x00000002
478#define PWRDN_IRQ_LEVEL_MASK 0x00000001
479
480
481/*
482 * defined Video Memory Color format for DMA control 0 register
483 * DMA0 bit[23:20]
484 */
485#define VMODE_RGB565 0x0
486#define VMODE_RGB1555 0x1
487#define VMODE_RGB888PACKED 0x2
488#define VMODE_RGB888UNPACKED 0x3
489#define VMODE_RGBA888 0x4
490#define VMODE_YUV422PACKED 0x5
491#define VMODE_YUV422PLANAR 0x6
492#define VMODE_YUV420PLANAR 0x7
493#define VMODE_SMPNCMD 0x8
494#define VMODE_PALETTE4BIT 0x9
495#define VMODE_PALETTE8BIT 0xa
496#define VMODE_RESERVED 0xb
497
498/*
499 * defined Graphic Memory Color format for DMA control 0 register
500 * DMA0 bit[19:16]
501 */
502#define GMODE_RGB565 0x0
503#define GMODE_RGB1555 0x1
504#define GMODE_RGB888PACKED 0x2
505#define GMODE_RGB888UNPACKED 0x3
506#define GMODE_RGBA888 0x4
507#define GMODE_YUV422PACKED 0x5
508#define GMODE_YUV422PLANAR 0x6
509#define GMODE_YUV420PLANAR 0x7
510#define GMODE_SMPNCMD 0x8
511#define GMODE_PALETTE4BIT 0x9
512#define GMODE_PALETTE8BIT 0xa
513#define GMODE_RESERVED 0xb
514
515/*
516 * define for DMA control 1 register
517 */
518#define DMA1_FRAME_TRIG 31 /* bit location */
519#define DMA1_VSYNC_MODE 28
520#define DMA1_VSYNC_INV 27
521#define DMA1_CKEY 24
522#define DMA1_CARRY 23
523#define DMA1_LNBUF_ENA 22
524#define DMA1_GATED_ENA 21
525#define DMA1_PWRDN_ENA 20
526#define DMA1_DSCALE 18
527#define DMA1_ALPHA_MODE 16
528#define DMA1_ALPHA 08
529#define DMA1_PXLCMD 00
530
531/*
532 * defined for Configure Dumb Mode
533 * DUMB LCD Panel bit[31:28]
534 */
535#define DUMB16_RGB565_0 0x0
536#define DUMB16_RGB565_1 0x1
537#define DUMB18_RGB666_0 0x2
538#define DUMB18_RGB666_1 0x3
539#define DUMB12_RGB444_0 0x4
540#define DUMB12_RGB444_1 0x5
541#define DUMB24_RGB888_0 0x6
542#define DUMB_BLANK 0x7
543
544/*
545 * defined for Configure I/O Pin Allocation Mode
546 * LCD LCD I/O Pads control register bit[3:0]
547 */
548#define IOPAD_DUMB24 0x0
549#define IOPAD_DUMB18SPI 0x1
550#define IOPAD_DUMB18GPIO 0x2
551#define IOPAD_DUMB16SPI 0x3
552#define IOPAD_DUMB16GPIO 0x4
553#define IOPAD_DUMB12 0x5
554#define IOPAD_SMART18SPI 0x6
555#define IOPAD_SMART16SPI 0x7
556#define IOPAD_SMART8BOTH 0x8
557
558#endif /* __PXA168FB_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 14:49:02 -0500