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authorTomi Valkeinen <tomi.valkeinen@ti.com>2012-08-21 02:09:47 -0400
committerFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2012-08-23 08:37:21 -0400
commit35d678664873041026171b4b5e1cec49299e33a0 (patch)
tree0e4e82ed0be75f870e0c937a68f2e416e249b7c4 /drivers/video
parent25682362564fa0c950d9afe798def2ec9c3676a2 (diff)
OMAPDSS: Fix SDI PLL locking
Commit f476ae9dab3234532d41d36beb4ba7be838fa786 (OMAPDSS: APPLY: Remove DISPC writes to manager's lcd parameters in interface) broke the SDI output, as it causes the SDI PLL locking to fail. LCLK and PCLK divisors are located in shadow registers, and we normally write them to DISPC registers when enabling the output. However, SDI uses pck-free as source clock for its PLL, and pck-free is affected by the divisors. And as we need the PLL before enabling the output, we need to write the divisors early. It seems just writing to the DISPC register is enough, and we don't need to care about the shadow register mechanism for pck-free. The exact reason for this is unknown. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reported-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/omap2/dss/sdi.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
index 5d31699fbd3c..f43bfe17b3b6 100644
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@ -105,6 +105,20 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
105 105
106 sdi_config_lcd_manager(dssdev); 106 sdi_config_lcd_manager(dssdev);
107 107
108 /*
109 * LCLK and PCLK divisors are located in shadow registers, and we
110 * normally write them to DISPC registers when enabling the output.
111 * However, SDI uses pck-free as source clock for its PLL, and pck-free
112 * is affected by the divisors. And as we need the PLL before enabling
113 * the output, we need to write the divisors early.
114 *
115 * It seems just writing to the DISPC register is enough, and we don't
116 * need to care about the shadow register mechanism for pck-free. The
117 * exact reason for this is unknown.
118 */
119 dispc_mgr_set_clock_div(dssdev->manager->id,
120 &sdi.mgr_config.clock_info);
121
108 dss_sdi_init(dssdev->phy.sdi.datapairs); 122 dss_sdi_init(dssdev->phy.sdi.datapairs);
109 r = dss_sdi_enable(); 123 r = dss_sdi_enable();
110 if (r) 124 if (r)