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authorAnatolij Gustschin <agust@denx.de>2011-05-13 06:52:29 -0400
committerAnatolij Gustschin <agust@denx.de>2011-05-24 10:28:51 -0400
commit12ed0c4baa4144ab3560ae793b5120316d74c0fe (patch)
tree9f11d4848972490c5b8a4825428ebfbe5a211e4d /drivers/video
parent3cadf9455c31de340ed77394dfad330caeb66b58 (diff)
video: mb862xxfb: relocate register space to get contiguous vram
By default the GDC registers are located in the middle of the 64MiB area for video RAM and registers. When 32MiB VRAM or more is used, relocate the register space to the top of the 64MiB space so that we get the contiguous VRAM for GDC frame buffer layers, drawing frames, capture and cursor buffers. Signed-off-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/mb862xx/mb862xx_reg.h6
-rw-r--r--drivers/video/mb862xx/mb862xxfb.c14
2 files changed, 15 insertions, 5 deletions
diff --git a/drivers/video/mb862xx/mb862xx_reg.h b/drivers/video/mb862xx/mb862xx_reg.h
index 2ba65e118500..737fc011caff 100644
--- a/drivers/video/mb862xx/mb862xx_reg.h
+++ b/drivers/video/mb862xx/mb862xx_reg.h
@@ -5,11 +5,8 @@
5#ifndef _MB862XX_REG_H 5#ifndef _MB862XX_REG_H
6#define _MB862XX_REG_H 6#define _MB862XX_REG_H
7 7
8#ifdef MB862XX_MMIO_BOTTOM
9#define MB862XX_MMIO_BASE 0x03fc0000
10#else
11#define MB862XX_MMIO_BASE 0x01fc0000 8#define MB862XX_MMIO_BASE 0x01fc0000
12#endif 9#define MB862XX_MMIO_HIGH_BASE 0x03fc0000
13#define MB862XX_I2C_BASE 0x0000c000 10#define MB862XX_I2C_BASE 0x0000c000
14#define MB862XX_DISP_BASE 0x00010000 11#define MB862XX_DISP_BASE 0x00010000
15#define MB862XX_CAP_BASE 0x00018000 12#define MB862XX_CAP_BASE 0x00018000
@@ -23,6 +20,7 @@
23#define GC_IMASK 0x00000024 20#define GC_IMASK 0x00000024
24#define GC_SRST 0x0000002c 21#define GC_SRST 0x0000002c
25#define GC_CCF 0x00000038 22#define GC_CCF 0x00000038
23#define GC_RSW 0x0000005c
26#define GC_CID 0x000000f0 24#define GC_CID 0x000000f0
27#define GC_REVISION 0x00000084 25#define GC_REVISION 0x00000084
28 26
diff --git a/drivers/video/mb862xx/mb862xxfb.c b/drivers/video/mb862xx/mb862xxfb.c
index a1b81e73394c..ffb6a2c36d3c 100644
--- a/drivers/video/mb862xx/mb862xxfb.c
+++ b/drivers/video/mb862xx/mb862xxfb.c
@@ -742,6 +742,12 @@ static int coralp_init(struct mb862xxfb_par *par)
742 742
743 par->refclk = GC_DISP_REFCLK_400; 743 par->refclk = GC_DISP_REFCLK_400;
744 744
745 if (par->mapped_vram >= 0x2000000) {
746 /* relocate gdc registers space */
747 writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
748 udelay(1); /* wait at least 20 bus cycles */
749 }
750
745 ver = inreg(host, GC_CID); 751 ver = inreg(host, GC_CID);
746 cn = (ver & GC_CID_CNAME_MSK) >> 8; 752 cn = (ver & GC_CID_CNAME_MSK) >> 8;
747 ver = ver & GC_CID_VERSION_MSK; 753 ver = ver & GC_CID_VERSION_MSK;
@@ -907,7 +913,13 @@ static int __devinit mb862xx_pci_probe(struct pci_dev *pdev,
907 case PCI_DEVICE_ID_FUJITSU_CORALPA: 913 case PCI_DEVICE_ID_FUJITSU_CORALPA:
908 par->fb_base_phys = pci_resource_start(par->pdev, 0); 914 par->fb_base_phys = pci_resource_start(par->pdev, 0);
909 par->mapped_vram = CORALP_MEM_SIZE; 915 par->mapped_vram = CORALP_MEM_SIZE;
910 par->mmio_base_phys = par->fb_base_phys + MB862XX_MMIO_BASE; 916 if (par->mapped_vram >= 0x2000000) {
917 par->mmio_base_phys = par->fb_base_phys +
918 MB862XX_MMIO_HIGH_BASE;
919 } else {
920 par->mmio_base_phys = par->fb_base_phys +
921 MB862XX_MMIO_BASE;
922 }
911 par->mmio_len = MB862XX_MMIO_SIZE; 923 par->mmio_len = MB862XX_MMIO_SIZE;
912 par->type = BT_CORALP; 924 par->type = BT_CORALP;
913 break; 925 break;