diff options
author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2011-05-16 06:43:04 -0400 |
---|---|---|
committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2011-07-25 03:08:13 -0400 |
commit | 94c042ce589b6b81e5dc0020fce2d248940412bd (patch) | |
tree | f8716440a70a01501227b5a3cc14a09349f35e2e /drivers/video | |
parent | 5ed8cf5b8e053832a3d0552e0a9681a3ff0325ee (diff) |
OMAP: DSS2: Handle dpll4_m4_ck in dss_get/put_clocks
Get and put for dpll4_m4_ck was handled in dss_init/dss_exit. Move the
code to dss_get/put_clocks(), which is a better place to handle it.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video')
-rw-r--r-- | drivers/video/omap2/dss/dss.c | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index d0b3f81b3724..bcd4a07adcc8 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c | |||
@@ -669,7 +669,6 @@ static int dss_init(void) | |||
669 | int r; | 669 | int r; |
670 | u32 rev; | 670 | u32 rev; |
671 | struct resource *dss_mem; | 671 | struct resource *dss_mem; |
672 | struct clk *dpll4_m4_ck; | ||
673 | 672 | ||
674 | dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); | 673 | dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); |
675 | if (!dss_mem) { | 674 | if (!dss_mem) { |
@@ -715,26 +714,6 @@ static int dss_init(void) | |||
715 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ | 714 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ |
716 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ | 715 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ |
717 | #endif | 716 | #endif |
718 | if (cpu_is_omap34xx()) { | ||
719 | dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); | ||
720 | if (IS_ERR(dpll4_m4_ck)) { | ||
721 | DSSERR("Failed to get dpll4_m4_ck\n"); | ||
722 | r = PTR_ERR(dpll4_m4_ck); | ||
723 | goto fail1; | ||
724 | } | ||
725 | } else if (cpu_is_omap44xx()) { | ||
726 | dpll4_m4_ck = clk_get(NULL, "dpll_per_m5x2_ck"); | ||
727 | if (IS_ERR(dpll4_m4_ck)) { | ||
728 | DSSERR("Failed to get dpll4_m4_ck\n"); | ||
729 | r = PTR_ERR(dpll4_m4_ck); | ||
730 | goto fail1; | ||
731 | } | ||
732 | } else { /* omap24xx */ | ||
733 | dpll4_m4_ck = NULL; | ||
734 | } | ||
735 | |||
736 | dss.dpll4_m4_ck = dpll4_m4_ck; | ||
737 | |||
738 | dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; | 717 | dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; |
739 | dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; | 718 | dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; |
740 | dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; | 719 | dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; |
@@ -749,17 +728,12 @@ static int dss_init(void) | |||
749 | 728 | ||
750 | return 0; | 729 | return 0; |
751 | 730 | ||
752 | fail1: | ||
753 | iounmap(dss.base); | ||
754 | fail0: | 731 | fail0: |
755 | return r; | 732 | return r; |
756 | } | 733 | } |
757 | 734 | ||
758 | static void dss_exit(void) | 735 | static void dss_exit(void) |
759 | { | 736 | { |
760 | if (dss.dpll4_m4_ck) | ||
761 | clk_put(dss.dpll4_m4_ck); | ||
762 | |||
763 | iounmap(dss.base); | 737 | iounmap(dss.base); |
764 | } | 738 | } |
765 | 739 | ||
@@ -845,6 +819,7 @@ static int dss_get_clock(struct clk **clock, const char *clk_name) | |||
845 | static int dss_get_clocks(void) | 819 | static int dss_get_clocks(void) |
846 | { | 820 | { |
847 | int r; | 821 | int r; |
822 | struct clk *dpll4_m4_ck; | ||
848 | struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; | 823 | struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; |
849 | 824 | ||
850 | dss.dss_ick = NULL; | 825 | dss.dss_ick = NULL; |
@@ -884,6 +859,27 @@ static int dss_get_clocks(void) | |||
884 | goto err; | 859 | goto err; |
885 | } | 860 | } |
886 | 861 | ||
862 | if (cpu_is_omap34xx()) { | ||
863 | dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); | ||
864 | if (IS_ERR(dpll4_m4_ck)) { | ||
865 | DSSERR("Failed to get dpll4_m4_ck\n"); | ||
866 | r = PTR_ERR(dpll4_m4_ck); | ||
867 | goto err; | ||
868 | } | ||
869 | } else if (cpu_is_omap44xx()) { | ||
870 | dpll4_m4_ck = clk_get(NULL, "dpll_per_m5x2_ck"); | ||
871 | if (IS_ERR(dpll4_m4_ck)) { | ||
872 | DSSERR("Failed to get dpll_per_m5x2_ck\n"); | ||
873 | r = PTR_ERR(dpll4_m4_ck); | ||
874 | goto err; | ||
875 | } | ||
876 | } else { /* omap24xx */ | ||
877 | dpll4_m4_ck = NULL; | ||
878 | } | ||
879 | |||
880 | dss.dpll4_m4_ck = dpll4_m4_ck; | ||
881 | |||
882 | |||
887 | return 0; | 883 | return 0; |
888 | 884 | ||
889 | err: | 885 | err: |
@@ -897,12 +893,16 @@ err: | |||
897 | clk_put(dss.dss_tv_fck); | 893 | clk_put(dss.dss_tv_fck); |
898 | if (dss.dss_video_fck) | 894 | if (dss.dss_video_fck) |
899 | clk_put(dss.dss_video_fck); | 895 | clk_put(dss.dss_video_fck); |
896 | if (dss.dpll4_m4_ck) | ||
897 | clk_put(dss.dpll4_m4_ck); | ||
900 | 898 | ||
901 | return r; | 899 | return r; |
902 | } | 900 | } |
903 | 901 | ||
904 | static void dss_put_clocks(void) | 902 | static void dss_put_clocks(void) |
905 | { | 903 | { |
904 | if (dss.dpll4_m4_ck) | ||
905 | clk_put(dss.dpll4_m4_ck); | ||
906 | if (dss.dss_video_fck) | 906 | if (dss.dss_video_fck) |
907 | clk_put(dss.dss_video_fck); | 907 | clk_put(dss.dss_video_fck); |
908 | if (dss.dss_tv_fck) | 908 | if (dss.dss_tv_fck) |