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authorPaul Mackerras <paulus@samba.org>2006-03-28 21:24:50 -0500
committerPaul Mackerras <paulus@samba.org>2006-03-28 21:24:50 -0500
commitbac30d1a78d0f11c613968fc8b351a91ed465386 (patch)
treee52f3c876522a2f6047a6ec1c27df2e8a79486b8 /drivers/video
parente8222502ee6157e2713da9e0792c21f4ad458d50 (diff)
parentca9ba4471c1203bb6e759b76e83167fec54fe590 (diff)
Merge ../linux-2.6
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/Kconfig27
-rw-r--r--drivers/video/Makefile1
-rw-r--r--drivers/video/acornfb.c8
-rw-r--r--drivers/video/asiliantfb.c14
-rw-r--r--drivers/video/aty/aty128fb.c4
-rw-r--r--drivers/video/aty/atyfb_base.c16
-rw-r--r--drivers/video/aty/mach64_gx.c3
-rw-r--r--drivers/video/aty/radeon_base.c6
-rw-r--r--drivers/video/au1200fb.c3844
-rw-r--r--drivers/video/au1200fb.h572
-rw-r--r--drivers/video/chipsfb.c14
-rw-r--r--drivers/video/console/Kconfig24
-rw-r--r--drivers/video/console/fonts.c2
-rw-r--r--drivers/video/console/newport_con.c4
-rw-r--r--drivers/video/console/vgacon.c271
-rw-r--r--drivers/video/fbcmap.c4
-rw-r--r--drivers/video/fbmem.c31
-rw-r--r--drivers/video/fbmon.c6
-rw-r--r--drivers/video/fbsysfs.c4
-rw-r--r--drivers/video/geode/Kconfig17
-rw-r--r--drivers/video/geode/Makefile4
-rw-r--r--drivers/video/geode/display_gx.c156
-rw-r--r--drivers/video/geode/display_gx.h96
-rw-r--r--drivers/video/geode/gxfb_core.c423
-rw-r--r--drivers/video/geode/video_gx.c262
-rw-r--r--drivers/video/geode/video_gx.h47
-rw-r--r--drivers/video/i810/i810-i2c.c3
-rw-r--r--drivers/video/imsttfb.c32
-rw-r--r--drivers/video/macmodes.c2
-rw-r--r--drivers/video/matrox/matroxfb_g450.c2
-rw-r--r--drivers/video/matrox/matroxfb_maven.c78
-rw-r--r--drivers/video/modedb.c6
-rw-r--r--drivers/video/neofb.c8
-rw-r--r--drivers/video/nvidia/nv_accel.c12
-rw-r--r--drivers/video/nvidia/nv_i2c.c3
-rw-r--r--drivers/video/nvidia/nv_type.h1
-rw-r--r--drivers/video/nvidia/nvidia.c119
-rw-r--r--drivers/video/pmagb-b-fb.c2
-rw-r--r--drivers/video/radeonfb.c2
-rw-r--r--drivers/video/riva/fbdev.c2
-rw-r--r--drivers/video/savage/savagefb-i2c.c3
-rw-r--r--drivers/video/sis/init301.c11
-rw-r--r--drivers/video/sstfb.c11
-rw-r--r--drivers/video/virgefb.c3
44 files changed, 5924 insertions, 236 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index fdebd60a3250..22e9d696fdd2 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -70,6 +70,22 @@ config FB_MACMODES
70 depends on FB 70 depends on FB
71 default n 71 default n
72 72
73config FB_FIRMWARE_EDID
74 bool "Enable firmware EDID"
75 depends on FB
76 default y
77 ---help---
78 This enables access to the EDID transferred from the firmware.
79 On the i386, this is from the Video BIOS. Enable this if DDC/I2C
80 transfers do not work for your driver and if you are using
81 nvidiafb, i810fb or savagefb.
82
83 In general, choosing Y for this option is safe. If you
84 experience extremely long delays while booting before you get
85 something on your display, try setting this to N. Matrox cards in
86 combination with certain motherboards and monitors are known to
87 suffer from this problem.
88
73config FB_MODE_HELPERS 89config FB_MODE_HELPERS
74 bool "Enable Video Mode Handling Helpers" 90 bool "Enable Video Mode Handling Helpers"
75 depends on FB 91 depends on FB
@@ -1202,6 +1218,17 @@ config FB_AU1100
1202 bool "Au1100 LCD Driver" 1218 bool "Au1100 LCD Driver"
1203 depends on (FB = y) && EXPERIMENTAL && PCI && MIPS && MIPS_PB1100=y 1219 depends on (FB = y) && EXPERIMENTAL && PCI && MIPS && MIPS_PB1100=y
1204 1220
1221config FB_AU1200
1222 bool "Au1200 LCD Driver"
1223 depends on FB && MIPS && SOC_AU1200
1224 select FB_CFB_FILLRECT
1225 select FB_CFB_COPYAREA
1226 select FB_CFB_IMAGEBLIT
1227 help
1228 This is the framebuffer driver for the AMD Au1200 SOC. It can drive
1229 various panels and CRTs by passing in kernel cmd line option
1230 au1200fb:panel=<name>.
1231
1205source "drivers/video/geode/Kconfig" 1232source "drivers/video/geode/Kconfig"
1206 1233
1207config FB_FFB 1234config FB_FFB
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index aa434e725c0d..cb90218515ac 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -86,6 +86,7 @@ obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o
86obj-$(CONFIG_FB_PXA) += pxafb.o 86obj-$(CONFIG_FB_PXA) += pxafb.o
87obj-$(CONFIG_FB_W100) += w100fb.o 87obj-$(CONFIG_FB_W100) += w100fb.o
88obj-$(CONFIG_FB_AU1100) += au1100fb.o 88obj-$(CONFIG_FB_AU1100) += au1100fb.o
89obj-$(CONFIG_FB_AU1200) += au1200fb.o
89obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o 90obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o
90obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o 91obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o
91obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o 92obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o
diff --git a/drivers/video/acornfb.c b/drivers/video/acornfb.c
index 76448d6ae896..98baecccb3fd 100644
--- a/drivers/video/acornfb.c
+++ b/drivers/video/acornfb.c
@@ -1308,7 +1308,7 @@ static int __init acornfb_probe(struct platform_device *dev)
1308 /* 1308 /*
1309 * Try to select a suitable default mode 1309 * Try to select a suitable default mode
1310 */ 1310 */
1311 for (i = 0; i < sizeof(modedb) / sizeof(*modedb); i++) { 1311 for (i = 0; i < ARRAY_SIZE(modedb); i++) {
1312 unsigned long hs; 1312 unsigned long hs;
1313 1313
1314 hs = modedb[i].refresh * 1314 hs = modedb[i].refresh *
@@ -1380,7 +1380,7 @@ static int __init acornfb_probe(struct platform_device *dev)
1380 */ 1380 */
1381 free_unused_pages(PAGE_OFFSET + size, PAGE_OFFSET + MAX_SIZE); 1381 free_unused_pages(PAGE_OFFSET + size, PAGE_OFFSET + MAX_SIZE);
1382#endif 1382#endif
1383 1383
1384 fb_info.fix.smem_len = size; 1384 fb_info.fix.smem_len = size;
1385 current_par.palette_size = VIDC_PALETTE_SIZE; 1385 current_par.palette_size = VIDC_PALETTE_SIZE;
1386 1386
@@ -1391,7 +1391,7 @@ static int __init acornfb_probe(struct platform_device *dev)
1391 */ 1391 */
1392 do { 1392 do {
1393 rc = fb_find_mode(&fb_info.var, &fb_info, NULL, modedb, 1393 rc = fb_find_mode(&fb_info.var, &fb_info, NULL, modedb,
1394 sizeof(modedb) / sizeof(*modedb), 1394 ARRAY_SIZE(modedb),
1395 &acornfb_default_mode, DEFAULT_BPP); 1395 &acornfb_default_mode, DEFAULT_BPP);
1396 /* 1396 /*
1397 * If we found an exact match, all ok. 1397 * If we found an exact match, all ok.
@@ -1408,7 +1408,7 @@ static int __init acornfb_probe(struct platform_device *dev)
1408 break; 1408 break;
1409 1409
1410 rc = fb_find_mode(&fb_info.var, &fb_info, NULL, modedb, 1410 rc = fb_find_mode(&fb_info.var, &fb_info, NULL, modedb,
1411 sizeof(modedb) / sizeof(*modedb), 1411 ARRAY_SIZE(modedb),
1412 &acornfb_default_mode, DEFAULT_BPP); 1412 &acornfb_default_mode, DEFAULT_BPP);
1413 if (rc) 1413 if (rc)
1414 break; 1414 break;
diff --git a/drivers/video/asiliantfb.c b/drivers/video/asiliantfb.c
index c924d81f7978..29f9f0dfe3b4 100644
--- a/drivers/video/asiliantfb.c
+++ b/drivers/video/asiliantfb.c
@@ -353,8 +353,6 @@ struct chips_init_reg {
353 unsigned char data; 353 unsigned char data;
354}; 354};
355 355
356#define N_ELTS(x) (sizeof(x) / sizeof(x[0]))
357
358static struct chips_init_reg chips_init_sr[] = 356static struct chips_init_reg chips_init_sr[] =
359{ 357{
360 {0x00, 0x03}, /* Reset register */ 358 {0x00, 0x03}, /* Reset register */
@@ -460,22 +458,22 @@ static void __devinit chips_hw_init(struct fb_info *p)
460{ 458{
461 int i; 459 int i;
462 460
463 for (i = 0; i < N_ELTS(chips_init_xr); ++i) 461 for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
464 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data); 462 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
465 write_xr(0x81, 0x12); 463 write_xr(0x81, 0x12);
466 write_xr(0x82, 0x08); 464 write_xr(0x82, 0x08);
467 write_xr(0x20, 0x00); 465 write_xr(0x20, 0x00);
468 for (i = 0; i < N_ELTS(chips_init_sr); ++i) 466 for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
469 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data); 467 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
470 for (i = 0; i < N_ELTS(chips_init_gr); ++i) 468 for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
471 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data); 469 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
472 for (i = 0; i < N_ELTS(chips_init_ar); ++i) 470 for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
473 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data); 471 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
474 /* Enable video output in attribute index register */ 472 /* Enable video output in attribute index register */
475 writeb(0x20, mmio_base + 0x780); 473 writeb(0x20, mmio_base + 0x780);
476 for (i = 0; i < N_ELTS(chips_init_cr); ++i) 474 for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
477 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data); 475 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
478 for (i = 0; i < N_ELTS(chips_init_fr); ++i) 476 for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
479 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data); 477 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
480} 478}
481 479
diff --git a/drivers/video/aty/aty128fb.c b/drivers/video/aty/aty128fb.c
index f07be22e119d..f7bbff4ddc6a 100644
--- a/drivers/video/aty/aty128fb.c
+++ b/drivers/video/aty/aty128fb.c
@@ -1726,9 +1726,9 @@ static int __init aty128_init(struct pci_dev *pdev, const struct pci_device_id *
1726 strcpy(video_card, "Rage128 XX "); 1726 strcpy(video_card, "Rage128 XX ");
1727 video_card[8] = ent->device >> 8; 1727 video_card[8] = ent->device >> 8;
1728 video_card[9] = ent->device & 0xFF; 1728 video_card[9] = ent->device & 0xFF;
1729 1729
1730 /* range check to make sure */ 1730 /* range check to make sure */
1731 if (ent->driver_data < (sizeof(r128_family)/sizeof(char *))) 1731 if (ent->driver_data < ARRAY_SIZE(r128_family))
1732 strncat(video_card, r128_family[ent->driver_data], sizeof(video_card)); 1732 strncat(video_card, r128_family[ent->driver_data], sizeof(video_card));
1733 1733
1734 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev); 1734 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
diff --git a/drivers/video/aty/atyfb_base.c b/drivers/video/aty/atyfb_base.c
index 1b1f24e2bfbe..b39e72d5413b 100644
--- a/drivers/video/aty/atyfb_base.c
+++ b/drivers/video/aty/atyfb_base.c
@@ -435,7 +435,7 @@ static int __devinit correct_chipset(struct atyfb_par *par)
435 const char *name; 435 const char *name;
436 int i; 436 int i;
437 437
438 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--) 438 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
439 if (par->pci_id == aty_chips[i].pci_id) 439 if (par->pci_id == aty_chips[i].pci_id)
440 break; 440 break;
441 441
@@ -2169,10 +2169,10 @@ static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2169 2169
2170 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) { 2170 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2171 refresh_tbl = ragexl_tbl; 2171 refresh_tbl = ragexl_tbl;
2172 size = sizeof(ragexl_tbl)/sizeof(int); 2172 size = ARRAY_SIZE(ragexl_tbl);
2173 } else { 2173 } else {
2174 refresh_tbl = ragepro_tbl; 2174 refresh_tbl = ragepro_tbl;
2175 size = sizeof(ragepro_tbl)/sizeof(int); 2175 size = ARRAY_SIZE(ragepro_tbl);
2176 } 2176 }
2177 2177
2178 for (i=0; i < size; i++) { 2178 for (i=0; i < size; i++) {
@@ -2299,6 +2299,10 @@ static int __init aty_init(struct fb_info *info, const char *name)
2299 case CLK_ATI18818_1: 2299 case CLK_ATI18818_1:
2300 par->pll_ops = &aty_pll_ati18818_1; 2300 par->pll_ops = &aty_pll_ati18818_1;
2301 break; 2301 break;
2302 case CLK_IBMRGB514:
2303 par->pll_ops = &aty_pll_ibm514;
2304 break;
2305#if 0 /* dead code */
2302 case CLK_STG1703: 2306 case CLK_STG1703:
2303 par->pll_ops = &aty_pll_stg1703; 2307 par->pll_ops = &aty_pll_stg1703;
2304 break; 2308 break;
@@ -2308,9 +2312,7 @@ static int __init aty_init(struct fb_info *info, const char *name)
2308 case CLK_ATT20C408: 2312 case CLK_ATT20C408:
2309 par->pll_ops = &aty_pll_att20c408; 2313 par->pll_ops = &aty_pll_att20c408;
2310 break; 2314 break;
2311 case CLK_IBMRGB514: 2315#endif
2312 par->pll_ops = &aty_pll_ibm514;
2313 break;
2314 default: 2316 default:
2315 PRINTKI("aty_init: CLK type not implemented yet!"); 2317 PRINTKI("aty_init: CLK type not implemented yet!");
2316 par->pll_ops = &aty_pll_unsupported; 2318 par->pll_ops = &aty_pll_unsupported;
@@ -3398,7 +3400,7 @@ static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_devi
3398 struct atyfb_par *par; 3400 struct atyfb_par *par;
3399 int i, rc = -ENOMEM; 3401 int i, rc = -ENOMEM;
3400 3402
3401 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--) 3403 for (i = ARRAY_SIZE(aty_chips); i >= 0; i--)
3402 if (pdev->device == aty_chips[i].pci_id) 3404 if (pdev->device == aty_chips[i].pci_id)
3403 break; 3405 break;
3404 3406
diff --git a/drivers/video/aty/mach64_gx.c b/drivers/video/aty/mach64_gx.c
index 01fdff79483b..2045639cb671 100644
--- a/drivers/video/aty/mach64_gx.c
+++ b/drivers/video/aty/mach64_gx.c
@@ -149,8 +149,7 @@ static int aty_var_to_pll_514(const struct fb_info *info, u32 vclk_per,
149 }; 149 };
150 int i; 150 int i;
151 151
152 for (i = 0; i < sizeof(RGB514_clocks) / sizeof(*RGB514_clocks); 152 for (i = 0; i < ARRAY_SIZE(RGB514_clocks); i++)
153 i++)
154 if (vclk_per <= RGB514_clocks[i].limit) { 153 if (vclk_per <= RGB514_clocks[i].limit) {
155 pll->ibm514.m = RGB514_clocks[i].m; 154 pll->ibm514.m = RGB514_clocks[i].m;
156 pll->ibm514.n = RGB514_clocks[i].n; 155 pll->ibm514.n = RGB514_clocks[i].n;
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c
index c9f0c5a07e6e..9a6b5b39b88e 100644
--- a/drivers/video/aty/radeon_base.c
+++ b/drivers/video/aty/radeon_base.c
@@ -1067,7 +1067,7 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1067 1067
1068 1068
1069 if (regno > 255) 1069 if (regno > 255)
1070 return 1; 1070 return -EINVAL;
1071 1071
1072 red >>= 8; 1072 red >>= 8;
1073 green >>= 8; 1073 green >>= 8;
@@ -1086,9 +1086,9 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1086 pindex = regno * 8; 1086 pindex = regno * 8;
1087 1087
1088 if (rinfo->depth == 16 && regno > 63) 1088 if (rinfo->depth == 16 && regno > 63)
1089 return 1; 1089 return -EINVAL;
1090 if (rinfo->depth == 15 && regno > 31) 1090 if (rinfo->depth == 15 && regno > 31)
1091 return 1; 1091 return -EINVAL;
1092 1092
1093 /* For 565, the green component is mixed one order 1093 /* For 565, the green component is mixed one order
1094 * below 1094 * below
diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c
new file mode 100644
index 000000000000..b367de30b98c
--- /dev/null
+++ b/drivers/video/au1200fb.c
@@ -0,0 +1,3844 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1200 LCD Driver.
4 *
5 * Copyright 2004-2005 AMD
6 * Author: AMD
7 *
8 * Based on:
9 * linux/drivers/video/skeletonfb.c -- Skeleton for a frame buffer device
10 * Created 28 Dec 1997 by Geert Uytterhoeven
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#include <linux/module.h>
34#include <linux/platform_device.h>
35#include <linux/kernel.h>
36#include <linux/errno.h>
37#include <linux/string.h>
38#include <linux/mm.h>
39#include <linux/fb.h>
40#include <linux/init.h>
41#include <linux/interrupt.h>
42#include <linux/ctype.h>
43#include <linux/dma-mapping.h>
44
45#include <asm/mach-au1x00/au1000.h>
46#include "au1200fb.h"
47
48#ifdef CONFIG_PM
49#include <asm/mach-au1x00/au1xxx_pm.h>
50#endif
51
52#ifndef CONFIG_FB_AU1200_DEVS
53#define CONFIG_FB_AU1200_DEVS 4
54#endif
55
56#define DRIVER_NAME "au1200fb"
57#define DRIVER_DESC "LCD controller driver for AU1200 processors"
58
59#define DEBUG 1
60
61#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
62#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
63#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
64
65#if DEBUG
66#define print_dbg(f, arg...) printk(KERN_DEBUG __FILE__ ": " f "\n", ## arg)
67#else
68#define print_dbg(f, arg...) do {} while (0)
69#endif
70
71
72#define AU1200_LCD_FB_IOCTL 0x46FF
73
74#define AU1200_LCD_SET_SCREEN 1
75#define AU1200_LCD_GET_SCREEN 2
76#define AU1200_LCD_SET_WINDOW 3
77#define AU1200_LCD_GET_WINDOW 4
78#define AU1200_LCD_SET_PANEL 5
79#define AU1200_LCD_GET_PANEL 6
80
81#define SCREEN_SIZE (1<< 1)
82#define SCREEN_BACKCOLOR (1<< 2)
83#define SCREEN_BRIGHTNESS (1<< 3)
84#define SCREEN_COLORKEY (1<< 4)
85#define SCREEN_MASK (1<< 5)
86
87struct au1200_lcd_global_regs_t {
88 unsigned int flags;
89 unsigned int xsize;
90 unsigned int ysize;
91 unsigned int backcolor;
92 unsigned int brightness;
93 unsigned int colorkey;
94 unsigned int mask;
95 unsigned int panel_choice;
96 char panel_desc[80];
97
98};
99
100#define WIN_POSITION (1<< 0)
101#define WIN_ALPHA_COLOR (1<< 1)
102#define WIN_ALPHA_MODE (1<< 2)
103#define WIN_PRIORITY (1<< 3)
104#define WIN_CHANNEL (1<< 4)
105#define WIN_BUFFER_FORMAT (1<< 5)
106#define WIN_COLOR_ORDER (1<< 6)
107#define WIN_PIXEL_ORDER (1<< 7)
108#define WIN_SIZE (1<< 8)
109#define WIN_COLORKEY_MODE (1<< 9)
110#define WIN_DOUBLE_BUFFER_MODE (1<< 10)
111#define WIN_RAM_ARRAY_MODE (1<< 11)
112#define WIN_BUFFER_SCALE (1<< 12)
113#define WIN_ENABLE (1<< 13)
114
115struct au1200_lcd_window_regs_t {
116 unsigned int flags;
117 unsigned int xpos;
118 unsigned int ypos;
119 unsigned int alpha_color;
120 unsigned int alpha_mode;
121 unsigned int priority;
122 unsigned int channel;
123 unsigned int buffer_format;
124 unsigned int color_order;
125 unsigned int pixel_order;
126 unsigned int xsize;
127 unsigned int ysize;
128 unsigned int colorkey_mode;
129 unsigned int double_buffer_mode;
130 unsigned int ram_array_mode;
131 unsigned int xscale;
132 unsigned int yscale;
133 unsigned int enable;
134};
135
136
137struct au1200_lcd_iodata_t {
138 unsigned int subcmd;
139 struct au1200_lcd_global_regs_t global;
140 struct au1200_lcd_window_regs_t window;
141};
142
143#if defined(__BIG_ENDIAN)
144#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
145#else
146#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
147#endif
148#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
149
150/* Private, per-framebuffer management information (independent of the panel itself) */
151struct au1200fb_device {
152 struct fb_info fb_info; /* FB driver info record */
153
154 int plane;
155 unsigned char* fb_mem; /* FrameBuffer memory map */
156 unsigned int fb_len;
157 dma_addr_t fb_phys;
158};
159
160static struct au1200fb_device _au1200fb_devices[CONFIG_FB_AU1200_DEVS];
161/********************************************************************/
162
163/* LCD controller restrictions */
164#define AU1200_LCD_MAX_XRES 1280
165#define AU1200_LCD_MAX_YRES 1024
166#define AU1200_LCD_MAX_BPP 32
167#define AU1200_LCD_MAX_CLK 96000000 /* fixme: this needs to go away ? */
168#define AU1200_LCD_NBR_PALETTE_ENTRIES 256
169
170/* Default number of visible screen buffer to allocate */
171#define AU1200FB_NBR_VIDEO_BUFFERS 1
172
173/********************************************************************/
174
175static struct au1200_lcd *lcd = (struct au1200_lcd *) AU1200_LCD_ADDR;
176static int window_index = 2; /* default is zero */
177static int panel_index = 2; /* default is zero */
178static struct window_settings *win;
179static struct panel_settings *panel;
180static int noblanking = 1;
181static int nohwcursor = 0;
182
183struct window_settings {
184 unsigned char name[64];
185 uint32 mode_backcolor;
186 uint32 mode_colorkey;
187 uint32 mode_colorkeymsk;
188 struct {
189 int xres;
190 int yres;
191 int xpos;
192 int ypos;
193 uint32 mode_winctrl1; /* winctrl1[FRM,CCO,PO,PIPE] */
194 uint32 mode_winenable;
195 } w[4];
196};
197
198#if defined(__BIG_ENDIAN)
199#define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_00
200#else
201#define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_01
202#endif
203
204extern int board_au1200fb_panel_init (void);
205extern int board_au1200fb_panel_shutdown (void);
206
207#ifdef CONFIG_PM
208int au1200fb_pm_callback(au1xxx_power_dev_t *dev,
209 au1xxx_request_t request, void *data);
210au1xxx_power_dev_t *LCD_pm_dev;
211#endif
212
213/*
214 * Default window configurations
215 */
216static struct window_settings windows[] = {
217 { /* Index 0 */
218 "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
219 /* mode_backcolor */ 0x006600ff,
220 /* mode_colorkey,msk*/ 0, 0,
221 {
222 {
223 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
224 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
225 LCD_WINCTRL1_PO_16BPP,
226 /* mode_winenable*/ LCD_WINENABLE_WEN0,
227 },
228 {
229 /* xres, yres, xpos, ypos */ 100, 100, 100, 100,
230 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
231 LCD_WINCTRL1_PO_16BPP |
232 LCD_WINCTRL1_PIPE,
233 /* mode_winenable*/ LCD_WINENABLE_WEN1,
234 },
235 {
236 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
237 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
238 LCD_WINCTRL1_PO_16BPP,
239 /* mode_winenable*/ 0,
240 },
241 {
242 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
243 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
244 LCD_WINCTRL1_PO_16BPP |
245 LCD_WINCTRL1_PIPE,
246 /* mode_winenable*/ 0,
247 },
248 },
249 },
250
251 { /* Index 1 */
252 "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
253 /* mode_backcolor */ 0x006600ff,
254 /* mode_colorkey,msk*/ 0, 0,
255 {
256 {
257 /* xres, yres, xpos, ypos */ 320, 240, 5, 5,
258 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_24BPP |
259 LCD_WINCTRL1_PO_00,
260 /* mode_winenable*/ LCD_WINENABLE_WEN0,
261 },
262 {
263 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
264 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565
265 | LCD_WINCTRL1_PO_16BPP,
266 /* mode_winenable*/ 0,
267 },
268 {
269 /* xres, yres, xpos, ypos */ 100, 100, 0, 0,
270 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
271 LCD_WINCTRL1_PO_16BPP |
272 LCD_WINCTRL1_PIPE,
273 /* mode_winenable*/ 0/*LCD_WINENABLE_WEN2*/,
274 },
275 {
276 /* xres, yres, xpos, ypos */ 200, 25, 0, 0,
277 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
278 LCD_WINCTRL1_PO_16BPP |
279 LCD_WINCTRL1_PIPE,
280 /* mode_winenable*/ 0,
281 },
282 },
283 },
284 { /* Index 2 */
285 "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
286 /* mode_backcolor */ 0x006600ff,
287 /* mode_colorkey,msk*/ 0, 0,
288 {
289 {
290 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
291 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
292 LCD_WINCTRL1_PO_16BPP,
293 /* mode_winenable*/ LCD_WINENABLE_WEN0,
294 },
295 {
296 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
297 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
298 LCD_WINCTRL1_PO_16BPP,
299 /* mode_winenable*/ 0,
300 },
301 {
302 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
303 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_32BPP |
304 LCD_WINCTRL1_PO_00|LCD_WINCTRL1_PIPE,
305 /* mode_winenable*/ 0/*LCD_WINENABLE_WEN2*/,
306 },
307 {
308 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
309 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
310 LCD_WINCTRL1_PO_16BPP |
311 LCD_WINCTRL1_PIPE,
312 /* mode_winenable*/ 0,
313 },
314 },
315 },
316 /* Need VGA 640 @ 24bpp, @ 32bpp */
317 /* Need VGA 800 @ 24bpp, @ 32bpp */
318 /* Need VGA 1024 @ 24bpp, @ 32bpp */
319};
320
321/*
322 * Controller configurations for various panels.
323 */
324
325struct panel_settings
326{
327 const char name[25]; /* Full name <vendor>_<model> */
328
329 struct fb_monspecs monspecs; /* FB monitor specs */
330
331 /* panel timings */
332 uint32 mode_screen;
333 uint32 mode_horztiming;
334 uint32 mode_verttiming;
335 uint32 mode_clkcontrol;
336 uint32 mode_pwmdiv;
337 uint32 mode_pwmhi;
338 uint32 mode_outmask;
339 uint32 mode_fifoctrl;
340 uint32 mode_toyclksrc;
341 uint32 mode_backlight;
342 uint32 mode_auxpll;
343 int (*device_init)(void);
344 int (*device_shutdown)(void);
345#define Xres min_xres
346#define Yres min_yres
347 u32 min_xres; /* Minimum horizontal resolution */
348 u32 max_xres; /* Maximum horizontal resolution */
349 u32 min_yres; /* Minimum vertical resolution */
350 u32 max_yres; /* Maximum vertical resolution */
351};
352
353/********************************************************************/
354/* fixme: Maybe a modedb for the CRT ? otherwise panels should be as-is */
355
356/* List of panels known to work with the AU1200 LCD controller.
357 * To add a new panel, enter the same specifications as the
358 * Generic_TFT one, and MAKE SURE that it doesn't conflicts
359 * with the controller restrictions. Restrictions are:
360 *
361 * STN color panels: max_bpp <= 12
362 * STN mono panels: max_bpp <= 4
363 * TFT panels: max_bpp <= 16
364 * max_xres <= 800
365 * max_yres <= 600
366 */
367static struct panel_settings known_lcd_panels[] =
368{
369 [0] = { /* QVGA 320x240 H:33.3kHz V:110Hz */
370 .name = "QVGA_320x240",
371 .monspecs = {
372 .modedb = NULL,
373 .modedb_len = 0,
374 .hfmin = 30000,
375 .hfmax = 70000,
376 .vfmin = 60,
377 .vfmax = 60,
378 .dclkmin = 6000000,
379 .dclkmax = 28000000,
380 .input = FB_DISP_RGB,
381 },
382 .mode_screen = LCD_SCREEN_SX_N(320) |
383 LCD_SCREEN_SY_N(240),
384 .mode_horztiming = 0x00c4623b,
385 .mode_verttiming = 0x00502814,
386 .mode_clkcontrol = 0x00020002, /* /4=24Mhz */
387 .mode_pwmdiv = 0x00000000,
388 .mode_pwmhi = 0x00000000,
389 .mode_outmask = 0x00FFFFFF,
390 .mode_fifoctrl = 0x2f2f2f2f,
391 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
392 .mode_backlight = 0x00000000,
393 .mode_auxpll = 8, /* 96MHz AUXPLL */
394 .device_init = NULL,
395 .device_shutdown = NULL,
396 320, 320,
397 240, 240,
398 },
399
400 [1] = { /* VGA 640x480 H:30.3kHz V:58Hz */
401 .name = "VGA_640x480",
402 .monspecs = {
403 .modedb = NULL,
404 .modedb_len = 0,
405 .hfmin = 30000,
406 .hfmax = 70000,
407 .vfmin = 60,
408 .vfmax = 60,
409 .dclkmin = 6000000,
410 .dclkmax = 28000000,
411 .input = FB_DISP_RGB,
412 },
413 .mode_screen = 0x13f9df80,
414 .mode_horztiming = 0x003c5859,
415 .mode_verttiming = 0x00741201,
416 .mode_clkcontrol = 0x00020001, /* /4=24Mhz */
417 .mode_pwmdiv = 0x00000000,
418 .mode_pwmhi = 0x00000000,
419 .mode_outmask = 0x00FFFFFF,
420 .mode_fifoctrl = 0x2f2f2f2f,
421 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
422 .mode_backlight = 0x00000000,
423 .mode_auxpll = 8, /* 96MHz AUXPLL */
424 .device_init = NULL,
425 .device_shutdown = NULL,
426 640, 480,
427 640, 480,
428 },
429
430 [2] = { /* SVGA 800x600 H:46.1kHz V:69Hz */
431 .name = "SVGA_800x600",
432 .monspecs = {
433 .modedb = NULL,
434 .modedb_len = 0,
435 .hfmin = 30000,
436 .hfmax = 70000,
437 .vfmin = 60,
438 .vfmax = 60,
439 .dclkmin = 6000000,
440 .dclkmax = 28000000,
441 .input = FB_DISP_RGB,
442 },
443 .mode_screen = 0x18fa5780,
444 .mode_horztiming = 0x00dc7e77,
445 .mode_verttiming = 0x00584805,
446 .mode_clkcontrol = 0x00020000, /* /2=48Mhz */
447 .mode_pwmdiv = 0x00000000,
448 .mode_pwmhi = 0x00000000,
449 .mode_outmask = 0x00FFFFFF,
450 .mode_fifoctrl = 0x2f2f2f2f,
451 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
452 .mode_backlight = 0x00000000,
453 .mode_auxpll = 8, /* 96MHz AUXPLL */
454 .device_init = NULL,
455 .device_shutdown = NULL,
456 800, 800,
457 600, 600,
458 },
459
460 [3] = { /* XVGA 1024x768 H:56.2kHz V:70Hz */
461 .name = "XVGA_1024x768",
462 .monspecs = {
463 .modedb = NULL,
464 .modedb_len = 0,
465 .hfmin = 30000,
466 .hfmax = 70000,
467 .vfmin = 60,
468 .vfmax = 60,
469 .dclkmin = 6000000,
470 .dclkmax = 28000000,
471 .input = FB_DISP_RGB,
472 },
473 .mode_screen = 0x1ffaff80,
474 .mode_horztiming = 0x007d0e57,
475 .mode_verttiming = 0x00740a01,
476 .mode_clkcontrol = 0x000A0000, /* /1 */
477 .mode_pwmdiv = 0x00000000,
478 .mode_pwmhi = 0x00000000,
479 .mode_outmask = 0x00FFFFFF,
480 .mode_fifoctrl = 0x2f2f2f2f,
481 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
482 .mode_backlight = 0x00000000,
483 .mode_auxpll = 6, /* 72MHz AUXPLL */
484 .device_init = NULL,
485 .device_shutdown = NULL,
486 1024, 1024,
487 768, 768,
488 },
489
490 [4] = { /* XVGA XVGA 1280x1024 H:68.5kHz V:65Hz */
491 .name = "XVGA_1280x1024",
492 .monspecs = {
493 .modedb = NULL,
494 .modedb_len = 0,
495 .hfmin = 30000,
496 .hfmax = 70000,
497 .vfmin = 60,
498 .vfmax = 60,
499 .dclkmin = 6000000,
500 .dclkmax = 28000000,
501 .input = FB_DISP_RGB,
502 },
503 .mode_screen = 0x27fbff80,
504 .mode_horztiming = 0x00cdb2c7,
505 .mode_verttiming = 0x00600002,
506 .mode_clkcontrol = 0x000A0000, /* /1 */
507 .mode_pwmdiv = 0x00000000,
508 .mode_pwmhi = 0x00000000,
509 .mode_outmask = 0x00FFFFFF,
510 .mode_fifoctrl = 0x2f2f2f2f,
511 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
512 .mode_backlight = 0x00000000,
513 .mode_auxpll = 10, /* 120MHz AUXPLL */
514 .device_init = NULL,
515 .device_shutdown = NULL,
516 1280, 1280,
517 1024, 1024,
518 },
519
520 [5] = { /* Samsung 1024x768 TFT */
521 .name = "Samsung_1024x768_TFT",
522 .monspecs = {
523 .modedb = NULL,
524 .modedb_len = 0,
525 .hfmin = 30000,
526 .hfmax = 70000,
527 .vfmin = 60,
528 .vfmax = 60,
529 .dclkmin = 6000000,
530 .dclkmax = 28000000,
531 .input = FB_DISP_RGB,
532 },
533 .mode_screen = 0x1ffaff80,
534 .mode_horztiming = 0x018cc677,
535 .mode_verttiming = 0x00241217,
536 .mode_clkcontrol = 0x00000000, /* SCB 0x1 /4=24Mhz */
537 .mode_pwmdiv = 0x8000063f, /* SCB 0x0 */
538 .mode_pwmhi = 0x03400000, /* SCB 0x0 */
539 .mode_outmask = 0x00FFFFFF,
540 .mode_fifoctrl = 0x2f2f2f2f,
541 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
542 .mode_backlight = 0x00000000,
543 .mode_auxpll = 8, /* 96MHz AUXPLL */
544 .device_init = board_au1200fb_panel_init,
545 .device_shutdown = board_au1200fb_panel_shutdown,
546 1024, 1024,
547 768, 768,
548 },
549
550 [6] = { /* Toshiba 640x480 TFT */
551 .name = "Toshiba_640x480_TFT",
552 .monspecs = {
553 .modedb = NULL,
554 .modedb_len = 0,
555 .hfmin = 30000,
556 .hfmax = 70000,
557 .vfmin = 60,
558 .vfmax = 60,
559 .dclkmin = 6000000,
560 .dclkmax = 28000000,
561 .input = FB_DISP_RGB,
562 },
563 .mode_screen = LCD_SCREEN_SX_N(640) |
564 LCD_SCREEN_SY_N(480),
565 .mode_horztiming = LCD_HORZTIMING_HPW_N(96) |
566 LCD_HORZTIMING_HND1_N(13) | LCD_HORZTIMING_HND2_N(51),
567 .mode_verttiming = LCD_VERTTIMING_VPW_N(2) |
568 LCD_VERTTIMING_VND1_N(11) | LCD_VERTTIMING_VND2_N(32),
569 .mode_clkcontrol = 0x00000000, /* /4=24Mhz */
570 .mode_pwmdiv = 0x8000063f,
571 .mode_pwmhi = 0x03400000,
572 .mode_outmask = 0x00fcfcfc,
573 .mode_fifoctrl = 0x2f2f2f2f,
574 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
575 .mode_backlight = 0x00000000,
576 .mode_auxpll = 8, /* 96MHz AUXPLL */
577 .device_init = board_au1200fb_panel_init,
578 .device_shutdown = board_au1200fb_panel_shutdown,
579 640, 480,
580 640, 480,
581 },
582
583 [7] = { /* Sharp 320x240 TFT */
584 .name = "Sharp_320x240_TFT",
585 .monspecs = {
586 .modedb = NULL,
587 .modedb_len = 0,
588 .hfmin = 12500,
589 .hfmax = 20000,
590 .vfmin = 38,
591 .vfmax = 81,
592 .dclkmin = 4500000,
593 .dclkmax = 6800000,
594 .input = FB_DISP_RGB,
595 },
596 .mode_screen = LCD_SCREEN_SX_N(320) |
597 LCD_SCREEN_SY_N(240),
598 .mode_horztiming = LCD_HORZTIMING_HPW_N(60) |
599 LCD_HORZTIMING_HND1_N(13) | LCD_HORZTIMING_HND2_N(2),
600 .mode_verttiming = LCD_VERTTIMING_VPW_N(2) |
601 LCD_VERTTIMING_VND1_N(2) | LCD_VERTTIMING_VND2_N(5),
602 .mode_clkcontrol = LCD_CLKCONTROL_PCD_N(7), /*16=6Mhz*/
603 .mode_pwmdiv = 0x8000063f,
604 .mode_pwmhi = 0x03400000,
605 .mode_outmask = 0x00fcfcfc,
606 .mode_fifoctrl = 0x2f2f2f2f,
607 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
608 .mode_backlight = 0x00000000,
609 .mode_auxpll = 8, /* 96MHz AUXPLL */
610 .device_init = board_au1200fb_panel_init,
611 .device_shutdown = board_au1200fb_panel_shutdown,
612 320, 320,
613 240, 240,
614 },
615
616 [8] = { /* Toppoly TD070WGCB2 7" 856x480 TFT */
617 .name = "Toppoly_TD070WGCB2",
618 .monspecs = {
619 .modedb = NULL,
620 .modedb_len = 0,
621 .hfmin = 30000,
622 .hfmax = 70000,
623 .vfmin = 60,
624 .vfmax = 60,
625 .dclkmin = 6000000,
626 .dclkmax = 28000000,
627 .input = FB_DISP_RGB,
628 },
629 .mode_screen = LCD_SCREEN_SX_N(856) |
630 LCD_SCREEN_SY_N(480),
631 .mode_horztiming = LCD_HORZTIMING_HND2_N(43) |
632 LCD_HORZTIMING_HND1_N(43) | LCD_HORZTIMING_HPW_N(114),
633 .mode_verttiming = LCD_VERTTIMING_VND2_N(20) |
634 LCD_VERTTIMING_VND1_N(21) | LCD_VERTTIMING_VPW_N(4),
635 .mode_clkcontrol = 0x00020001, /* /4=24Mhz */
636 .mode_pwmdiv = 0x8000063f,
637 .mode_pwmhi = 0x03400000,
638 .mode_outmask = 0x00fcfcfc,
639 .mode_fifoctrl = 0x2f2f2f2f,
640 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
641 .mode_backlight = 0x00000000,
642 .mode_auxpll = 8, /* 96MHz AUXPLL */
643 .device_init = board_au1200fb_panel_init,
644 .device_shutdown = board_au1200fb_panel_shutdown,
645 856, 856,
646 480, 480,
647 },
648};
649
650#define NUM_PANELS (ARRAY_SIZE(known_lcd_panels))
651
652/********************************************************************/
653
654#ifdef CONFIG_PM
655static int set_brightness(unsigned int brightness)
656{
657 unsigned int hi1, divider;
658
659 /* limit brightness pwm duty to >= 30/1600 */
660 if (brightness < 30) {
661 brightness = 30;
662 }
663 divider = (lcd->pwmdiv & 0x3FFFF) + 1;
664 hi1 = (lcd->pwmhi >> 16) + 1;
665 hi1 = (((brightness & 0xFF) + 1) * divider >> 8);
666 lcd->pwmhi &= 0xFFFF;
667 lcd->pwmhi |= (hi1 << 16);
668
669 return brightness;
670}
671#endif /* CONFIG_PM */
672
673static int winbpp (unsigned int winctrl1)
674{
675 int bits = 0;
676
677 /* how many bits are needed for each pixel format */
678 switch (winctrl1 & LCD_WINCTRL1_FRM) {
679 case LCD_WINCTRL1_FRM_1BPP:
680 bits = 1;
681 break;
682 case LCD_WINCTRL1_FRM_2BPP:
683 bits = 2;
684 break;
685 case LCD_WINCTRL1_FRM_4BPP:
686 bits = 4;
687 break;
688 case LCD_WINCTRL1_FRM_8BPP:
689 bits = 8;
690 break;
691 case LCD_WINCTRL1_FRM_12BPP:
692 case LCD_WINCTRL1_FRM_16BPP655:
693 case LCD_WINCTRL1_FRM_16BPP565:
694 case LCD_WINCTRL1_FRM_16BPP556:
695 case LCD_WINCTRL1_FRM_16BPPI1555:
696 case LCD_WINCTRL1_FRM_16BPPI5551:
697 case LCD_WINCTRL1_FRM_16BPPA1555:
698 case LCD_WINCTRL1_FRM_16BPPA5551:
699 bits = 16;
700 break;
701 case LCD_WINCTRL1_FRM_24BPP:
702 case LCD_WINCTRL1_FRM_32BPP:
703 bits = 32;
704 break;
705 }
706
707 return bits;
708}
709
710static int fbinfo2index (struct fb_info *fb_info)
711{
712 int i;
713
714 for (i = 0; i < CONFIG_FB_AU1200_DEVS; ++i) {
715 if (fb_info == (struct fb_info *)(&_au1200fb_devices[i].fb_info))
716 return i;
717 }
718 printk("au1200fb: ERROR: fbinfo2index failed!\n");
719 return -1;
720}
721
722static int au1200_setlocation (struct au1200fb_device *fbdev, int plane,
723 int xpos, int ypos)
724{
725 uint32 winctrl0, winctrl1, winenable, fb_offset = 0;
726 int xsz, ysz;
727
728 /* FIX!!! NOT CHECKING FOR COMPLETE OFFSCREEN YET */
729
730 winctrl0 = lcd->window[plane].winctrl0;
731 winctrl1 = lcd->window[plane].winctrl1;
732 winctrl0 &= (LCD_WINCTRL0_A | LCD_WINCTRL0_AEN);
733 winctrl1 &= ~(LCD_WINCTRL1_SZX | LCD_WINCTRL1_SZY);
734
735 /* Check for off-screen adjustments */
736 xsz = win->w[plane].xres;
737 ysz = win->w[plane].yres;
738 if ((xpos + win->w[plane].xres) > panel->Xres) {
739 /* Off-screen to the right */
740 xsz = panel->Xres - xpos; /* off by 1 ??? */
741 /*printk("off screen right\n");*/
742 }
743
744 if ((ypos + win->w[plane].yres) > panel->Yres) {
745 /* Off-screen to the bottom */
746 ysz = panel->Yres - ypos; /* off by 1 ??? */
747 /*printk("off screen bottom\n");*/
748 }
749
750 if (xpos < 0) {
751 /* Off-screen to the left */
752 xsz = win->w[plane].xres + xpos;
753 fb_offset += (((0 - xpos) * winbpp(lcd->window[plane].winctrl1))/8);
754 xpos = 0;
755 /*printk("off screen left\n");*/
756 }
757
758 if (ypos < 0) {
759 /* Off-screen to the top */
760 ysz = win->w[plane].yres + ypos;
761 /* fixme: fb_offset += ((0-ypos)*fb_pars[plane].line_length); */
762 ypos = 0;
763 /*printk("off screen top\n");*/
764 }
765
766 /* record settings */
767 win->w[plane].xpos = xpos;
768 win->w[plane].ypos = ypos;
769
770 xsz -= 1;
771 ysz -= 1;
772 winctrl0 |= (xpos << 21);
773 winctrl0 |= (ypos << 10);
774 winctrl1 |= (xsz << 11);
775 winctrl1 |= (ysz << 0);
776
777 /* Disable the window while making changes, then restore WINEN */
778 winenable = lcd->winenable & (1 << plane);
779 au_sync();
780 lcd->winenable &= ~(1 << plane);
781 lcd->window[plane].winctrl0 = winctrl0;
782 lcd->window[plane].winctrl1 = winctrl1;
783 lcd->window[plane].winbuf0 =
784 lcd->window[plane].winbuf1 = fbdev->fb_phys;
785 lcd->window[plane].winbufctrl = 0; /* select winbuf0 */
786 lcd->winenable |= winenable;
787 au_sync();
788
789 return 0;
790}
791
792static void au1200_setpanel (struct panel_settings *newpanel)
793{
794 /*
795 * Perform global setup/init of LCD controller
796 */
797 uint32 winenable;
798
799 /* Make sure all windows disabled */
800 winenable = lcd->winenable;
801 lcd->winenable = 0;
802 au_sync();
803 /*
804 * Ensure everything is disabled before reconfiguring
805 */
806 if (lcd->screen & LCD_SCREEN_SEN) {
807 /* Wait for vertical sync period */
808 lcd->intstatus = LCD_INT_SS;
809 while ((lcd->intstatus & LCD_INT_SS) == 0) {
810 au_sync();
811 }
812
813 lcd->screen &= ~LCD_SCREEN_SEN; /*disable the controller*/
814
815 do {
816 lcd->intstatus = lcd->intstatus; /*clear interrupts*/
817 au_sync();
818 /*wait for controller to shut down*/
819 } while ((lcd->intstatus & LCD_INT_SD) == 0);
820
821 /* Call shutdown of current panel (if up) */
822 /* this must occur last, because if an external clock is driving
823 the controller, the clock cannot be turned off before first
824 shutting down the controller.
825 */
826 if (panel->device_shutdown != NULL)
827 panel->device_shutdown();
828 }
829
830 /* Newpanel == NULL indicates a shutdown operation only */
831 if (newpanel == NULL)
832 return;
833
834 panel = newpanel;
835
836 printk("Panel(%s), %dx%d\n", panel->name, panel->Xres, panel->Yres);
837
838 /*
839 * Setup clocking if internal LCD clock source (assumes sys_auxpll valid)
840 */
841 if (!(panel->mode_clkcontrol & LCD_CLKCONTROL_EXT))
842 {
843 uint32 sys_clksrc;
844 au_writel(panel->mode_auxpll, SYS_AUXPLL);
845 sys_clksrc = au_readl(SYS_CLKSRC) & ~0x0000001f;
846 sys_clksrc |= panel->mode_toyclksrc;
847 au_writel(sys_clksrc, SYS_CLKSRC);
848 }
849
850 /*
851 * Configure panel timings
852 */
853 lcd->screen = panel->mode_screen;
854 lcd->horztiming = panel->mode_horztiming;
855 lcd->verttiming = panel->mode_verttiming;
856 lcd->clkcontrol = panel->mode_clkcontrol;
857 lcd->pwmdiv = panel->mode_pwmdiv;
858 lcd->pwmhi = panel->mode_pwmhi;
859 lcd->outmask = panel->mode_outmask;
860 lcd->fifoctrl = panel->mode_fifoctrl;
861 au_sync();
862
863 /* fixme: Check window settings to make sure still valid
864 * for new geometry */
865#if 0
866 au1200_setlocation(fbdev, 0, win->w[0].xpos, win->w[0].ypos);
867 au1200_setlocation(fbdev, 1, win->w[1].xpos, win->w[1].ypos);
868 au1200_setlocation(fbdev, 2, win->w[2].xpos, win->w[2].ypos);
869 au1200_setlocation(fbdev, 3, win->w[3].xpos, win->w[3].ypos);
870#endif
871 lcd->winenable = winenable;
872
873 /*
874 * Re-enable screen now that it is configured
875 */
876 lcd->screen |= LCD_SCREEN_SEN;
877 au_sync();
878
879 /* Call init of panel */
880 if (panel->device_init != NULL) panel->device_init();
881
882 /* FIX!!!! not appropriate on panel change!!! Global setup/init */
883 lcd->intenable = 0;
884 lcd->intstatus = ~0;
885 lcd->backcolor = win->mode_backcolor;
886
887 /* Setup Color Key - FIX!!! */
888 lcd->colorkey = win->mode_colorkey;
889 lcd->colorkeymsk = win->mode_colorkeymsk;
890
891 /* Setup HWCursor - FIX!!! Need to support this eventually */
892 lcd->hwc.cursorctrl = 0;
893 lcd->hwc.cursorpos = 0;
894 lcd->hwc.cursorcolor0 = 0;
895 lcd->hwc.cursorcolor1 = 0;
896 lcd->hwc.cursorcolor2 = 0;
897 lcd->hwc.cursorcolor3 = 0;
898
899
900#if 0
901#define D(X) printk("%25s: %08X\n", #X, X)
902 D(lcd->screen);
903 D(lcd->horztiming);
904 D(lcd->verttiming);
905 D(lcd->clkcontrol);
906 D(lcd->pwmdiv);
907 D(lcd->pwmhi);
908 D(lcd->outmask);
909 D(lcd->fifoctrl);
910 D(lcd->window[0].winctrl0);
911 D(lcd->window[0].winctrl1);
912 D(lcd->window[0].winctrl2);
913 D(lcd->window[0].winbuf0);
914 D(lcd->window[0].winbuf1);
915 D(lcd->window[0].winbufctrl);
916 D(lcd->window[1].winctrl0);
917 D(lcd->window[1].winctrl1);
918 D(lcd->window[1].winctrl2);
919 D(lcd->window[1].winbuf0);
920 D(lcd->window[1].winbuf1);
921 D(lcd->window[1].winbufctrl);
922 D(lcd->window[2].winctrl0);
923 D(lcd->window[2].winctrl1);
924 D(lcd->window[2].winctrl2);
925 D(lcd->window[2].winbuf0);
926 D(lcd->window[2].winbuf1);
927 D(lcd->window[2].winbufctrl);
928 D(lcd->window[3].winctrl0);
929 D(lcd->window[3].winctrl1);
930 D(lcd->window[3].winctrl2);
931 D(lcd->window[3].winbuf0);
932 D(lcd->window[3].winbuf1);
933 D(lcd->window[3].winbufctrl);
934 D(lcd->winenable);
935 D(lcd->intenable);
936 D(lcd->intstatus);
937 D(lcd->backcolor);
938 D(lcd->winenable);
939 D(lcd->colorkey);
940 D(lcd->colorkeymsk);
941 D(lcd->hwc.cursorctrl);
942 D(lcd->hwc.cursorpos);
943 D(lcd->hwc.cursorcolor0);
944 D(lcd->hwc.cursorcolor1);
945 D(lcd->hwc.cursorcolor2);
946 D(lcd->hwc.cursorcolor3);
947#endif
948}
949
950static void au1200_setmode(struct au1200fb_device *fbdev)
951{
952 int plane = fbdev->plane;
953 /* Window/plane setup */
954 lcd->window[plane].winctrl1 = ( 0
955 | LCD_WINCTRL1_PRI_N(plane)
956 | win->w[plane].mode_winctrl1 /* FRM,CCO,PO,PIPE */
957 ) ;
958
959 au1200_setlocation(fbdev, plane, win->w[plane].xpos, win->w[plane].ypos);
960
961 lcd->window[plane].winctrl2 = ( 0
962 | LCD_WINCTRL2_CKMODE_00
963 | LCD_WINCTRL2_DBM
964 | LCD_WINCTRL2_BX_N( fbdev->fb_info.fix.line_length)
965 | LCD_WINCTRL2_SCX_1
966 | LCD_WINCTRL2_SCY_1
967 ) ;
968 lcd->winenable |= win->w[plane].mode_winenable;
969 au_sync();
970}
971
972
973/* Inline helpers */
974
975/*#define panel_is_dual(panel) ((panel->mode_screen & LCD_SCREEN_PT) == LCD_SCREEN_PT_010)*/
976/*#define panel_is_active(panel)((panel->mode_screen & LCD_SCREEN_PT) == LCD_SCREEN_PT_010)*/
977
978#define panel_is_color(panel) ((panel->mode_screen & LCD_SCREEN_PT) <= LCD_SCREEN_PT_CDSTN)
979
980/* Bitfields format supported by the controller. */
981static struct fb_bitfield rgb_bitfields[][4] = {
982 /* Red, Green, Blue, Transp */
983 [LCD_WINCTRL1_FRM_16BPP655 >> 25] =
984 { { 10, 6, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
985
986 [LCD_WINCTRL1_FRM_16BPP565 >> 25] =
987 { { 11, 5, 0 }, { 5, 6, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
988
989 [LCD_WINCTRL1_FRM_16BPP556 >> 25] =
990 { { 11, 5, 0 }, { 6, 5, 0 }, { 0, 6, 0 }, { 0, 0, 0 } },
991
992 [LCD_WINCTRL1_FRM_16BPPI1555 >> 25] =
993 { { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
994
995 [LCD_WINCTRL1_FRM_16BPPI5551 >> 25] =
996 { { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 0, 0 } },
997
998 [LCD_WINCTRL1_FRM_16BPPA1555 >> 25] =
999 { { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 15, 1, 0 } },
1000
1001 [LCD_WINCTRL1_FRM_16BPPA5551 >> 25] =
1002 { { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 1, 0 } },
1003
1004 [LCD_WINCTRL1_FRM_24BPP >> 25] =
1005 { { 16, 8, 0 }, { 8, 8, 0 }, { 0, 8, 0 }, { 0, 0, 0 } },
1006
1007 [LCD_WINCTRL1_FRM_32BPP >> 25] =
1008 { { 16, 8, 0 }, { 8, 8, 0 }, { 0, 8, 0 }, { 24, 0, 0 } },
1009};
1010
1011/*-------------------------------------------------------------------------*/
1012
1013/* Helpers */
1014
1015static void au1200fb_update_fbinfo(struct fb_info *fbi)
1016{
1017 /* FIX!!!! This also needs to take the window pixel format into account!!! */
1018
1019 /* Update var-dependent FB info */
1020 if (panel_is_color(panel)) {
1021 if (fbi->var.bits_per_pixel <= 8) {
1022 /* palettized */
1023 fbi->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1024 fbi->fix.line_length = fbi->var.xres_virtual /
1025 (8/fbi->var.bits_per_pixel);
1026 } else {
1027 /* non-palettized */
1028 fbi->fix.visual = FB_VISUAL_TRUECOLOR;
1029 fbi->fix.line_length = fbi->var.xres_virtual * (fbi->var.bits_per_pixel / 8);
1030 }
1031 } else {
1032 /* mono FIX!!! mono 8 and 4 bits */
1033 fbi->fix.visual = FB_VISUAL_MONO10;
1034 fbi->fix.line_length = fbi->var.xres_virtual / 8;
1035 }
1036
1037 fbi->screen_size = fbi->fix.line_length * fbi->var.yres_virtual;
1038 print_dbg("line length: %d\n", fbi->fix.line_length);
1039 print_dbg("bits_per_pixel: %d\n", fbi->var.bits_per_pixel);
1040}
1041
1042/*-------------------------------------------------------------------------*/
1043
1044/* AU1200 framebuffer driver */
1045
1046/* fb_check_var
1047 * Validate var settings with hardware restrictions and modify it if necessary
1048 */
1049static int au1200fb_fb_check_var(struct fb_var_screeninfo *var,
1050 struct fb_info *fbi)
1051{
1052 struct au1200fb_device *fbdev = (struct au1200fb_device *)fbi;
1053 u32 pixclock;
1054 int screen_size, plane;
1055
1056 plane = fbdev->plane;
1057
1058 /* Make sure that the mode respect all LCD controller and
1059 * panel restrictions. */
1060 var->xres = win->w[plane].xres;
1061 var->yres = win->w[plane].yres;
1062
1063 /* No need for virtual resolution support */
1064 var->xres_virtual = var->xres;
1065 var->yres_virtual = var->yres;
1066
1067 var->bits_per_pixel = winbpp(win->w[plane].mode_winctrl1);
1068
1069 screen_size = var->xres_virtual * var->yres_virtual;
1070 if (var->bits_per_pixel > 8) screen_size *= (var->bits_per_pixel / 8);
1071 else screen_size /= (8/var->bits_per_pixel);
1072
1073 if (fbdev->fb_len < screen_size)
1074 return -EINVAL; /* Virtual screen is to big, abort */
1075
1076 /* FIX!!!! what are the implicaitons of ignoring this for windows ??? */
1077 /* The max LCD clock is fixed to 48MHz (value of AUX_CLK). The pixel
1078 * clock can only be obtain by dividing this value by an even integer.
1079 * Fallback to a slower pixel clock if necessary. */
1080 pixclock = max((u32)(PICOS2KHZ(var->pixclock) * 1000), fbi->monspecs.dclkmin);
1081 pixclock = min(pixclock, min(fbi->monspecs.dclkmax, (u32)AU1200_LCD_MAX_CLK/2));
1082
1083 if (AU1200_LCD_MAX_CLK % pixclock) {
1084 int diff = AU1200_LCD_MAX_CLK % pixclock;
1085 pixclock -= diff;
1086 }
1087
1088 var->pixclock = KHZ2PICOS(pixclock/1000);
1089#if 0
1090 if (!panel_is_active(panel)) {
1091 int pcd = AU1200_LCD_MAX_CLK / (pixclock * 2) - 1;
1092
1093 if (!panel_is_color(panel)
1094 && (panel->control_base & LCD_CONTROL_MPI) && (pcd < 3)) {
1095 /* STN 8bit mono panel support is up to 6MHz pixclock */
1096 var->pixclock = KHZ2PICOS(6000);
1097 } else if (!pcd) {
1098 /* Other STN panel support is up to 12MHz */
1099 var->pixclock = KHZ2PICOS(12000);
1100 }
1101 }
1102#endif
1103 /* Set bitfield accordingly */
1104 switch (var->bits_per_pixel) {
1105 case 16:
1106 {
1107 /* 16bpp True color.
1108 * These must be set to MATCH WINCTRL[FORM] */
1109 int idx;
1110 idx = (win->w[0].mode_winctrl1 & LCD_WINCTRL1_FRM) >> 25;
1111 var->red = rgb_bitfields[idx][0];
1112 var->green = rgb_bitfields[idx][1];
1113 var->blue = rgb_bitfields[idx][2];
1114 var->transp = rgb_bitfields[idx][3];
1115 break;
1116 }
1117
1118 case 32:
1119 {
1120 /* 32bpp True color.
1121 * These must be set to MATCH WINCTRL[FORM] */
1122 int idx;
1123 idx = (win->w[0].mode_winctrl1 & LCD_WINCTRL1_FRM) >> 25;
1124 var->red = rgb_bitfields[idx][0];
1125 var->green = rgb_bitfields[idx][1];
1126 var->blue = rgb_bitfields[idx][2];
1127 var->transp = rgb_bitfields[idx][3];
1128 break;
1129 }
1130 default:
1131 print_dbg("Unsupported depth %dbpp", var->bits_per_pixel);
1132 return -EINVAL;
1133 }
1134
1135 return 0;
1136}
1137
1138/* fb_set_par
1139 * Set hardware with var settings. This will enable the controller with a
1140 * specific mode, normally validated with the fb_check_var method
1141 */
1142static int au1200fb_fb_set_par(struct fb_info *fbi)
1143{
1144 struct au1200fb_device *fbdev = (struct au1200fb_device *)fbi;
1145
1146 au1200fb_update_fbinfo(fbi);
1147 au1200_setmode(fbdev);
1148
1149 return 0;
1150}
1151
1152/* fb_setcolreg
1153 * Set color in LCD palette.
1154 */
1155static int au1200fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green,
1156 unsigned blue, unsigned transp, struct fb_info *fbi)
1157{
1158 volatile u32 *palette = lcd->palette;
1159 u32 value;
1160
1161 if (regno > (AU1200_LCD_NBR_PALETTE_ENTRIES - 1))
1162 return -EINVAL;
1163
1164 if (fbi->var.grayscale) {
1165 /* Convert color to grayscale */
1166 red = green = blue =
1167 (19595 * red + 38470 * green + 7471 * blue) >> 16;
1168 }
1169
1170 if (fbi->fix.visual == FB_VISUAL_TRUECOLOR) {
1171 /* Place color in the pseudopalette */
1172 if (regno > 16)
1173 return -EINVAL;
1174
1175 palette = (u32*) fbi->pseudo_palette;
1176
1177 red >>= (16 - fbi->var.red.length);
1178 green >>= (16 - fbi->var.green.length);
1179 blue >>= (16 - fbi->var.blue.length);
1180
1181 value = (red << fbi->var.red.offset) |
1182 (green << fbi->var.green.offset)|
1183 (blue << fbi->var.blue.offset);
1184 value &= 0xFFFF;
1185
1186 } else if (1 /*FIX!!! panel_is_active(fbdev->panel)*/) {
1187 /* COLOR TFT PALLETTIZED (use RGB 565) */
1188 value = (red & 0xF800)|((green >> 5) &
1189 0x07E0)|((blue >> 11) & 0x001F);
1190 value &= 0xFFFF;
1191
1192 } else if (0 /*panel_is_color(fbdev->panel)*/) {
1193 /* COLOR STN MODE */
1194 value = 0x1234;
1195 value &= 0xFFF;
1196 } else {
1197 /* MONOCHROME MODE */
1198 value = (green >> 12) & 0x000F;
1199 value &= 0xF;
1200 }
1201
1202 palette[regno] = value;
1203
1204 return 0;
1205}
1206
1207/* fb_blank
1208 * Blank the screen. Depending on the mode, the screen will be
1209 * activated with the backlight color, or desactivated
1210 */
1211static int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi)
1212{
1213 /* Short-circuit screen blanking */
1214 if (noblanking)
1215 return 0;
1216
1217 switch (blank_mode) {
1218
1219 case FB_BLANK_UNBLANK:
1220 case FB_BLANK_NORMAL:
1221 /* printk("turn on panel\n"); */
1222 au1200_setpanel(panel);
1223 break;
1224 case FB_BLANK_VSYNC_SUSPEND:
1225 case FB_BLANK_HSYNC_SUSPEND:
1226 case FB_BLANK_POWERDOWN:
1227 /* printk("turn off panel\n"); */
1228 au1200_setpanel(NULL);
1229 break;
1230 default:
1231 break;
1232
1233 }
1234
1235 /* FB_BLANK_NORMAL is a soft blank */
1236 return (blank_mode == FB_BLANK_NORMAL) ? -EINVAL : 0;
1237}
1238
1239/* fb_mmap
1240 * Map video memory in user space. We don't use the generic fb_mmap
1241 * method mainly to allow the use of the TLB streaming flag (CCA=6)
1242 */
1243static int au1200fb_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1244
1245{
1246 unsigned int len;
1247 unsigned long start=0, off;
1248 struct au1200fb_device *fbdev = (struct au1200fb_device *) info;
1249
1250#ifdef CONFIG_PM
1251 au1xxx_pm_access(LCD_pm_dev);
1252#endif
1253
1254 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) {
1255 return -EINVAL;
1256 }
1257
1258 start = fbdev->fb_phys & PAGE_MASK;
1259 len = PAGE_ALIGN((start & ~PAGE_MASK) + fbdev->fb_len);
1260
1261 off = vma->vm_pgoff << PAGE_SHIFT;
1262
1263 if ((vma->vm_end - vma->vm_start + off) > len) {
1264 return -EINVAL;
1265 }
1266
1267 off += start;
1268 vma->vm_pgoff = off >> PAGE_SHIFT;
1269
1270 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1271 pgprot_val(vma->vm_page_prot) |= _CACHE_MASK; /* CCA=7 */
1272
1273 vma->vm_flags |= VM_IO;
1274
1275 return io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
1276 vma->vm_end - vma->vm_start,
1277 vma->vm_page_prot);
1278
1279 return 0;
1280}
1281
1282static void set_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata)
1283{
1284
1285 unsigned int hi1, divider;
1286
1287 /* SCREEN_SIZE: user cannot reset size, must switch panel choice */
1288
1289 if (pdata->flags & SCREEN_BACKCOLOR)
1290 lcd->backcolor = pdata->backcolor;
1291
1292 if (pdata->flags & SCREEN_BRIGHTNESS) {
1293
1294 // limit brightness pwm duty to >= 30/1600
1295 if (pdata->brightness < 30) {
1296 pdata->brightness = 30;
1297 }
1298 divider = (lcd->pwmdiv & 0x3FFFF) + 1;
1299 hi1 = (lcd->pwmhi >> 16) + 1;
1300 hi1 = (((pdata->brightness & 0xFF)+1) * divider >> 8);
1301 lcd->pwmhi &= 0xFFFF;
1302 lcd->pwmhi |= (hi1 << 16);
1303 }
1304
1305 if (pdata->flags & SCREEN_COLORKEY)
1306 lcd->colorkey = pdata->colorkey;
1307
1308 if (pdata->flags & SCREEN_MASK)
1309 lcd->colorkeymsk = pdata->mask;
1310 au_sync();
1311}
1312
1313static void get_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata)
1314{
1315 unsigned int hi1, divider;
1316
1317 pdata->xsize = ((lcd->screen & LCD_SCREEN_SX) >> 19) + 1;
1318 pdata->ysize = ((lcd->screen & LCD_SCREEN_SY) >> 8) + 1;
1319
1320 pdata->backcolor = lcd->backcolor;
1321 pdata->colorkey = lcd->colorkey;
1322 pdata->mask = lcd->colorkeymsk;
1323
1324 // brightness
1325 hi1 = (lcd->pwmhi >> 16) + 1;
1326 divider = (lcd->pwmdiv & 0x3FFFF) + 1;
1327 pdata->brightness = ((hi1 << 8) / divider) - 1;
1328 au_sync();
1329}
1330
1331static void set_window(unsigned int plane,
1332 struct au1200_lcd_window_regs_t *pdata)
1333{
1334 unsigned int val, bpp;
1335
1336 /* Window control register 0 */
1337 if (pdata->flags & WIN_POSITION) {
1338 val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_OX |
1339 LCD_WINCTRL0_OY);
1340 val |= ((pdata->xpos << 21) & LCD_WINCTRL0_OX);
1341 val |= ((pdata->ypos << 10) & LCD_WINCTRL0_OY);
1342 lcd->window[plane].winctrl0 = val;
1343 }
1344 if (pdata->flags & WIN_ALPHA_COLOR) {
1345 val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_A);
1346 val |= ((pdata->alpha_color << 2) & LCD_WINCTRL0_A);
1347 lcd->window[plane].winctrl0 = val;
1348 }
1349 if (pdata->flags & WIN_ALPHA_MODE) {
1350 val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_AEN);
1351 val |= ((pdata->alpha_mode << 1) & LCD_WINCTRL0_AEN);
1352 lcd->window[plane].winctrl0 = val;
1353 }
1354
1355 /* Window control register 1 */
1356 if (pdata->flags & WIN_PRIORITY) {
1357 val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PRI);
1358 val |= ((pdata->priority << 30) & LCD_WINCTRL1_PRI);
1359 lcd->window[plane].winctrl1 = val;
1360 }
1361 if (pdata->flags & WIN_CHANNEL) {
1362 val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PIPE);
1363 val |= ((pdata->channel << 29) & LCD_WINCTRL1_PIPE);
1364 lcd->window[plane].winctrl1 = val;
1365 }
1366 if (pdata->flags & WIN_BUFFER_FORMAT) {
1367 val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_FRM);
1368 val |= ((pdata->buffer_format << 25) & LCD_WINCTRL1_FRM);
1369 lcd->window[plane].winctrl1 = val;
1370 }
1371 if (pdata->flags & WIN_COLOR_ORDER) {
1372 val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_CCO);
1373 val |= ((pdata->color_order << 24) & LCD_WINCTRL1_CCO);
1374 lcd->window[plane].winctrl1 = val;
1375 }
1376 if (pdata->flags & WIN_PIXEL_ORDER) {
1377 val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PO);
1378 val |= ((pdata->pixel_order << 22) & LCD_WINCTRL1_PO);
1379 lcd->window[plane].winctrl1 = val;
1380 }
1381 if (pdata->flags & WIN_SIZE) {
1382 val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_SZX |
1383 LCD_WINCTRL1_SZY);
1384 val |= (((pdata->xsize << 11) - 1) & LCD_WINCTRL1_SZX);
1385 val |= (((pdata->ysize) - 1) & LCD_WINCTRL1_SZY);
1386 lcd->window[plane].winctrl1 = val;
1387 /* program buffer line width */
1388 bpp = winbpp(val) / 8;
1389 val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_BX);
1390 val |= (((pdata->xsize * bpp) << 8) & LCD_WINCTRL2_BX);
1391 lcd->window[plane].winctrl2 = val;
1392 }
1393
1394 /* Window control register 2 */
1395 if (pdata->flags & WIN_COLORKEY_MODE) {
1396 val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_CKMODE);
1397 val |= ((pdata->colorkey_mode << 24) & LCD_WINCTRL2_CKMODE);
1398 lcd->window[plane].winctrl2 = val;
1399 }
1400 if (pdata->flags & WIN_DOUBLE_BUFFER_MODE) {
1401 val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_DBM);
1402 val |= ((pdata->double_buffer_mode << 23) & LCD_WINCTRL2_DBM);
1403 lcd->window[plane].winctrl2 = val;
1404 }
1405 if (pdata->flags & WIN_RAM_ARRAY_MODE) {
1406 val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_RAM);
1407 val |= ((pdata->ram_array_mode << 21) & LCD_WINCTRL2_RAM);
1408 lcd->window[plane].winctrl2 = val;
1409 }
1410
1411 /* Buffer line width programmed with WIN_SIZE */
1412
1413 if (pdata->flags & WIN_BUFFER_SCALE) {
1414 val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_SCX |
1415 LCD_WINCTRL2_SCY);
1416 val |= ((pdata->xsize << 11) & LCD_WINCTRL2_SCX);
1417 val |= ((pdata->ysize) & LCD_WINCTRL2_SCY);
1418 lcd->window[plane].winctrl2 = val;
1419 }
1420
1421 if (pdata->flags & WIN_ENABLE) {
1422 val = lcd->winenable;
1423 val &= ~(1<<plane);
1424 val |= (pdata->enable & 1) << plane;
1425 lcd->winenable = val;
1426 }
1427 au_sync();
1428}
1429
1430static void get_window(unsigned int plane,
1431 struct au1200_lcd_window_regs_t *pdata)
1432{
1433 /* Window control register 0 */
1434 pdata->xpos = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_OX) >> 21;
1435 pdata->ypos = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_OY) >> 10;
1436 pdata->alpha_color = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_A) >> 2;
1437 pdata->alpha_mode = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_AEN) >> 1;
1438
1439 /* Window control register 1 */
1440 pdata->priority = (lcd->window[plane].winctrl1& LCD_WINCTRL1_PRI) >> 30;
1441 pdata->channel = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_PIPE) >> 29;
1442 pdata->buffer_format = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_FRM) >> 25;
1443 pdata->color_order = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_CCO) >> 24;
1444 pdata->pixel_order = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_PO) >> 22;
1445 pdata->xsize = ((lcd->window[plane].winctrl1 & LCD_WINCTRL1_SZX) >> 11) + 1;
1446 pdata->ysize = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_SZY) + 1;
1447
1448 /* Window control register 2 */
1449 pdata->colorkey_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_CKMODE) >> 24;
1450 pdata->double_buffer_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_DBM) >> 23;
1451 pdata->ram_array_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_RAM) >> 21;
1452
1453 pdata->enable = (lcd->winenable >> plane) & 1;
1454 au_sync();
1455}
1456
1457static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd,
1458 unsigned long arg)
1459{
1460 int plane;
1461 int val;
1462
1463#ifdef CONFIG_PM
1464 au1xxx_pm_access(LCD_pm_dev);
1465#endif
1466
1467 plane = fbinfo2index(info);
1468 print_dbg("au1200fb: ioctl %d on plane %d\n", cmd, plane);
1469
1470 if (cmd == AU1200_LCD_FB_IOCTL) {
1471 struct au1200_lcd_iodata_t iodata;
1472
1473 if (copy_from_user(&iodata, (void __user *) arg, sizeof(iodata)))
1474 return -EFAULT;
1475
1476 print_dbg("FB IOCTL called\n");
1477
1478 switch (iodata.subcmd) {
1479 case AU1200_LCD_SET_SCREEN:
1480 print_dbg("AU1200_LCD_SET_SCREEN\n");
1481 set_global(cmd, &iodata.global);
1482 break;
1483
1484 case AU1200_LCD_GET_SCREEN:
1485 print_dbg("AU1200_LCD_GET_SCREEN\n");
1486 get_global(cmd, &iodata.global);
1487 break;
1488
1489 case AU1200_LCD_SET_WINDOW:
1490 print_dbg("AU1200_LCD_SET_WINDOW\n");
1491 set_window(plane, &iodata.window);
1492 break;
1493
1494 case AU1200_LCD_GET_WINDOW:
1495 print_dbg("AU1200_LCD_GET_WINDOW\n");
1496 get_window(plane, &iodata.window);
1497 break;
1498
1499 case AU1200_LCD_SET_PANEL:
1500 print_dbg("AU1200_LCD_SET_PANEL\n");
1501 if ((iodata.global.panel_choice >= 0) &&
1502 (iodata.global.panel_choice <
1503 NUM_PANELS))
1504 {
1505 struct panel_settings *newpanel;
1506 panel_index = iodata.global.panel_choice;
1507 newpanel = &known_lcd_panels[panel_index];
1508 au1200_setpanel(newpanel);
1509 }
1510 break;
1511
1512 case AU1200_LCD_GET_PANEL:
1513 print_dbg("AU1200_LCD_GET_PANEL\n");
1514 iodata.global.panel_choice = panel_index;
1515 break;
1516
1517 default:
1518 return -EINVAL;
1519 }
1520
1521 val = copy_to_user((void __user *) arg, &iodata, sizeof(iodata));
1522 if (val) {
1523 print_dbg("error: could not copy %d bytes\n", val);
1524 return -EFAULT;
1525 }
1526 }
1527
1528 return 0;
1529}
1530
1531
1532static struct fb_ops au1200fb_fb_ops = {
1533 .owner = THIS_MODULE,
1534 .fb_check_var = au1200fb_fb_check_var,
1535 .fb_set_par = au1200fb_fb_set_par,
1536 .fb_setcolreg = au1200fb_fb_setcolreg,
1537 .fb_blank = au1200fb_fb_blank,
1538 .fb_fillrect = cfb_fillrect,
1539 .fb_copyarea = cfb_copyarea,
1540 .fb_imageblit = cfb_imageblit,
1541 .fb_sync = NULL,
1542 .fb_ioctl = au1200fb_ioctl,
1543 .fb_mmap = au1200fb_fb_mmap,
1544};
1545
1546/*-------------------------------------------------------------------------*/
1547
1548static irqreturn_t au1200fb_handle_irq(int irq, void* dev_id, struct pt_regs *regs)
1549{
1550 /* Nothing to do for now, just clear any pending interrupt */
1551 lcd->intstatus = lcd->intstatus;
1552 au_sync();
1553
1554 return IRQ_HANDLED;
1555}
1556
1557/*-------------------------------------------------------------------------*/
1558
1559/* AU1200 LCD device probe helpers */
1560
1561static int au1200fb_init_fbinfo(struct au1200fb_device *fbdev)
1562{
1563 struct fb_info *fbi = &fbdev->fb_info;
1564 int bpp;
1565
1566 memset(fbi, 0, sizeof(struct fb_info));
1567 fbi->fbops = &au1200fb_fb_ops;
1568
1569 bpp = winbpp(win->w[fbdev->plane].mode_winctrl1);
1570
1571 /* Copy monitor specs from panel data */
1572 /* fixme: we're setting up LCD controller windows, so these dont give a
1573 damn as to what the monitor specs are (the panel itself does, but that
1574 isnt done here...so maybe need a generic catchall monitor setting??? */
1575 memcpy(&fbi->monspecs, &panel->monspecs, sizeof(struct fb_monspecs));
1576
1577 /* We first try the user mode passed in argument. If that failed,
1578 * or if no one has been specified, we default to the first mode of the
1579 * panel list. Note that after this call, var data will be set */
1580 if (!fb_find_mode(&fbi->var,
1581 fbi,
1582 NULL, /* drv_info.opt_mode, */
1583 fbi->monspecs.modedb,
1584 fbi->monspecs.modedb_len,
1585 fbi->monspecs.modedb,
1586 bpp)) {
1587
1588 print_err("Cannot find valid mode for panel %s", panel->name);
1589 return -EFAULT;
1590 }
1591
1592 fbi->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
1593 if (!fbi->pseudo_palette) {
1594 return -ENOMEM;
1595 }
1596 memset(fbi->pseudo_palette, 0, sizeof(u32) * 16);
1597
1598 if (fb_alloc_cmap(&fbi->cmap, AU1200_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
1599 print_err("Fail to allocate colormap (%d entries)",
1600 AU1200_LCD_NBR_PALETTE_ENTRIES);
1601 kfree(fbi->pseudo_palette);
1602 return -EFAULT;
1603 }
1604
1605 strncpy(fbi->fix.id, "AU1200", sizeof(fbi->fix.id));
1606 fbi->fix.smem_start = fbdev->fb_phys;
1607 fbi->fix.smem_len = fbdev->fb_len;
1608 fbi->fix.type = FB_TYPE_PACKED_PIXELS;
1609 fbi->fix.xpanstep = 0;
1610 fbi->fix.ypanstep = 0;
1611 fbi->fix.mmio_start = 0;
1612 fbi->fix.mmio_len = 0;
1613 fbi->fix.accel = FB_ACCEL_NONE;
1614
1615 fbi->screen_base = (char __iomem *) fbdev->fb_mem;
1616
1617 au1200fb_update_fbinfo(fbi);
1618
1619 return 0;
1620}
1621
1622/*-------------------------------------------------------------------------*/
1623
1624/* AU1200 LCD controller device driver */
1625
1626static int au1200fb_drv_probe(struct device *dev)
1627{
1628 struct au1200fb_device *fbdev;
1629 unsigned long page;
1630 int bpp, plane, ret;
1631
1632 if (!dev)
1633 return -EINVAL;
1634
1635 for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane) {
1636 bpp = winbpp(win->w[plane].mode_winctrl1);
1637 if (win->w[plane].xres == 0)
1638 win->w[plane].xres = panel->Xres;
1639 if (win->w[plane].yres == 0)
1640 win->w[plane].yres = panel->Yres;
1641
1642 fbdev = &_au1200fb_devices[plane];
1643 memset(fbdev, 0, sizeof(struct au1200fb_device));
1644 fbdev->plane = plane;
1645
1646 /* Allocate the framebuffer to the maximum screen size */
1647 fbdev->fb_len = (win->w[plane].xres * win->w[plane].yres * bpp) / 8;
1648
1649 fbdev->fb_mem = dma_alloc_noncoherent(dev,
1650 PAGE_ALIGN(fbdev->fb_len),
1651 &fbdev->fb_phys, GFP_KERNEL);
1652 if (!fbdev->fb_mem) {
1653 print_err("fail to allocate frambuffer (size: %dK))",
1654 fbdev->fb_len / 1024);
1655 return -ENOMEM;
1656 }
1657
1658 /*
1659 * Set page reserved so that mmap will work. This is necessary
1660 * since we'll be remapping normal memory.
1661 */
1662 for (page = (unsigned long)fbdev->fb_phys;
1663 page < PAGE_ALIGN((unsigned long)fbdev->fb_phys +
1664 fbdev->fb_len);
1665 page += PAGE_SIZE) {
1666 SetPageReserved(pfn_to_page(page >> PAGE_SHIFT)); /* LCD DMA is NOT coherent on Au1200 */
1667 }
1668 print_dbg("Framebuffer memory map at %p", fbdev->fb_mem);
1669 print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024);
1670
1671 /* Init FB data */
1672 if ((ret = au1200fb_init_fbinfo(fbdev)) < 0)
1673 goto failed;
1674
1675 /* Register new framebuffer */
1676 if ((ret = register_framebuffer(&fbdev->fb_info)) < 0) {
1677 print_err("cannot register new framebuffer");
1678 goto failed;
1679 }
1680
1681 au1200fb_fb_set_par(&fbdev->fb_info);
1682
1683#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
1684 if (plane == 0)
1685 if (fb_prepare_logo(&fbdev->fb_info, FB_ROTATE_UR)) {
1686 /* Start display and show logo on boot */
1687 fb_set_cmap(&fbdev->fb_info.cmap,
1688 &fbdev->fb_info);
1689
1690 fb_show_logo(&fbdev->fb_info, FB_ROTATE_UR);
1691 }
1692#endif
1693 }
1694
1695 /* Now hook interrupt too */
1696 if ((ret = request_irq(AU1200_LCD_INT, au1200fb_handle_irq,
1697 SA_INTERRUPT | SA_SHIRQ, "lcd", (void *)dev)) < 0) {
1698 print_err("fail to request interrupt line %d (err: %d)",
1699 AU1200_LCD_INT, ret);
1700 goto failed;
1701 }
1702
1703 return 0;
1704
1705failed:
1706 /* NOTE: This only does the current plane/window that failed; others are still active */
1707 if (fbdev->fb_mem)
1708 dma_free_noncoherent(dev, PAGE_ALIGN(fbdev->fb_len),
1709 fbdev->fb_mem, fbdev->fb_phys);
1710 if (fbdev->fb_info.cmap.len != 0)
1711 fb_dealloc_cmap(&fbdev->fb_info.cmap);
1712 if (fbdev->fb_info.pseudo_palette)
1713 kfree(fbdev->fb_info.pseudo_palette);
1714 if (plane == 0)
1715 free_irq(AU1200_LCD_INT, (void*)dev);
1716 return ret;
1717}
1718
1719static int au1200fb_drv_remove(struct device *dev)
1720{
1721 struct au1200fb_device *fbdev;
1722 int plane;
1723
1724 if (!dev)
1725 return -ENODEV;
1726
1727 /* Turn off the panel */
1728 au1200_setpanel(NULL);
1729
1730 for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane)
1731 {
1732 fbdev = &_au1200fb_devices[plane];
1733
1734 /* Clean up all probe data */
1735 unregister_framebuffer(&fbdev->fb_info);
1736 if (fbdev->fb_mem)
1737 dma_free_noncoherent(dev, PAGE_ALIGN(fbdev->fb_len),
1738 fbdev->fb_mem, fbdev->fb_phys);
1739 if (fbdev->fb_info.cmap.len != 0)
1740 fb_dealloc_cmap(&fbdev->fb_info.cmap);
1741 if (fbdev->fb_info.pseudo_palette)
1742 kfree(fbdev->fb_info.pseudo_palette);
1743 }
1744
1745 free_irq(AU1200_LCD_INT, (void *)dev);
1746
1747 return 0;
1748}
1749
1750#ifdef CONFIG_PM
1751static int au1200fb_drv_suspend(struct device *dev, u32 state, u32 level)
1752{
1753 /* TODO */
1754 return 0;
1755}
1756
1757static int au1200fb_drv_resume(struct device *dev, u32 level)
1758{
1759 /* TODO */
1760 return 0;
1761}
1762#endif /* CONFIG_PM */
1763
1764static struct device_driver au1200fb_driver = {
1765 .name = "au1200-lcd",
1766 .bus = &platform_bus_type,
1767 .probe = au1200fb_drv_probe,
1768 .remove = au1200fb_drv_remove,
1769#ifdef CONFIG_PM
1770 .suspend = au1200fb_drv_suspend,
1771 .resume = au1200fb_drv_resume,
1772#endif
1773};
1774
1775/*-------------------------------------------------------------------------*/
1776
1777/* Kernel driver */
1778
1779static void au1200fb_setup(void)
1780{
1781 char* options = NULL;
1782 char* this_opt;
1783 int num_panels = ARRAY_SIZE(known_lcd_panels);
1784 int panel_idx = -1;
1785
1786 fb_get_options(DRIVER_NAME, &options);
1787
1788 if (options) {
1789 while ((this_opt = strsep(&options,",")) != NULL) {
1790 /* Panel option - can be panel name,
1791 * "bs" for board-switch, or number/index */
1792 if (!strncmp(this_opt, "panel:", 6)) {
1793 int i;
1794 long int li;
1795 char *endptr;
1796 this_opt += 6;
1797 /* First check for index, which allows
1798 * to short circuit this mess */
1799 li = simple_strtol(this_opt, &endptr, 0);
1800 if (*endptr == '\0') {
1801 panel_idx = (int)li;
1802 }
1803 else if (strcmp(this_opt, "bs") == 0) {
1804 extern int board_au1200fb_panel(void);
1805 panel_idx = board_au1200fb_panel();
1806 }
1807
1808 else
1809 for (i = 0; i < num_panels; i++) {
1810 if (!strcmp(this_opt, known_lcd_panels[i].name)) {
1811 panel_idx = i;
1812 break;
1813 }
1814 }
1815
1816 if ((panel_idx < 0) || (panel_idx >= num_panels)) {
1817 print_warn("Panel %s not supported!", this_opt);
1818 }
1819 else
1820 panel_index = panel_idx;
1821 }
1822
1823 else if (strncmp(this_opt, "nohwcursor", 10) == 0) {
1824 nohwcursor = 1;
1825 }
1826
1827 /* Unsupported option */
1828 else {
1829 print_warn("Unsupported option \"%s\"", this_opt);
1830 }
1831 }
1832 }
1833}
1834
1835#ifdef CONFIG_PM
1836static int au1200fb_pm_callback(au1xxx_power_dev_t *dev,
1837 au1xxx_request_t request, void *data) {
1838 int retval = -1;
1839 unsigned int d = 0;
1840 unsigned int brightness = 0;
1841
1842 if (request == AU1XXX_PM_SLEEP) {
1843 board_au1200fb_panel_shutdown();
1844 }
1845 else if (request == AU1XXX_PM_WAKEUP) {
1846 if(dev->prev_state == SLEEP_STATE)
1847 {
1848 int plane;
1849 au1200_setpanel(panel);
1850 for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane) {
1851 struct au1200fb_device *fbdev;
1852 fbdev = &_au1200fb_devices[plane];
1853 au1200fb_fb_set_par(&fbdev->fb_info);
1854 }
1855 }
1856
1857 d = *((unsigned int*)data);
1858 if(d <=10) brightness = 26;
1859 else if(d<=20) brightness = 51;
1860 else if(d<=30) brightness = 77;
1861 else if(d<=40) brightness = 102;
1862 else if(d<=50) brightness = 128;
1863 else if(d<=60) brightness = 153;
1864 else if(d<=70) brightness = 179;
1865 else if(d<=80) brightness = 204;
1866 else if(d<=90) brightness = 230;
1867 else brightness = 255;
1868 set_brightness(brightness);
1869 } else if (request == AU1XXX_PM_GETSTATUS) {
1870 return dev->cur_state;
1871 } else if (request == AU1XXX_PM_ACCESS) {
1872 if (dev->cur_state != SLEEP_STATE)
1873 return retval;
1874 else {
1875 au1200_setpanel(panel);
1876 }
1877 } else if (request == AU1XXX_PM_IDLE) {
1878 } else if (request == AU1XXX_PM_CLEANUP) {
1879 }
1880
1881 return retval;
1882}
1883#endif
1884
1885static int __init au1200fb_init(void)
1886{
1887 print_info("" DRIVER_DESC "");
1888
1889 /* Setup driver with options */
1890 au1200fb_setup();
1891
1892 /* Point to the panel selected */
1893 panel = &known_lcd_panels[panel_index];
1894 win = &windows[window_index];
1895
1896 printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name);
1897 printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name);
1898
1899 /* Kickstart the panel, the framebuffers/windows come soon enough */
1900 au1200_setpanel(panel);
1901
1902 #ifdef CONFIG_PM
1903 LCD_pm_dev = new_au1xxx_power_device("LCD", &au1200fb_pm_callback, NULL);
1904 if ( LCD_pm_dev == NULL)
1905 printk(KERN_INFO "Unable to create a power management device entry for the au1200fb.\n");
1906 else
1907 printk(KERN_INFO "Power management device entry for the au1200fb loaded.\n");
1908 #endif
1909
1910 return driver_register(&au1200fb_driver);
1911}
1912
1913static void __exit au1200fb_cleanup(void)
1914{
1915 driver_unregister(&au1200fb_driver);
1916}
1917
1918module_init(au1200fb_init);
1919module_exit(au1200fb_cleanup);
1920
1921MODULE_DESCRIPTION(DRIVER_DESC);
1922MODULE_LICENSE("GPL");
1923/*
1924 * BRIEF MODULE DESCRIPTION
1925 * Au1200 LCD Driver.
1926 *
1927 * Copyright 2004-2005 AMD
1928 * Author: AMD
1929 *
1930 * Based on:
1931 * linux/drivers/video/skeletonfb.c -- Skeleton for a frame buffer device
1932 * Created 28 Dec 1997 by Geert Uytterhoeven
1933 *
1934 * This program is free software; you can redistribute it and/or modify it
1935 * under the terms of the GNU General Public License as published by the
1936 * Free Software Foundation; either version 2 of the License, or (at your
1937 * option) any later version.
1938 *
1939 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1940 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1941 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1942 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1943 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1944 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1945 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1946 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1947 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1948 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1949 *
1950 * You should have received a copy of the GNU General Public License along
1951 * with this program; if not, write to the Free Software Foundation, Inc.,
1952 * 675 Mass Ave, Cambridge, MA 02139, USA.
1953 */
1954
1955#include <linux/module.h>
1956#include <linux/platform_device.h>
1957#include <linux/kernel.h>
1958#include <linux/errno.h>
1959#include <linux/string.h>
1960#include <linux/mm.h>
1961#include <linux/fb.h>
1962#include <linux/init.h>
1963#include <linux/interrupt.h>
1964#include <linux/ctype.h>
1965#include <linux/dma-mapping.h>
1966
1967#include <asm/mach-au1x00/au1000.h>
1968#include "au1200fb.h"
1969
1970#ifdef CONFIG_PM
1971#include <asm/mach-au1x00/au1xxx_pm.h>
1972#endif
1973
1974#ifndef CONFIG_FB_AU1200_DEVS
1975#define CONFIG_FB_AU1200_DEVS 4
1976#endif
1977
1978#define DRIVER_NAME "au1200fb"
1979#define DRIVER_DESC "LCD controller driver for AU1200 processors"
1980
1981#define DEBUG 1
1982
1983#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
1984#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
1985#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
1986
1987#if DEBUG
1988#define print_dbg(f, arg...) printk(KERN_DEBUG __FILE__ ": " f "\n", ## arg)
1989#else
1990#define print_dbg(f, arg...) do {} while (0)
1991#endif
1992
1993
1994#define AU1200_LCD_FB_IOCTL 0x46FF
1995
1996#define AU1200_LCD_SET_SCREEN 1
1997#define AU1200_LCD_GET_SCREEN 2
1998#define AU1200_LCD_SET_WINDOW 3
1999#define AU1200_LCD_GET_WINDOW 4
2000#define AU1200_LCD_SET_PANEL 5
2001#define AU1200_LCD_GET_PANEL 6
2002
2003#define SCREEN_SIZE (1<< 1)
2004#define SCREEN_BACKCOLOR (1<< 2)
2005#define SCREEN_BRIGHTNESS (1<< 3)
2006#define SCREEN_COLORKEY (1<< 4)
2007#define SCREEN_MASK (1<< 5)
2008
2009struct au1200_lcd_global_regs_t {
2010 unsigned int flags;
2011 unsigned int xsize;
2012 unsigned int ysize;
2013 unsigned int backcolor;
2014 unsigned int brightness;
2015 unsigned int colorkey;
2016 unsigned int mask;
2017 unsigned int panel_choice;
2018 char panel_desc[80];
2019
2020};
2021
2022#define WIN_POSITION (1<< 0)
2023#define WIN_ALPHA_COLOR (1<< 1)
2024#define WIN_ALPHA_MODE (1<< 2)
2025#define WIN_PRIORITY (1<< 3)
2026#define WIN_CHANNEL (1<< 4)
2027#define WIN_BUFFER_FORMAT (1<< 5)
2028#define WIN_COLOR_ORDER (1<< 6)
2029#define WIN_PIXEL_ORDER (1<< 7)
2030#define WIN_SIZE (1<< 8)
2031#define WIN_COLORKEY_MODE (1<< 9)
2032#define WIN_DOUBLE_BUFFER_MODE (1<< 10)
2033#define WIN_RAM_ARRAY_MODE (1<< 11)
2034#define WIN_BUFFER_SCALE (1<< 12)
2035#define WIN_ENABLE (1<< 13)
2036
2037struct au1200_lcd_window_regs_t {
2038 unsigned int flags;
2039 unsigned int xpos;
2040 unsigned int ypos;
2041 unsigned int alpha_color;
2042 unsigned int alpha_mode;
2043 unsigned int priority;
2044 unsigned int channel;
2045 unsigned int buffer_format;
2046 unsigned int color_order;
2047 unsigned int pixel_order;
2048 unsigned int xsize;
2049 unsigned int ysize;
2050 unsigned int colorkey_mode;
2051 unsigned int double_buffer_mode;
2052 unsigned int ram_array_mode;
2053 unsigned int xscale;
2054 unsigned int yscale;
2055 unsigned int enable;
2056};
2057
2058
2059struct au1200_lcd_iodata_t {
2060 unsigned int subcmd;
2061 struct au1200_lcd_global_regs_t global;
2062 struct au1200_lcd_window_regs_t window;
2063};
2064
2065#if defined(__BIG_ENDIAN)
2066#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
2067#else
2068#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
2069#endif
2070#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
2071
2072/* Private, per-framebuffer management information (independent of the panel itself) */
2073struct au1200fb_device {
2074 struct fb_info fb_info; /* FB driver info record */
2075
2076 int plane;
2077 unsigned char* fb_mem; /* FrameBuffer memory map */
2078 unsigned int fb_len;
2079 dma_addr_t fb_phys;
2080};
2081
2082static struct au1200fb_device _au1200fb_devices[CONFIG_FB_AU1200_DEVS];
2083/********************************************************************/
2084
2085/* LCD controller restrictions */
2086#define AU1200_LCD_MAX_XRES 1280
2087#define AU1200_LCD_MAX_YRES 1024
2088#define AU1200_LCD_MAX_BPP 32
2089#define AU1200_LCD_MAX_CLK 96000000 /* fixme: this needs to go away ? */
2090#define AU1200_LCD_NBR_PALETTE_ENTRIES 256
2091
2092/* Default number of visible screen buffer to allocate */
2093#define AU1200FB_NBR_VIDEO_BUFFERS 1
2094
2095/********************************************************************/
2096
2097static struct au1200_lcd *lcd = (struct au1200_lcd *) AU1200_LCD_ADDR;
2098static int window_index = 2; /* default is zero */
2099static int panel_index = 2; /* default is zero */
2100static struct window_settings *win;
2101static struct panel_settings *panel;
2102static int noblanking = 1;
2103static int nohwcursor = 0;
2104
2105struct window_settings {
2106 unsigned char name[64];
2107 uint32 mode_backcolor;
2108 uint32 mode_colorkey;
2109 uint32 mode_colorkeymsk;
2110 struct {
2111 int xres;
2112 int yres;
2113 int xpos;
2114 int ypos;
2115 uint32 mode_winctrl1; /* winctrl1[FRM,CCO,PO,PIPE] */
2116 uint32 mode_winenable;
2117 } w[4];
2118};
2119
2120#if defined(__BIG_ENDIAN)
2121#define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_00
2122#else
2123#define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_01
2124#endif
2125
2126extern int board_au1200fb_panel_init (void);
2127extern int board_au1200fb_panel_shutdown (void);
2128
2129#ifdef CONFIG_PM
2130int au1200fb_pm_callback(au1xxx_power_dev_t *dev,
2131 au1xxx_request_t request, void *data);
2132au1xxx_power_dev_t *LCD_pm_dev;
2133#endif
2134
2135/*
2136 * Default window configurations
2137 */
2138static struct window_settings windows[] = {
2139 { /* Index 0 */
2140 "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
2141 /* mode_backcolor */ 0x006600ff,
2142 /* mode_colorkey,msk*/ 0, 0,
2143 {
2144 {
2145 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
2146 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
2147 LCD_WINCTRL1_PO_16BPP,
2148 /* mode_winenable*/ LCD_WINENABLE_WEN0,
2149 },
2150 {
2151 /* xres, yres, xpos, ypos */ 100, 100, 100, 100,
2152 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
2153 LCD_WINCTRL1_PO_16BPP |
2154 LCD_WINCTRL1_PIPE,
2155 /* mode_winenable*/ LCD_WINENABLE_WEN1,
2156 },
2157 {
2158 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
2159 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
2160 LCD_WINCTRL1_PO_16BPP,
2161 /* mode_winenable*/ 0,
2162 },
2163 {
2164 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
2165 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
2166 LCD_WINCTRL1_PO_16BPP |
2167 LCD_WINCTRL1_PIPE,
2168 /* mode_winenable*/ 0,
2169 },
2170 },
2171 },
2172
2173 { /* Index 1 */
2174 "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
2175 /* mode_backcolor */ 0x006600ff,
2176 /* mode_colorkey,msk*/ 0, 0,
2177 {
2178 {
2179 /* xres, yres, xpos, ypos */ 320, 240, 5, 5,
2180 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_24BPP |
2181 LCD_WINCTRL1_PO_00,
2182 /* mode_winenable*/ LCD_WINENABLE_WEN0,
2183 },
2184 {
2185 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
2186 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565
2187 | LCD_WINCTRL1_PO_16BPP,
2188 /* mode_winenable*/ 0,
2189 },
2190 {
2191 /* xres, yres, xpos, ypos */ 100, 100, 0, 0,
2192 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
2193 LCD_WINCTRL1_PO_16BPP |
2194 LCD_WINCTRL1_PIPE,
2195 /* mode_winenable*/ 0/*LCD_WINENABLE_WEN2*/,
2196 },
2197 {
2198 /* xres, yres, xpos, ypos */ 200, 25, 0, 0,
2199 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
2200 LCD_WINCTRL1_PO_16BPP |
2201 LCD_WINCTRL1_PIPE,
2202 /* mode_winenable*/ 0,
2203 },
2204 },
2205 },
2206 { /* Index 2 */
2207 "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
2208 /* mode_backcolor */ 0x006600ff,
2209 /* mode_colorkey,msk*/ 0, 0,
2210 {
2211 {
2212 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
2213 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
2214 LCD_WINCTRL1_PO_16BPP,
2215 /* mode_winenable*/ LCD_WINENABLE_WEN0,
2216 },
2217 {
2218 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
2219 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
2220 LCD_WINCTRL1_PO_16BPP,
2221 /* mode_winenable*/ 0,
2222 },
2223 {
2224 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
2225 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_32BPP |
2226 LCD_WINCTRL1_PO_00|LCD_WINCTRL1_PIPE,
2227 /* mode_winenable*/ 0/*LCD_WINENABLE_WEN2*/,
2228 },
2229 {
2230 /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
2231 /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
2232 LCD_WINCTRL1_PO_16BPP |
2233 LCD_WINCTRL1_PIPE,
2234 /* mode_winenable*/ 0,
2235 },
2236 },
2237 },
2238 /* Need VGA 640 @ 24bpp, @ 32bpp */
2239 /* Need VGA 800 @ 24bpp, @ 32bpp */
2240 /* Need VGA 1024 @ 24bpp, @ 32bpp */
2241};
2242
2243/*
2244 * Controller configurations for various panels.
2245 */
2246
2247struct panel_settings
2248{
2249 const char name[25]; /* Full name <vendor>_<model> */
2250
2251 struct fb_monspecs monspecs; /* FB monitor specs */
2252
2253 /* panel timings */
2254 uint32 mode_screen;
2255 uint32 mode_horztiming;
2256 uint32 mode_verttiming;
2257 uint32 mode_clkcontrol;
2258 uint32 mode_pwmdiv;
2259 uint32 mode_pwmhi;
2260 uint32 mode_outmask;
2261 uint32 mode_fifoctrl;
2262 uint32 mode_toyclksrc;
2263 uint32 mode_backlight;
2264 uint32 mode_auxpll;
2265 int (*device_init)(void);
2266 int (*device_shutdown)(void);
2267#define Xres min_xres
2268#define Yres min_yres
2269 u32 min_xres; /* Minimum horizontal resolution */
2270 u32 max_xres; /* Maximum horizontal resolution */
2271 u32 min_yres; /* Minimum vertical resolution */
2272 u32 max_yres; /* Maximum vertical resolution */
2273};
2274
2275/********************************************************************/
2276/* fixme: Maybe a modedb for the CRT ? otherwise panels should be as-is */
2277
2278/* List of panels known to work with the AU1200 LCD controller.
2279 * To add a new panel, enter the same specifications as the
2280 * Generic_TFT one, and MAKE SURE that it doesn't conflicts
2281 * with the controller restrictions. Restrictions are:
2282 *
2283 * STN color panels: max_bpp <= 12
2284 * STN mono panels: max_bpp <= 4
2285 * TFT panels: max_bpp <= 16
2286 * max_xres <= 800
2287 * max_yres <= 600
2288 */
2289static struct panel_settings known_lcd_panels[] =
2290{
2291 [0] = { /* QVGA 320x240 H:33.3kHz V:110Hz */
2292 .name = "QVGA_320x240",
2293 .monspecs = {
2294 .modedb = NULL,
2295 .modedb_len = 0,
2296 .hfmin = 30000,
2297 .hfmax = 70000,
2298 .vfmin = 60,
2299 .vfmax = 60,
2300 .dclkmin = 6000000,
2301 .dclkmax = 28000000,
2302 .input = FB_DISP_RGB,
2303 },
2304 .mode_screen = LCD_SCREEN_SX_N(320) |
2305 LCD_SCREEN_SY_N(240),
2306 .mode_horztiming = 0x00c4623b,
2307 .mode_verttiming = 0x00502814,
2308 .mode_clkcontrol = 0x00020002, /* /4=24Mhz */
2309 .mode_pwmdiv = 0x00000000,
2310 .mode_pwmhi = 0x00000000,
2311 .mode_outmask = 0x00FFFFFF,
2312 .mode_fifoctrl = 0x2f2f2f2f,
2313 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
2314 .mode_backlight = 0x00000000,
2315 .mode_auxpll = 8, /* 96MHz AUXPLL */
2316 .device_init = NULL,
2317 .device_shutdown = NULL,
2318 320, 320,
2319 240, 240,
2320 },
2321
2322 [1] = { /* VGA 640x480 H:30.3kHz V:58Hz */
2323 .name = "VGA_640x480",
2324 .monspecs = {
2325 .modedb = NULL,
2326 .modedb_len = 0,
2327 .hfmin = 30000,
2328 .hfmax = 70000,
2329 .vfmin = 60,
2330 .vfmax = 60,
2331 .dclkmin = 6000000,
2332 .dclkmax = 28000000,
2333 .input = FB_DISP_RGB,
2334 },
2335 .mode_screen = 0x13f9df80,
2336 .mode_horztiming = 0x003c5859,
2337 .mode_verttiming = 0x00741201,
2338 .mode_clkcontrol = 0x00020001, /* /4=24Mhz */
2339 .mode_pwmdiv = 0x00000000,
2340 .mode_pwmhi = 0x00000000,
2341 .mode_outmask = 0x00FFFFFF,
2342 .mode_fifoctrl = 0x2f2f2f2f,
2343 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
2344 .mode_backlight = 0x00000000,
2345 .mode_auxpll = 8, /* 96MHz AUXPLL */
2346 .device_init = NULL,
2347 .device_shutdown = NULL,
2348 640, 480,
2349 640, 480,
2350 },
2351
2352 [2] = { /* SVGA 800x600 H:46.1kHz V:69Hz */
2353 .name = "SVGA_800x600",
2354 .monspecs = {
2355 .modedb = NULL,
2356 .modedb_len = 0,
2357 .hfmin = 30000,
2358 .hfmax = 70000,
2359 .vfmin = 60,
2360 .vfmax = 60,
2361 .dclkmin = 6000000,
2362 .dclkmax = 28000000,
2363 .input = FB_DISP_RGB,
2364 },
2365 .mode_screen = 0x18fa5780,
2366 .mode_horztiming = 0x00dc7e77,
2367 .mode_verttiming = 0x00584805,
2368 .mode_clkcontrol = 0x00020000, /* /2=48Mhz */
2369 .mode_pwmdiv = 0x00000000,
2370 .mode_pwmhi = 0x00000000,
2371 .mode_outmask = 0x00FFFFFF,
2372 .mode_fifoctrl = 0x2f2f2f2f,
2373 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
2374 .mode_backlight = 0x00000000,
2375 .mode_auxpll = 8, /* 96MHz AUXPLL */
2376 .device_init = NULL,
2377 .device_shutdown = NULL,
2378 800, 800,
2379 600, 600,
2380 },
2381
2382 [3] = { /* XVGA 1024x768 H:56.2kHz V:70Hz */
2383 .name = "XVGA_1024x768",
2384 .monspecs = {
2385 .modedb = NULL,
2386 .modedb_len = 0,
2387 .hfmin = 30000,
2388 .hfmax = 70000,
2389 .vfmin = 60,
2390 .vfmax = 60,
2391 .dclkmin = 6000000,
2392 .dclkmax = 28000000,
2393 .input = FB_DISP_RGB,
2394 },
2395 .mode_screen = 0x1ffaff80,
2396 .mode_horztiming = 0x007d0e57,
2397 .mode_verttiming = 0x00740a01,
2398 .mode_clkcontrol = 0x000A0000, /* /1 */
2399 .mode_pwmdiv = 0x00000000,
2400 .mode_pwmhi = 0x00000000,
2401 .mode_outmask = 0x00FFFFFF,
2402 .mode_fifoctrl = 0x2f2f2f2f,
2403 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
2404 .mode_backlight = 0x00000000,
2405 .mode_auxpll = 6, /* 72MHz AUXPLL */
2406 .device_init = NULL,
2407 .device_shutdown = NULL,
2408 1024, 1024,
2409 768, 768,
2410 },
2411
2412 [4] = { /* XVGA XVGA 1280x1024 H:68.5kHz V:65Hz */
2413 .name = "XVGA_1280x1024",
2414 .monspecs = {
2415 .modedb = NULL,
2416 .modedb_len = 0,
2417 .hfmin = 30000,
2418 .hfmax = 70000,
2419 .vfmin = 60,
2420 .vfmax = 60,
2421 .dclkmin = 6000000,
2422 .dclkmax = 28000000,
2423 .input = FB_DISP_RGB,
2424 },
2425 .mode_screen = 0x27fbff80,
2426 .mode_horztiming = 0x00cdb2c7,
2427 .mode_verttiming = 0x00600002,
2428 .mode_clkcontrol = 0x000A0000, /* /1 */
2429 .mode_pwmdiv = 0x00000000,
2430 .mode_pwmhi = 0x00000000,
2431 .mode_outmask = 0x00FFFFFF,
2432 .mode_fifoctrl = 0x2f2f2f2f,
2433 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
2434 .mode_backlight = 0x00000000,
2435 .mode_auxpll = 10, /* 120MHz AUXPLL */
2436 .device_init = NULL,
2437 .device_shutdown = NULL,
2438 1280, 1280,
2439 1024, 1024,
2440 },
2441
2442 [5] = { /* Samsung 1024x768 TFT */
2443 .name = "Samsung_1024x768_TFT",
2444 .monspecs = {
2445 .modedb = NULL,
2446 .modedb_len = 0,
2447 .hfmin = 30000,
2448 .hfmax = 70000,
2449 .vfmin = 60,
2450 .vfmax = 60,
2451 .dclkmin = 6000000,
2452 .dclkmax = 28000000,
2453 .input = FB_DISP_RGB,
2454 },
2455 .mode_screen = 0x1ffaff80,
2456 .mode_horztiming = 0x018cc677,
2457 .mode_verttiming = 0x00241217,
2458 .mode_clkcontrol = 0x00000000, /* SCB 0x1 /4=24Mhz */
2459 .mode_pwmdiv = 0x8000063f, /* SCB 0x0 */
2460 .mode_pwmhi = 0x03400000, /* SCB 0x0 */
2461 .mode_outmask = 0x00FFFFFF,
2462 .mode_fifoctrl = 0x2f2f2f2f,
2463 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
2464 .mode_backlight = 0x00000000,
2465 .mode_auxpll = 8, /* 96MHz AUXPLL */
2466 .device_init = board_au1200fb_panel_init,
2467 .device_shutdown = board_au1200fb_panel_shutdown,
2468 1024, 1024,
2469 768, 768,
2470 },
2471
2472 [6] = { /* Toshiba 640x480 TFT */
2473 .name = "Toshiba_640x480_TFT",
2474 .monspecs = {
2475 .modedb = NULL,
2476 .modedb_len = 0,
2477 .hfmin = 30000,
2478 .hfmax = 70000,
2479 .vfmin = 60,
2480 .vfmax = 60,
2481 .dclkmin = 6000000,
2482 .dclkmax = 28000000,
2483 .input = FB_DISP_RGB,
2484 },
2485 .mode_screen = LCD_SCREEN_SX_N(640) |
2486 LCD_SCREEN_SY_N(480),
2487 .mode_horztiming = LCD_HORZTIMING_HPW_N(96) |
2488 LCD_HORZTIMING_HND1_N(13) | LCD_HORZTIMING_HND2_N(51),
2489 .mode_verttiming = LCD_VERTTIMING_VPW_N(2) |
2490 LCD_VERTTIMING_VND1_N(11) | LCD_VERTTIMING_VND2_N(32),
2491 .mode_clkcontrol = 0x00000000, /* /4=24Mhz */
2492 .mode_pwmdiv = 0x8000063f,
2493 .mode_pwmhi = 0x03400000,
2494 .mode_outmask = 0x00fcfcfc,
2495 .mode_fifoctrl = 0x2f2f2f2f,
2496 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
2497 .mode_backlight = 0x00000000,
2498 .mode_auxpll = 8, /* 96MHz AUXPLL */
2499 .device_init = board_au1200fb_panel_init,
2500 .device_shutdown = board_au1200fb_panel_shutdown,
2501 640, 480,
2502 640, 480,
2503 },
2504
2505 [7] = { /* Sharp 320x240 TFT */
2506 .name = "Sharp_320x240_TFT",
2507 .monspecs = {
2508 .modedb = NULL,
2509 .modedb_len = 0,
2510 .hfmin = 12500,
2511 .hfmax = 20000,
2512 .vfmin = 38,
2513 .vfmax = 81,
2514 .dclkmin = 4500000,
2515 .dclkmax = 6800000,
2516 .input = FB_DISP_RGB,
2517 },
2518 .mode_screen = LCD_SCREEN_SX_N(320) |
2519 LCD_SCREEN_SY_N(240),
2520 .mode_horztiming = LCD_HORZTIMING_HPW_N(60) |
2521 LCD_HORZTIMING_HND1_N(13) | LCD_HORZTIMING_HND2_N(2),
2522 .mode_verttiming = LCD_VERTTIMING_VPW_N(2) |
2523 LCD_VERTTIMING_VND1_N(2) | LCD_VERTTIMING_VND2_N(5),
2524 .mode_clkcontrol = LCD_CLKCONTROL_PCD_N(7), /*16=6Mhz*/
2525 .mode_pwmdiv = 0x8000063f,
2526 .mode_pwmhi = 0x03400000,
2527 .mode_outmask = 0x00fcfcfc,
2528 .mode_fifoctrl = 0x2f2f2f2f,
2529 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
2530 .mode_backlight = 0x00000000,
2531 .mode_auxpll = 8, /* 96MHz AUXPLL */
2532 .device_init = board_au1200fb_panel_init,
2533 .device_shutdown = board_au1200fb_panel_shutdown,
2534 320, 320,
2535 240, 240,
2536 },
2537
2538 [8] = { /* Toppoly TD070WGCB2 7" 856x480 TFT */
2539 .name = "Toppoly_TD070WGCB2",
2540 .monspecs = {
2541 .modedb = NULL,
2542 .modedb_len = 0,
2543 .hfmin = 30000,
2544 .hfmax = 70000,
2545 .vfmin = 60,
2546 .vfmax = 60,
2547 .dclkmin = 6000000,
2548 .dclkmax = 28000000,
2549 .input = FB_DISP_RGB,
2550 },
2551 .mode_screen = LCD_SCREEN_SX_N(856) |
2552 LCD_SCREEN_SY_N(480),
2553 .mode_horztiming = LCD_HORZTIMING_HND2_N(43) |
2554 LCD_HORZTIMING_HND1_N(43) | LCD_HORZTIMING_HPW_N(114),
2555 .mode_verttiming = LCD_VERTTIMING_VND2_N(20) |
2556 LCD_VERTTIMING_VND1_N(21) | LCD_VERTTIMING_VPW_N(4),
2557 .mode_clkcontrol = 0x00020001, /* /4=24Mhz */
2558 .mode_pwmdiv = 0x8000063f,
2559 .mode_pwmhi = 0x03400000,
2560 .mode_outmask = 0x00fcfcfc,
2561 .mode_fifoctrl = 0x2f2f2f2f,
2562 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
2563 .mode_backlight = 0x00000000,
2564 .mode_auxpll = 8, /* 96MHz AUXPLL */
2565 .device_init = board_au1200fb_panel_init,
2566 .device_shutdown = board_au1200fb_panel_shutdown,
2567 856, 856,
2568 480, 480,
2569 },
2570};
2571
2572#define NUM_PANELS (ARRAY_SIZE(known_lcd_panels))
2573
2574/********************************************************************/
2575
2576#ifdef CONFIG_PM
2577static int set_brightness(unsigned int brightness)
2578{
2579 unsigned int hi1, divider;
2580
2581 /* limit brightness pwm duty to >= 30/1600 */
2582 if (brightness < 30) {
2583 brightness = 30;
2584 }
2585 divider = (lcd->pwmdiv & 0x3FFFF) + 1;
2586 hi1 = (lcd->pwmhi >> 16) + 1;
2587 hi1 = (((brightness & 0xFF) + 1) * divider >> 8);
2588 lcd->pwmhi &= 0xFFFF;
2589 lcd->pwmhi |= (hi1 << 16);
2590
2591 return brightness;
2592}
2593#endif /* CONFIG_PM */
2594
2595static int winbpp (unsigned int winctrl1)
2596{
2597 int bits = 0;
2598
2599 /* how many bits are needed for each pixel format */
2600 switch (winctrl1 & LCD_WINCTRL1_FRM) {
2601 case LCD_WINCTRL1_FRM_1BPP:
2602 bits = 1;
2603 break;
2604 case LCD_WINCTRL1_FRM_2BPP:
2605 bits = 2;
2606 break;
2607 case LCD_WINCTRL1_FRM_4BPP:
2608 bits = 4;
2609 break;
2610 case LCD_WINCTRL1_FRM_8BPP:
2611 bits = 8;
2612 break;
2613 case LCD_WINCTRL1_FRM_12BPP:
2614 case LCD_WINCTRL1_FRM_16BPP655:
2615 case LCD_WINCTRL1_FRM_16BPP565:
2616 case LCD_WINCTRL1_FRM_16BPP556:
2617 case LCD_WINCTRL1_FRM_16BPPI1555:
2618 case LCD_WINCTRL1_FRM_16BPPI5551:
2619 case LCD_WINCTRL1_FRM_16BPPA1555:
2620 case LCD_WINCTRL1_FRM_16BPPA5551:
2621 bits = 16;
2622 break;
2623 case LCD_WINCTRL1_FRM_24BPP:
2624 case LCD_WINCTRL1_FRM_32BPP:
2625 bits = 32;
2626 break;
2627 }
2628
2629 return bits;
2630}
2631
2632static int fbinfo2index (struct fb_info *fb_info)
2633{
2634 int i;
2635
2636 for (i = 0; i < CONFIG_FB_AU1200_DEVS; ++i) {
2637 if (fb_info == (struct fb_info *)(&_au1200fb_devices[i].fb_info))
2638 return i;
2639 }
2640 printk("au1200fb: ERROR: fbinfo2index failed!\n");
2641 return -1;
2642}
2643
2644static int au1200_setlocation (struct au1200fb_device *fbdev, int plane,
2645 int xpos, int ypos)
2646{
2647 uint32 winctrl0, winctrl1, winenable, fb_offset = 0;
2648 int xsz, ysz;
2649
2650 /* FIX!!! NOT CHECKING FOR COMPLETE OFFSCREEN YET */
2651
2652 winctrl0 = lcd->window[plane].winctrl0;
2653 winctrl1 = lcd->window[plane].winctrl1;
2654 winctrl0 &= (LCD_WINCTRL0_A | LCD_WINCTRL0_AEN);
2655 winctrl1 &= ~(LCD_WINCTRL1_SZX | LCD_WINCTRL1_SZY);
2656
2657 /* Check for off-screen adjustments */
2658 xsz = win->w[plane].xres;
2659 ysz = win->w[plane].yres;
2660 if ((xpos + win->w[plane].xres) > panel->Xres) {
2661 /* Off-screen to the right */
2662 xsz = panel->Xres - xpos; /* off by 1 ??? */
2663 /*printk("off screen right\n");*/
2664 }
2665
2666 if ((ypos + win->w[plane].yres) > panel->Yres) {
2667 /* Off-screen to the bottom */
2668 ysz = panel->Yres - ypos; /* off by 1 ??? */
2669 /*printk("off screen bottom\n");*/
2670 }
2671
2672 if (xpos < 0) {
2673 /* Off-screen to the left */
2674 xsz = win->w[plane].xres + xpos;
2675 fb_offset += (((0 - xpos) * winbpp(lcd->window[plane].winctrl1))/8);
2676 xpos = 0;
2677 /*printk("off screen left\n");*/
2678 }
2679
2680 if (ypos < 0) {
2681 /* Off-screen to the top */
2682 ysz = win->w[plane].yres + ypos;
2683 /* fixme: fb_offset += ((0-ypos)*fb_pars[plane].line_length); */
2684 ypos = 0;
2685 /*printk("off screen top\n");*/
2686 }
2687
2688 /* record settings */
2689 win->w[plane].xpos = xpos;
2690 win->w[plane].ypos = ypos;
2691
2692 xsz -= 1;
2693 ysz -= 1;
2694 winctrl0 |= (xpos << 21);
2695 winctrl0 |= (ypos << 10);
2696 winctrl1 |= (xsz << 11);
2697 winctrl1 |= (ysz << 0);
2698
2699 /* Disable the window while making changes, then restore WINEN */
2700 winenable = lcd->winenable & (1 << plane);
2701 au_sync();
2702 lcd->winenable &= ~(1 << plane);
2703 lcd->window[plane].winctrl0 = winctrl0;
2704 lcd->window[plane].winctrl1 = winctrl1;
2705 lcd->window[plane].winbuf0 =
2706 lcd->window[plane].winbuf1 = fbdev->fb_phys;
2707 lcd->window[plane].winbufctrl = 0; /* select winbuf0 */
2708 lcd->winenable |= winenable;
2709 au_sync();
2710
2711 return 0;
2712}
2713
2714static void au1200_setpanel (struct panel_settings *newpanel)
2715{
2716 /*
2717 * Perform global setup/init of LCD controller
2718 */
2719 uint32 winenable;
2720
2721 /* Make sure all windows disabled */
2722 winenable = lcd->winenable;
2723 lcd->winenable = 0;
2724 au_sync();
2725 /*
2726 * Ensure everything is disabled before reconfiguring
2727 */
2728 if (lcd->screen & LCD_SCREEN_SEN) {
2729 /* Wait for vertical sync period */
2730 lcd->intstatus = LCD_INT_SS;
2731 while ((lcd->intstatus & LCD_INT_SS) == 0) {
2732 au_sync();
2733 }
2734
2735 lcd->screen &= ~LCD_SCREEN_SEN; /*disable the controller*/
2736
2737 do {
2738 lcd->intstatus = lcd->intstatus; /*clear interrupts*/
2739 au_sync();
2740 /*wait for controller to shut down*/
2741 } while ((lcd->intstatus & LCD_INT_SD) == 0);
2742
2743 /* Call shutdown of current panel (if up) */
2744 /* this must occur last, because if an external clock is driving
2745 the controller, the clock cannot be turned off before first
2746 shutting down the controller.
2747 */
2748 if (panel->device_shutdown != NULL)
2749 panel->device_shutdown();
2750 }
2751
2752 /* Newpanel == NULL indicates a shutdown operation only */
2753 if (newpanel == NULL)
2754 return;
2755
2756 panel = newpanel;
2757
2758 printk("Panel(%s), %dx%d\n", panel->name, panel->Xres, panel->Yres);
2759
2760 /*
2761 * Setup clocking if internal LCD clock source (assumes sys_auxpll valid)
2762 */
2763 if (!(panel->mode_clkcontrol & LCD_CLKCONTROL_EXT))
2764 {
2765 uint32 sys_clksrc;
2766 au_writel(panel->mode_auxpll, SYS_AUXPLL);
2767 sys_clksrc = au_readl(SYS_CLKSRC) & ~0x0000001f;
2768 sys_clksrc |= panel->mode_toyclksrc;
2769 au_writel(sys_clksrc, SYS_CLKSRC);
2770 }
2771
2772 /*
2773 * Configure panel timings
2774 */
2775 lcd->screen = panel->mode_screen;
2776 lcd->horztiming = panel->mode_horztiming;
2777 lcd->verttiming = panel->mode_verttiming;
2778 lcd->clkcontrol = panel->mode_clkcontrol;
2779 lcd->pwmdiv = panel->mode_pwmdiv;
2780 lcd->pwmhi = panel->mode_pwmhi;
2781 lcd->outmask = panel->mode_outmask;
2782 lcd->fifoctrl = panel->mode_fifoctrl;
2783 au_sync();
2784
2785 /* fixme: Check window settings to make sure still valid
2786 * for new geometry */
2787#if 0
2788 au1200_setlocation(fbdev, 0, win->w[0].xpos, win->w[0].ypos);
2789 au1200_setlocation(fbdev, 1, win->w[1].xpos, win->w[1].ypos);
2790 au1200_setlocation(fbdev, 2, win->w[2].xpos, win->w[2].ypos);
2791 au1200_setlocation(fbdev, 3, win->w[3].xpos, win->w[3].ypos);
2792#endif
2793 lcd->winenable = winenable;
2794
2795 /*
2796 * Re-enable screen now that it is configured
2797 */
2798 lcd->screen |= LCD_SCREEN_SEN;
2799 au_sync();
2800
2801 /* Call init of panel */
2802 if (panel->device_init != NULL) panel->device_init();
2803
2804 /* FIX!!!! not appropriate on panel change!!! Global setup/init */
2805 lcd->intenable = 0;
2806 lcd->intstatus = ~0;
2807 lcd->backcolor = win->mode_backcolor;
2808
2809 /* Setup Color Key - FIX!!! */
2810 lcd->colorkey = win->mode_colorkey;
2811 lcd->colorkeymsk = win->mode_colorkeymsk;
2812
2813 /* Setup HWCursor - FIX!!! Need to support this eventually */
2814 lcd->hwc.cursorctrl = 0;
2815 lcd->hwc.cursorpos = 0;
2816 lcd->hwc.cursorcolor0 = 0;
2817 lcd->hwc.cursorcolor1 = 0;
2818 lcd->hwc.cursorcolor2 = 0;
2819 lcd->hwc.cursorcolor3 = 0;
2820
2821
2822#if 0
2823#define D(X) printk("%25s: %08X\n", #X, X)
2824 D(lcd->screen);
2825 D(lcd->horztiming);
2826 D(lcd->verttiming);
2827 D(lcd->clkcontrol);
2828 D(lcd->pwmdiv);
2829 D(lcd->pwmhi);
2830 D(lcd->outmask);
2831 D(lcd->fifoctrl);
2832 D(lcd->window[0].winctrl0);
2833 D(lcd->window[0].winctrl1);
2834 D(lcd->window[0].winctrl2);
2835 D(lcd->window[0].winbuf0);
2836 D(lcd->window[0].winbuf1);
2837 D(lcd->window[0].winbufctrl);
2838 D(lcd->window[1].winctrl0);
2839 D(lcd->window[1].winctrl1);
2840 D(lcd->window[1].winctrl2);
2841 D(lcd->window[1].winbuf0);
2842 D(lcd->window[1].winbuf1);
2843 D(lcd->window[1].winbufctrl);
2844 D(lcd->window[2].winctrl0);
2845 D(lcd->window[2].winctrl1);
2846 D(lcd->window[2].winctrl2);
2847 D(lcd->window[2].winbuf0);
2848 D(lcd->window[2].winbuf1);
2849 D(lcd->window[2].winbufctrl);
2850 D(lcd->window[3].winctrl0);
2851 D(lcd->window[3].winctrl1);
2852 D(lcd->window[3].winctrl2);
2853 D(lcd->window[3].winbuf0);
2854 D(lcd->window[3].winbuf1);
2855 D(lcd->window[3].winbufctrl);
2856 D(lcd->winenable);
2857 D(lcd->intenable);
2858 D(lcd->intstatus);
2859 D(lcd->backcolor);
2860 D(lcd->winenable);
2861 D(lcd->colorkey);
2862 D(lcd->colorkeymsk);
2863 D(lcd->hwc.cursorctrl);
2864 D(lcd->hwc.cursorpos);
2865 D(lcd->hwc.cursorcolor0);
2866 D(lcd->hwc.cursorcolor1);
2867 D(lcd->hwc.cursorcolor2);
2868 D(lcd->hwc.cursorcolor3);
2869#endif
2870}
2871
2872static void au1200_setmode(struct au1200fb_device *fbdev)
2873{
2874 int plane = fbdev->plane;
2875 /* Window/plane setup */
2876 lcd->window[plane].winctrl1 = ( 0
2877 | LCD_WINCTRL1_PRI_N(plane)
2878 | win->w[plane].mode_winctrl1 /* FRM,CCO,PO,PIPE */
2879 ) ;
2880
2881 au1200_setlocation(fbdev, plane, win->w[plane].xpos, win->w[plane].ypos);
2882
2883 lcd->window[plane].winctrl2 = ( 0
2884 | LCD_WINCTRL2_CKMODE_00
2885 | LCD_WINCTRL2_DBM
2886 | LCD_WINCTRL2_BX_N( fbdev->fb_info.fix.line_length)
2887 | LCD_WINCTRL2_SCX_1
2888 | LCD_WINCTRL2_SCY_1
2889 ) ;
2890 lcd->winenable |= win->w[plane].mode_winenable;
2891 au_sync();
2892}
2893
2894
2895/* Inline helpers */
2896
2897/*#define panel_is_dual(panel) ((panel->mode_screen & LCD_SCREEN_PT) == LCD_SCREEN_PT_010)*/
2898/*#define panel_is_active(panel)((panel->mode_screen & LCD_SCREEN_PT) == LCD_SCREEN_PT_010)*/
2899
2900#define panel_is_color(panel) ((panel->mode_screen & LCD_SCREEN_PT) <= LCD_SCREEN_PT_CDSTN)
2901
2902/* Bitfields format supported by the controller. */
2903static struct fb_bitfield rgb_bitfields[][4] = {
2904 /* Red, Green, Blue, Transp */
2905 [LCD_WINCTRL1_FRM_16BPP655 >> 25] =
2906 { { 10, 6, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
2907
2908 [LCD_WINCTRL1_FRM_16BPP565 >> 25] =
2909 { { 11, 5, 0 }, { 5, 6, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
2910
2911 [LCD_WINCTRL1_FRM_16BPP556 >> 25] =
2912 { { 11, 5, 0 }, { 6, 5, 0 }, { 0, 6, 0 }, { 0, 0, 0 } },
2913
2914 [LCD_WINCTRL1_FRM_16BPPI1555 >> 25] =
2915 { { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
2916
2917 [LCD_WINCTRL1_FRM_16BPPI5551 >> 25] =
2918 { { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 0, 0 } },
2919
2920 [LCD_WINCTRL1_FRM_16BPPA1555 >> 25] =
2921 { { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 15, 1, 0 } },
2922
2923 [LCD_WINCTRL1_FRM_16BPPA5551 >> 25] =
2924 { { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 1, 0 } },
2925
2926 [LCD_WINCTRL1_FRM_24BPP >> 25] =
2927 { { 16, 8, 0 }, { 8, 8, 0 }, { 0, 8, 0 }, { 0, 0, 0 } },
2928
2929 [LCD_WINCTRL1_FRM_32BPP >> 25] =
2930 { { 16, 8, 0 }, { 8, 8, 0 }, { 0, 8, 0 }, { 24, 0, 0 } },
2931};
2932
2933/*-------------------------------------------------------------------------*/
2934
2935/* Helpers */
2936
2937static void au1200fb_update_fbinfo(struct fb_info *fbi)
2938{
2939 /* FIX!!!! This also needs to take the window pixel format into account!!! */
2940
2941 /* Update var-dependent FB info */
2942 if (panel_is_color(panel)) {
2943 if (fbi->var.bits_per_pixel <= 8) {
2944 /* palettized */
2945 fbi->fix.visual = FB_VISUAL_PSEUDOCOLOR;
2946 fbi->fix.line_length = fbi->var.xres_virtual /
2947 (8/fbi->var.bits_per_pixel);
2948 } else {
2949 /* non-palettized */
2950 fbi->fix.visual = FB_VISUAL_TRUECOLOR;
2951 fbi->fix.line_length = fbi->var.xres_virtual * (fbi->var.bits_per_pixel / 8);
2952 }
2953 } else {
2954 /* mono FIX!!! mono 8 and 4 bits */
2955 fbi->fix.visual = FB_VISUAL_MONO10;
2956 fbi->fix.line_length = fbi->var.xres_virtual / 8;
2957 }
2958
2959 fbi->screen_size = fbi->fix.line_length * fbi->var.yres_virtual;
2960 print_dbg("line length: %d\n", fbi->fix.line_length);
2961 print_dbg("bits_per_pixel: %d\n", fbi->var.bits_per_pixel);
2962}
2963
2964/*-------------------------------------------------------------------------*/
2965
2966/* AU1200 framebuffer driver */
2967
2968/* fb_check_var
2969 * Validate var settings with hardware restrictions and modify it if necessary
2970 */
2971static int au1200fb_fb_check_var(struct fb_var_screeninfo *var,
2972 struct fb_info *fbi)
2973{
2974 struct au1200fb_device *fbdev = (struct au1200fb_device *)fbi;
2975 u32 pixclock;
2976 int screen_size, plane;
2977
2978 plane = fbdev->plane;
2979
2980 /* Make sure that the mode respect all LCD controller and
2981 * panel restrictions. */
2982 var->xres = win->w[plane].xres;
2983 var->yres = win->w[plane].yres;
2984
2985 /* No need for virtual resolution support */
2986 var->xres_virtual = var->xres;
2987 var->yres_virtual = var->yres;
2988
2989 var->bits_per_pixel = winbpp(win->w[plane].mode_winctrl1);
2990
2991 screen_size = var->xres_virtual * var->yres_virtual;
2992 if (var->bits_per_pixel > 8) screen_size *= (var->bits_per_pixel / 8);
2993 else screen_size /= (8/var->bits_per_pixel);
2994
2995 if (fbdev->fb_len < screen_size)
2996 return -EINVAL; /* Virtual screen is to big, abort */
2997
2998 /* FIX!!!! what are the implicaitons of ignoring this for windows ??? */
2999 /* The max LCD clock is fixed to 48MHz (value of AUX_CLK). The pixel
3000 * clock can only be obtain by dividing this value by an even integer.
3001 * Fallback to a slower pixel clock if necessary. */
3002 pixclock = max((u32)(PICOS2KHZ(var->pixclock) * 1000), fbi->monspecs.dclkmin);
3003 pixclock = min(pixclock, min(fbi->monspecs.dclkmax, (u32)AU1200_LCD_MAX_CLK/2));
3004
3005 if (AU1200_LCD_MAX_CLK % pixclock) {
3006 int diff = AU1200_LCD_MAX_CLK % pixclock;
3007 pixclock -= diff;
3008 }
3009
3010 var->pixclock = KHZ2PICOS(pixclock/1000);
3011#if 0
3012 if (!panel_is_active(panel)) {
3013 int pcd = AU1200_LCD_MAX_CLK / (pixclock * 2) - 1;
3014
3015 if (!panel_is_color(panel)
3016 && (panel->control_base & LCD_CONTROL_MPI) && (pcd < 3)) {
3017 /* STN 8bit mono panel support is up to 6MHz pixclock */
3018 var->pixclock = KHZ2PICOS(6000);
3019 } else if (!pcd) {
3020 /* Other STN panel support is up to 12MHz */
3021 var->pixclock = KHZ2PICOS(12000);
3022 }
3023 }
3024#endif
3025 /* Set bitfield accordingly */
3026 switch (var->bits_per_pixel) {
3027 case 16:
3028 {
3029 /* 16bpp True color.
3030 * These must be set to MATCH WINCTRL[FORM] */
3031 int idx;
3032 idx = (win->w[0].mode_winctrl1 & LCD_WINCTRL1_FRM) >> 25;
3033 var->red = rgb_bitfields[idx][0];
3034 var->green = rgb_bitfields[idx][1];
3035 var->blue = rgb_bitfields[idx][2];
3036 var->transp = rgb_bitfields[idx][3];
3037 break;
3038 }
3039
3040 case 32:
3041 {
3042 /* 32bpp True color.
3043 * These must be set to MATCH WINCTRL[FORM] */
3044 int idx;
3045 idx = (win->w[0].mode_winctrl1 & LCD_WINCTRL1_FRM) >> 25;
3046 var->red = rgb_bitfields[idx][0];
3047 var->green = rgb_bitfields[idx][1];
3048 var->blue = rgb_bitfields[idx][2];
3049 var->transp = rgb_bitfields[idx][3];
3050 break;
3051 }
3052 default:
3053 print_dbg("Unsupported depth %dbpp", var->bits_per_pixel);
3054 return -EINVAL;
3055 }
3056
3057 return 0;
3058}
3059
3060/* fb_set_par
3061 * Set hardware with var settings. This will enable the controller with a
3062 * specific mode, normally validated with the fb_check_var method
3063 */
3064static int au1200fb_fb_set_par(struct fb_info *fbi)
3065{
3066 struct au1200fb_device *fbdev = (struct au1200fb_device *)fbi;
3067
3068 au1200fb_update_fbinfo(fbi);
3069 au1200_setmode(fbdev);
3070
3071 return 0;
3072}
3073
3074/* fb_setcolreg
3075 * Set color in LCD palette.
3076 */
3077static int au1200fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green,
3078 unsigned blue, unsigned transp, struct fb_info *fbi)
3079{
3080 volatile u32 *palette = lcd->palette;
3081 u32 value;
3082
3083 if (regno > (AU1200_LCD_NBR_PALETTE_ENTRIES - 1))
3084 return -EINVAL;
3085
3086 if (fbi->var.grayscale) {
3087 /* Convert color to grayscale */
3088 red = green = blue =
3089 (19595 * red + 38470 * green + 7471 * blue) >> 16;
3090 }
3091
3092 if (fbi->fix.visual == FB_VISUAL_TRUECOLOR) {
3093 /* Place color in the pseudopalette */
3094 if (regno > 16)
3095 return -EINVAL;
3096
3097 palette = (u32*) fbi->pseudo_palette;
3098
3099 red >>= (16 - fbi->var.red.length);
3100 green >>= (16 - fbi->var.green.length);
3101 blue >>= (16 - fbi->var.blue.length);
3102
3103 value = (red << fbi->var.red.offset) |
3104 (green << fbi->var.green.offset)|
3105 (blue << fbi->var.blue.offset);
3106 value &= 0xFFFF;
3107
3108 } else if (1 /*FIX!!! panel_is_active(fbdev->panel)*/) {
3109 /* COLOR TFT PALLETTIZED (use RGB 565) */
3110 value = (red & 0xF800)|((green >> 5) &
3111 0x07E0)|((blue >> 11) & 0x001F);
3112 value &= 0xFFFF;
3113
3114 } else if (0 /*panel_is_color(fbdev->panel)*/) {
3115 /* COLOR STN MODE */
3116 value = 0x1234;
3117 value &= 0xFFF;
3118 } else {
3119 /* MONOCHROME MODE */
3120 value = (green >> 12) & 0x000F;
3121 value &= 0xF;
3122 }
3123
3124 palette[regno] = value;
3125
3126 return 0;
3127}
3128
3129/* fb_blank
3130 * Blank the screen. Depending on the mode, the screen will be
3131 * activated with the backlight color, or desactivated
3132 */
3133static int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi)
3134{
3135 /* Short-circuit screen blanking */
3136 if (noblanking)
3137 return 0;
3138
3139 switch (blank_mode) {
3140
3141 case FB_BLANK_UNBLANK:
3142 case FB_BLANK_NORMAL:
3143 /* printk("turn on panel\n"); */
3144 au1200_setpanel(panel);
3145 break;
3146 case FB_BLANK_VSYNC_SUSPEND:
3147 case FB_BLANK_HSYNC_SUSPEND:
3148 case FB_BLANK_POWERDOWN:
3149 /* printk("turn off panel\n"); */
3150 au1200_setpanel(NULL);
3151 break;
3152 default:
3153 break;
3154
3155 }
3156
3157 /* FB_BLANK_NORMAL is a soft blank */
3158 return (blank_mode == FB_BLANK_NORMAL) ? -EINVAL : 0;
3159}
3160
3161/* fb_mmap
3162 * Map video memory in user space. We don't use the generic fb_mmap
3163 * method mainly to allow the use of the TLB streaming flag (CCA=6)
3164 */
3165static int au1200fb_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
3166
3167{
3168 unsigned int len;
3169 unsigned long start=0, off;
3170 struct au1200fb_device *fbdev = (struct au1200fb_device *) info;
3171
3172#ifdef CONFIG_PM
3173 au1xxx_pm_access(LCD_pm_dev);
3174#endif
3175
3176 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) {
3177 return -EINVAL;
3178 }
3179
3180 start = fbdev->fb_phys & PAGE_MASK;
3181 len = PAGE_ALIGN((start & ~PAGE_MASK) + fbdev->fb_len);
3182
3183 off = vma->vm_pgoff << PAGE_SHIFT;
3184
3185 if ((vma->vm_end - vma->vm_start + off) > len) {
3186 return -EINVAL;
3187 }
3188
3189 off += start;
3190 vma->vm_pgoff = off >> PAGE_SHIFT;
3191
3192 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3193 pgprot_val(vma->vm_page_prot) |= _CACHE_MASK; /* CCA=7 */
3194
3195 vma->vm_flags |= VM_IO;
3196
3197 return io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
3198 vma->vm_end - vma->vm_start,
3199 vma->vm_page_prot);
3200
3201 return 0;
3202}
3203
3204static void set_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata)
3205{
3206
3207 unsigned int hi1, divider;
3208
3209 /* SCREEN_SIZE: user cannot reset size, must switch panel choice */
3210
3211 if (pdata->flags & SCREEN_BACKCOLOR)
3212 lcd->backcolor = pdata->backcolor;
3213
3214 if (pdata->flags & SCREEN_BRIGHTNESS) {
3215
3216 // limit brightness pwm duty to >= 30/1600
3217 if (pdata->brightness < 30) {
3218 pdata->brightness = 30;
3219 }
3220 divider = (lcd->pwmdiv & 0x3FFFF) + 1;
3221 hi1 = (lcd->pwmhi >> 16) + 1;
3222 hi1 = (((pdata->brightness & 0xFF)+1) * divider >> 8);
3223 lcd->pwmhi &= 0xFFFF;
3224 lcd->pwmhi |= (hi1 << 16);
3225 }
3226
3227 if (pdata->flags & SCREEN_COLORKEY)
3228 lcd->colorkey = pdata->colorkey;
3229
3230 if (pdata->flags & SCREEN_MASK)
3231 lcd->colorkeymsk = pdata->mask;
3232 au_sync();
3233}
3234
3235static void get_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata)
3236{
3237 unsigned int hi1, divider;
3238
3239 pdata->xsize = ((lcd->screen & LCD_SCREEN_SX) >> 19) + 1;
3240 pdata->ysize = ((lcd->screen & LCD_SCREEN_SY) >> 8) + 1;
3241
3242 pdata->backcolor = lcd->backcolor;
3243 pdata->colorkey = lcd->colorkey;
3244 pdata->mask = lcd->colorkeymsk;
3245
3246 // brightness
3247 hi1 = (lcd->pwmhi >> 16) + 1;
3248 divider = (lcd->pwmdiv & 0x3FFFF) + 1;
3249 pdata->brightness = ((hi1 << 8) / divider) - 1;
3250 au_sync();
3251}
3252
3253static void set_window(unsigned int plane,
3254 struct au1200_lcd_window_regs_t *pdata)
3255{
3256 unsigned int val, bpp;
3257
3258 /* Window control register 0 */
3259 if (pdata->flags & WIN_POSITION) {
3260 val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_OX |
3261 LCD_WINCTRL0_OY);
3262 val |= ((pdata->xpos << 21) & LCD_WINCTRL0_OX);
3263 val |= ((pdata->ypos << 10) & LCD_WINCTRL0_OY);
3264 lcd->window[plane].winctrl0 = val;
3265 }
3266 if (pdata->flags & WIN_ALPHA_COLOR) {
3267 val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_A);
3268 val |= ((pdata->alpha_color << 2) & LCD_WINCTRL0_A);
3269 lcd->window[plane].winctrl0 = val;
3270 }
3271 if (pdata->flags & WIN_ALPHA_MODE) {
3272 val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_AEN);
3273 val |= ((pdata->alpha_mode << 1) & LCD_WINCTRL0_AEN);
3274 lcd->window[plane].winctrl0 = val;
3275 }
3276
3277 /* Window control register 1 */
3278 if (pdata->flags & WIN_PRIORITY) {
3279 val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PRI);
3280 val |= ((pdata->priority << 30) & LCD_WINCTRL1_PRI);
3281 lcd->window[plane].winctrl1 = val;
3282 }
3283 if (pdata->flags & WIN_CHANNEL) {
3284 val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PIPE);
3285 val |= ((pdata->channel << 29) & LCD_WINCTRL1_PIPE);
3286 lcd->window[plane].winctrl1 = val;
3287 }
3288 if (pdata->flags & WIN_BUFFER_FORMAT) {
3289 val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_FRM);
3290 val |= ((pdata->buffer_format << 25) & LCD_WINCTRL1_FRM);
3291 lcd->window[plane].winctrl1 = val;
3292 }
3293 if (pdata->flags & WIN_COLOR_ORDER) {
3294 val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_CCO);
3295 val |= ((pdata->color_order << 24) & LCD_WINCTRL1_CCO);
3296 lcd->window[plane].winctrl1 = val;
3297 }
3298 if (pdata->flags & WIN_PIXEL_ORDER) {
3299 val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PO);
3300 val |= ((pdata->pixel_order << 22) & LCD_WINCTRL1_PO);
3301 lcd->window[plane].winctrl1 = val;
3302 }
3303 if (pdata->flags & WIN_SIZE) {
3304 val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_SZX |
3305 LCD_WINCTRL1_SZY);
3306 val |= (((pdata->xsize << 11) - 1) & LCD_WINCTRL1_SZX);
3307 val |= (((pdata->ysize) - 1) & LCD_WINCTRL1_SZY);
3308 lcd->window[plane].winctrl1 = val;
3309 /* program buffer line width */
3310 bpp = winbpp(val) / 8;
3311 val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_BX);
3312 val |= (((pdata->xsize * bpp) << 8) & LCD_WINCTRL2_BX);
3313 lcd->window[plane].winctrl2 = val;
3314 }
3315
3316 /* Window control register 2 */
3317 if (pdata->flags & WIN_COLORKEY_MODE) {
3318 val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_CKMODE);
3319 val |= ((pdata->colorkey_mode << 24) & LCD_WINCTRL2_CKMODE);
3320 lcd->window[plane].winctrl2 = val;
3321 }
3322 if (pdata->flags & WIN_DOUBLE_BUFFER_MODE) {
3323 val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_DBM);
3324 val |= ((pdata->double_buffer_mode << 23) & LCD_WINCTRL2_DBM);
3325 lcd->window[plane].winctrl2 = val;
3326 }
3327 if (pdata->flags & WIN_RAM_ARRAY_MODE) {
3328 val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_RAM);
3329 val |= ((pdata->ram_array_mode << 21) & LCD_WINCTRL2_RAM);
3330 lcd->window[plane].winctrl2 = val;
3331 }
3332
3333 /* Buffer line width programmed with WIN_SIZE */
3334
3335 if (pdata->flags & WIN_BUFFER_SCALE) {
3336 val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_SCX |
3337 LCD_WINCTRL2_SCY);
3338 val |= ((pdata->xsize << 11) & LCD_WINCTRL2_SCX);
3339 val |= ((pdata->ysize) & LCD_WINCTRL2_SCY);
3340 lcd->window[plane].winctrl2 = val;
3341 }
3342
3343 if (pdata->flags & WIN_ENABLE) {
3344 val = lcd->winenable;
3345 val &= ~(1<<plane);
3346 val |= (pdata->enable & 1) << plane;
3347 lcd->winenable = val;
3348 }
3349 au_sync();
3350}
3351
3352static void get_window(unsigned int plane,
3353 struct au1200_lcd_window_regs_t *pdata)
3354{
3355 /* Window control register 0 */
3356 pdata->xpos = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_OX) >> 21;
3357 pdata->ypos = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_OY) >> 10;
3358 pdata->alpha_color = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_A) >> 2;
3359 pdata->alpha_mode = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_AEN) >> 1;
3360
3361 /* Window control register 1 */
3362 pdata->priority = (lcd->window[plane].winctrl1& LCD_WINCTRL1_PRI) >> 30;
3363 pdata->channel = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_PIPE) >> 29;
3364 pdata->buffer_format = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_FRM) >> 25;
3365 pdata->color_order = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_CCO) >> 24;
3366 pdata->pixel_order = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_PO) >> 22;
3367 pdata->xsize = ((lcd->window[plane].winctrl1 & LCD_WINCTRL1_SZX) >> 11) + 1;
3368 pdata->ysize = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_SZY) + 1;
3369
3370 /* Window control register 2 */
3371 pdata->colorkey_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_CKMODE) >> 24;
3372 pdata->double_buffer_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_DBM) >> 23;
3373 pdata->ram_array_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_RAM) >> 21;
3374
3375 pdata->enable = (lcd->winenable >> plane) & 1;
3376 au_sync();
3377}
3378
3379static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd,
3380 unsigned long arg)
3381{
3382 int plane;
3383 int val;
3384
3385#ifdef CONFIG_PM
3386 au1xxx_pm_access(LCD_pm_dev);
3387#endif
3388
3389 plane = fbinfo2index(info);
3390 print_dbg("au1200fb: ioctl %d on plane %d\n", cmd, plane);
3391
3392 if (cmd == AU1200_LCD_FB_IOCTL) {
3393 struct au1200_lcd_iodata_t iodata;
3394
3395 if (copy_from_user(&iodata, (void __user *) arg, sizeof(iodata)))
3396 return -EFAULT;
3397
3398 print_dbg("FB IOCTL called\n");
3399
3400 switch (iodata.subcmd) {
3401 case AU1200_LCD_SET_SCREEN:
3402 print_dbg("AU1200_LCD_SET_SCREEN\n");
3403 set_global(cmd, &iodata.global);
3404 break;
3405
3406 case AU1200_LCD_GET_SCREEN:
3407 print_dbg("AU1200_LCD_GET_SCREEN\n");
3408 get_global(cmd, &iodata.global);
3409 break;
3410
3411 case AU1200_LCD_SET_WINDOW:
3412 print_dbg("AU1200_LCD_SET_WINDOW\n");
3413 set_window(plane, &iodata.window);
3414 break;
3415
3416 case AU1200_LCD_GET_WINDOW:
3417 print_dbg("AU1200_LCD_GET_WINDOW\n");
3418 get_window(plane, &iodata.window);
3419 break;
3420
3421 case AU1200_LCD_SET_PANEL:
3422 print_dbg("AU1200_LCD_SET_PANEL\n");
3423 if ((iodata.global.panel_choice >= 0) &&
3424 (iodata.global.panel_choice <
3425 NUM_PANELS))
3426 {
3427 struct panel_settings *newpanel;
3428 panel_index = iodata.global.panel_choice;
3429 newpanel = &known_lcd_panels[panel_index];
3430 au1200_setpanel(newpanel);
3431 }
3432 break;
3433
3434 case AU1200_LCD_GET_PANEL:
3435 print_dbg("AU1200_LCD_GET_PANEL\n");
3436 iodata.global.panel_choice = panel_index;
3437 break;
3438
3439 default:
3440 return -EINVAL;
3441 }
3442
3443 val = copy_to_user((void __user *) arg, &iodata, sizeof(iodata));
3444 if (val) {
3445 print_dbg("error: could not copy %d bytes\n", val);
3446 return -EFAULT;
3447 }
3448 }
3449
3450 return 0;
3451}
3452
3453
3454static struct fb_ops au1200fb_fb_ops = {
3455 .owner = THIS_MODULE,
3456 .fb_check_var = au1200fb_fb_check_var,
3457 .fb_set_par = au1200fb_fb_set_par,
3458 .fb_setcolreg = au1200fb_fb_setcolreg,
3459 .fb_blank = au1200fb_fb_blank,
3460 .fb_fillrect = cfb_fillrect,
3461 .fb_copyarea = cfb_copyarea,
3462 .fb_imageblit = cfb_imageblit,
3463 .fb_sync = NULL,
3464 .fb_ioctl = au1200fb_ioctl,
3465 .fb_mmap = au1200fb_fb_mmap,
3466};
3467
3468/*-------------------------------------------------------------------------*/
3469
3470static irqreturn_t au1200fb_handle_irq(int irq, void* dev_id, struct pt_regs *regs)
3471{
3472 /* Nothing to do for now, just clear any pending interrupt */
3473 lcd->intstatus = lcd->intstatus;
3474 au_sync();
3475
3476 return IRQ_HANDLED;
3477}
3478
3479/*-------------------------------------------------------------------------*/
3480
3481/* AU1200 LCD device probe helpers */
3482
3483static int au1200fb_init_fbinfo(struct au1200fb_device *fbdev)
3484{
3485 struct fb_info *fbi = &fbdev->fb_info;
3486 int bpp;
3487
3488 memset(fbi, 0, sizeof(struct fb_info));
3489 fbi->fbops = &au1200fb_fb_ops;
3490
3491 bpp = winbpp(win->w[fbdev->plane].mode_winctrl1);
3492
3493 /* Copy monitor specs from panel data */
3494 /* fixme: we're setting up LCD controller windows, so these dont give a
3495 damn as to what the monitor specs are (the panel itself does, but that
3496 isnt done here...so maybe need a generic catchall monitor setting??? */
3497 memcpy(&fbi->monspecs, &panel->monspecs, sizeof(struct fb_monspecs));
3498
3499 /* We first try the user mode passed in argument. If that failed,
3500 * or if no one has been specified, we default to the first mode of the
3501 * panel list. Note that after this call, var data will be set */
3502 if (!fb_find_mode(&fbi->var,
3503 fbi,
3504 NULL, /* drv_info.opt_mode, */
3505 fbi->monspecs.modedb,
3506 fbi->monspecs.modedb_len,
3507 fbi->monspecs.modedb,
3508 bpp)) {
3509
3510 print_err("Cannot find valid mode for panel %s", panel->name);
3511 return -EFAULT;
3512 }
3513
3514 fbi->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
3515 if (!fbi->pseudo_palette) {
3516 return -ENOMEM;
3517 }
3518 memset(fbi->pseudo_palette, 0, sizeof(u32) * 16);
3519
3520 if (fb_alloc_cmap(&fbi->cmap, AU1200_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
3521 print_err("Fail to allocate colormap (%d entries)",
3522 AU1200_LCD_NBR_PALETTE_ENTRIES);
3523 kfree(fbi->pseudo_palette);
3524 return -EFAULT;
3525 }
3526
3527 strncpy(fbi->fix.id, "AU1200", sizeof(fbi->fix.id));
3528 fbi->fix.smem_start = fbdev->fb_phys;
3529 fbi->fix.smem_len = fbdev->fb_len;
3530 fbi->fix.type = FB_TYPE_PACKED_PIXELS;
3531 fbi->fix.xpanstep = 0;
3532 fbi->fix.ypanstep = 0;
3533 fbi->fix.mmio_start = 0;
3534 fbi->fix.mmio_len = 0;
3535 fbi->fix.accel = FB_ACCEL_NONE;
3536
3537 fbi->screen_base = (char __iomem *) fbdev->fb_mem;
3538
3539 au1200fb_update_fbinfo(fbi);
3540
3541 return 0;
3542}
3543
3544/*-------------------------------------------------------------------------*/
3545
3546/* AU1200 LCD controller device driver */
3547
3548static int au1200fb_drv_probe(struct device *dev)
3549{
3550 struct au1200fb_device *fbdev;
3551 unsigned long page;
3552 int bpp, plane, ret;
3553
3554 if (!dev)
3555 return -EINVAL;
3556
3557 for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane) {
3558 bpp = winbpp(win->w[plane].mode_winctrl1);
3559 if (win->w[plane].xres == 0)
3560 win->w[plane].xres = panel->Xres;
3561 if (win->w[plane].yres == 0)
3562 win->w[plane].yres = panel->Yres;
3563
3564 fbdev = &_au1200fb_devices[plane];
3565 memset(fbdev, 0, sizeof(struct au1200fb_device));
3566 fbdev->plane = plane;
3567
3568 /* Allocate the framebuffer to the maximum screen size */
3569 fbdev->fb_len = (win->w[plane].xres * win->w[plane].yres * bpp) / 8;
3570
3571 fbdev->fb_mem = dma_alloc_noncoherent(dev,
3572 PAGE_ALIGN(fbdev->fb_len),
3573 &fbdev->fb_phys, GFP_KERNEL);
3574 if (!fbdev->fb_mem) {
3575 print_err("fail to allocate frambuffer (size: %dK))",
3576 fbdev->fb_len / 1024);
3577 return -ENOMEM;
3578 }
3579
3580 /*
3581 * Set page reserved so that mmap will work. This is necessary
3582 * since we'll be remapping normal memory.
3583 */
3584 for (page = (unsigned long)fbdev->fb_phys;
3585 page < PAGE_ALIGN((unsigned long)fbdev->fb_phys +
3586 fbdev->fb_len);
3587 page += PAGE_SIZE) {
3588 SetPageReserved(pfn_to_page(page >> PAGE_SHIFT)); /* LCD DMA is NOT coherent on Au1200 */
3589 }
3590 print_dbg("Framebuffer memory map at %p", fbdev->fb_mem);
3591 print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024);
3592
3593 /* Init FB data */
3594 if ((ret = au1200fb_init_fbinfo(fbdev)) < 0)
3595 goto failed;
3596
3597 /* Register new framebuffer */
3598 if ((ret = register_framebuffer(&fbdev->fb_info)) < 0) {
3599 print_err("cannot register new framebuffer");
3600 goto failed;
3601 }
3602
3603 au1200fb_fb_set_par(&fbdev->fb_info);
3604
3605#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
3606 if (plane == 0)
3607 if (fb_prepare_logo(&fbdev->fb_info, FB_ROTATE_UR)) {
3608 /* Start display and show logo on boot */
3609 fb_set_cmap(&fbdev->fb_info.cmap,
3610 &fbdev->fb_info);
3611
3612 fb_show_logo(&fbdev->fb_info, FB_ROTATE_UR);
3613 }
3614#endif
3615 }
3616
3617 /* Now hook interrupt too */
3618 if ((ret = request_irq(AU1200_LCD_INT, au1200fb_handle_irq,
3619 SA_INTERRUPT | SA_SHIRQ, "lcd", (void *)dev)) < 0) {
3620 print_err("fail to request interrupt line %d (err: %d)",
3621 AU1200_LCD_INT, ret);
3622 goto failed;
3623 }
3624
3625 return 0;
3626
3627failed:
3628 /* NOTE: This only does the current plane/window that failed; others are still active */
3629 if (fbdev->fb_mem)
3630 dma_free_noncoherent(dev, PAGE_ALIGN(fbdev->fb_len),
3631 fbdev->fb_mem, fbdev->fb_phys);
3632 if (fbdev->fb_info.cmap.len != 0)
3633 fb_dealloc_cmap(&fbdev->fb_info.cmap);
3634 if (fbdev->fb_info.pseudo_palette)
3635 kfree(fbdev->fb_info.pseudo_palette);
3636 if (plane == 0)
3637 free_irq(AU1200_LCD_INT, (void*)dev);
3638 return ret;
3639}
3640
3641static int au1200fb_drv_remove(struct device *dev)
3642{
3643 struct au1200fb_device *fbdev;
3644 int plane;
3645
3646 if (!dev)
3647 return -ENODEV;
3648
3649 /* Turn off the panel */
3650 au1200_setpanel(NULL);
3651
3652 for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane)
3653 {
3654 fbdev = &_au1200fb_devices[plane];
3655
3656 /* Clean up all probe data */
3657 unregister_framebuffer(&fbdev->fb_info);
3658 if (fbdev->fb_mem)
3659 dma_free_noncoherent(dev, PAGE_ALIGN(fbdev->fb_len),
3660 fbdev->fb_mem, fbdev->fb_phys);
3661 if (fbdev->fb_info.cmap.len != 0)
3662 fb_dealloc_cmap(&fbdev->fb_info.cmap);
3663 if (fbdev->fb_info.pseudo_palette)
3664 kfree(fbdev->fb_info.pseudo_palette);
3665 }
3666
3667 free_irq(AU1200_LCD_INT, (void *)dev);
3668
3669 return 0;
3670}
3671
3672#ifdef CONFIG_PM
3673static int au1200fb_drv_suspend(struct device *dev, u32 state, u32 level)
3674{
3675 /* TODO */
3676 return 0;
3677}
3678
3679static int au1200fb_drv_resume(struct device *dev, u32 level)
3680{
3681 /* TODO */
3682 return 0;
3683}
3684#endif /* CONFIG_PM */
3685
3686static struct device_driver au1200fb_driver = {
3687 .name = "au1200-lcd",
3688 .bus = &platform_bus_type,
3689 .probe = au1200fb_drv_probe,
3690 .remove = au1200fb_drv_remove,
3691#ifdef CONFIG_PM
3692 .suspend = au1200fb_drv_suspend,
3693 .resume = au1200fb_drv_resume,
3694#endif
3695};
3696
3697/*-------------------------------------------------------------------------*/
3698
3699/* Kernel driver */
3700
3701static void au1200fb_setup(void)
3702{
3703 char* options = NULL;
3704 char* this_opt;
3705 int num_panels = ARRAY_SIZE(known_lcd_panels);
3706 int panel_idx = -1;
3707
3708 fb_get_options(DRIVER_NAME, &options);
3709
3710 if (options) {
3711 while ((this_opt = strsep(&options,",")) != NULL) {
3712 /* Panel option - can be panel name,
3713 * "bs" for board-switch, or number/index */
3714 if (!strncmp(this_opt, "panel:", 6)) {
3715 int i;
3716 long int li;
3717 char *endptr;
3718 this_opt += 6;
3719 /* First check for index, which allows
3720 * to short circuit this mess */
3721 li = simple_strtol(this_opt, &endptr, 0);
3722 if (*endptr == '\0') {
3723 panel_idx = (int)li;
3724 }
3725 else if (strcmp(this_opt, "bs") == 0) {
3726 extern int board_au1200fb_panel(void);
3727 panel_idx = board_au1200fb_panel();
3728 }
3729
3730 else
3731 for (i = 0; i < num_panels; i++) {
3732 if (!strcmp(this_opt, known_lcd_panels[i].name)) {
3733 panel_idx = i;
3734 break;
3735 }
3736 }
3737
3738 if ((panel_idx < 0) || (panel_idx >= num_panels)) {
3739 print_warn("Panel %s not supported!", this_opt);
3740 }
3741 else
3742 panel_index = panel_idx;
3743 }
3744
3745 else if (strncmp(this_opt, "nohwcursor", 10) == 0) {
3746 nohwcursor = 1;
3747 }
3748
3749 /* Unsupported option */
3750 else {
3751 print_warn("Unsupported option \"%s\"", this_opt);
3752 }
3753 }
3754 }
3755}
3756
3757#ifdef CONFIG_PM
3758static int au1200fb_pm_callback(au1xxx_power_dev_t *dev,
3759 au1xxx_request_t request, void *data) {
3760 int retval = -1;
3761 unsigned int d = 0;
3762 unsigned int brightness = 0;
3763
3764 if (request == AU1XXX_PM_SLEEP) {
3765 board_au1200fb_panel_shutdown();
3766 }
3767 else if (request == AU1XXX_PM_WAKEUP) {
3768 if(dev->prev_state == SLEEP_STATE)
3769 {
3770 int plane;
3771 au1200_setpanel(panel);
3772 for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane) {
3773 struct au1200fb_device *fbdev;
3774 fbdev = &_au1200fb_devices[plane];
3775 au1200fb_fb_set_par(&fbdev->fb_info);
3776 }
3777 }
3778
3779 d = *((unsigned int*)data);
3780 if(d <=10) brightness = 26;
3781 else if(d<=20) brightness = 51;
3782 else if(d<=30) brightness = 77;
3783 else if(d<=40) brightness = 102;
3784 else if(d<=50) brightness = 128;
3785 else if(d<=60) brightness = 153;
3786 else if(d<=70) brightness = 179;
3787 else if(d<=80) brightness = 204;
3788 else if(d<=90) brightness = 230;
3789 else brightness = 255;
3790 set_brightness(brightness);
3791 } else if (request == AU1XXX_PM_GETSTATUS) {
3792 return dev->cur_state;
3793 } else if (request == AU1XXX_PM_ACCESS) {
3794 if (dev->cur_state != SLEEP_STATE)
3795 return retval;
3796 else {
3797 au1200_setpanel(panel);
3798 }
3799 } else if (request == AU1XXX_PM_IDLE) {
3800 } else if (request == AU1XXX_PM_CLEANUP) {
3801 }
3802
3803 return retval;
3804}
3805#endif
3806
3807static int __init au1200fb_init(void)
3808{
3809 print_info("" DRIVER_DESC "");
3810
3811 /* Setup driver with options */
3812 au1200fb_setup();
3813
3814 /* Point to the panel selected */
3815 panel = &known_lcd_panels[panel_index];
3816 win = &windows[window_index];
3817
3818 printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name);
3819 printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name);
3820
3821 /* Kickstart the panel, the framebuffers/windows come soon enough */
3822 au1200_setpanel(panel);
3823
3824 #ifdef CONFIG_PM
3825 LCD_pm_dev = new_au1xxx_power_device("LCD", &au1200fb_pm_callback, NULL);
3826 if ( LCD_pm_dev == NULL)
3827 printk(KERN_INFO "Unable to create a power management device entry for the au1200fb.\n");
3828 else
3829 printk(KERN_INFO "Power management device entry for the au1200fb loaded.\n");
3830 #endif
3831
3832 return driver_register(&au1200fb_driver);
3833}
3834
3835static void __exit au1200fb_cleanup(void)
3836{
3837 driver_unregister(&au1200fb_driver);
3838}
3839
3840module_init(au1200fb_init);
3841module_exit(au1200fb_cleanup);
3842
3843MODULE_DESCRIPTION(DRIVER_DESC);
3844MODULE_LICENSE("GPL");
diff --git a/drivers/video/au1200fb.h b/drivers/video/au1200fb.h
new file mode 100644
index 000000000000..e2672714d8d4
--- /dev/null
+++ b/drivers/video/au1200fb.h
@@ -0,0 +1,572 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Hardware definitions for the Au1200 LCD controller
4 *
5 * Copyright 2004 AMD
6 * Author: AMD
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef _AU1200LCD_H
30#define _AU1200LCD_H
31
32/********************************************************************/
33#define AU1200_LCD_ADDR 0xB5000000
34
35#define uint8 unsigned char
36#define uint32 unsigned int
37
38struct au1200_lcd {
39 volatile uint32 reserved0;
40 volatile uint32 screen;
41 volatile uint32 backcolor;
42 volatile uint32 horztiming;
43 volatile uint32 verttiming;
44 volatile uint32 clkcontrol;
45 volatile uint32 pwmdiv;
46 volatile uint32 pwmhi;
47 volatile uint32 reserved1;
48 volatile uint32 winenable;
49 volatile uint32 colorkey;
50 volatile uint32 colorkeymsk;
51 struct
52 {
53 volatile uint32 cursorctrl;
54 volatile uint32 cursorpos;
55 volatile uint32 cursorcolor0;
56 volatile uint32 cursorcolor1;
57 volatile uint32 cursorcolor2;
58 uint32 cursorcolor3;
59 } hwc;
60 volatile uint32 intstatus;
61 volatile uint32 intenable;
62 volatile uint32 outmask;
63 volatile uint32 fifoctrl;
64 uint32 reserved2[(0x0100-0x0058)/4];
65 struct
66 {
67 volatile uint32 winctrl0;
68 volatile uint32 winctrl1;
69 volatile uint32 winctrl2;
70 volatile uint32 winbuf0;
71 volatile uint32 winbuf1;
72 volatile uint32 winbufctrl;
73 uint32 winreserved0;
74 uint32 winreserved1;
75 } window[4];
76
77 uint32 reserved3[(0x0400-0x0180)/4];
78
79 volatile uint32 palette[(0x0800-0x0400)/4];
80
81 volatile uint8 cursorpattern[256];
82};
83
84/* lcd_screen */
85#define LCD_SCREEN_SEN (1<<31)
86#define LCD_SCREEN_SX (0x07FF<<19)
87#define LCD_SCREEN_SY (0x07FF<< 8)
88#define LCD_SCREEN_SWP (1<<7)
89#define LCD_SCREEN_SWD (1<<6)
90#define LCD_SCREEN_PT (7<<0)
91#define LCD_SCREEN_PT_TFT (0<<0)
92#define LCD_SCREEN_SX_N(WIDTH) ((WIDTH-1)<<19)
93#define LCD_SCREEN_SY_N(HEIGHT) ((HEIGHT-1)<<8)
94#define LCD_SCREEN_PT_CSTN (1<<0)
95#define LCD_SCREEN_PT_CDSTN (2<<0)
96#define LCD_SCREEN_PT_M8STN (3<<0)
97#define LCD_SCREEN_PT_M4STN (4<<0)
98
99/* lcd_backcolor */
100#define LCD_BACKCOLOR_SBGR (0xFF<<16)
101#define LCD_BACKCOLOR_SBGG (0xFF<<8)
102#define LCD_BACKCOLOR_SBGB (0xFF<<0)
103#define LCD_BACKCOLOR_SBGR_N(N) ((N)<<16)
104#define LCD_BACKCOLOR_SBGG_N(N) ((N)<<8)
105#define LCD_BACKCOLOR_SBGB_N(N) ((N)<<0)
106
107/* lcd_winenable */
108#define LCD_WINENABLE_WEN3 (1<<3)
109#define LCD_WINENABLE_WEN2 (1<<2)
110#define LCD_WINENABLE_WEN1 (1<<1)
111#define LCD_WINENABLE_WEN0 (1<<0)
112
113/* lcd_colorkey */
114#define LCD_COLORKEY_CKR (0xFF<<16)
115#define LCD_COLORKEY_CKG (0xFF<<8)
116#define LCD_COLORKEY_CKB (0xFF<<0)
117#define LCD_COLORKEY_CKR_N(N) ((N)<<16)
118#define LCD_COLORKEY_CKG_N(N) ((N)<<8)
119#define LCD_COLORKEY_CKB_N(N) ((N)<<0)
120
121/* lcd_colorkeymsk */
122#define LCD_COLORKEYMSK_CKMR (0xFF<<16)
123#define LCD_COLORKEYMSK_CKMG (0xFF<<8)
124#define LCD_COLORKEYMSK_CKMB (0xFF<<0)
125#define LCD_COLORKEYMSK_CKMR_N(N) ((N)<<16)
126#define LCD_COLORKEYMSK_CKMG_N(N) ((N)<<8)
127#define LCD_COLORKEYMSK_CKMB_N(N) ((N)<<0)
128
129/* lcd windows control 0 */
130#define LCD_WINCTRL0_OX (0x07FF<<21)
131#define LCD_WINCTRL0_OY (0x07FF<<10)
132#define LCD_WINCTRL0_A (0x00FF<<2)
133#define LCD_WINCTRL0_AEN (1<<1)
134#define LCD_WINCTRL0_OX_N(N) ((N)<<21)
135#define LCD_WINCTRL0_OY_N(N) ((N)<<10)
136#define LCD_WINCTRL0_A_N(N) ((N)<<2)
137
138/* lcd windows control 1 */
139#define LCD_WINCTRL1_PRI (3<<30)
140#define LCD_WINCTRL1_PIPE (1<<29)
141#define LCD_WINCTRL1_FRM (0xF<<25)
142#define LCD_WINCTRL1_CCO (1<<24)
143#define LCD_WINCTRL1_PO (3<<22)
144#define LCD_WINCTRL1_SZX (0x07FF<<11)
145#define LCD_WINCTRL1_SZY (0x07FF<<0)
146#define LCD_WINCTRL1_FRM_1BPP (0<<25)
147#define LCD_WINCTRL1_FRM_2BPP (1<<25)
148#define LCD_WINCTRL1_FRM_4BPP (2<<25)
149#define LCD_WINCTRL1_FRM_8BPP (3<<25)
150#define LCD_WINCTRL1_FRM_12BPP (4<<25)
151#define LCD_WINCTRL1_FRM_16BPP655 (5<<25)
152#define LCD_WINCTRL1_FRM_16BPP565 (6<<25)
153#define LCD_WINCTRL1_FRM_16BPP556 (7<<25)
154#define LCD_WINCTRL1_FRM_16BPPI1555 (8<<25)
155#define LCD_WINCTRL1_FRM_16BPPI5551 (9<<25)
156#define LCD_WINCTRL1_FRM_16BPPA1555 (10<<25)
157#define LCD_WINCTRL1_FRM_16BPPA5551 (11<<25)
158#define LCD_WINCTRL1_FRM_24BPP (12<<25)
159#define LCD_WINCTRL1_FRM_32BPP (13<<25)
160#define LCD_WINCTRL1_PRI_N(N) ((N)<<30)
161#define LCD_WINCTRL1_PO_00 (0<<22)
162#define LCD_WINCTRL1_PO_01 (1<<22)
163#define LCD_WINCTRL1_PO_10 (2<<22)
164#define LCD_WINCTRL1_PO_11 (3<<22)
165#define LCD_WINCTRL1_SZX_N(N) ((N-1)<<11)
166#define LCD_WINCTRL1_SZY_N(N) ((N-1)<<0)
167
168/* lcd windows control 2 */
169#define LCD_WINCTRL2_CKMODE (3<<24)
170#define LCD_WINCTRL2_DBM (1<<23)
171#define LCD_WINCTRL2_RAM (3<<21)
172#define LCD_WINCTRL2_BX (0x1FFF<<8)
173#define LCD_WINCTRL2_SCX (0xF<<4)
174#define LCD_WINCTRL2_SCY (0xF<<0)
175#define LCD_WINCTRL2_CKMODE_00 (0<<24)
176#define LCD_WINCTRL2_CKMODE_01 (1<<24)
177#define LCD_WINCTRL2_CKMODE_10 (2<<24)
178#define LCD_WINCTRL2_CKMODE_11 (3<<24)
179#define LCD_WINCTRL2_RAM_NONE (0<<21)
180#define LCD_WINCTRL2_RAM_PALETTE (1<<21)
181#define LCD_WINCTRL2_RAM_GAMMA (2<<21)
182#define LCD_WINCTRL2_RAM_BUFFER (3<<21)
183#define LCD_WINCTRL2_BX_N(N) ((N)<<8)
184#define LCD_WINCTRL2_SCX_1 (0<<4)
185#define LCD_WINCTRL2_SCX_2 (1<<4)
186#define LCD_WINCTRL2_SCX_4 (2<<4)
187#define LCD_WINCTRL2_SCY_1 (0<<0)
188#define LCD_WINCTRL2_SCY_2 (1<<0)
189#define LCD_WINCTRL2_SCY_4 (2<<0)
190
191/* lcd windows buffer control */
192#define LCD_WINBUFCTRL_DB (1<<1)
193#define LCD_WINBUFCTRL_DBN (1<<0)
194
195/* lcd_intstatus, lcd_intenable */
196#define LCD_INT_IFO (0xF<<14)
197#define LCD_INT_IFU (0xF<<10)
198#define LCD_INT_OFO (1<<9)
199#define LCD_INT_OFU (1<<8)
200#define LCD_INT_WAIT (1<<3)
201#define LCD_INT_SD (1<<2)
202#define LCD_INT_SA (1<<1)
203#define LCD_INT_SS (1<<0)
204
205/* lcd_horztiming */
206#define LCD_HORZTIMING_HND2 (0x1FF<<18)
207#define LCD_HORZTIMING_HND1 (0x1FF<<9)
208#define LCD_HORZTIMING_HPW (0x1FF<<0)
209#define LCD_HORZTIMING_HND2_N(N)(((N)-1)<<18)
210#define LCD_HORZTIMING_HND1_N(N)(((N)-1)<<9)
211#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<0)
212
213/* lcd_verttiming */
214#define LCD_VERTTIMING_VND2 (0x1FF<<18)
215#define LCD_VERTTIMING_VND1 (0x1FF<<9)
216#define LCD_VERTTIMING_VPW (0x1FF<<0)
217#define LCD_VERTTIMING_VND2_N(N)(((N)-1)<<18)
218#define LCD_VERTTIMING_VND1_N(N)(((N)-1)<<9)
219#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<0)
220
221/* lcd_clkcontrol */
222#define LCD_CLKCONTROL_EXT (1<<22)
223#define LCD_CLKCONTROL_DELAY (3<<20)
224#define LCD_CLKCONTROL_CDD (1<<19)
225#define LCD_CLKCONTROL_IB (1<<18)
226#define LCD_CLKCONTROL_IC (1<<17)
227#define LCD_CLKCONTROL_IH (1<<16)
228#define LCD_CLKCONTROL_IV (1<<15)
229#define LCD_CLKCONTROL_BF (0x1F<<10)
230#define LCD_CLKCONTROL_PCD (0x3FF<<0)
231#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10)
232#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0)
233
234/* lcd_pwmdiv */
235#define LCD_PWMDIV_EN (1<<31)
236#define LCD_PWMDIV_PWMDIV (0x1FFFF<<0)
237#define LCD_PWMDIV_PWMDIV_N(N) ((N)<<0)
238
239/* lcd_pwmhi */
240#define LCD_PWMHI_PWMHI1 (0xFFFF<<16)
241#define LCD_PWMHI_PWMHI0 (0xFFFF<<0)
242#define LCD_PWMHI_PWMHI1_N(N) ((N)<<16)
243#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0)
244
245/* lcd_hwccon */
246#define LCD_HWCCON_EN (1<<0)
247
248/* lcd_cursorpos */
249#define LCD_CURSORPOS_HWCXOFF (0x1F<<27)
250#define LCD_CURSORPOS_HWCXPOS (0x07FF<<16)
251#define LCD_CURSORPOS_HWCYOFF (0x1F<<11)
252#define LCD_CURSORPOS_HWCYPOS (0x07FF<<0)
253#define LCD_CURSORPOS_HWCXOFF_N(N) ((N)<<27)
254#define LCD_CURSORPOS_HWCXPOS_N(N) ((N)<<16)
255#define LCD_CURSORPOS_HWCYOFF_N(N) ((N)<<11)
256#define LCD_CURSORPOS_HWCYPOS_N(N) ((N)<<0)
257
258/* lcd_cursorcolor */
259#define LCD_CURSORCOLOR_HWCA (0xFF<<24)
260#define LCD_CURSORCOLOR_HWCR (0xFF<<16)
261#define LCD_CURSORCOLOR_HWCG (0xFF<<8)
262#define LCD_CURSORCOLOR_HWCB (0xFF<<0)
263#define LCD_CURSORCOLOR_HWCA_N(N) ((N)<<24)
264#define LCD_CURSORCOLOR_HWCR_N(N) ((N)<<16)
265#define LCD_CURSORCOLOR_HWCG_N(N) ((N)<<8)
266#define LCD_CURSORCOLOR_HWCB_N(N) ((N)<<0)
267
268/* lcd_fifoctrl */
269#define LCD_FIFOCTRL_F3IF (1<<29)
270#define LCD_FIFOCTRL_F3REQ (0x1F<<24)
271#define LCD_FIFOCTRL_F2IF (1<<29)
272#define LCD_FIFOCTRL_F2REQ (0x1F<<16)
273#define LCD_FIFOCTRL_F1IF (1<<29)
274#define LCD_FIFOCTRL_F1REQ (0x1F<<8)
275#define LCD_FIFOCTRL_F0IF (1<<29)
276#define LCD_FIFOCTRL_F0REQ (0x1F<<0)
277#define LCD_FIFOCTRL_F3REQ_N(N) ((N-1)<<24)
278#define LCD_FIFOCTRL_F2REQ_N(N) ((N-1)<<16)
279#define LCD_FIFOCTRL_F1REQ_N(N) ((N-1)<<8)
280#define LCD_FIFOCTRL_F0REQ_N(N) ((N-1)<<0)
281
282/* lcd_outmask */
283#define LCD_OUTMASK_MASK (0x00FFFFFF)
284
285/********************************************************************/
286#endif /* _AU1200LCD_H */
287/*
288 * BRIEF MODULE DESCRIPTION
289 * Hardware definitions for the Au1200 LCD controller
290 *
291 * Copyright 2004 AMD
292 * Author: AMD
293 *
294 * This program is free software; you can redistribute it and/or modify it
295 * under the terms of the GNU General Public License as published by the
296 * Free Software Foundation; either version 2 of the License, or (at your
297 * option) any later version.
298 *
299 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
300 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
301 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
302 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
303 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
304 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
305 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
306 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
307 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
308 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
309 *
310 * You should have received a copy of the GNU General Public License along
311 * with this program; if not, write to the Free Software Foundation, Inc.,
312 * 675 Mass Ave, Cambridge, MA 02139, USA.
313 */
314
315#ifndef _AU1200LCD_H
316#define _AU1200LCD_H
317
318/********************************************************************/
319#define AU1200_LCD_ADDR 0xB5000000
320
321#define uint8 unsigned char
322#define uint32 unsigned int
323
324struct au1200_lcd {
325 volatile uint32 reserved0;
326 volatile uint32 screen;
327 volatile uint32 backcolor;
328 volatile uint32 horztiming;
329 volatile uint32 verttiming;
330 volatile uint32 clkcontrol;
331 volatile uint32 pwmdiv;
332 volatile uint32 pwmhi;
333 volatile uint32 reserved1;
334 volatile uint32 winenable;
335 volatile uint32 colorkey;
336 volatile uint32 colorkeymsk;
337 struct
338 {
339 volatile uint32 cursorctrl;
340 volatile uint32 cursorpos;
341 volatile uint32 cursorcolor0;
342 volatile uint32 cursorcolor1;
343 volatile uint32 cursorcolor2;
344 uint32 cursorcolor3;
345 } hwc;
346 volatile uint32 intstatus;
347 volatile uint32 intenable;
348 volatile uint32 outmask;
349 volatile uint32 fifoctrl;
350 uint32 reserved2[(0x0100-0x0058)/4];
351 struct
352 {
353 volatile uint32 winctrl0;
354 volatile uint32 winctrl1;
355 volatile uint32 winctrl2;
356 volatile uint32 winbuf0;
357 volatile uint32 winbuf1;
358 volatile uint32 winbufctrl;
359 uint32 winreserved0;
360 uint32 winreserved1;
361 } window[4];
362
363 uint32 reserved3[(0x0400-0x0180)/4];
364
365 volatile uint32 palette[(0x0800-0x0400)/4];
366
367 volatile uint8 cursorpattern[256];
368};
369
370/* lcd_screen */
371#define LCD_SCREEN_SEN (1<<31)
372#define LCD_SCREEN_SX (0x07FF<<19)
373#define LCD_SCREEN_SY (0x07FF<< 8)
374#define LCD_SCREEN_SWP (1<<7)
375#define LCD_SCREEN_SWD (1<<6)
376#define LCD_SCREEN_PT (7<<0)
377#define LCD_SCREEN_PT_TFT (0<<0)
378#define LCD_SCREEN_SX_N(WIDTH) ((WIDTH-1)<<19)
379#define LCD_SCREEN_SY_N(HEIGHT) ((HEIGHT-1)<<8)
380#define LCD_SCREEN_PT_CSTN (1<<0)
381#define LCD_SCREEN_PT_CDSTN (2<<0)
382#define LCD_SCREEN_PT_M8STN (3<<0)
383#define LCD_SCREEN_PT_M4STN (4<<0)
384
385/* lcd_backcolor */
386#define LCD_BACKCOLOR_SBGR (0xFF<<16)
387#define LCD_BACKCOLOR_SBGG (0xFF<<8)
388#define LCD_BACKCOLOR_SBGB (0xFF<<0)
389#define LCD_BACKCOLOR_SBGR_N(N) ((N)<<16)
390#define LCD_BACKCOLOR_SBGG_N(N) ((N)<<8)
391#define LCD_BACKCOLOR_SBGB_N(N) ((N)<<0)
392
393/* lcd_winenable */
394#define LCD_WINENABLE_WEN3 (1<<3)
395#define LCD_WINENABLE_WEN2 (1<<2)
396#define LCD_WINENABLE_WEN1 (1<<1)
397#define LCD_WINENABLE_WEN0 (1<<0)
398
399/* lcd_colorkey */
400#define LCD_COLORKEY_CKR (0xFF<<16)
401#define LCD_COLORKEY_CKG (0xFF<<8)
402#define LCD_COLORKEY_CKB (0xFF<<0)
403#define LCD_COLORKEY_CKR_N(N) ((N)<<16)
404#define LCD_COLORKEY_CKG_N(N) ((N)<<8)
405#define LCD_COLORKEY_CKB_N(N) ((N)<<0)
406
407/* lcd_colorkeymsk */
408#define LCD_COLORKEYMSK_CKMR (0xFF<<16)
409#define LCD_COLORKEYMSK_CKMG (0xFF<<8)
410#define LCD_COLORKEYMSK_CKMB (0xFF<<0)
411#define LCD_COLORKEYMSK_CKMR_N(N) ((N)<<16)
412#define LCD_COLORKEYMSK_CKMG_N(N) ((N)<<8)
413#define LCD_COLORKEYMSK_CKMB_N(N) ((N)<<0)
414
415/* lcd windows control 0 */
416#define LCD_WINCTRL0_OX (0x07FF<<21)
417#define LCD_WINCTRL0_OY (0x07FF<<10)
418#define LCD_WINCTRL0_A (0x00FF<<2)
419#define LCD_WINCTRL0_AEN (1<<1)
420#define LCD_WINCTRL0_OX_N(N) ((N)<<21)
421#define LCD_WINCTRL0_OY_N(N) ((N)<<10)
422#define LCD_WINCTRL0_A_N(N) ((N)<<2)
423
424/* lcd windows control 1 */
425#define LCD_WINCTRL1_PRI (3<<30)
426#define LCD_WINCTRL1_PIPE (1<<29)
427#define LCD_WINCTRL1_FRM (0xF<<25)
428#define LCD_WINCTRL1_CCO (1<<24)
429#define LCD_WINCTRL1_PO (3<<22)
430#define LCD_WINCTRL1_SZX (0x07FF<<11)
431#define LCD_WINCTRL1_SZY (0x07FF<<0)
432#define LCD_WINCTRL1_FRM_1BPP (0<<25)
433#define LCD_WINCTRL1_FRM_2BPP (1<<25)
434#define LCD_WINCTRL1_FRM_4BPP (2<<25)
435#define LCD_WINCTRL1_FRM_8BPP (3<<25)
436#define LCD_WINCTRL1_FRM_12BPP (4<<25)
437#define LCD_WINCTRL1_FRM_16BPP655 (5<<25)
438#define LCD_WINCTRL1_FRM_16BPP565 (6<<25)
439#define LCD_WINCTRL1_FRM_16BPP556 (7<<25)
440#define LCD_WINCTRL1_FRM_16BPPI1555 (8<<25)
441#define LCD_WINCTRL1_FRM_16BPPI5551 (9<<25)
442#define LCD_WINCTRL1_FRM_16BPPA1555 (10<<25)
443#define LCD_WINCTRL1_FRM_16BPPA5551 (11<<25)
444#define LCD_WINCTRL1_FRM_24BPP (12<<25)
445#define LCD_WINCTRL1_FRM_32BPP (13<<25)
446#define LCD_WINCTRL1_PRI_N(N) ((N)<<30)
447#define LCD_WINCTRL1_PO_00 (0<<22)
448#define LCD_WINCTRL1_PO_01 (1<<22)
449#define LCD_WINCTRL1_PO_10 (2<<22)
450#define LCD_WINCTRL1_PO_11 (3<<22)
451#define LCD_WINCTRL1_SZX_N(N) ((N-1)<<11)
452#define LCD_WINCTRL1_SZY_N(N) ((N-1)<<0)
453
454/* lcd windows control 2 */
455#define LCD_WINCTRL2_CKMODE (3<<24)
456#define LCD_WINCTRL2_DBM (1<<23)
457#define LCD_WINCTRL2_RAM (3<<21)
458#define LCD_WINCTRL2_BX (0x1FFF<<8)
459#define LCD_WINCTRL2_SCX (0xF<<4)
460#define LCD_WINCTRL2_SCY (0xF<<0)
461#define LCD_WINCTRL2_CKMODE_00 (0<<24)
462#define LCD_WINCTRL2_CKMODE_01 (1<<24)
463#define LCD_WINCTRL2_CKMODE_10 (2<<24)
464#define LCD_WINCTRL2_CKMODE_11 (3<<24)
465#define LCD_WINCTRL2_RAM_NONE (0<<21)
466#define LCD_WINCTRL2_RAM_PALETTE (1<<21)
467#define LCD_WINCTRL2_RAM_GAMMA (2<<21)
468#define LCD_WINCTRL2_RAM_BUFFER (3<<21)
469#define LCD_WINCTRL2_BX_N(N) ((N)<<8)
470#define LCD_WINCTRL2_SCX_1 (0<<4)
471#define LCD_WINCTRL2_SCX_2 (1<<4)
472#define LCD_WINCTRL2_SCX_4 (2<<4)
473#define LCD_WINCTRL2_SCY_1 (0<<0)
474#define LCD_WINCTRL2_SCY_2 (1<<0)
475#define LCD_WINCTRL2_SCY_4 (2<<0)
476
477/* lcd windows buffer control */
478#define LCD_WINBUFCTRL_DB (1<<1)
479#define LCD_WINBUFCTRL_DBN (1<<0)
480
481/* lcd_intstatus, lcd_intenable */
482#define LCD_INT_IFO (0xF<<14)
483#define LCD_INT_IFU (0xF<<10)
484#define LCD_INT_OFO (1<<9)
485#define LCD_INT_OFU (1<<8)
486#define LCD_INT_WAIT (1<<3)
487#define LCD_INT_SD (1<<2)
488#define LCD_INT_SA (1<<1)
489#define LCD_INT_SS (1<<0)
490
491/* lcd_horztiming */
492#define LCD_HORZTIMING_HND2 (0x1FF<<18)
493#define LCD_HORZTIMING_HND1 (0x1FF<<9)
494#define LCD_HORZTIMING_HPW (0x1FF<<0)
495#define LCD_HORZTIMING_HND2_N(N)(((N)-1)<<18)
496#define LCD_HORZTIMING_HND1_N(N)(((N)-1)<<9)
497#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<0)
498
499/* lcd_verttiming */
500#define LCD_VERTTIMING_VND2 (0x1FF<<18)
501#define LCD_VERTTIMING_VND1 (0x1FF<<9)
502#define LCD_VERTTIMING_VPW (0x1FF<<0)
503#define LCD_VERTTIMING_VND2_N(N)(((N)-1)<<18)
504#define LCD_VERTTIMING_VND1_N(N)(((N)-1)<<9)
505#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<0)
506
507/* lcd_clkcontrol */
508#define LCD_CLKCONTROL_EXT (1<<22)
509#define LCD_CLKCONTROL_DELAY (3<<20)
510#define LCD_CLKCONTROL_CDD (1<<19)
511#define LCD_CLKCONTROL_IB (1<<18)
512#define LCD_CLKCONTROL_IC (1<<17)
513#define LCD_CLKCONTROL_IH (1<<16)
514#define LCD_CLKCONTROL_IV (1<<15)
515#define LCD_CLKCONTROL_BF (0x1F<<10)
516#define LCD_CLKCONTROL_PCD (0x3FF<<0)
517#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10)
518#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0)
519
520/* lcd_pwmdiv */
521#define LCD_PWMDIV_EN (1<<31)
522#define LCD_PWMDIV_PWMDIV (0x1FFFF<<0)
523#define LCD_PWMDIV_PWMDIV_N(N) ((N)<<0)
524
525/* lcd_pwmhi */
526#define LCD_PWMHI_PWMHI1 (0xFFFF<<16)
527#define LCD_PWMHI_PWMHI0 (0xFFFF<<0)
528#define LCD_PWMHI_PWMHI1_N(N) ((N)<<16)
529#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0)
530
531/* lcd_hwccon */
532#define LCD_HWCCON_EN (1<<0)
533
534/* lcd_cursorpos */
535#define LCD_CURSORPOS_HWCXOFF (0x1F<<27)
536#define LCD_CURSORPOS_HWCXPOS (0x07FF<<16)
537#define LCD_CURSORPOS_HWCYOFF (0x1F<<11)
538#define LCD_CURSORPOS_HWCYPOS (0x07FF<<0)
539#define LCD_CURSORPOS_HWCXOFF_N(N) ((N)<<27)
540#define LCD_CURSORPOS_HWCXPOS_N(N) ((N)<<16)
541#define LCD_CURSORPOS_HWCYOFF_N(N) ((N)<<11)
542#define LCD_CURSORPOS_HWCYPOS_N(N) ((N)<<0)
543
544/* lcd_cursorcolor */
545#define LCD_CURSORCOLOR_HWCA (0xFF<<24)
546#define LCD_CURSORCOLOR_HWCR (0xFF<<16)
547#define LCD_CURSORCOLOR_HWCG (0xFF<<8)
548#define LCD_CURSORCOLOR_HWCB (0xFF<<0)
549#define LCD_CURSORCOLOR_HWCA_N(N) ((N)<<24)
550#define LCD_CURSORCOLOR_HWCR_N(N) ((N)<<16)
551#define LCD_CURSORCOLOR_HWCG_N(N) ((N)<<8)
552#define LCD_CURSORCOLOR_HWCB_N(N) ((N)<<0)
553
554/* lcd_fifoctrl */
555#define LCD_FIFOCTRL_F3IF (1<<29)
556#define LCD_FIFOCTRL_F3REQ (0x1F<<24)
557#define LCD_FIFOCTRL_F2IF (1<<29)
558#define LCD_FIFOCTRL_F2REQ (0x1F<<16)
559#define LCD_FIFOCTRL_F1IF (1<<29)
560#define LCD_FIFOCTRL_F1REQ (0x1F<<8)
561#define LCD_FIFOCTRL_F0IF (1<<29)
562#define LCD_FIFOCTRL_F0REQ (0x1F<<0)
563#define LCD_FIFOCTRL_F3REQ_N(N) ((N-1)<<24)
564#define LCD_FIFOCTRL_F2REQ_N(N) ((N-1)<<16)
565#define LCD_FIFOCTRL_F1REQ_N(N) ((N-1)<<8)
566#define LCD_FIFOCTRL_F0REQ_N(N) ((N-1)<<0)
567
568/* lcd_outmask */
569#define LCD_OUTMASK_MASK (0x00FFFFFF)
570
571/********************************************************************/
572#endif /* _AU1200LCD_H */
diff --git a/drivers/video/chipsfb.c b/drivers/video/chipsfb.c
index bc061d4ec786..72ff6bf75e5e 100644
--- a/drivers/video/chipsfb.c
+++ b/drivers/video/chipsfb.c
@@ -178,8 +178,6 @@ struct chips_init_reg {
178 unsigned char data; 178 unsigned char data;
179}; 179};
180 180
181#define N_ELTS(x) (sizeof(x) / sizeof(x[0]))
182
183static struct chips_init_reg chips_init_sr[] = { 181static struct chips_init_reg chips_init_sr[] = {
184 { 0x00, 0x03 }, 182 { 0x00, 0x03 },
185 { 0x01, 0x01 }, 183 { 0x01, 0x01 },
@@ -287,18 +285,18 @@ static void __init chips_hw_init(void)
287{ 285{
288 int i; 286 int i;
289 287
290 for (i = 0; i < N_ELTS(chips_init_xr); ++i) 288 for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
291 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data); 289 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
292 outb(0x29, 0x3c2); /* set misc output reg */ 290 outb(0x29, 0x3c2); /* set misc output reg */
293 for (i = 0; i < N_ELTS(chips_init_sr); ++i) 291 for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
294 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data); 292 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
295 for (i = 0; i < N_ELTS(chips_init_gr); ++i) 293 for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
296 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data); 294 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
297 for (i = 0; i < N_ELTS(chips_init_ar); ++i) 295 for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
298 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data); 296 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
299 for (i = 0; i < N_ELTS(chips_init_cr); ++i) 297 for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
300 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data); 298 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
301 for (i = 0; i < N_ELTS(chips_init_fr); ++i) 299 for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
302 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data); 300 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
303} 301}
304 302
diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index 6ee449858a5c..4444bef68fba 100644
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -26,6 +26,30 @@ config VGA_CONSOLE
26# fi 26# fi
27# fi 27# fi
28 28
29config VGACON_SOFT_SCROLLBACK
30 bool "Enable Scrollback Buffer in System RAM"
31 depends on VGA_CONSOLE
32 default n
33 help
34 The scrollback buffer of the standard VGA console is located in
35 the VGA RAM. The size of this RAM is fixed and is quite small.
36 If you require a larger scrollback buffer, this can be placed in
37 System RAM which is dynamically allocated during intialization.
38 Placing the scrollback buffer in System RAM will slightly slow
39 down the console.
40
41 If you want this feature, say 'Y' here and enter the amount of
42 RAM to allocate for this buffer. If unsure, say 'N'.
43
44config VGACON_SOFT_SCROLLBACK_SIZE
45 int "Scrollback Buffer Size (in KB)"
46 depends on VGACON_SOFT_SCROLLBACK
47 default "64"
48 help
49 Enter the amount of System RAM to allocate for the scrollback
50 buffer. Each 64KB will give you approximately 16 80x25
51 screenfuls of scrollback buffer
52
29config VIDEO_SELECT 53config VIDEO_SELECT
30 bool "Video mode selection support" 54 bool "Video mode selection support"
31 depends on X86 && VGA_CONSOLE 55 depends on X86 && VGA_CONSOLE
diff --git a/drivers/video/console/fonts.c b/drivers/video/console/fonts.c
index 4fd07d9eca03..0cc1bfda76a6 100644
--- a/drivers/video/console/fonts.c
+++ b/drivers/video/console/fonts.c
@@ -66,7 +66,7 @@ static const struct font_desc *fonts[] = {
66#endif 66#endif
67}; 67};
68 68
69#define num_fonts (sizeof(fonts)/sizeof(*fonts)) 69#define num_fonts ARRAY_SIZE(fonts)
70 70
71#ifdef NO_FONTS 71#ifdef NO_FONTS
72#error No fonts configured. 72#error No fonts configured.
diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c
index 762c7a593141..e99fe30e568c 100644
--- a/drivers/video/console/newport_con.c
+++ b/drivers/video/console/newport_con.c
@@ -149,7 +149,7 @@ static inline void newport_clear_lines(int ystart, int yend, int ci)
149 newport_clear_screen(0, ystart, 1280 + 63, yend, ci); 149 newport_clear_screen(0, ystart, 1280 + 63, yend, ci);
150} 150}
151 151
152void newport_reset(void) 152static void newport_reset(void)
153{ 153{
154 unsigned short treg; 154 unsigned short treg;
155 int i; 155 int i;
@@ -193,7 +193,7 @@ void newport_reset(void)
193 * calculate the actual screen size by reading 193 * calculate the actual screen size by reading
194 * the video timing out of the VC2 194 * the video timing out of the VC2
195 */ 195 */
196void newport_get_screensize(void) 196static void newport_get_screensize(void)
197{ 197{
198 int i, cols; 198 int i, cols;
199 unsigned short ventry, treg; 199 unsigned short ventry, treg;
diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c
index 5a86978537d2..d5a04b68c4d4 100644
--- a/drivers/video/console/vgacon.c
+++ b/drivers/video/console/vgacon.c
@@ -93,7 +93,6 @@ static u8 vgacon_build_attr(struct vc_data *c, u8 color, u8 intensity,
93static void vgacon_invert_region(struct vc_data *c, u16 * p, int count); 93static void vgacon_invert_region(struct vc_data *c, u16 * p, int count);
94static unsigned long vgacon_uni_pagedir[2]; 94static unsigned long vgacon_uni_pagedir[2];
95 95
96
97/* Description of the hardware situation */ 96/* Description of the hardware situation */
98static unsigned long vga_vram_base; /* Base of video memory */ 97static unsigned long vga_vram_base; /* Base of video memory */
99static unsigned long vga_vram_end; /* End of video memory */ 98static unsigned long vga_vram_end; /* End of video memory */
@@ -161,6 +160,201 @@ static inline void write_vga(unsigned char reg, unsigned int val)
161 spin_unlock_irqrestore(&vga_lock, flags); 160 spin_unlock_irqrestore(&vga_lock, flags);
162} 161}
163 162
163static inline void vga_set_mem_top(struct vc_data *c)
164{
165 write_vga(12, (c->vc_visible_origin - vga_vram_base) / 2);
166}
167
168#ifdef CONFIG_VGACON_SOFT_SCROLLBACK
169#include <linux/bootmem.h>
170/* software scrollback */
171static void *vgacon_scrollback;
172static int vgacon_scrollback_tail;
173static int vgacon_scrollback_size;
174static int vgacon_scrollback_rows;
175static int vgacon_scrollback_cnt;
176static int vgacon_scrollback_cur;
177static int vgacon_scrollback_save;
178static int vgacon_scrollback_restore;
179
180static void vgacon_scrollback_init(int pitch)
181{
182 int rows = CONFIG_VGACON_SOFT_SCROLLBACK_SIZE * 1024/pitch;
183
184 if (vgacon_scrollback) {
185 vgacon_scrollback_cnt = 0;
186 vgacon_scrollback_tail = 0;
187 vgacon_scrollback_cur = 0;
188 vgacon_scrollback_rows = rows - 1;
189 vgacon_scrollback_size = rows * pitch;
190 }
191}
192
193static void __init vgacon_scrollback_startup(void)
194{
195 vgacon_scrollback = alloc_bootmem(CONFIG_VGACON_SOFT_SCROLLBACK_SIZE
196 * 1024);
197 vgacon_scrollback_init(vga_video_num_columns * 2);
198}
199
200static void vgacon_scrollback_update(struct vc_data *c, int t, int count)
201{
202 void *p;
203
204 if (!vgacon_scrollback_size || c->vc_num != fg_console)
205 return;
206
207 p = (void *) (c->vc_origin + t * c->vc_size_row);
208
209 while (count--) {
210 scr_memcpyw(vgacon_scrollback + vgacon_scrollback_tail,
211 p, c->vc_size_row);
212 vgacon_scrollback_cnt++;
213 p += c->vc_size_row;
214 vgacon_scrollback_tail += c->vc_size_row;
215
216 if (vgacon_scrollback_tail >= vgacon_scrollback_size)
217 vgacon_scrollback_tail = 0;
218
219 if (vgacon_scrollback_cnt > vgacon_scrollback_rows)
220 vgacon_scrollback_cnt = vgacon_scrollback_rows;
221
222 vgacon_scrollback_cur = vgacon_scrollback_cnt;
223 }
224}
225
226static void vgacon_restore_screen(struct vc_data *c)
227{
228 vgacon_scrollback_save = 0;
229
230 if (!vga_is_gfx && !vgacon_scrollback_restore) {
231 scr_memcpyw((u16 *) c->vc_origin, (u16 *) c->vc_screenbuf,
232 c->vc_screenbuf_size > vga_vram_size ?
233 vga_vram_size : c->vc_screenbuf_size);
234 vgacon_scrollback_restore = 1;
235 vgacon_scrollback_cur = vgacon_scrollback_cnt;
236 }
237}
238
239static int vgacon_scrolldelta(struct vc_data *c, int lines)
240{
241 int start, end, count, soff, diff;
242 void *d, *s;
243
244 if (!lines) {
245 c->vc_visible_origin = c->vc_origin;
246 vga_set_mem_top(c);
247 return 1;
248 }
249
250 if (!vgacon_scrollback)
251 return 1;
252
253 if (!vgacon_scrollback_save) {
254 vgacon_cursor(c, CM_ERASE);
255 vgacon_save_screen(c);
256 vgacon_scrollback_save = 1;
257 }
258
259 vgacon_scrollback_restore = 0;
260 start = vgacon_scrollback_cur + lines;
261 end = start + abs(lines);
262
263 if (start < 0)
264 start = 0;
265
266 if (start > vgacon_scrollback_cnt)
267 start = vgacon_scrollback_cnt;
268
269 if (end < 0)
270 end = 0;
271
272 if (end > vgacon_scrollback_cnt)
273 end = vgacon_scrollback_cnt;
274
275 vgacon_scrollback_cur = start;
276 count = end - start;
277 soff = vgacon_scrollback_tail - ((vgacon_scrollback_cnt - end) *
278 c->vc_size_row);
279 soff -= count * c->vc_size_row;
280
281 if (soff < 0)
282 soff += vgacon_scrollback_size;
283
284 count = vgacon_scrollback_cnt - start;
285
286 if (count > c->vc_rows)
287 count = c->vc_rows;
288
289 diff = c->vc_rows - count;
290
291 d = (void *) c->vc_origin;
292 s = (void *) c->vc_screenbuf;
293
294 while (count--) {
295 scr_memcpyw(d, vgacon_scrollback + soff, c->vc_size_row);
296 d += c->vc_size_row;
297 soff += c->vc_size_row;
298
299 if (soff >= vgacon_scrollback_size)
300 soff = 0;
301 }
302
303 if (diff == c->vc_rows) {
304 vgacon_cursor(c, CM_MOVE);
305 } else {
306 while (diff--) {
307 scr_memcpyw(d, s, c->vc_size_row);
308 d += c->vc_size_row;
309 s += c->vc_size_row;
310 }
311 }
312
313 return 1;
314}
315#else
316#define vgacon_scrollback_startup(...) do { } while (0)
317#define vgacon_scrollback_init(...) do { } while (0)
318#define vgacon_scrollback_update(...) do { } while (0)
319
320static void vgacon_restore_screen(struct vc_data *c)
321{
322 if (c->vc_origin != c->vc_visible_origin)
323 vgacon_scrolldelta(c, 0);
324}
325
326static int vgacon_scrolldelta(struct vc_data *c, int lines)
327{
328 if (!lines) /* Turn scrollback off */
329 c->vc_visible_origin = c->vc_origin;
330 else {
331 int margin = c->vc_size_row * 4;
332 int ul, we, p, st;
333
334 if (vga_rolled_over >
335 (c->vc_scr_end - vga_vram_base) + margin) {
336 ul = c->vc_scr_end - vga_vram_base;
337 we = vga_rolled_over + c->vc_size_row;
338 } else {
339 ul = 0;
340 we = vga_vram_size;
341 }
342 p = (c->vc_visible_origin - vga_vram_base - ul + we) % we +
343 lines * c->vc_size_row;
344 st = (c->vc_origin - vga_vram_base - ul + we) % we;
345 if (st < 2 * margin)
346 margin = 0;
347 if (p < margin)
348 p = 0;
349 if (p > st - margin)
350 p = st;
351 c->vc_visible_origin = vga_vram_base + (p + ul) % we;
352 }
353 vga_set_mem_top(c);
354 return 1;
355}
356#endif /* CONFIG_VGACON_SOFT_SCROLLBACK */
357
164static const char __init *vgacon_startup(void) 358static const char __init *vgacon_startup(void)
165{ 359{
166 const char *display_desc = NULL; 360 const char *display_desc = NULL;
@@ -330,7 +524,7 @@ static const char __init *vgacon_startup(void)
330 524
331 vgacon_xres = ORIG_VIDEO_COLS * VGA_FONTWIDTH; 525 vgacon_xres = ORIG_VIDEO_COLS * VGA_FONTWIDTH;
332 vgacon_yres = vga_scan_lines; 526 vgacon_yres = vga_scan_lines;
333 527 vgacon_scrollback_startup();
334 return display_desc; 528 return display_desc;
335} 529}
336 530
@@ -357,11 +551,6 @@ static void vgacon_init(struct vc_data *c, int init)
357 con_set_default_unimap(c); 551 con_set_default_unimap(c);
358} 552}
359 553
360static inline void vga_set_mem_top(struct vc_data *c)
361{
362 write_vga(12, (c->vc_visible_origin - vga_vram_base) / 2);
363}
364
365static void vgacon_deinit(struct vc_data *c) 554static void vgacon_deinit(struct vc_data *c)
366{ 555{
367 /* When closing the last console, reset video origin */ 556 /* When closing the last console, reset video origin */
@@ -433,29 +622,37 @@ static void vgacon_set_cursor_size(int xpos, int from, int to)
433 cursor_size_lastto = to; 622 cursor_size_lastto = to;
434 623
435 spin_lock_irqsave(&vga_lock, flags); 624 spin_lock_irqsave(&vga_lock, flags);
436 outb_p(0x0a, vga_video_port_reg); /* Cursor start */ 625 if (vga_video_type >= VIDEO_TYPE_VGAC) {
437 curs = inb_p(vga_video_port_val); 626 outb_p(VGA_CRTC_CURSOR_START, vga_video_port_reg);
438 outb_p(0x0b, vga_video_port_reg); /* Cursor end */ 627 curs = inb_p(vga_video_port_val);
439 cure = inb_p(vga_video_port_val); 628 outb_p(VGA_CRTC_CURSOR_END, vga_video_port_reg);
629 cure = inb_p(vga_video_port_val);
630 } else {
631 curs = 0;
632 cure = 0;
633 }
440 634
441 curs = (curs & 0xc0) | from; 635 curs = (curs & 0xc0) | from;
442 cure = (cure & 0xe0) | to; 636 cure = (cure & 0xe0) | to;
443 637
444 outb_p(0x0a, vga_video_port_reg); /* Cursor start */ 638 outb_p(VGA_CRTC_CURSOR_START, vga_video_port_reg);
445 outb_p(curs, vga_video_port_val); 639 outb_p(curs, vga_video_port_val);
446 outb_p(0x0b, vga_video_port_reg); /* Cursor end */ 640 outb_p(VGA_CRTC_CURSOR_END, vga_video_port_reg);
447 outb_p(cure, vga_video_port_val); 641 outb_p(cure, vga_video_port_val);
448 spin_unlock_irqrestore(&vga_lock, flags); 642 spin_unlock_irqrestore(&vga_lock, flags);
449} 643}
450 644
451static void vgacon_cursor(struct vc_data *c, int mode) 645static void vgacon_cursor(struct vc_data *c, int mode)
452{ 646{
453 if (c->vc_origin != c->vc_visible_origin) 647 vgacon_restore_screen(c);
454 vgacon_scrolldelta(c, 0); 648
455 switch (mode) { 649 switch (mode) {
456 case CM_ERASE: 650 case CM_ERASE:
457 write_vga(14, (c->vc_pos - vga_vram_base) / 2); 651 write_vga(14, (c->vc_pos - vga_vram_base) / 2);
458 vgacon_set_cursor_size(c->vc_x, 31, 30); 652 if (vga_video_type >= VIDEO_TYPE_VGAC)
653 vgacon_set_cursor_size(c->vc_x, 31, 30);
654 else
655 vgacon_set_cursor_size(c->vc_x, 31, 31);
459 break; 656 break;
460 657
461 case CM_MOVE: 658 case CM_MOVE:
@@ -493,7 +690,10 @@ static void vgacon_cursor(struct vc_data *c, int mode)
493 10 ? 1 : 2)); 690 10 ? 1 : 2));
494 break; 691 break;
495 case CUR_NONE: 692 case CUR_NONE:
496 vgacon_set_cursor_size(c->vc_x, 31, 30); 693 if (vga_video_type >= VIDEO_TYPE_VGAC)
694 vgacon_set_cursor_size(c->vc_x, 31, 30);
695 else
696 vgacon_set_cursor_size(c->vc_x, 31, 31);
497 break; 697 break;
498 default: 698 default:
499 vgacon_set_cursor_size(c->vc_x, 1, 699 vgacon_set_cursor_size(c->vc_x, 1,
@@ -595,6 +795,7 @@ static int vgacon_switch(struct vc_data *c)
595 vgacon_doresize(c, c->vc_cols, c->vc_rows); 795 vgacon_doresize(c, c->vc_cols, c->vc_rows);
596 } 796 }
597 797
798 vgacon_scrollback_init(c->vc_size_row);
598 return 0; /* Redrawing not needed */ 799 return 0; /* Redrawing not needed */
599} 800}
600 801
@@ -1062,37 +1263,6 @@ static int vgacon_resize(struct vc_data *c, unsigned int width,
1062 return 0; 1263 return 0;
1063} 1264}
1064 1265
1065static int vgacon_scrolldelta(struct vc_data *c, int lines)
1066{
1067 if (!lines) /* Turn scrollback off */
1068 c->vc_visible_origin = c->vc_origin;
1069 else {
1070 int margin = c->vc_size_row * 4;
1071 int ul, we, p, st;
1072
1073 if (vga_rolled_over >
1074 (c->vc_scr_end - vga_vram_base) + margin) {
1075 ul = c->vc_scr_end - vga_vram_base;
1076 we = vga_rolled_over + c->vc_size_row;
1077 } else {
1078 ul = 0;
1079 we = vga_vram_size;
1080 }
1081 p = (c->vc_visible_origin - vga_vram_base - ul + we) % we +
1082 lines * c->vc_size_row;
1083 st = (c->vc_origin - vga_vram_base - ul + we) % we;
1084 if (st < 2 * margin)
1085 margin = 0;
1086 if (p < margin)
1087 p = 0;
1088 if (p > st - margin)
1089 p = st;
1090 c->vc_visible_origin = vga_vram_base + (p + ul) % we;
1091 }
1092 vga_set_mem_top(c);
1093 return 1;
1094}
1095
1096static int vgacon_set_origin(struct vc_data *c) 1266static int vgacon_set_origin(struct vc_data *c)
1097{ 1267{
1098 if (vga_is_gfx || /* We don't play origin tricks in graphic modes */ 1268 if (vga_is_gfx || /* We don't play origin tricks in graphic modes */
@@ -1135,15 +1305,14 @@ static int vgacon_scroll(struct vc_data *c, int t, int b, int dir,
1135 if (t || b != c->vc_rows || vga_is_gfx) 1305 if (t || b != c->vc_rows || vga_is_gfx)
1136 return 0; 1306 return 0;
1137 1307
1138 if (c->vc_origin != c->vc_visible_origin)
1139 vgacon_scrolldelta(c, 0);
1140
1141 if (!vga_hardscroll_enabled || lines >= c->vc_rows / 2) 1308 if (!vga_hardscroll_enabled || lines >= c->vc_rows / 2)
1142 return 0; 1309 return 0;
1143 1310
1311 vgacon_restore_screen(c);
1144 oldo = c->vc_origin; 1312 oldo = c->vc_origin;
1145 delta = lines * c->vc_size_row; 1313 delta = lines * c->vc_size_row;
1146 if (dir == SM_UP) { 1314 if (dir == SM_UP) {
1315 vgacon_scrollback_update(c, t, lines);
1147 if (c->vc_scr_end + delta >= vga_vram_end) { 1316 if (c->vc_scr_end + delta >= vga_vram_end) {
1148 scr_memcpyw((u16 *) vga_vram_base, 1317 scr_memcpyw((u16 *) vga_vram_base,
1149 (u16 *) (oldo + delta), 1318 (u16 *) (oldo + delta),
diff --git a/drivers/video/fbcmap.c b/drivers/video/fbcmap.c
index c32a2a50bfa2..1f98392a43b3 100644
--- a/drivers/video/fbcmap.c
+++ b/drivers/video/fbcmap.c
@@ -85,7 +85,7 @@ static struct fb_cmap default_16_colors = {
85 * Allocates memory for a colormap @cmap. @len is the 85 * Allocates memory for a colormap @cmap. @len is the
86 * number of entries in the palette. 86 * number of entries in the palette.
87 * 87 *
88 * Returns -1 errno on error, or zero on success. 88 * Returns negative errno on error, or zero on success.
89 * 89 *
90 */ 90 */
91 91
@@ -116,7 +116,7 @@ int fb_alloc_cmap(struct fb_cmap *cmap, int len, int transp)
116 116
117fail: 117fail:
118 fb_dealloc_cmap(cmap); 118 fb_dealloc_cmap(cmap);
119 return -1; 119 return -ENOMEM;
120} 120}
121 121
122/** 122/**
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c
index 07d882b14396..b1a8dca76430 100644
--- a/drivers/video/fbmem.c
+++ b/drivers/video/fbmem.c
@@ -55,7 +55,7 @@
55 55
56#define FBPIXMAPSIZE (1024 * 8) 56#define FBPIXMAPSIZE (1024 * 8)
57 57
58static struct notifier_block *fb_notifier_list; 58static BLOCKING_NOTIFIER_HEAD(fb_notifier_list);
59struct fb_info *registered_fb[FB_MAX]; 59struct fb_info *registered_fb[FB_MAX];
60int num_registered_fb; 60int num_registered_fb;
61 61
@@ -784,7 +784,7 @@ fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var)
784 784
785 event.info = info; 785 event.info = info;
786 event.data = &mode1; 786 event.data = &mode1;
787 ret = notifier_call_chain(&fb_notifier_list, 787 ret = blocking_notifier_call_chain(&fb_notifier_list,
788 FB_EVENT_MODE_DELETE, &event); 788 FB_EVENT_MODE_DELETE, &event);
789 } 789 }
790 790
@@ -830,8 +830,8 @@ fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var)
830 830
831 info->flags &= ~FBINFO_MISC_USEREVENT; 831 info->flags &= ~FBINFO_MISC_USEREVENT;
832 event.info = info; 832 event.info = info;
833 notifier_call_chain(&fb_notifier_list, evnt, 833 blocking_notifier_call_chain(&fb_notifier_list,
834 &event); 834 evnt, &event);
835 } 835 }
836 } 836 }
837 } 837 }
@@ -854,7 +854,8 @@ fb_blank(struct fb_info *info, int blank)
854 854
855 event.info = info; 855 event.info = info;
856 event.data = &blank; 856 event.data = &blank;
857 notifier_call_chain(&fb_notifier_list, FB_EVENT_BLANK, &event); 857 blocking_notifier_call_chain(&fb_notifier_list,
858 FB_EVENT_BLANK, &event);
858 } 859 }
859 860
860 return ret; 861 return ret;
@@ -925,7 +926,7 @@ fb_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
925 con2fb.framebuffer = -1; 926 con2fb.framebuffer = -1;
926 event.info = info; 927 event.info = info;
927 event.data = &con2fb; 928 event.data = &con2fb;
928 notifier_call_chain(&fb_notifier_list, 929 blocking_notifier_call_chain(&fb_notifier_list,
929 FB_EVENT_GET_CONSOLE_MAP, &event); 930 FB_EVENT_GET_CONSOLE_MAP, &event);
930 return copy_to_user(argp, &con2fb, 931 return copy_to_user(argp, &con2fb,
931 sizeof(con2fb)) ? -EFAULT : 0; 932 sizeof(con2fb)) ? -EFAULT : 0;
@@ -944,7 +945,7 @@ fb_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
944 return -EINVAL; 945 return -EINVAL;
945 event.info = info; 946 event.info = info;
946 event.data = &con2fb; 947 event.data = &con2fb;
947 return notifier_call_chain(&fb_notifier_list, 948 return blocking_notifier_call_chain(&fb_notifier_list,
948 FB_EVENT_SET_CONSOLE_MAP, 949 FB_EVENT_SET_CONSOLE_MAP,
949 &event); 950 &event);
950 case FBIOBLANK: 951 case FBIOBLANK:
@@ -1324,7 +1325,7 @@ register_framebuffer(struct fb_info *fb_info)
1324 devfs_mk_cdev(MKDEV(FB_MAJOR, i), 1325 devfs_mk_cdev(MKDEV(FB_MAJOR, i),
1325 S_IFCHR | S_IRUGO | S_IWUGO, "fb/%d", i); 1326 S_IFCHR | S_IRUGO | S_IWUGO, "fb/%d", i);
1326 event.info = fb_info; 1327 event.info = fb_info;
1327 notifier_call_chain(&fb_notifier_list, 1328 blocking_notifier_call_chain(&fb_notifier_list,
1328 FB_EVENT_FB_REGISTERED, &event); 1329 FB_EVENT_FB_REGISTERED, &event);
1329 return 0; 1330 return 0;
1330} 1331}
@@ -1366,7 +1367,7 @@ unregister_framebuffer(struct fb_info *fb_info)
1366 */ 1367 */
1367int fb_register_client(struct notifier_block *nb) 1368int fb_register_client(struct notifier_block *nb)
1368{ 1369{
1369 return notifier_chain_register(&fb_notifier_list, nb); 1370 return blocking_notifier_chain_register(&fb_notifier_list, nb);
1370} 1371}
1371 1372
1372/** 1373/**
@@ -1375,7 +1376,7 @@ int fb_register_client(struct notifier_block *nb)
1375 */ 1376 */
1376int fb_unregister_client(struct notifier_block *nb) 1377int fb_unregister_client(struct notifier_block *nb)
1377{ 1378{
1378 return notifier_chain_unregister(&fb_notifier_list, nb); 1379 return blocking_notifier_chain_unregister(&fb_notifier_list, nb);
1379} 1380}
1380 1381
1381/** 1382/**
@@ -1393,11 +1394,13 @@ void fb_set_suspend(struct fb_info *info, int state)
1393 1394
1394 event.info = info; 1395 event.info = info;
1395 if (state) { 1396 if (state) {
1396 notifier_call_chain(&fb_notifier_list, FB_EVENT_SUSPEND, &event); 1397 blocking_notifier_call_chain(&fb_notifier_list,
1398 FB_EVENT_SUSPEND, &event);
1397 info->state = FBINFO_STATE_SUSPENDED; 1399 info->state = FBINFO_STATE_SUSPENDED;
1398 } else { 1400 } else {
1399 info->state = FBINFO_STATE_RUNNING; 1401 info->state = FBINFO_STATE_RUNNING;
1400 notifier_call_chain(&fb_notifier_list, FB_EVENT_RESUME, &event); 1402 blocking_notifier_call_chain(&fb_notifier_list,
1403 FB_EVENT_RESUME, &event);
1401 } 1404 }
1402} 1405}
1403 1406
@@ -1469,7 +1472,7 @@ int fb_new_modelist(struct fb_info *info)
1469 1472
1470 if (!list_empty(&info->modelist)) { 1473 if (!list_empty(&info->modelist)) {
1471 event.info = info; 1474 event.info = info;
1472 err = notifier_call_chain(&fb_notifier_list, 1475 err = blocking_notifier_call_chain(&fb_notifier_list,
1473 FB_EVENT_NEW_MODELIST, 1476 FB_EVENT_NEW_MODELIST,
1474 &event); 1477 &event);
1475 } 1478 }
@@ -1495,7 +1498,7 @@ int fb_con_duit(struct fb_info *info, int event, void *data)
1495 evnt.info = info; 1498 evnt.info = info;
1496 evnt.data = data; 1499 evnt.data = data;
1497 1500
1498 return notifier_call_chain(&fb_notifier_list, event, &evnt); 1501 return blocking_notifier_call_chain(&fb_notifier_list, event, &evnt);
1499} 1502}
1500EXPORT_SYMBOL(fb_con_duit); 1503EXPORT_SYMBOL(fb_con_duit);
1501 1504
diff --git a/drivers/video/fbmon.c b/drivers/video/fbmon.c
index 7c74e7325d95..53beeb4a9998 100644
--- a/drivers/video/fbmon.c
+++ b/drivers/video/fbmon.c
@@ -1281,7 +1281,7 @@ int fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info)
1281 -EINVAL : 0; 1281 -EINVAL : 0;
1282} 1282}
1283 1283
1284#if defined(__i386__) 1284#if defined(CONFIG_FB_FIRMWARE_EDID) && defined(__i386__)
1285#include <linux/pci.h> 1285#include <linux/pci.h>
1286 1286
1287/* 1287/*
@@ -1311,11 +1311,11 @@ const unsigned char *fb_firmware_edid(struct device *device)
1311{ 1311{
1312 return NULL; 1312 return NULL;
1313} 1313}
1314#endif /* _i386_ */ 1314#endif
1315EXPORT_SYMBOL(fb_firmware_edid);
1315 1316
1316EXPORT_SYMBOL(fb_parse_edid); 1317EXPORT_SYMBOL(fb_parse_edid);
1317EXPORT_SYMBOL(fb_edid_to_monspecs); 1318EXPORT_SYMBOL(fb_edid_to_monspecs);
1318EXPORT_SYMBOL(fb_firmware_edid);
1319EXPORT_SYMBOL(fb_get_mode); 1319EXPORT_SYMBOL(fb_get_mode);
1320EXPORT_SYMBOL(fb_validate_mode); 1320EXPORT_SYMBOL(fb_validate_mode);
1321EXPORT_SYMBOL(fb_destroy_modedb); 1321EXPORT_SYMBOL(fb_destroy_modedb);
diff --git a/drivers/video/fbsysfs.c b/drivers/video/fbsysfs.c
index 6d26057337e2..b72b05250a9d 100644
--- a/drivers/video/fbsysfs.c
+++ b/drivers/video/fbsysfs.c
@@ -348,7 +348,7 @@ static ssize_t store_cmap(struct class_device *class_device, const char *buf,
348 fb_copy_cmap(&umap, &fb_info->cmap); 348 fb_copy_cmap(&umap, &fb_info->cmap);
349 fb_dealloc_cmap(&umap); 349 fb_dealloc_cmap(&umap);
350 350
351 return rc; 351 return rc ?: count;
352 } 352 }
353 for (i = 0; i < length; i++) { 353 for (i = 0; i < length; i++) {
354 u16 red, blue, green, tsp; 354 u16 red, blue, green, tsp;
@@ -367,7 +367,7 @@ static ssize_t store_cmap(struct class_device *class_device, const char *buf,
367 if (transp) 367 if (transp)
368 fb_info->cmap.transp[i] = tsp; 368 fb_info->cmap.transp[i] = tsp;
369 } 369 }
370 return 0; 370 return count;
371} 371}
372 372
373static ssize_t show_cmap(struct class_device *class_device, char *buf) 373static ssize_t show_cmap(struct class_device *class_device, char *buf)
diff --git a/drivers/video/geode/Kconfig b/drivers/video/geode/Kconfig
index 42fb9a89a792..4e173ef20a7d 100644
--- a/drivers/video/geode/Kconfig
+++ b/drivers/video/geode/Kconfig
@@ -8,9 +8,24 @@ config FB_GEODE
8 Say 'Y' here to allow you to select framebuffer drivers for 8 Say 'Y' here to allow you to select framebuffer drivers for
9 the AMD Geode family of processors. 9 the AMD Geode family of processors.
10 10
11config FB_GEODE_GX
12 tristate "AMD Geode GX framebuffer support (EXPERIMENTAL)"
13 depends on FB && FB_GEODE && EXPERIMENTAL
14 select FB_CFB_FILLRECT
15 select FB_CFB_COPYAREA
16 select FB_CFB_IMAGEBLIT
17 ---help---
18 Framebuffer driver for the display controller integrated into the
19 AMD Geode GX processors.
20
21 To compile this driver as a module, choose M here: the module will be
22 called gxfb.
23
24 If unsure, say N.
25
11config FB_GEODE_GX1 26config FB_GEODE_GX1
12 tristate "AMD Geode GX1 framebuffer support (EXPERIMENTAL)" 27 tristate "AMD Geode GX1 framebuffer support (EXPERIMENTAL)"
13 depends on FB_GEODE && EXPERIMENTAL 28 depends on FB && FB_GEODE && EXPERIMENTAL
14 select FB_CFB_FILLRECT 29 select FB_CFB_FILLRECT
15 select FB_CFB_COPYAREA 30 select FB_CFB_COPYAREA
16 select FB_CFB_IMAGEBLIT 31 select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/geode/Makefile b/drivers/video/geode/Makefile
index 13ad501ea990..f896565bc312 100644
--- a/drivers/video/geode/Makefile
+++ b/drivers/video/geode/Makefile
@@ -1,5 +1,7 @@
1# Makefile for the Geode family framebuffer drivers 1# Makefile for the Geode family framebuffer drivers
2 2
3obj-$(CONFIG_FB_GEODE_GX1) += gx1fb.o 3obj-$(CONFIG_FB_GEODE_GX1) += gx1fb.o
4obj-$(CONFIG_FB_GEODE_GX) += gxfb.o
4 5
5gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o 6gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o
7gxfb-objs := gxfb_core.o display_gx.o video_gx.o
diff --git a/drivers/video/geode/display_gx.c b/drivers/video/geode/display_gx.c
new file mode 100644
index 000000000000..825c3405f5c2
--- /dev/null
+++ b/drivers/video/geode/display_gx.c
@@ -0,0 +1,156 @@
1/*
2 * Geode GX display controller.
3 *
4 * Copyright (C) 2005 Arcom Control Systems Ltd.
5 *
6 * Portions from AMD's original 2.4 driver:
7 * Copyright (C) 2004 Advanced Micro Devices, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by * the
11 * Free Software Foundation; either version 2 of the License, or * (at your
12 * option) any later version.
13 */
14#include <linux/spinlock.h>
15#include <linux/fb.h>
16#include <linux/delay.h>
17#include <asm/io.h>
18#include <asm/div64.h>
19#include <asm/delay.h>
20
21#include "geodefb.h"
22#include "display_gx.h"
23
24int gx_frame_buffer_size(void)
25{
26 /* Assuming 16 MiB. */
27 return 16*1024*1024;
28}
29
30int gx_line_delta(int xres, int bpp)
31{
32 /* Must be a multiple of 8 bytes. */
33 return (xres * (bpp >> 3) + 7) & ~0x7;
34}
35
36static void gx_set_mode(struct fb_info *info)
37{
38 struct geodefb_par *par = info->par;
39 u32 gcfg, dcfg;
40 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
41 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
42
43 /* Unlock the display controller registers. */
44 readl(par->dc_regs + DC_UNLOCK);
45 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
46
47 gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
48 dcfg = readl(par->dc_regs + DC_DISPLAY_CFG);
49
50 /* Disable the timing generator. */
51 dcfg &= ~(DC_DCFG_TGEN);
52 writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
53
54 /* Wait for pending memory requests before disabling the FIFO load. */
55 udelay(100);
56
57 /* Disable FIFO load and compression. */
58 gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
59 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
60
61 /* Setup DCLK and its divisor. */
62 par->vid_ops->set_dclk(info);
63
64 /*
65 * Setup new mode.
66 */
67
68 /* Clear all unused feature bits. */
69 gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE;
70 dcfg = 0;
71
72 /* Set FIFO priority (default 6/5) and enable. */
73 /* FIXME: increase fifo priority for 1280x1024 and higher modes? */
74 gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
75
76 /* Framebuffer start offset. */
77 writel(0, par->dc_regs + DC_FB_ST_OFFSET);
78
79 /* Line delta and line buffer length. */
80 writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH);
81 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
82 par->dc_regs + DC_LINE_SIZE);
83
84 /* Enable graphics and video data and unmask address lines. */
85 dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M;
86
87 /* Set pixel format. */
88 switch (info->var.bits_per_pixel) {
89 case 8:
90 dcfg |= DC_DCFG_DISP_MODE_8BPP;
91 break;
92 case 16:
93 dcfg |= DC_DCFG_DISP_MODE_16BPP;
94 dcfg |= DC_DCFG_16BPP_MODE_565;
95 break;
96 case 32:
97 dcfg |= DC_DCFG_DISP_MODE_24BPP;
98 dcfg |= DC_DCFG_PALB;
99 break;
100 }
101
102 /* Enable timing generator. */
103 dcfg |= DC_DCFG_TGEN;
104
105 /* Horizontal and vertical timings. */
106 hactive = info->var.xres;
107 hblankstart = hactive;
108 hsyncstart = hblankstart + info->var.right_margin;
109 hsyncend = hsyncstart + info->var.hsync_len;
110 hblankend = hsyncend + info->var.left_margin;
111 htotal = hblankend;
112
113 vactive = info->var.yres;
114 vblankstart = vactive;
115 vsyncstart = vblankstart + info->var.lower_margin;
116 vsyncend = vsyncstart + info->var.vsync_len;
117 vblankend = vsyncend + info->var.upper_margin;
118 vtotal = vblankend;
119
120 writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING);
121 writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING);
122 writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING);
123
124 writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING);
125 writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING);
126 writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING);
127
128 /* Write final register values. */
129 writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
130 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
131
132 par->vid_ops->configure_display(info);
133
134 /* Relock display controller registers */
135 writel(0, par->dc_regs + DC_UNLOCK);
136}
137
138static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
139 unsigned red, unsigned green, unsigned blue)
140{
141 struct geodefb_par *par = info->par;
142 int val;
143
144 /* Hardware palette is in RGB 8-8-8 format. */
145 val = (red << 8) & 0xff0000;
146 val |= (green) & 0x00ff00;
147 val |= (blue >> 8) & 0x0000ff;
148
149 writel(regno, par->dc_regs + DC_PAL_ADDRESS);
150 writel(val, par->dc_regs + DC_PAL_DATA);
151}
152
153struct geode_dc_ops gx_dc_ops = {
154 .set_mode = gx_set_mode,
155 .set_palette_reg = gx_set_hw_palette_reg,
156};
diff --git a/drivers/video/geode/display_gx.h b/drivers/video/geode/display_gx.h
new file mode 100644
index 000000000000..86c623361305
--- /dev/null
+++ b/drivers/video/geode/display_gx.h
@@ -0,0 +1,96 @@
1/*
2 * Geode GX display controller
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#ifndef __DISPLAY_GX_H__
12#define __DISPLAY_GX_H__
13
14int gx_frame_buffer_size(void);
15int gx_line_delta(int xres, int bpp);
16
17extern struct geode_dc_ops gx_dc_ops;
18
19/* Display controller registers */
20
21#define DC_UNLOCK 0x00
22# define DC_UNLOCK_CODE 0x00004758
23
24#define DC_GENERAL_CFG 0x04
25# define DC_GCFG_DFLE 0x00000001
26# define DC_GCFG_CURE 0x00000002
27# define DC_GCFG_ICNE 0x00000004
28# define DC_GCFG_VIDE 0x00000008
29# define DC_GCFG_CMPE 0x00000020
30# define DC_GCFG_DECE 0x00000040
31# define DC_GCFG_VGAE 0x00000080
32# define DC_GCFG_DFHPSL_MASK 0x00000F00
33# define DC_GCFG_DFHPSL_POS 8
34# define DC_GCFG_DFHPEL_MASK 0x0000F000
35# define DC_GCFG_DFHPEL_POS 12
36# define DC_GCFG_STFM 0x00010000
37# define DC_GCFG_FDTY 0x00020000
38# define DC_GCFG_VGAFT 0x00040000
39# define DC_GCFG_VDSE 0x00080000
40# define DC_GCFG_YUVM 0x00100000
41# define DC_GCFG_VFSL 0x00800000
42# define DC_GCFG_SIGE 0x01000000
43# define DC_GCFG_SGRE 0x02000000
44# define DC_GCFG_SGFR 0x04000000
45# define DC_GCFG_CRC_MODE 0x08000000
46# define DC_GCFG_DIAG 0x10000000
47# define DC_GCFG_CFRW 0x20000000
48
49#define DC_DISPLAY_CFG 0x08
50# define DC_DCFG_TGEN 0x00000001
51# define DC_DCFG_GDEN 0x00000008
52# define DC_DCFG_VDEN 0x00000010
53# define DC_DCFG_TRUP 0x00000040
54# define DC_DCFG_DISP_MODE_MASK 0x00000300
55# define DC_DCFG_DISP_MODE_8BPP 0x00000000
56# define DC_DCFG_DISP_MODE_16BPP 0x00000100
57# define DC_DCFG_DISP_MODE_24BPP 0x00000200
58# define DC_DCFG_16BPP_MODE_MASK 0x00000c00
59# define DC_DCFG_16BPP_MODE_565 0x00000000
60# define DC_DCFG_16BPP_MODE_555 0x00000100
61# define DC_DCFG_16BPP_MODE_444 0x00000200
62# define DC_DCFG_DCEN 0x00080000
63# define DC_DCFG_PALB 0x02000000
64# define DC_DCFG_FRLK 0x04000000
65# define DC_DCFG_VISL 0x08000000
66# define DC_DCFG_FRSL 0x20000000
67# define DC_DCFG_A18M 0x40000000
68# define DC_DCFG_A20M 0x80000000
69
70#define DC_FB_ST_OFFSET 0x10
71
72#define DC_LINE_SIZE 0x30
73# define DC_LINE_SIZE_FB_LINE_SIZE_MASK 0x000007ff
74# define DC_LINE_SIZE_FB_LINE_SIZE_POS 0
75# define DC_LINE_SIZE_CB_LINE_SIZE_MASK 0x007f0000
76# define DC_LINE_SIZE_CB_LINE_SIZE_POS 16
77# define DC_LINE_SIZE_VID_LINE_SIZE_MASK 0xff000000
78# define DC_LINE_SIZE_VID_LINE_SIZE_POS 24
79
80#define DC_GFX_PITCH 0x34
81# define DC_GFX_PITCH_FB_PITCH_MASK 0x0000ffff
82# define DC_GFX_PITCH_FB_PITCH_POS 0
83# define DC_GFX_PITCH_CB_PITCH_MASK 0xffff0000
84# define DC_GFX_PITCH_CB_PITCH_POS 16
85
86#define DC_H_ACTIVE_TIMING 0x40
87#define DC_H_BLANK_TIMING 0x44
88#define DC_H_SYNC_TIMING 0x48
89#define DC_V_ACTIVE_TIMING 0x50
90#define DC_V_BLANK_TIMING 0x54
91#define DC_V_SYNC_TIMING 0x58
92
93#define DC_PAL_ADDRESS 0x70
94#define DC_PAL_DATA 0x74
95
96#endif /* !__DISPLAY_GX1_H__ */
diff --git a/drivers/video/geode/gxfb_core.c b/drivers/video/geode/gxfb_core.c
new file mode 100644
index 000000000000..89c34b15f5d4
--- /dev/null
+++ b/drivers/video/geode/gxfb_core.c
@@ -0,0 +1,423 @@
1/*
2 * Geode GX framebuffer driver.
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 *
12 * This driver assumes that the BIOS has created a virtual PCI device header
13 * for the video device. The PCI header is assumed to contain the following
14 * BARs:
15 *
16 * BAR0 - framebuffer memory
17 * BAR1 - graphics processor registers
18 * BAR2 - display controller registers
19 * BAR3 - video processor and flat panel control registers.
20 *
21 * 16 MiB of framebuffer memory is assumed to be available.
22 */
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/errno.h>
26#include <linux/string.h>
27#include <linux/mm.h>
28#include <linux/tty.h>
29#include <linux/slab.h>
30#include <linux/delay.h>
31#include <linux/fb.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34
35#include "geodefb.h"
36#include "display_gx.h"
37#include "video_gx.h"
38
39static char mode_option[32] = "640x480-16@60";
40
41/* Modes relevant to the GX (taken from modedb.c) */
42static const struct fb_videomode __initdata gx_modedb[] = {
43 /* 640x480-60 VESA */
44 { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
45 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
46 /* 640x480-75 VESA */
47 { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
48 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
49 /* 640x480-85 VESA */
50 { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
51 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
52 /* 800x600-60 VESA */
53 { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
54 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
55 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
56 /* 800x600-75 VESA */
57 { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
58 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
59 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
60 /* 800x600-85 VESA */
61 { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
62 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
63 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
64 /* 1024x768-60 VESA */
65 { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
66 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
67 /* 1024x768-75 VESA */
68 { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
69 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
70 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
71 /* 1024x768-85 VESA */
72 { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
73 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
74 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
75 /* 1280x960-60 VESA */
76 { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
77 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
78 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
79 /* 1280x960-85 VESA */
80 { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
81 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
82 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
83 /* 1280x1024-60 VESA */
84 { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
85 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
86 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
87 /* 1280x1024-75 VESA */
88 { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
89 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
90 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
91 /* 1280x1024-85 VESA */
92 { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
93 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
94 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
95 /* 1600x1200-60 VESA */
96 { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
97 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
98 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
99 /* 1600x1200-75 VESA */
100 { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
101 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
102 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
103 /* 1600x1200-85 VESA */
104 { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
105 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
106 FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
107};
108
109static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
110{
111 if (var->xres > 1600 || var->yres > 1200)
112 return -EINVAL;
113 if ((var->xres > 1280 || var->yres > 1024) && var->bits_per_pixel > 16)
114 return -EINVAL;
115
116 if (var->bits_per_pixel == 32) {
117 var->red.offset = 16; var->red.length = 8;
118 var->green.offset = 8; var->green.length = 8;
119 var->blue.offset = 0; var->blue.length = 8;
120 } else if (var->bits_per_pixel == 16) {
121 var->red.offset = 11; var->red.length = 5;
122 var->green.offset = 5; var->green.length = 6;
123 var->blue.offset = 0; var->blue.length = 5;
124 } else if (var->bits_per_pixel == 8) {
125 var->red.offset = 0; var->red.length = 8;
126 var->green.offset = 0; var->green.length = 8;
127 var->blue.offset = 0; var->blue.length = 8;
128 } else
129 return -EINVAL;
130 var->transp.offset = 0; var->transp.length = 0;
131
132 /* Enough video memory? */
133 if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
134 return -EINVAL;
135
136 /* FIXME: Check timing parameters here? */
137
138 return 0;
139}
140
141static int gxfb_set_par(struct fb_info *info)
142{
143 struct geodefb_par *par = info->par;
144
145 if (info->var.bits_per_pixel > 8) {
146 info->fix.visual = FB_VISUAL_TRUECOLOR;
147 fb_dealloc_cmap(&info->cmap);
148 } else {
149 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
150 fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
151 }
152
153 info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel);
154
155 par->dc_ops->set_mode(info);
156
157 return 0;
158}
159
160static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
161{
162 chan &= 0xffff;
163 chan >>= 16 - bf->length;
164 return chan << bf->offset;
165}
166
167static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
168 unsigned blue, unsigned transp,
169 struct fb_info *info)
170{
171 struct geodefb_par *par = info->par;
172
173 if (info->var.grayscale) {
174 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
175 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
176 }
177
178 /* Truecolor has hardware independent palette */
179 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
180 u32 *pal = info->pseudo_palette;
181 u32 v;
182
183 if (regno >= 16)
184 return -EINVAL;
185
186 v = chan_to_field(red, &info->var.red);
187 v |= chan_to_field(green, &info->var.green);
188 v |= chan_to_field(blue, &info->var.blue);
189
190 pal[regno] = v;
191 } else {
192 if (regno >= 256)
193 return -EINVAL;
194
195 par->dc_ops->set_palette_reg(info, regno, red, green, blue);
196 }
197
198 return 0;
199}
200
201static int gxfb_blank(int blank_mode, struct fb_info *info)
202{
203 struct geodefb_par *par = info->par;
204
205 return par->vid_ops->blank_display(info, blank_mode);
206}
207
208static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
209{
210 struct geodefb_par *par = info->par;
211 int fb_len;
212 int ret;
213
214 ret = pci_enable_device(dev);
215 if (ret < 0)
216 return ret;
217
218 ret = pci_request_region(dev, 3, "gxfb (video processor)");
219 if (ret < 0)
220 return ret;
221 par->vid_regs = ioremap(pci_resource_start(dev, 3),
222 pci_resource_len(dev, 3));
223 if (!par->vid_regs)
224 return -ENOMEM;
225
226 ret = pci_request_region(dev, 2, "gxfb (display controller)");
227 if (ret < 0)
228 return ret;
229 par->dc_regs = ioremap(pci_resource_start(dev, 2), pci_resource_len(dev, 2));
230 if (!par->dc_regs)
231 return -ENOMEM;
232
233 ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
234 if (ret < 0)
235 return ret;
236 if ((fb_len = gx_frame_buffer_size()) < 0)
237 return -ENOMEM;
238 info->fix.smem_start = pci_resource_start(dev, 0);
239 info->fix.smem_len = fb_len;
240 info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
241 if (!info->screen_base)
242 return -ENOMEM;
243
244 dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n",
245 info->fix.smem_len / 1024, info->fix.smem_start);
246
247 return 0;
248}
249
250static struct fb_ops gxfb_ops = {
251 .owner = THIS_MODULE,
252 .fb_check_var = gxfb_check_var,
253 .fb_set_par = gxfb_set_par,
254 .fb_setcolreg = gxfb_setcolreg,
255 .fb_blank = gxfb_blank,
256 /* No HW acceleration for now. */
257 .fb_fillrect = cfb_fillrect,
258 .fb_copyarea = cfb_copyarea,
259 .fb_imageblit = cfb_imageblit,
260};
261
262static struct fb_info * __init gxfb_init_fbinfo(struct device *dev)
263{
264 struct geodefb_par *par;
265 struct fb_info *info;
266
267 /* Alloc enough space for the pseudo palette. */
268 info = framebuffer_alloc(sizeof(struct geodefb_par) + sizeof(u32) * 16, dev);
269 if (!info)
270 return NULL;
271
272 par = info->par;
273
274 strcpy(info->fix.id, "Geode GX");
275
276 info->fix.type = FB_TYPE_PACKED_PIXELS;
277 info->fix.type_aux = 0;
278 info->fix.xpanstep = 0;
279 info->fix.ypanstep = 0;
280 info->fix.ywrapstep = 0;
281 info->fix.accel = FB_ACCEL_NONE;
282
283 info->var.nonstd = 0;
284 info->var.activate = FB_ACTIVATE_NOW;
285 info->var.height = -1;
286 info->var.width = -1;
287 info->var.accel_flags = 0;
288 info->var.vmode = FB_VMODE_NONINTERLACED;
289
290 info->fbops = &gxfb_ops;
291 info->flags = FBINFO_DEFAULT;
292 info->node = -1;
293
294 info->pseudo_palette = (void *)par + sizeof(struct geodefb_par);
295
296 info->var.grayscale = 0;
297
298 return info;
299}
300
301static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
302{
303 struct geodefb_par *par;
304 struct fb_info *info;
305 int ret;
306
307 info = gxfb_init_fbinfo(&pdev->dev);
308 if (!info)
309 return -ENOMEM;
310 par = info->par;
311
312 /* GX display controller and GX video device. */
313 par->dc_ops = &gx_dc_ops;
314 par->vid_ops = &gx_vid_ops;
315
316 if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
317 dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
318 goto err;
319 }
320
321 ret = fb_find_mode(&info->var, info, mode_option,
322 gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16);
323 if (ret == 0 || ret == 4) {
324 dev_err(&pdev->dev, "could not find valid video mode\n");
325 ret = -EINVAL;
326 goto err;
327 }
328
329 /* Clear the frame buffer of garbage. */
330 memset_io(info->screen_base, 0, info->fix.smem_len);
331
332 gxfb_check_var(&info->var, info);
333 gxfb_set_par(info);
334
335 if (register_framebuffer(info) < 0) {
336 ret = -EINVAL;
337 goto err;
338 }
339 pci_set_drvdata(pdev, info);
340 printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id);
341 return 0;
342
343 err:
344 if (info->screen_base) {
345 iounmap(info->screen_base);
346 pci_release_region(pdev, 0);
347 }
348 if (par->vid_regs) {
349 iounmap(par->vid_regs);
350 pci_release_region(pdev, 3);
351 }
352 if (par->dc_regs) {
353 iounmap(par->dc_regs);
354 pci_release_region(pdev, 2);
355 }
356
357 pci_disable_device(pdev);
358
359 if (info)
360 framebuffer_release(info);
361 return ret;
362}
363
364static void gxfb_remove(struct pci_dev *pdev)
365{
366 struct fb_info *info = pci_get_drvdata(pdev);
367 struct geodefb_par *par = info->par;
368
369 unregister_framebuffer(info);
370
371 iounmap((void __iomem *)info->screen_base);
372 pci_release_region(pdev, 0);
373
374 iounmap(par->vid_regs);
375 pci_release_region(pdev, 3);
376
377 iounmap(par->dc_regs);
378 pci_release_region(pdev, 2);
379
380 pci_disable_device(pdev);
381 pci_set_drvdata(pdev, NULL);
382
383 framebuffer_release(info);
384}
385
386static struct pci_device_id gxfb_id_table[] = {
387 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_VIDEO,
388 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
389 0xff0000, 0 },
390 { 0, }
391};
392
393MODULE_DEVICE_TABLE(pci, gxfb_id_table);
394
395static struct pci_driver gxfb_driver = {
396 .name = "gxfb",
397 .id_table = gxfb_id_table,
398 .probe = gxfb_probe,
399 .remove = gxfb_remove,
400};
401
402static int __init gxfb_init(void)
403{
404#ifndef MODULE
405 if (fb_get_options("gxfb", NULL))
406 return -ENODEV;
407#endif
408 return pci_register_driver(&gxfb_driver);
409}
410
411static void __exit gxfb_cleanup(void)
412{
413 pci_unregister_driver(&gxfb_driver);
414}
415
416module_init(gxfb_init);
417module_exit(gxfb_cleanup);
418
419module_param_string(mode, mode_option, sizeof(mode_option), 0444);
420MODULE_PARM_DESC(mode, "video mode (<x>x<y>[-<bpp>][@<refr>])");
421
422MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
423MODULE_LICENSE("GPL");
diff --git a/drivers/video/geode/video_gx.c b/drivers/video/geode/video_gx.c
new file mode 100644
index 000000000000..2b2a7880ea75
--- /dev/null
+++ b/drivers/video/geode/video_gx.c
@@ -0,0 +1,262 @@
1/*
2 * Geode GX video processor device.
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * Portions from AMD's original 2.4 driver:
7 * Copyright (C) 2004 Advanced Micro Devices, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/fb.h>
15#include <linux/delay.h>
16#include <asm/io.h>
17#include <asm/delay.h>
18#include <asm/msr.h>
19
20#include "geodefb.h"
21#include "video_gx.h"
22
23
24/*
25 * Tables of register settings for various DOTCLKs.
26 */
27struct gx_pll_entry {
28 long pixclock; /* ps */
29 u32 sys_rstpll_bits;
30 u32 dotpll_value;
31};
32
33#define POSTDIV3 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
34#define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2)
35#define PREDIV2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
36
37static const struct gx_pll_entry gx_pll_table_48MHz[] = {
38 { 40123, POSTDIV3, 0x00000BF2 }, /* 24.9230 */
39 { 39721, 0, 0x00000037 }, /* 25.1750 */
40 { 35308, POSTDIV3|PREMULT2, 0x00000B1A }, /* 28.3220 */
41 { 31746, POSTDIV3, 0x000002D2 }, /* 31.5000 */
42 { 27777, POSTDIV3|PREMULT2, 0x00000FE2 }, /* 36.0000 */
43 { 26666, POSTDIV3, 0x0000057A }, /* 37.5000 */
44 { 25000, POSTDIV3, 0x0000030A }, /* 40.0000 */
45 { 22271, 0, 0x00000063 }, /* 44.9000 */
46 { 20202, 0, 0x0000054B }, /* 49.5000 */
47 { 20000, 0, 0x0000026E }, /* 50.0000 */
48 { 19860, PREMULT2, 0x00000037 }, /* 50.3500 */
49 { 18518, POSTDIV3|PREMULT2, 0x00000B0D }, /* 54.0000 */
50 { 17777, 0, 0x00000577 }, /* 56.2500 */
51 { 17733, 0, 0x000007F7 }, /* 56.3916 */
52 { 17653, 0, 0x0000057B }, /* 56.6444 */
53 { 16949, PREMULT2, 0x00000707 }, /* 59.0000 */
54 { 15873, POSTDIV3|PREMULT2, 0x00000B39 }, /* 63.0000 */
55 { 15384, POSTDIV3|PREMULT2, 0x00000B45 }, /* 65.0000 */
56 { 14814, POSTDIV3|PREMULT2, 0x00000FC1 }, /* 67.5000 */
57 { 14124, POSTDIV3, 0x00000561 }, /* 70.8000 */
58 { 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */
59 { 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */
60 { 13333, 0, 0x00000052 }, /* 75.0000 */
61 { 12698, 0, 0x00000056 }, /* 78.7500 */
62 { 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */
63 { 11135, PREMULT2, 0x00000262 }, /* 89.8000 */
64 { 10582, 0, 0x000002D2 }, /* 94.5000 */
65 { 10101, PREMULT2, 0x00000B4A }, /* 99.0000 */
66 { 10000, PREMULT2, 0x00000036 }, /* 100.0000 */
67 { 9259, 0, 0x000007E2 }, /* 108.0000 */
68 { 8888, 0, 0x000007F6 }, /* 112.5000 */
69 { 7692, POSTDIV3|PREMULT2, 0x00000FB0 }, /* 130.0000 */
70 { 7407, POSTDIV3|PREMULT2, 0x00000B50 }, /* 135.0000 */
71 { 6349, 0, 0x00000055 }, /* 157.5000 */
72 { 6172, 0, 0x000009C1 }, /* 162.0000 */
73 { 5787, PREMULT2, 0x0000002D }, /* 172.798 */
74 { 5698, 0, 0x000002C1 }, /* 175.5000 */
75 { 5291, 0, 0x000002D1 }, /* 189.0000 */
76 { 4938, 0, 0x00000551 }, /* 202.5000 */
77 { 4357, 0, 0x0000057D }, /* 229.5000 */
78};
79
80static const struct gx_pll_entry gx_pll_table_14MHz[] = {
81 { 39721, 0, 0x00000037 }, /* 25.1750 */
82 { 35308, 0, 0x00000B7B }, /* 28.3220 */
83 { 31746, 0, 0x000004D3 }, /* 31.5000 */
84 { 27777, 0, 0x00000BE3 }, /* 36.0000 */
85 { 26666, 0, 0x0000074F }, /* 37.5000 */
86 { 25000, 0, 0x0000050B }, /* 40.0000 */
87 { 22271, 0, 0x00000063 }, /* 44.9000 */
88 { 20202, 0, 0x0000054B }, /* 49.5000 */
89 { 20000, 0, 0x0000026E }, /* 50.0000 */
90 { 19860, 0, 0x000007C3 }, /* 50.3500 */
91 { 18518, 0, 0x000007E3 }, /* 54.0000 */
92 { 17777, 0, 0x00000577 }, /* 56.2500 */
93 { 17733, 0, 0x000002FB }, /* 56.3916 */
94 { 17653, 0, 0x0000057B }, /* 56.6444 */
95 { 16949, 0, 0x0000058B }, /* 59.0000 */
96 { 15873, 0, 0x0000095E }, /* 63.0000 */
97 { 15384, 0, 0x0000096A }, /* 65.0000 */
98 { 14814, 0, 0x00000BC2 }, /* 67.5000 */
99 { 14124, 0, 0x0000098A }, /* 70.8000 */
100 { 13888, 0, 0x00000BE2 }, /* 72.0000 */
101 { 13333, 0, 0x00000052 }, /* 75.0000 */
102 { 12698, 0, 0x00000056 }, /* 78.7500 */
103 { 12500, 0, 0x0000050A }, /* 80.0000 */
104 { 11135, 0, 0x0000078E }, /* 89.8000 */
105 { 10582, 0, 0x000002D2 }, /* 94.5000 */
106 { 10101, 0, 0x000011F6 }, /* 99.0000 */
107 { 10000, 0, 0x0000054E }, /* 100.0000 */
108 { 9259, 0, 0x000007E2 }, /* 108.0000 */
109 { 8888, 0, 0x000002FA }, /* 112.5000 */
110 { 7692, 0, 0x00000BB1 }, /* 130.0000 */
111 { 7407, 0, 0x00000975 }, /* 135.0000 */
112 { 6349, 0, 0x00000055 }, /* 157.5000 */
113 { 6172, 0, 0x000009C1 }, /* 162.0000 */
114 { 5698, 0, 0x000002C1 }, /* 175.5000 */
115 { 5291, 0, 0x00000539 }, /* 189.0000 */
116 { 4938, 0, 0x00000551 }, /* 202.5000 */
117 { 4357, 0, 0x0000057D }, /* 229.5000 */
118};
119
120static void gx_set_dclk_frequency(struct fb_info *info)
121{
122 const struct gx_pll_entry *pll_table;
123 int pll_table_len;
124 int i, best_i;
125 long min, diff;
126 u64 dotpll, sys_rstpll;
127 int timeout = 1000;
128
129 /* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
130 if (cpu_data->x86_mask == 1) {
131 pll_table = gx_pll_table_14MHz;
132 pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
133 } else {
134 pll_table = gx_pll_table_48MHz;
135 pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
136 }
137
138 /* Search the table for the closest pixclock. */
139 best_i = 0;
140 min = abs(pll_table[0].pixclock - info->var.pixclock);
141 for (i = 1; i < pll_table_len; i++) {
142 diff = abs(pll_table[i].pixclock - info->var.pixclock);
143 if (diff < min) {
144 min = diff;
145 best_i = i;
146 }
147 }
148
149 rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
150 rdmsrl(MSR_GLCP_DOTPLL, dotpll);
151
152 /* Program new M, N and P. */
153 dotpll &= 0x00000000ffffffffull;
154 dotpll |= (u64)pll_table[best_i].dotpll_value << 32;
155 dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
156 dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
157
158 wrmsrl(MSR_GLCP_DOTPLL, dotpll);
159
160 /* Program dividers. */
161 sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2
162 | MSR_GLCP_SYS_RSTPLL_DOTPREMULT2
163 | MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 );
164 sys_rstpll |= pll_table[best_i].sys_rstpll_bits;
165
166 wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
167
168 /* Clear reset bit to start PLL. */
169 dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
170 wrmsrl(MSR_GLCP_DOTPLL, dotpll);
171
172 /* Wait for LOCK bit. */
173 do {
174 rdmsrl(MSR_GLCP_DOTPLL, dotpll);
175 } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
176}
177
178static void gx_configure_display(struct fb_info *info)
179{
180 struct geodefb_par *par = info->par;
181 u32 dcfg, fp_pm;
182
183 dcfg = readl(par->vid_regs + GX_DCFG);
184
185 /* Clear bits from existing mode. */
186 dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
187 | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL
188 | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
189
190 /* Set default sync skew. */
191 dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT;
192
193 /* Enable hsync and vsync. */
194 dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN;
195
196 /* Sync polarities. */
197 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
198 dcfg |= GX_DCFG_CRT_HSYNC_POL;
199 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
200 dcfg |= GX_DCFG_CRT_VSYNC_POL;
201
202 writel(dcfg, par->vid_regs + GX_DCFG);
203
204 /* Power on flat panel. */
205 fp_pm = readl(par->vid_regs + GX_FP_PM);
206 fp_pm |= GX_FP_PM_P;
207 writel(fp_pm, par->vid_regs + GX_FP_PM);
208}
209
210static int gx_blank_display(struct fb_info *info, int blank_mode)
211{
212 struct geodefb_par *par = info->par;
213 u32 dcfg, fp_pm;
214 int blank, hsync, vsync;
215
216 /* CRT power saving modes. */
217 switch (blank_mode) {
218 case FB_BLANK_UNBLANK:
219 blank = 0; hsync = 1; vsync = 1;
220 break;
221 case FB_BLANK_NORMAL:
222 blank = 1; hsync = 1; vsync = 1;
223 break;
224 case FB_BLANK_VSYNC_SUSPEND:
225 blank = 1; hsync = 1; vsync = 0;
226 break;
227 case FB_BLANK_HSYNC_SUSPEND:
228 blank = 1; hsync = 0; vsync = 1;
229 break;
230 case FB_BLANK_POWERDOWN:
231 blank = 1; hsync = 0; vsync = 0;
232 break;
233 default:
234 return -EINVAL;
235 }
236 dcfg = readl(par->vid_regs + GX_DCFG);
237 dcfg &= ~(GX_DCFG_DAC_BL_EN
238 | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN);
239 if (!blank)
240 dcfg |= GX_DCFG_DAC_BL_EN;
241 if (hsync)
242 dcfg |= GX_DCFG_HSYNC_EN;
243 if (vsync)
244 dcfg |= GX_DCFG_VSYNC_EN;
245 writel(dcfg, par->vid_regs + GX_DCFG);
246
247 /* Power on/off flat panel. */
248 fp_pm = readl(par->vid_regs + GX_FP_PM);
249 if (blank_mode == FB_BLANK_POWERDOWN)
250 fp_pm &= ~GX_FP_PM_P;
251 else
252 fp_pm |= GX_FP_PM_P;
253 writel(fp_pm, par->vid_regs + GX_FP_PM);
254
255 return 0;
256}
257
258struct geode_vid_ops gx_vid_ops = {
259 .set_dclk = gx_set_dclk_frequency,
260 .configure_display = gx_configure_display,
261 .blank_display = gx_blank_display,
262};
diff --git a/drivers/video/geode/video_gx.h b/drivers/video/geode/video_gx.h
new file mode 100644
index 000000000000..2d9211f3ed84
--- /dev/null
+++ b/drivers/video/geode/video_gx.h
@@ -0,0 +1,47 @@
1/*
2 * Geode GX video device
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#ifndef __VIDEO_GX_H__
12#define __VIDEO_GX_H__
13
14extern struct geode_vid_ops gx_vid_ops;
15
16/* Geode GX video processor registers */
17
18#define GX_DCFG 0x0008
19# define GX_DCFG_CRT_EN 0x00000001
20# define GX_DCFG_HSYNC_EN 0x00000002
21# define GX_DCFG_VSYNC_EN 0x00000004
22# define GX_DCFG_DAC_BL_EN 0x00000008
23# define GX_DCFG_CRT_HSYNC_POL 0x00000100
24# define GX_DCFG_CRT_VSYNC_POL 0x00000200
25# define GX_DCFG_CRT_SYNC_SKW_MASK 0x0001C000
26# define GX_DCFG_CRT_SYNC_SKW_DFLT 0x00010000
27# define GX_DCFG_VG_CK 0x00100000
28# define GX_DCFG_GV_GAM 0x00200000
29# define GX_DCFG_DAC_VREF 0x04000000
30
31/* Geode GX flat panel display control registers */
32#define GX_FP_PM 0x410
33# define GX_FP_PM_P 0x01000000
34
35/* Geode GX clock control MSRs */
36
37#define MSR_GLCP_SYS_RSTPLL 0x4c000014
38# define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (0x0000000000000002ull)
39# define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (0x0000000000000004ull)
40# define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (0x0000000000000008ull)
41
42#define MSR_GLCP_DOTPLL 0x4c000015
43# define MSR_GLCP_DOTPLL_DOTRESET (0x0000000000000001ull)
44# define MSR_GLCP_DOTPLL_BYPASS (0x0000000000008000ull)
45# define MSR_GLCP_DOTPLL_LOCK (0x0000000002000000ull)
46
47#endif /* !__VIDEO_GX_H__ */
diff --git a/drivers/video/i810/i810-i2c.c b/drivers/video/i810/i810-i2c.c
index e3c8b5f1ca76..3fe3ae1aff12 100644
--- a/drivers/video/i810/i810-i2c.c
+++ b/drivers/video/i810/i810-i2c.c
@@ -210,8 +210,7 @@ int i810_probe_i2c_connector(struct fb_info *info, u8 **out_edid, int conn)
210 } 210 }
211 } 211 }
212 212
213 if (out_edid) 213 *out_edid = edid;
214 *out_edid = edid;
215 214
216 return (edid) ? 0 : 1; 215 return (edid) ? 0 : 1;
217} 216}
diff --git a/drivers/video/imsttfb.c b/drivers/video/imsttfb.c
index 7db42542eb19..f73c642b50c2 100644
--- a/drivers/video/imsttfb.c
+++ b/drivers/video/imsttfb.c
@@ -440,9 +440,9 @@ getclkMHz(struct imstt_par *par)
440static void 440static void
441setclkMHz(struct imstt_par *par, __u32 MHz) 441setclkMHz(struct imstt_par *par, __u32 MHz)
442{ 442{
443 __u32 clk_m, clk_n, clk_p, x, stage, spilled; 443 __u32 clk_m, clk_n, x, stage, spilled;
444 444
445 clk_m = clk_n = clk_p = 0; 445 clk_m = clk_n = 0;
446 stage = spilled = 0; 446 stage = spilled = 0;
447 for (;;) { 447 for (;;) {
448 switch (stage) { 448 switch (stage) {
@@ -453,7 +453,7 @@ setclkMHz(struct imstt_par *par, __u32 MHz)
453 clk_n++; 453 clk_n++;
454 break; 454 break;
455 } 455 }
456 x = 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1)); 456 x = 20 * (clk_m + 1) / (clk_n + 1);
457 if (x == MHz) 457 if (x == MHz)
458 break; 458 break;
459 if (x > MHz) { 459 if (x > MHz) {
@@ -466,7 +466,7 @@ setclkMHz(struct imstt_par *par, __u32 MHz)
466 466
467 par->init.pclk_m = clk_m; 467 par->init.pclk_m = clk_m;
468 par->init.pclk_n = clk_n; 468 par->init.pclk_n = clk_n;
469 par->init.pclk_p = clk_p; 469 par->init.pclk_p = 0;
470} 470}
471 471
472static struct imstt_regvals * 472static struct imstt_regvals *
@@ -1372,18 +1372,24 @@ init_imstt(struct fb_info *info)
1372 write_reg_le32(par->dc_regs, STGCTL, tmp & ~0x1); 1372 write_reg_le32(par->dc_regs, STGCTL, tmp & ~0x1);
1373 write_reg_le32(par->dc_regs, SSR, 0); 1373 write_reg_le32(par->dc_regs, SSR, 0);
1374 1374
1375 /* set default values for DAC registers */ 1375 /* set default values for DAC registers */
1376 if (par->ramdac == IBM) { 1376 if (par->ramdac == IBM) {
1377 par->cmap_regs[PPMASK] = 0xff; eieio(); 1377 par->cmap_regs[PPMASK] = 0xff;
1378 par->cmap_regs[PIDXHI] = 0; eieio(); 1378 eieio();
1379 for (i = 0; i < sizeof(ibm_initregs) / sizeof(*ibm_initregs); i++) { 1379 par->cmap_regs[PIDXHI] = 0;
1380 par->cmap_regs[PIDXLO] = ibm_initregs[i].addr; eieio(); 1380 eieio();
1381 par->cmap_regs[PIDXDATA] = ibm_initregs[i].value; eieio(); 1381 for (i = 0; i < ARRAY_SIZE(ibm_initregs); i++) {
1382 par->cmap_regs[PIDXLO] = ibm_initregs[i].addr;
1383 eieio();
1384 par->cmap_regs[PIDXDATA] = ibm_initregs[i].value;
1385 eieio();
1382 } 1386 }
1383 } else { 1387 } else {
1384 for (i = 0; i < sizeof(tvp_initregs) / sizeof(*tvp_initregs); i++) { 1388 for (i = 0; i < ARRAY_SIZE(tvp_initregs); i++) {
1385 par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr; eieio(); 1389 par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr;
1386 par->cmap_regs[TVPIDATA] = tvp_initregs[i].value; eieio(); 1390 eieio();
1391 par->cmap_regs[TVPIDATA] = tvp_initregs[i].value;
1392 eieio();
1387 } 1393 }
1388 } 1394 }
1389 1395
diff --git a/drivers/video/macmodes.c b/drivers/video/macmodes.c
index 2fc71081f7e7..c0385c6f7db5 100644
--- a/drivers/video/macmodes.c
+++ b/drivers/video/macmodes.c
@@ -380,7 +380,7 @@ int __init mac_find_mode(struct fb_var_screeninfo *var, struct fb_info *info,
380 if (mode_option && !strncmp(mode_option, "mac", 3)) { 380 if (mode_option && !strncmp(mode_option, "mac", 3)) {
381 mode_option += 3; 381 mode_option += 3;
382 db = mac_modedb; 382 db = mac_modedb;
383 dbsize = sizeof(mac_modedb)/sizeof(*mac_modedb); 383 dbsize = ARRAY_SIZE(mac_modedb);
384 } 384 }
385 return fb_find_mode(var, info, mode_option, db, dbsize, 385 return fb_find_mode(var, info, mode_option, db, dbsize,
386 &mac_modedb[DEFAULT_MODEDB_INDEX], default_bpp); 386 &mac_modedb[DEFAULT_MODEDB_INDEX], default_bpp);
diff --git a/drivers/video/matrox/matroxfb_g450.c b/drivers/video/matrox/matroxfb_g450.c
index c122d8743dd2..4d610b405d45 100644
--- a/drivers/video/matrox/matroxfb_g450.c
+++ b/drivers/video/matrox/matroxfb_g450.c
@@ -59,7 +59,7 @@ static const struct mctl g450_controls[] =
59 }, offsetof(struct matrox_fb_info, altout.tvo_params.testout) }, 59 }, offsetof(struct matrox_fb_info, altout.tvo_params.testout) },
60}; 60};
61 61
62#define G450CTRLS (sizeof(g450_controls)/sizeof(g450_controls[0])) 62#define G450CTRLS ARRAY_SIZE(g450_controls)
63 63
64/* Return: positive number: id found 64/* Return: positive number: id found
65 -EINVAL: id not found, return failure 65 -EINVAL: id not found, return failure
diff --git a/drivers/video/matrox/matroxfb_maven.c b/drivers/video/matrox/matroxfb_maven.c
index 6019710dc298..5d29a26b8cdf 100644
--- a/drivers/video/matrox/matroxfb_maven.c
+++ b/drivers/video/matrox/matroxfb_maven.c
@@ -89,12 +89,12 @@ static const struct mctl maven_controls[] =
89 }, offsetof(struct matrox_fb_info, altout.tvo_params.hue) }, 89 }, offsetof(struct matrox_fb_info, altout.tvo_params.hue) },
90 { { V4L2_CID_GAMMA, V4L2_CTRL_TYPE_INTEGER, 90 { { V4L2_CID_GAMMA, V4L2_CTRL_TYPE_INTEGER,
91 "gamma", 91 "gamma",
92 0, sizeof(maven_gamma)/sizeof(maven_gamma[0])-1, 1, 3, 92 0, ARRAY_SIZE(maven_gamma) - 1, 1, 3,
93 0, 93 0,
94 }, offsetof(struct matrox_fb_info, altout.tvo_params.gamma) }, 94 }, offsetof(struct matrox_fb_info, altout.tvo_params.gamma) },
95 { { MATROXFB_CID_TESTOUT, V4L2_CTRL_TYPE_BOOLEAN, 95 { { MATROXFB_CID_TESTOUT, V4L2_CTRL_TYPE_BOOLEAN,
96 "test output", 96 "test output",
97 0, 1, 1, 0, 97 0, 1, 1, 0,
98 0, 98 0,
99 }, offsetof(struct matrox_fb_info, altout.tvo_params.testout) }, 99 }, offsetof(struct matrox_fb_info, altout.tvo_params.testout) },
100 { { MATROXFB_CID_DEFLICKER, V4L2_CTRL_TYPE_INTEGER, 100 { { MATROXFB_CID_DEFLICKER, V4L2_CTRL_TYPE_INTEGER,
@@ -105,7 +105,7 @@ static const struct mctl maven_controls[] =
105 105
106}; 106};
107 107
108#define MAVCTRLS (sizeof(maven_controls)/sizeof(maven_controls[0])) 108#define MAVCTRLS ARRAY_SIZE(maven_controls)
109 109
110/* Return: positive number: id found 110/* Return: positive number: id found
111 -EINVAL: id not found, return failure 111 -EINVAL: id not found, return failure
@@ -129,7 +129,7 @@ static int get_ctrl_id(__u32 v4l2_id) {
129 129
130struct maven_data { 130struct maven_data {
131 struct matrox_fb_info* primary_head; 131 struct matrox_fb_info* primary_head;
132 struct i2c_client* client; 132 struct i2c_client client;
133 int version; 133 int version;
134}; 134};
135 135
@@ -970,7 +970,7 @@ static inline int maven_compute_timming(struct maven_data* md,
970 970
971static int maven_program_timming(struct maven_data* md, 971static int maven_program_timming(struct maven_data* md,
972 const struct mavenregs* m) { 972 const struct mavenregs* m) {
973 struct i2c_client* c = md->client; 973 struct i2c_client* c = &md->client;
974 974
975 if (m->mode == MATROXFB_OUTPUT_MODE_MONITOR) { 975 if (m->mode == MATROXFB_OUTPUT_MODE_MONITOR) {
976 LR(0x80); 976 LR(0x80);
@@ -1007,7 +1007,7 @@ static int maven_program_timming(struct maven_data* md,
1007} 1007}
1008 1008
1009static inline int maven_resync(struct maven_data* md) { 1009static inline int maven_resync(struct maven_data* md) {
1010 struct i2c_client* c = md->client; 1010 struct i2c_client* c = &md->client;
1011 maven_set_reg(c, 0x95, 0x20); /* start whole thing */ 1011 maven_set_reg(c, 0x95, 0x20); /* start whole thing */
1012 return 0; 1012 return 0;
1013} 1013}
@@ -1065,48 +1065,48 @@ static int maven_set_control (struct maven_data* md,
1065 maven_compute_bwlevel(md, &blacklevel, &whitelevel); 1065 maven_compute_bwlevel(md, &blacklevel, &whitelevel);
1066 blacklevel = (blacklevel >> 2) | ((blacklevel & 3) << 8); 1066 blacklevel = (blacklevel >> 2) | ((blacklevel & 3) << 8);
1067 whitelevel = (whitelevel >> 2) | ((whitelevel & 3) << 8); 1067 whitelevel = (whitelevel >> 2) | ((whitelevel & 3) << 8);
1068 maven_set_reg_pair(md->client, 0x0e, blacklevel); 1068 maven_set_reg_pair(&md->client, 0x0e, blacklevel);
1069 maven_set_reg_pair(md->client, 0x1e, whitelevel); 1069 maven_set_reg_pair(&md->client, 0x1e, whitelevel);
1070 } 1070 }
1071 break; 1071 break;
1072 case V4L2_CID_SATURATION: 1072 case V4L2_CID_SATURATION:
1073 { 1073 {
1074 maven_set_reg(md->client, 0x20, p->value); 1074 maven_set_reg(&md->client, 0x20, p->value);
1075 maven_set_reg(md->client, 0x22, p->value); 1075 maven_set_reg(&md->client, 0x22, p->value);
1076 } 1076 }
1077 break; 1077 break;
1078 case V4L2_CID_HUE: 1078 case V4L2_CID_HUE:
1079 { 1079 {
1080 maven_set_reg(md->client, 0x25, p->value); 1080 maven_set_reg(&md->client, 0x25, p->value);
1081 } 1081 }
1082 break; 1082 break;
1083 case V4L2_CID_GAMMA: 1083 case V4L2_CID_GAMMA:
1084 { 1084 {
1085 const struct maven_gamma* g; 1085 const struct maven_gamma* g;
1086 g = maven_compute_gamma(md); 1086 g = maven_compute_gamma(md);
1087 maven_set_reg(md->client, 0x83, g->reg83); 1087 maven_set_reg(&md->client, 0x83, g->reg83);
1088 maven_set_reg(md->client, 0x84, g->reg84); 1088 maven_set_reg(&md->client, 0x84, g->reg84);
1089 maven_set_reg(md->client, 0x85, g->reg85); 1089 maven_set_reg(&md->client, 0x85, g->reg85);
1090 maven_set_reg(md->client, 0x86, g->reg86); 1090 maven_set_reg(&md->client, 0x86, g->reg86);
1091 maven_set_reg(md->client, 0x87, g->reg87); 1091 maven_set_reg(&md->client, 0x87, g->reg87);
1092 maven_set_reg(md->client, 0x88, g->reg88); 1092 maven_set_reg(&md->client, 0x88, g->reg88);
1093 maven_set_reg(md->client, 0x89, g->reg89); 1093 maven_set_reg(&md->client, 0x89, g->reg89);
1094 maven_set_reg(md->client, 0x8a, g->reg8a); 1094 maven_set_reg(&md->client, 0x8a, g->reg8a);
1095 maven_set_reg(md->client, 0x8b, g->reg8b); 1095 maven_set_reg(&md->client, 0x8b, g->reg8b);
1096 } 1096 }
1097 break; 1097 break;
1098 case MATROXFB_CID_TESTOUT: 1098 case MATROXFB_CID_TESTOUT:
1099 { 1099 {
1100 unsigned char val 1100 unsigned char val
1101 = maven_get_reg (md->client,0x8d); 1101 = maven_get_reg(&md->client,0x8d);
1102 if (p->value) val |= 0x10; 1102 if (p->value) val |= 0x10;
1103 else val &= ~0x10; 1103 else val &= ~0x10;
1104 maven_set_reg (md->client, 0x8d, val); 1104 maven_set_reg(&md->client, 0x8d, val);
1105 } 1105 }
1106 break; 1106 break;
1107 case MATROXFB_CID_DEFLICKER: 1107 case MATROXFB_CID_DEFLICKER:
1108 { 1108 {
1109 maven_set_reg(md->client, 0x93, maven_compute_deflicker(md)); 1109 maven_set_reg(&md->client, 0x93, maven_compute_deflicker(md));
1110 } 1110 }
1111 break; 1111 break;
1112 } 1112 }
@@ -1185,7 +1185,6 @@ static int maven_init_client(struct i2c_client* clnt) {
1185 MINFO_FROM(container_of(clnt->adapter, struct i2c_bit_adapter, adapter)->minfo); 1185 MINFO_FROM(container_of(clnt->adapter, struct i2c_bit_adapter, adapter)->minfo);
1186 1186
1187 md->primary_head = MINFO; 1187 md->primary_head = MINFO;
1188 md->client = clnt;
1189 down_write(&ACCESS_FBINFO(altout.lock)); 1188 down_write(&ACCESS_FBINFO(altout.lock));
1190 ACCESS_FBINFO(outputs[1]).output = &maven_altout; 1189 ACCESS_FBINFO(outputs[1]).output = &maven_altout;
1191 ACCESS_FBINFO(outputs[1]).src = ACCESS_FBINFO(outputs[1]).default_src; 1190 ACCESS_FBINFO(outputs[1]).src = ACCESS_FBINFO(outputs[1]).default_src;
@@ -1243,19 +1242,17 @@ static int maven_detect_client(struct i2c_adapter* adapter, int address, int kin
1243 I2C_FUNC_SMBUS_BYTE_DATA | 1242 I2C_FUNC_SMBUS_BYTE_DATA |
1244 I2C_FUNC_PROTOCOL_MANGLING)) 1243 I2C_FUNC_PROTOCOL_MANGLING))
1245 goto ERROR0; 1244 goto ERROR0;
1246 if (!(new_client = (struct i2c_client*)kmalloc(sizeof(*new_client) + sizeof(*data), 1245 if (!(data = kzalloc(sizeof(*data), GFP_KERNEL))) {
1247 GFP_KERNEL))) {
1248 err = -ENOMEM; 1246 err = -ENOMEM;
1249 goto ERROR0; 1247 goto ERROR0;
1250 } 1248 }
1251 memset(new_client, 0, sizeof(*new_client) + sizeof(*data)); 1249 new_client = &data->client;
1252 data = (struct maven_data*)(new_client + 1);
1253 i2c_set_clientdata(new_client, data); 1250 i2c_set_clientdata(new_client, data);
1254 new_client->addr = address; 1251 new_client->addr = address;
1255 new_client->adapter = adapter; 1252 new_client->adapter = adapter;
1256 new_client->driver = &maven_driver; 1253 new_client->driver = &maven_driver;
1257 new_client->flags = 0; 1254 new_client->flags = 0;
1258 strcpy(new_client->name, "maven client"); 1255 strlcpy(new_client->name, "maven", I2C_NAME_SIZE);
1259 if ((err = i2c_attach_client(new_client))) 1256 if ((err = i2c_attach_client(new_client)))
1260 goto ERROR3; 1257 goto ERROR3;
1261 err = maven_init_client(new_client); 1258 err = maven_init_client(new_client);
@@ -1279,12 +1276,10 @@ static int maven_attach_adapter(struct i2c_adapter* adapter) {
1279static int maven_detach_client(struct i2c_client* client) { 1276static int maven_detach_client(struct i2c_client* client) {
1280 int err; 1277 int err;
1281 1278
1282 if ((err = i2c_detach_client(client))) { 1279 if ((err = i2c_detach_client(client)))
1283 printk(KERN_ERR "maven: Cannot deregister client\n");
1284 return err; 1280 return err;
1285 }
1286 maven_shutdown_client(client); 1281 maven_shutdown_client(client);
1287 kfree(client); 1282 kfree(i2c_get_clientdata(client));
1288 return 0; 1283 return 0;
1289} 1284}
1290 1285
@@ -1297,20 +1292,13 @@ static struct i2c_driver maven_driver={
1297 .detach_client = maven_detach_client, 1292 .detach_client = maven_detach_client,
1298}; 1293};
1299 1294
1300/* ************************** */ 1295static int __init matroxfb_maven_init(void)
1301 1296{
1302static int matroxfb_maven_init(void) { 1297 return i2c_add_driver(&maven_driver);
1303 int err;
1304
1305 err = i2c_add_driver(&maven_driver);
1306 if (err) {
1307 printk(KERN_ERR "maven: Maven driver failed to register (%d).\n", err);
1308 return err;
1309 }
1310 return 0;
1311} 1298}
1312 1299
1313static void matroxfb_maven_exit(void) { 1300static void __exit matroxfb_maven_exit(void)
1301{
1314 i2c_del_driver(&maven_driver); 1302 i2c_del_driver(&maven_driver);
1315} 1303}
1316 1304
diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c
index 1da2f84bdc25..26a1c618a205 100644
--- a/drivers/video/modedb.c
+++ b/drivers/video/modedb.c
@@ -183,6 +183,10 @@ static const struct fb_videomode modedb[] = {
183 NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, 183 NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
184 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED 184 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
185 }, { 185 }, {
186 /* 1680x1050 @ 60 Hz, 65.191 kHz hsync */
187 NULL, 60, 1680, 1050, 6848, 280, 104, 30, 3, 176, 6,
188 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
189 }, {
186 /* 1600x1200 @ 85 Hz, 105.77 kHz hsync */ 190 /* 1600x1200 @ 85 Hz, 105.77 kHz hsync */
187 NULL, 85, 1600, 1200, 4545, 272, 16, 37, 4, 192, 3, 191 NULL, 85, 1600, 1200, 4545, 272, 16, 37, 4, 192, 3,
188 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED 192 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
@@ -496,7 +500,7 @@ int fb_find_mode(struct fb_var_screeninfo *var,
496 /* Set up defaults */ 500 /* Set up defaults */
497 if (!db) { 501 if (!db) {
498 db = modedb; 502 db = modedb;
499 dbsize = sizeof(modedb)/sizeof(*modedb); 503 dbsize = ARRAY_SIZE(modedb);
500 } 504 }
501 if (!default_mode) 505 if (!default_mode)
502 default_mode = &modedb[DEFAULT_MODEDB_INDEX]; 506 default_mode = &modedb[DEFAULT_MODEDB_INDEX];
diff --git a/drivers/video/neofb.c b/drivers/video/neofb.c
index b961d5601bd9..24b12f71d5a8 100644
--- a/drivers/video/neofb.c
+++ b/drivers/video/neofb.c
@@ -165,20 +165,20 @@ static int neoFindMode(int xres, int yres, int depth)
165 165
166 switch (depth) { 166 switch (depth) {
167 case 8: 167 case 8:
168 size = sizeof(bios8) / sizeof(biosMode); 168 size = ARRAY_SIZE(bios8);
169 mode = bios8; 169 mode = bios8;
170 break; 170 break;
171 case 16: 171 case 16:
172 size = sizeof(bios16) / sizeof(biosMode); 172 size = ARRAY_SIZE(bios16);
173 mode = bios16; 173 mode = bios16;
174 break; 174 break;
175 case 24: 175 case 24:
176 size = sizeof(bios24) / sizeof(biosMode); 176 size = ARRAY_SIZE(bios24);
177 mode = bios24; 177 mode = bios24;
178 break; 178 break;
179#ifdef NO_32BIT_SUPPORT_YET 179#ifdef NO_32BIT_SUPPORT_YET
180 case 32: 180 case 32:
181 size = sizeof(bios32) / sizeof(biosMode); 181 size = ARRAY_SIZE(bios32);
182 mode = bios32; 182 mode = bios32;
183 break; 183 break;
184#endif 184#endif
diff --git a/drivers/video/nvidia/nv_accel.c b/drivers/video/nvidia/nv_accel.c
index f377a29ec97a..4aefb8f41637 100644
--- a/drivers/video/nvidia/nv_accel.c
+++ b/drivers/video/nvidia/nv_accel.c
@@ -300,6 +300,9 @@ int nvidiafb_sync(struct fb_info *info)
300{ 300{
301 struct nvidia_par *par = info->par; 301 struct nvidia_par *par = info->par;
302 302
303 if (info->state != FBINFO_STATE_RUNNING)
304 return 0;
305
303 if (!par->lockup) 306 if (!par->lockup)
304 NVFlush(par); 307 NVFlush(par);
305 308
@@ -313,6 +316,9 @@ void nvidiafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
313{ 316{
314 struct nvidia_par *par = info->par; 317 struct nvidia_par *par = info->par;
315 318
319 if (info->state != FBINFO_STATE_RUNNING)
320 return;
321
316 if (par->lockup) 322 if (par->lockup)
317 return cfb_copyarea(info, region); 323 return cfb_copyarea(info, region);
318 324
@@ -329,6 +335,9 @@ void nvidiafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
329 struct nvidia_par *par = info->par; 335 struct nvidia_par *par = info->par;
330 u32 color; 336 u32 color;
331 337
338 if (info->state != FBINFO_STATE_RUNNING)
339 return;
340
332 if (par->lockup) 341 if (par->lockup)
333 return cfb_fillrect(info, rect); 342 return cfb_fillrect(info, rect);
334 343
@@ -412,6 +421,9 @@ void nvidiafb_imageblit(struct fb_info *info, const struct fb_image *image)
412{ 421{
413 struct nvidia_par *par = info->par; 422 struct nvidia_par *par = info->par;
414 423
424 if (info->state != FBINFO_STATE_RUNNING)
425 return;
426
415 if (image->depth == 1 && !par->lockup) 427 if (image->depth == 1 && !par->lockup)
416 nvidiafb_mono_color_expand(info, image); 428 nvidiafb_mono_color_expand(info, image);
417 else 429 else
diff --git a/drivers/video/nvidia/nv_i2c.c b/drivers/video/nvidia/nv_i2c.c
index bd9eca05e146..1edb1c432b75 100644
--- a/drivers/video/nvidia/nv_i2c.c
+++ b/drivers/video/nvidia/nv_i2c.c
@@ -218,8 +218,7 @@ int nvidia_probe_i2c_connector(struct fb_info *info, int conn, u8 **out_edid)
218 } 218 }
219 } 219 }
220 220
221 if (out_edid) 221 *out_edid = edid;
222 *out_edid = edid;
223 222
224 return (edid) ? 0 : 1; 223 return (edid) ? 0 : 1;
225} 224}
diff --git a/drivers/video/nvidia/nv_type.h b/drivers/video/nvidia/nv_type.h
index e4a5b1da71c4..acdc26693402 100644
--- a/drivers/video/nvidia/nv_type.h
+++ b/drivers/video/nvidia/nv_type.h
@@ -129,6 +129,7 @@ struct nvidia_par {
129 int fpHeight; 129 int fpHeight;
130 int PanelTweak; 130 int PanelTweak;
131 int paneltweak; 131 int paneltweak;
132 int pm_state;
132 u32 crtcSync_read; 133 u32 crtcSync_read;
133 u32 fpSyncs; 134 u32 fpSyncs;
134 u32 dmaPut; 135 u32 dmaPut;
diff --git a/drivers/video/nvidia/nvidia.c b/drivers/video/nvidia/nvidia.c
index 7258b3245316..093ab9977c7c 100644
--- a/drivers/video/nvidia/nvidia.c
+++ b/drivers/video/nvidia/nvidia.c
@@ -21,6 +21,7 @@
21#include <linux/fb.h> 21#include <linux/fb.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/pci.h> 23#include <linux/pci.h>
24#include <linux/console.h>
24#ifdef CONFIG_MTRR 25#ifdef CONFIG_MTRR
25#include <asm/mtrr.h> 26#include <asm/mtrr.h>
26#endif 27#endif
@@ -297,6 +298,8 @@ static struct pci_device_id nvidiafb_pci_tbl[] = {
297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
298 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT, 299 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
301 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280,
302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
300 {PCI_VENDOR_ID_NVIDIA, 0x0252, 303 {PCI_VENDOR_ID_NVIDIA, 0x0252,
301 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
302 {PCI_VENDOR_ID_NVIDIA, 0x0313, 305 {PCI_VENDOR_ID_NVIDIA, 0x0313,
@@ -616,6 +619,30 @@ static int nvidia_panel_tweak(struct nvidia_par *par,
616 return tweak; 619 return tweak;
617} 620}
618 621
622static void nvidia_vga_protect(struct nvidia_par *par, int on)
623{
624 unsigned char tmp;
625
626 if (on) {
627 /*
628 * Turn off screen and disable sequencer.
629 */
630 tmp = NVReadSeq(par, 0x01);
631
632 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
633 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
634 } else {
635 /*
636 * Reenable sequencer, then turn on screen.
637 */
638
639 tmp = NVReadSeq(par, 0x01);
640
641 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
642 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
643 }
644}
645
619static void nvidia_save_vga(struct nvidia_par *par, 646static void nvidia_save_vga(struct nvidia_par *par,
620 struct _riva_hw_state *state) 647 struct _riva_hw_state *state)
621{ 648{
@@ -644,9 +671,9 @@ static void nvidia_save_vga(struct nvidia_par *par,
644 671
645#undef DUMP_REG 672#undef DUMP_REG
646 673
647static void nvidia_write_regs(struct nvidia_par *par) 674static void nvidia_write_regs(struct nvidia_par *par,
675 struct _riva_hw_state *state)
648{ 676{
649 struct _riva_hw_state *state = &par->ModeReg;
650 int i; 677 int i;
651 678
652 NVTRACE_ENTER(); 679 NVTRACE_ENTER();
@@ -695,32 +722,6 @@ static void nvidia_write_regs(struct nvidia_par *par)
695 NVTRACE_LEAVE(); 722 NVTRACE_LEAVE();
696} 723}
697 724
698static void nvidia_vga_protect(struct nvidia_par *par, int on)
699{
700 unsigned char tmp;
701
702 if (on) {
703 /*
704 * Turn off screen and disable sequencer.
705 */
706 tmp = NVReadSeq(par, 0x01);
707
708 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
709 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
710 } else {
711 /*
712 * Reenable sequencer, then turn on screen.
713 */
714
715 tmp = NVReadSeq(par, 0x01);
716
717 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
718 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
719 }
720}
721
722
723
724static int nvidia_calc_regs(struct fb_info *info) 725static int nvidia_calc_regs(struct fb_info *info)
725{ 726{
726 struct nvidia_par *par = info->par; 727 struct nvidia_par *par = info->par;
@@ -1069,7 +1070,8 @@ static int nvidiafb_set_par(struct fb_info *info)
1069 1070
1070 nvidia_vga_protect(par, 1); 1071 nvidia_vga_protect(par, 1);
1071 1072
1072 nvidia_write_regs(par); 1073 nvidia_write_regs(par, &par->ModeReg);
1074 NVSetStartAddress(par, 0);
1073 1075
1074#if defined (__BIG_ENDIAN) 1076#if defined (__BIG_ENDIAN)
1075 /* turn on LFB swapping */ 1077 /* turn on LFB swapping */
@@ -1378,6 +1380,57 @@ static struct fb_ops nvidia_fb_ops = {
1378 .fb_sync = nvidiafb_sync, 1380 .fb_sync = nvidiafb_sync,
1379}; 1381};
1380 1382
1383#ifdef CONFIG_PM
1384static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t state)
1385{
1386 struct fb_info *info = pci_get_drvdata(dev);
1387 struct nvidia_par *par = info->par;
1388
1389 acquire_console_sem();
1390 par->pm_state = state.event;
1391
1392 if (state.event == PM_EVENT_FREEZE) {
1393 dev->dev.power.power_state = state;
1394 } else {
1395 fb_set_suspend(info, 1);
1396 nvidiafb_blank(FB_BLANK_POWERDOWN, info);
1397 nvidia_write_regs(par, &par->SavedReg);
1398 pci_save_state(dev);
1399 pci_disable_device(dev);
1400 pci_set_power_state(dev, pci_choose_state(dev, state));
1401 }
1402
1403 release_console_sem();
1404 return 0;
1405}
1406
1407static int nvidiafb_resume(struct pci_dev *dev)
1408{
1409 struct fb_info *info = pci_get_drvdata(dev);
1410 struct nvidia_par *par = info->par;
1411
1412 acquire_console_sem();
1413 pci_set_power_state(dev, PCI_D0);
1414
1415 if (par->pm_state != PM_EVENT_FREEZE) {
1416 pci_restore_state(dev);
1417 pci_enable_device(dev);
1418 pci_set_master(dev);
1419 }
1420
1421 par->pm_state = PM_EVENT_ON;
1422 nvidiafb_set_par(info);
1423 fb_set_suspend (info, 0);
1424 nvidiafb_blank(FB_BLANK_UNBLANK, info);
1425
1426 release_console_sem();
1427 return 0;
1428}
1429#else
1430#define nvidiafb_suspend NULL
1431#define nvidiafb_resume NULL
1432#endif
1433
1381static int __devinit nvidia_set_fbinfo(struct fb_info *info) 1434static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1382{ 1435{
1383 struct fb_monspecs *specs = &info->monspecs; 1436 struct fb_monspecs *specs = &info->monspecs;
@@ -1721,8 +1774,6 @@ static void __exit nvidiafb_remove(struct pci_dev *pd)
1721 struct nvidia_par *par = info->par; 1774 struct nvidia_par *par = info->par;
1722 1775
1723 NVTRACE_ENTER(); 1776 NVTRACE_ENTER();
1724 if (!info)
1725 return;
1726 1777
1727 unregister_framebuffer(info); 1778 unregister_framebuffer(info);
1728#ifdef CONFIG_MTRR 1779#ifdef CONFIG_MTRR
@@ -1799,8 +1850,10 @@ static int __devinit nvidiafb_setup(char *options)
1799static struct pci_driver nvidiafb_driver = { 1850static struct pci_driver nvidiafb_driver = {
1800 .name = "nvidiafb", 1851 .name = "nvidiafb",
1801 .id_table = nvidiafb_pci_tbl, 1852 .id_table = nvidiafb_pci_tbl,
1802 .probe = nvidiafb_probe, 1853 .probe = nvidiafb_probe,
1803 .remove = __exit_p(nvidiafb_remove), 1854 .suspend = nvidiafb_suspend,
1855 .resume = nvidiafb_resume,
1856 .remove = __exit_p(nvidiafb_remove),
1804}; 1857};
1805 1858
1806/* ------------------------------------------------------------------------- * 1859/* ------------------------------------------------------------------------- *
diff --git a/drivers/video/pmagb-b-fb.c b/drivers/video/pmagb-b-fb.c
index eeeac924b500..73e2d7d16608 100644
--- a/drivers/video/pmagb-b-fb.c
+++ b/drivers/video/pmagb-b-fb.c
@@ -228,7 +228,7 @@ static void __init pmagbbfb_osc_setup(struct fb_info *info)
228 228
229 freq1 = (par->osc0 * count1 + count0 / 2) / count0; 229 freq1 = (par->osc0 * count1 + count0 / 2) / count0;
230 par->osc1 = freq1; 230 par->osc1 = freq1;
231 for (i = 0; i < sizeof(pmagbbfb_freqs) / sizeof(*pmagbbfb_freqs); i++) 231 for (i = 0; i < ARRAY_SIZE(pmagbbfb_freqs); i++)
232 if (freq1 >= pmagbbfb_freqs[i] - 232 if (freq1 >= pmagbbfb_freqs[i] -
233 (pmagbbfb_freqs[i] + 128) / 256 && 233 (pmagbbfb_freqs[i] + 128) / 256 &&
234 freq1 <= pmagbbfb_freqs[i] + 234 freq1 <= pmagbbfb_freqs[i] +
diff --git a/drivers/video/radeonfb.c b/drivers/video/radeonfb.c
index 04820fab964c..afb6c2ead599 100644
--- a/drivers/video/radeonfb.c
+++ b/drivers/video/radeonfb.c
@@ -759,7 +759,7 @@ static void __iomem *radeon_find_rom(struct radeonfb_info *rinfo)
759 rom = rom_base; 759 rom = rom_base;
760 760
761 for (i = 0; (i < 512) && (stage != 4); i++) { 761 for (i = 0; (i < 512) && (stage != 4); i++) {
762 for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) { 762 for (j = 0; j < ARRAY_SIZE(radeon_sig); j++) {
763 if (radeon_sig[j][0] == *rom) 763 if (radeon_sig[j][0] == *rom)
764 if (strncmp(radeon_sig[j], rom, 764 if (strncmp(radeon_sig[j], rom,
765 strlen(radeon_sig[j])) == 0) { 765 strlen(radeon_sig[j])) == 0) {
diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c
index b7bd6bb2c77c..3e9308f0f165 100644
--- a/drivers/video/riva/fbdev.c
+++ b/drivers/video/riva/fbdev.c
@@ -2073,8 +2073,6 @@ static void __exit rivafb_remove(struct pci_dev *pd)
2073 struct riva_par *par = info->par; 2073 struct riva_par *par = info->par;
2074 2074
2075 NVTRACE_ENTER(); 2075 NVTRACE_ENTER();
2076 if (!info)
2077 return;
2078 2076
2079#ifdef CONFIG_FB_RIVA_I2C 2077#ifdef CONFIG_FB_RIVA_I2C
2080 riva_delete_i2c_busses(par); 2078 riva_delete_i2c_busses(par);
diff --git a/drivers/video/savage/savagefb-i2c.c b/drivers/video/savage/savagefb-i2c.c
index 00719a91479f..21debed863ac 100644
--- a/drivers/video/savage/savagefb-i2c.c
+++ b/drivers/video/savage/savagefb-i2c.c
@@ -273,8 +273,7 @@ int savagefb_probe_i2c_connector(struct fb_info *info, u8 **out_edid)
273 } 273 }
274 } 274 }
275 275
276 if (out_edid) 276 *out_edid = edid;
277 *out_edid = edid;
278 277
279 return (edid) ? 0 : 1; 278 return (edid) ? 0 : 1;
280} 279}
diff --git a/drivers/video/sis/init301.c b/drivers/video/sis/init301.c
index 2d88f908170a..c3e070a6effd 100644
--- a/drivers/video/sis/init301.c
+++ b/drivers/video/sis/init301.c
@@ -8564,11 +8564,9 @@ SiS_ChrontelDoSomething3(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
8564static void 8564static void
8565SiS_ChrontelDoSomething2(struct SiS_Private *SiS_Pr) 8565SiS_ChrontelDoSomething2(struct SiS_Private *SiS_Pr)
8566{ 8566{
8567 unsigned short temp,tempcl,tempch; 8567 unsigned short temp;
8568 8568
8569 SiS_LongDelay(SiS_Pr, 1); 8569 SiS_LongDelay(SiS_Pr, 1);
8570 tempcl = 3;
8571 tempch = 0;
8572 8570
8573 do { 8571 do {
8574 temp = SiS_GetCH701x(SiS_Pr,0x66); 8572 temp = SiS_GetCH701x(SiS_Pr,0x66);
@@ -8582,13 +8580,6 @@ SiS_ChrontelDoSomething2(struct SiS_Private *SiS_Pr)
8582 8580
8583 SiS_SetCH701xForLCD(SiS_Pr); 8581 SiS_SetCH701xForLCD(SiS_Pr);
8584 8582
8585 if(tempcl == 0) {
8586 if(tempch == 3) break;
8587 SiS_ChrontelResetDB(SiS_Pr);
8588 tempcl = 3;
8589 tempch++;
8590 }
8591 tempcl--;
8592 temp = SiS_GetCH701x(SiS_Pr,0x76); 8583 temp = SiS_GetCH701x(SiS_Pr,0x76);
8593 temp &= 0xfb; /* Reset PLL */ 8584 temp &= 0xfb; /* Reset PLL */
8594 SiS_SetCH701x(SiS_Pr,0x76,temp); 8585 SiS_SetCH701x(SiS_Pr,0x76,temp);
diff --git a/drivers/video/sstfb.c b/drivers/video/sstfb.c
index 8c1a8b5135c6..c44de90ca12e 100644
--- a/drivers/video/sstfb.c
+++ b/drivers/video/sstfb.c
@@ -1194,10 +1194,11 @@ static struct dac_switch dacs[] __devinitdata = {
1194static int __devinit sst_detect_dactype(struct fb_info *info, struct sstfb_par *par) 1194static int __devinit sst_detect_dactype(struct fb_info *info, struct sstfb_par *par)
1195{ 1195{
1196 int i, ret = 0; 1196 int i, ret = 0;
1197 1197
1198 for (i=0; i<sizeof(dacs)/sizeof(dacs[0]); i++) { 1198 for (i = 0; i < ARRAY_SIZE(dacs); i++) {
1199 ret = dacs[i].detect(info); 1199 ret = dacs[i].detect(info);
1200 if (ret) break; 1200 if (ret)
1201 break;
1201 } 1202 }
1202 if (!ret) 1203 if (!ret)
1203 return 0; 1204 return 0;
@@ -1604,8 +1605,8 @@ static int sstfb_dump_regs(struct fb_info *info)
1604 {FBZMODE,"fbzmode"}, 1605 {FBZMODE,"fbzmode"},
1605 }; 1606 };
1606 1607
1607 const int pci_s = sizeof(pci_regs)/sizeof(pci_regs[0]); 1608 const int pci_s = ARRAY_SIZE(pci_regs);
1608 const int sst_s = sizeof(sst_regs)/sizeof(sst_regs[0]); 1609 const int sst_s = ARRAY_SIZE(sst_regs);
1609 struct sstfb_par *par = info->par; 1610 struct sstfb_par *par = info->par;
1610 struct pci_dev *dev = par->dev; 1611 struct pci_dev *dev = par->dev;
1611 u32 pci_res[pci_s]; 1612 u32 pci_res[pci_s];
diff --git a/drivers/video/virgefb.c b/drivers/video/virgefb.c
index ed78747487e2..5ea2345dab99 100644
--- a/drivers/video/virgefb.c
+++ b/drivers/video/virgefb.c
@@ -616,8 +616,7 @@ static struct {
616#endif 616#endif
617}; 617};
618 618
619#define arraysize(x) (sizeof(x)/sizeof(*(x))) 619#define NUM_TOTAL_MODES ARRAY_SIZE(virgefb_predefined)
620#define NUM_TOTAL_MODES arraysize(virgefb_predefined)
621 620
622/* 621/*
623 * Default to 800x600 for video=virge8:, virge16: or virge32: 622 * Default to 800x600 for video=virge8:, virge16: or virge32:
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 22:30:43 -0500