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authorDavid Miller <davem@davemloft.net>2011-01-11 18:51:26 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-03-22 02:47:07 -0400
commitea770789dce2d27afab39c3891a475624acbd82f (patch)
tree352ed0f19b74bff7dc6b80f7e05e7bf35b1f5d3f /drivers/video/vt8623fb.c
parentd907ec04cc498e11e039e0fff8eb58cf01e885da (diff)
svga: Make svga_wcrt_mask() take an iomem regbase pointer.
Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/video/vt8623fb.c')
-rw-r--r--drivers/video/vt8623fb.c36
1 files changed, 18 insertions, 18 deletions
diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c
index edcfee8bc90b..bc54b57db985 100644
--- a/drivers/video/vt8623fb.c
+++ b/drivers/video/vt8623fb.c
@@ -417,13 +417,13 @@ static int vt8623fb_set_par(struct fb_info *info)
417 417
418 /* Unlock registers */ 418 /* Unlock registers */
419 svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01); 419 svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01);
420 svga_wcrt_mask(0x11, 0x00, 0x80); 420 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
421 svga_wcrt_mask(0x47, 0x00, 0x01); 421 svga_wcrt_mask(par->state.vgabase, 0x47, 0x00, 0x01);
422 422
423 /* Device, screen and sync off */ 423 /* Device, screen and sync off */
424 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 424 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
425 svga_wcrt_mask(0x36, 0x30, 0x30); 425 svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
426 svga_wcrt_mask(0x17, 0x00, 0x80); 426 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
427 427
428 /* Set default values */ 428 /* Set default values */
429 svga_set_default_gfx_regs(par->state.vgabase); 429 svga_set_default_gfx_regs(par->state.vgabase);
@@ -437,13 +437,13 @@ static int vt8623fb_set_par(struct fb_info *info)
437 svga_wseq_multi(par->state.vgabase, vt8623_fetch_count_regs, fetch_value); 437 svga_wseq_multi(par->state.vgabase, vt8623_fetch_count_regs, fetch_value);
438 438
439 /* Clear H/V Skew */ 439 /* Clear H/V Skew */
440 svga_wcrt_mask(0x03, 0x00, 0x60); 440 svga_wcrt_mask(par->state.vgabase, 0x03, 0x00, 0x60);
441 svga_wcrt_mask(0x05, 0x00, 0x60); 441 svga_wcrt_mask(par->state.vgabase, 0x05, 0x00, 0x60);
442 442
443 if (info->var.vmode & FB_VMODE_DOUBLE) 443 if (info->var.vmode & FB_VMODE_DOUBLE)
444 svga_wcrt_mask(0x09, 0x80, 0x80); 444 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
445 else 445 else
446 svga_wcrt_mask(0x09, 0x00, 0x80); 446 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
447 447
448 svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus 448 svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus
449 svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus 449 svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus
@@ -468,18 +468,18 @@ static int vt8623fb_set_par(struct fb_info *info)
468 pr_debug("fb%d: text mode\n", info->node); 468 pr_debug("fb%d: text mode\n", info->node);
469 svga_set_textmode_vga_regs(); 469 svga_set_textmode_vga_regs();
470 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); 470 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
471 svga_wcrt_mask(0x11, 0x60, 0x70); 471 svga_wcrt_mask(par->state.vgabase, 0x11, 0x60, 0x70);
472 break; 472 break;
473 case 1: 473 case 1:
474 pr_debug("fb%d: 4 bit pseudocolor\n", info->node); 474 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
475 vga_wgfx(NULL, VGA_GFX_MODE, 0x40); 475 vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
476 svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE); 476 svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE);
477 svga_wcrt_mask(0x11, 0x00, 0x70); 477 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
478 break; 478 break;
479 case 2: 479 case 2:
480 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); 480 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
481 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); 481 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
482 svga_wcrt_mask(0x11, 0x00, 0x70); 482 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
483 break; 483 break;
484 case 3: 484 case 3:
485 pr_debug("fb%d: 8 bit pseudocolor\n", info->node); 485 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
@@ -506,8 +506,8 @@ static int vt8623fb_set_par(struct fb_info *info)
506 memset_io(info->screen_base, 0x00, screen_size); 506 memset_io(info->screen_base, 0x00, screen_size);
507 507
508 /* Device and screen back on */ 508 /* Device and screen back on */
509 svga_wcrt_mask(0x17, 0x80, 0x80); 509 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
510 svga_wcrt_mask(0x36, 0x00, 0x30); 510 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
511 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); 511 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
512 512
513 return 0; 513 return 0;
@@ -576,27 +576,27 @@ static int vt8623fb_blank(int blank_mode, struct fb_info *info)
576 switch (blank_mode) { 576 switch (blank_mode) {
577 case FB_BLANK_UNBLANK: 577 case FB_BLANK_UNBLANK:
578 pr_debug("fb%d: unblank\n", info->node); 578 pr_debug("fb%d: unblank\n", info->node);
579 svga_wcrt_mask(0x36, 0x00, 0x30); 579 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
580 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); 580 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
581 break; 581 break;
582 case FB_BLANK_NORMAL: 582 case FB_BLANK_NORMAL:
583 pr_debug("fb%d: blank\n", info->node); 583 pr_debug("fb%d: blank\n", info->node);
584 svga_wcrt_mask(0x36, 0x00, 0x30); 584 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
585 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 585 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
586 break; 586 break;
587 case FB_BLANK_HSYNC_SUSPEND: 587 case FB_BLANK_HSYNC_SUSPEND:
588 pr_debug("fb%d: DPMS standby (hsync off)\n", info->node); 588 pr_debug("fb%d: DPMS standby (hsync off)\n", info->node);
589 svga_wcrt_mask(0x36, 0x10, 0x30); 589 svga_wcrt_mask(par->state.vgabase, 0x36, 0x10, 0x30);
590 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 590 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
591 break; 591 break;
592 case FB_BLANK_VSYNC_SUSPEND: 592 case FB_BLANK_VSYNC_SUSPEND:
593 pr_debug("fb%d: DPMS suspend (vsync off)\n", info->node); 593 pr_debug("fb%d: DPMS suspend (vsync off)\n", info->node);
594 svga_wcrt_mask(0x36, 0x20, 0x30); 594 svga_wcrt_mask(par->state.vgabase, 0x36, 0x20, 0x30);
595 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 595 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
596 break; 596 break;
597 case FB_BLANK_POWERDOWN: 597 case FB_BLANK_POWERDOWN:
598 pr_debug("fb%d: DPMS off (no sync)\n", info->node); 598 pr_debug("fb%d: DPMS off (no sync)\n", info->node);
599 svga_wcrt_mask(0x36, 0x30, 0x30); 599 svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
600 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 600 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
601 break; 601 break;
602 } 602 }